Memory structure

Abstract

The invention provides a memory structure. The memory structure includes a substrate, a first gate structure, a second gate structure, and a plurality of channel bodies. The substrate has an upper surface. The first gate structure and the second gate structure are arranged on the substrate, are separated from each other in the first direction and extend along the second direction respectively. The channel bodies are separated from each other in the second direction and the third direction and respectively pass through the first gate structure and the second gate structure along the first direction. The first direction, the second direction and the third direction are mutually staggered, the upper surface is parallel to the first direction and the second direction, and the normal direction of the upper surface is parallel to the third direction. A first length of the first gate structure in the first direction and a second length of the second gate structure in the first direction are different from each other.

Description

Technical Field

[0001] The present invention relates to semiconductor structures, and more particularly to memory structures. Background Art

[0002] To meet market demands, memory structures are being driven to ever-smaller sizes. Various types of three-dimensional memory structures are rapidly developing. However, current three-dimensional memory structures still require further refinement to maintain performance while minimizing size. Summary of the Invention

[0003] The present invention relates to a memory structure based on a thyristor operation mechanism, which has the advantages of high scalability and fast operation speed.

[0004] According to one embodiment of the present invention, a memory structure is proposed. The memory structure includes a substrate, a first gate structure and a second gate structure, and a plurality of channel bodies. The substrate has an upper surface. The first gate structure and the second gate structure are arranged on the substrate, separated from each other in a first direction and extending respectively along a second direction. The channel bodies are separated from each other in a second direction and a third direction and pass through the first gate structure and the second gate structure respectively along the first direction. The first direction, the second direction and the third direction are staggered with each other, the upper surface is parallel to the first direction and the second direction, and the normal direction of the upper surface is parallel to the third direction. A first length of the first gate structure in the first direction and a second length of the second gate structure in the first direction are different from each other.

[0005] In order to better understand the above and other aspects of the present invention, the following embodiments are specifically described in detail with reference to the accompanying drawings: BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1A A three-dimensional schematic diagram of a memory structure according to an embodiment of the present invention is shown;

[0007] Figure 1B A schematic three-dimensional diagram of a memory structure according to another embodiment of the present invention is shown;

[0008] Figure 2 FIG2 is a perspective diagram illustrating a memory structure according to yet another embodiment of the present invention;

[0009] Figure 3 FIG2 is a perspective diagram illustrating a memory structure according to another embodiment of the present invention;

[0010] Figure 4A FIG. 1 is a partial top view of a memory structure according to embodiment A1 of the present invention;

[0011] Figure 4B Draw Figure 4A A partial cross-sectional view of a memory structure;

[0012] Figure 5A A partial top view of a memory structure according to a comparative example A1 is shown;

[0013] Figure 5B Draw Figure 5A A partial cross-sectional view of a memory structure;

[0014] Figure 6A and Figure 6B Schematic diagrams showing current-voltage relationship curves of the memory cells of Example A1 and Comparative Example A1 when different voltages are applied;

[0015] Figure 7A and Figure 7B illustrates a time-bias waveform diagram of a first gate structure, a second gate structure, and a bit line of a memory cell in different operating states according to the memory structure of Example A1;

[0016] Figure 7C A graph showing the relationship between current and holding time of Example A1 and Comparative Example A1 is shown;

[0017] Figure 8A A bit line current-bit line voltage relationship curve diagram of the memory cells of embodiments A1-A4 is shown;

[0018] Figure 8B A graph showing the relationship between the bit line current and the bit line voltage of the memory cells of Examples A1 and B2-B4 is shown;

[0019] Figure 9A A partial cross-sectional view of the memory structure of Example A4 is shown;

[0020] Figure 9B A schematic diagram illustrating a bit line current-bit line voltage relationship curve of one of the memory cells of the memory structure of Example A4;

[0021] Figure 9C shows how the bias voltage and current change over time in different operating states of Example A4;

[0022] Figure 10 An equivalent circuit diagram of a memory structure according to an embodiment of the present invention is shown;

[0023] Figure 11 shows the simulation results of the read operation of the memory cell CC;

[0024] Figure 12A shows the simulation results of the programming operation of the memory cell CC in the "0" state;

[0025] Figure 12B shows the simulation results of the programming operation of the memory cell CC in the "1" state;

[0026] Figure 12C shows the simulation results of the programming operation of the memory cell CD in the "0" state;

[0027] Figure 12D shows the simulation results of the programming operation of the memory cell CD in the "1" state;

[0028] Figure 13A Shows the simulation results of the erase operation of the memory cell CC in the "0" state

[0029] Figure 13B shows the simulation results of the erase operation of the memory cell CC in the "1" state;

[0030] Figure 13C shows the simulation results of the erase operation of the memory cell CD in the "0" state; and

[0031] Figure 13D FIG. 4 shows the simulation results of the erase operation of the memory cell CD in the “1” state.

[0032] Description of reference numerals:

[0033] 10, 10', 20, 30, 40, 50: memory structure

[0034] 100: Substrate

[0035] 100a: Upper surface

[0036] 112, 112', 212, 312, 412, 512: first gate structure

[0037] 114, 114', 214, 314, 414, 514: second gate structure

[0038] 120: Channel body

[0039] 120a: First end

[0040] 120b: Second end

[0041] 118: Dielectric film

[0042] 140: First side plug

[0043] 150: Second side plug

[0044] 162: First Contact

[0045] 164: Second Contact

[0046] 264, 362: Contact

[0047] 516: Third gate structure

[0048] 1121~1123, 1121'~1123', 1141~1143, 1141'~1143', 2141~2143, 3121~3123: Part

[0049] BL: bit line

[0050] BL1: First line

[0051] BL2: Second bit line

[0052] CA, CB, CC, CD: memory cells

[0053] CSL: Common Source Line

[0054] FWD: forward bias

[0055] CP: First side pad

[0056] D1, D2, D3: Direction

[0057] ERS: Erase Operation

[0058] ERS disturb: programming interruption

[0059] F: characteristic scale

[0060] Hold: Maintain operation

[0061] I BL : Bit line current

[0062] L112, L112': first length

[0063] L114, L114': Second length

[0064] PGM: Programming Operation

[0065] PGM disturb: Programming interrupted

[0066] REV: reverse bias

[0067] R162, R164, R264, R362: Landing Zone

[0068] Read: Read operation

[0069] Read disturb: Read interrupt

[0070] TA1, TA2, TB1, TB2, TC1, TC2, TD1, TD2: transistors

[0071] V BL : Bit line voltage

[0072] VFB1~VFB4: Breakdown voltage

[0073] Write "0": Write logical value "0"

[0074] Write "1": Write logical value "1"

[0075] W1~W13,WT:arrow

[0076] WS: Double Arrow DETAILED DESCRIPTION

[0077] The following examples, along with accompanying figures, illustrate the memory structure proposed by the present invention in detail. However, the present invention is not limited thereto. The descriptions in the examples, such as the detailed structures, operating methods, and material applications, are for illustrative purposes only, and the scope of protection of this disclosure is not limited to the described aspects.

[0078] At the same time, it should be noted that the present invention does not show all possible embodiments. Those skilled in the relevant art may, without departing from the spirit and scope of the present disclosure, change and modify the structure and operation method of the embodiment to meet the needs of actual application. Therefore, other embodiments not proposed in the present invention may also be applicable. Furthermore, the drawings are simplified to facilitate the clear description of the contents of the embodiments, and the dimensional ratios in the drawings are not drawn in proportion to the actual products. Therefore, the description and drawings are only used to describe the embodiments, and are not used to limit the scope of protection of the present disclosure. The same or similar element symbols are used to represent the same or similar originals.

[0079] Please refer to Figure 1A , which illustrates a three-dimensional schematic diagram of a memory structure 10 according to an embodiment of the present invention. The memory structure 10 includes a substrate 100, a first gate structure 112 and a second gate structure 114, a plurality of channel bodies 120, a plurality of pads CP, a first side plug 140, a plurality of second side plugs 150, a plurality of contacts (e.g., a plurality of first contacts 162 and a plurality of second contacts 164), and a plurality of dielectric films 118. To simplify the diagram, Figure 1A Some insulating materials are omitted, for example, the insulating materials between the substrate 100 , the channel body 120 , the first gate structure 112 and the second gate structure 114 are omitted.

[0080] like Figure 1AAs shown, the substrate 100 has an upper surface 100a. The first gate structure 112 and the second gate structure 114 are disposed on the substrate 100, separated from each other in the first direction D1 and respectively extend along the second direction D2. For example, the length of the first gate structure 112 and the second gate structure 114 in the second direction D2 is greater than the length of the first gate structure 112 and the second gate structure 114 in the first direction D1. In other words, the memory structure 10 of this embodiment includes two gate structures, namely the first gate structure 112 and the second gate structure 114, and the operation of the memory structure 10 is controlled by the bias applied by the first gate structure 112 and the second gate structure 114. The channel body 120 is separated from each other in the second direction D2 and the third direction D3 and respectively extends along the first direction D1 and passes through the first gate structure 112 and the second gate structure 114. As Figure 1A As shown, the first direction D1, the second direction D2, and the third direction D3 intersect with each other. The upper surface 100a of the substrate 100 extends in the first direction D1 and the second direction D2, and the normal direction of the upper surface 100a is parallel to the third direction D3. The first direction D1, the second direction D2, and the third direction D3 are substantially perpendicular to each other. The channel body 120 can be orthogonal to the first gate structure 112 and the second gate structure 114.

[0081] exist Figure 1AIn the embodiment, the first gate structure 112 and the second gate structure 114 have asymmetric lengths. Specifically, a first length L112 of the first gate structure 112 in the first direction D1 and a second length L114 of the second gate structure 114 in the first direction D1 are different. For example, the first length L112 is less than the second length L114. However, the present invention is not limited thereto. In this embodiment, the first gate structure 112 includes a plurality of portions 1121-1123. The portions 1121-1123 have the same length in the first direction D1, namely, the first length L112. The second gate structure 114 includes a plurality of portions 1141-1143. The portions 1141-1143 have the same length in the first direction D1, namely, the second length L114. Each portion 1121-1123 of the first gate structure 112 extends along the second direction D2. The portions 1121-1123 are separated from each other along the third direction D3, for example, by insulating material (not shown) so as not to directly contact each other. The lengths of portions 1121-1123 in the second direction D2 are different from one another. For example, the lengths of portions 1121-1123 in the second direction D2 decrease along the second direction D2. That is, the length of portion 1121 in the second direction D2 is greater than the length of portion 1122 in the second direction D2, and the length of portion 1122 in the second direction D2 is greater than the length of portion 1123 in the second direction D2. Each portion 1141-1143 of the second gate structure 114 extends along the second direction D2, and portions 1141-1143 are separated from one another along the third direction D3, for example, by insulating material (not shown) so as not to be in direct contact with one another. Similarly, the lengths of portions 1141 to 1143 in the second direction D2 are different from each other. For example, the lengths of portions 1141 to 1143 in the second direction D2 decrease along the second direction D2, that is, the length of portion 1141 in the second direction D2 is greater than the length of portion 1142 in the second direction D2, and the length of portion 1142 in the second direction D2 is greater than the length of portion 1143 in the second direction D2.

[0082] like Figure 1AAs shown, the contact pads CP are stacked and separated from each other along the third direction D3. Each contact pad CP is connected to a corresponding first end 120a of the channel body 120. For example, each contact pad CP is connected to three first ends 120a of three channel bodies 120 that overlap in the second direction D2. The first side plugs 140 extend along the third direction D3 and connect all of the contact pads CP. The second side plugs 150 extend along the third direction D3 and are separated from each other in the second direction D2. Each second side plug 150 is connected to a corresponding second end 120b of the channel body 120. For example, each second side plug 150 is connected to three second ends 120b of three channel bodies 120 that overlap in the third direction D3. The second ends 120b are opposite to the first ends 120a, that is, the first end 120a and the second end 120b are opposite ends of the channel body 120 extending in the first direction D1. The first gate structure 112 is closer to the first end 120a than the second gate structure 114, and the second gate structure 114 is closer to the second end 120b than the first gate structure 112. According to one embodiment, the first end 120a includes a first conductivity type dopant, and the second end 120b includes a second conductivity type dopant, where the second conductivity type dopant is different from the first conductivity type dopant. For example, the first conductivity type dopant is an N-type dopant and the second conductivity type dopant is a P-type dopant, that is, the first end 120a includes a high concentration of N-type dopant (N+), and the second end 120b includes a high concentration of P-type dopant (P+).

[0083] like Figure 1A As shown, the dielectric film 118 is disposed between the first gate structure 112 and the channel body 120, and between the second gate structure 114 and the channel body 120. Each portion 1121-1123 of the first gate structure 112 can surround multiple channel bodies 120 and the dielectric film 118, for example, three channel bodies 120 and dielectric films 118 at the same level, with the portions 1121-1123 forming three gate-all-around (GAA) structures. Each portion 1141-1143 of the second gate structure 114 can surround multiple channel bodies 120 and the dielectric film 118, for example, three channel bodies 120 and dielectric films 118 at the same level, with the portions 1141-1143 forming three gate-all-around (GAA) structures.

[0084] exist Figure 1A, the first contacts 162 are separated from each other along the second direction D2 and extend along the third direction D3 to electrically contact the multiple first landing areas R162 on the portions 1121 to 1123 of the first gate structure 112. The heights of the first contacts 162 in the third direction D3 are different from each other, for example, forming a stepped contact, and the first landing areas R162 form a stepped structure. The second contacts 164 are separated from each other along the second direction D2 and extend along the third direction D3 to electrically contact the multiple second landing areas R164 on the portions 1141 to 1143 of the second gate structure 114. The heights of the second contacts 164 in the third direction D3 are different from each other, for example, forming a stepped contact, and the second landing areas R164 form another stepped structure. Since portions 1121-1123 of the first gate structure 112 and portions 1141-1143 of the second gate structure 114 can be biased via the stepped first contacts 162 and second contacts 164, respectively, the word line biases of different layers (pages) can be independently adjusted, thereby enabling page erase and making it easier to adjust the disturbance and retention of unselected pages (details will be described below).

[0085] According to one embodiment, the memory structure 10 further includes a plurality of memory cells (eg Figure 10 Memory cells CA-CD shown in FIG, each memory cell (eg memory cells CA-CD) is formed by a corresponding one of the channel body 120 and the first gate structure 112 and the second gate structure 114, as shown in FIG. Figure 10 The equivalent circuit diagram is shown in the figure.

[0086] Please refer back Figure 1A According to this embodiment, the first gate structure 112 and the second gate structure 114 can each serve as a plurality of word lines (WL). For example, each portion 1121-1123 of the first gate structure 112 can serve as a word line, meaning the first gate structure 112 can correspond to three word lines; and each portion 1141-1143 of the second gate structure 114 can serve as a word line, meaning the second gate structure 114 can correspond to three word lines. The first-side plug 140 can serve as a common source line (CSL). Each second-side plug 150 can serve as a bit line (BL).

[0087] In some embodiments, the substrate 100 may include a semiconductor substrate, such as a bulk silicon substrate. In this embodiment, the channel body 120 may be formed by a selective epitaxial growth process, and the material of the channel body 120 may include single crystal silicon. During operation (e.g., programming or erasing) of the memory structure 10, the channel body 120 may be used to store carriers (e.g., electrons or holes). The dielectric film 118 does not need to have the function of storing carriers (e.g., electrons or holes), so the dielectric film 118 does not include a charge storage structure, such as an oxide-nitride-oxide (ONO) structure. In one embodiment, the material of the dielectric film 118 includes a dielectric material, such as an oxide, and the dielectric film 118 may be a single-layer structure. In one embodiment, the material of the dielectric film 118 may include a high dielectric constant material (high-k material). In one embodiment, the first contacts 162 , the second contacts 164 , the first side plugs 140 , the second side plugs 150 , the first gate structure 112 , and the second gate structure 114 may be made of semiconductor materials or metal materials.

[0088] Compared to the embodiment in which the first gate structure and the second gate structure have the same length in the first direction D1 (for example, both are 90 nm), the first length L112 of the first gate structure 112 in the first direction D1 of this embodiment is smaller than the second length L114 of the second gate structure 114 in the first direction D1 (for example, the first length L112 = 30 nm, the second length L114 = 90 nm). That is, the first gate structure 112 can occupy a smaller volume, thereby reducing the size of the memory structure to meet the requirements of miniaturization.

[0089] Figure 1B A schematic perspective view of a memory structure 10' according to another embodiment of the present invention is shown. A major difference between the memory structure 10' and the memory structure 10 is that the first length L112' and the second length L114' are different. Other identical parts will not be described in detail.

[0090] Please refer to Figure 1BThe first gate structure 112' (including portions 1121' to 1123') and the second gate structure 114' (including portions 1141' to 1143') have asymmetric lengths, that is, a first length L112' of the first gate structure 112' in the first direction D1 and a second length L114' of the second gate structure 114' in the first direction D1 are different from each other. For example, the second length L114' is smaller than the first length L112', but the present invention is not limited thereto.

[0091] Compared to the embodiment in which the first gate structure and the second gate structure have the same length in the first direction D1 (for example, both are 90 nm), the second length L114' of the second gate structure 114' in the first direction D1 of this embodiment is smaller than the first length L112' of the first gate structure 112' in the first direction D1 (for example, the first length L112'=90 nm, the second length L114'=30 nm). That is, the second gate structure 114' can occupy a smaller volume, thereby reducing the size of the memory structure to meet the requirements of miniaturization.

[0092] Figure 2 FIG2 is a perspective diagram of a memory structure 20 according to another embodiment of the present invention. A major difference between the memory structure 20 and the memory structure 10 is the difference in the first gate structure 212. Other identical parts will not be described in detail again.

[0093] Please refer to Figure 2 The first gate structure 212 is a continuous structure in the third direction D3, rather than a plurality of separate parts. Similar to the second gate structure 114, the second gate structure 214 includes a plurality of parts 2141-2143. The parts 2141-2143 of the second gate structure 214 extend along the second direction D2 and are separated from each other along the third direction D3. The first gate structure 212 corresponds to all of the channel bodies 120, for example, surrounding all of the channel bodies 120. Similar to the second gate structure 114, the parts 2141-2143 of the second gate structure 214 correspond to portions of the channel bodies 120, for example, each part 2141-2143 surrounds three overlapping channel bodies 120 in the second direction D2. Similar to the second contacts 164 , the contacts 264 are separated from each other along the second direction D2 and extend along the third direction D3 to electrically contact a plurality of landing regions R264 on the portions 2141 ˜ 2143 of the second gate structure 214 . The landing regions R264 form a stepped structure.

[0094] Figure 3FIG. 3 is a schematic perspective view of a memory structure 30 according to another embodiment of the present invention. A major difference between the memory structure 30 and the memory structure 10 is the difference in the second gate structure 314. Other identical parts will not be described in detail again.

[0095] Please refer to Figure 3 The second gate structure 314 is a continuous structure in the third direction D3 and is not a plurality of separate parts. Similar to the first gate structure 112, the first gate structure 312 includes a plurality of parts 3121-3123. The parts 3121-3123 of the first gate structure 312 extend along the second direction D2 and are separated from each other along the third direction D3. The second gate structure 314 corresponds to all channel bodies 120, for example, surrounding all channel bodies 120. Similar to the first gate structure 112, the parts 3121-3123 of the first gate structure 312 correspond to portions of the channel bodies 120, for example, each part 3121-3123 surrounds three overlapping channel bodies 120 in the second direction D2. Similar to the first contacts 162 , the contacts 362 are separated from each other along the second direction D2 and extend along the third direction D3 to electrically contact a plurality of landing regions R362 on the portions 3121 ˜ 3123 of the first gate structure 312 . The landing regions R362 form a stepped structure.

[0096] exist Figures 1A to 3 In the present invention, the memory structure 10 to 30 includes a plurality of memory cells, each of which is a thyristor. More specifically, the memory cells of the memory structures 10 to 30 control the operation of the thyristor through the gate, so the memory cells are also called gate-controlled-thyristors (GCTs). Based on the characteristics of the gate-controlled thyristors, the access speed of the memory structures 10 to 30 can reach the level of random access memory (RAM). That is, the operating mechanism of the memory structures 10 to 30 of the present invention is all based on thyristors. It should be understood that the memory structure of the present invention is not limited to Figures 1A to 3 The embodiment shown.

[0097] Figure 4A FIG. 1 is a partial top view of a memory structure 40 according to embodiment A1 of the present invention. Figure 4B Draw Figure 4A A partial cross-sectional view of the memory structure 40. A major difference between the memory structure 40 and the memory structure 10 is that the first gate structure 412 and the second gate structure 414 are symmetrical to each other. Other identical parts will not be described in detail. To make the figure more concise, Figure 4A and Figure 4B Insulating materials and dielectric films are omitted.

[0098] Please also refer to Figure 4A and Figure 4B The first gate structure 412 and the second gate structure 414 have symmetrical lengths, that is, the length of the first gate structure 412 in the first direction D1 is equal to the length of the second gate structure 414 in the first direction D1 (for example, both are equal to 90 nm).

[0099] Figure 5A FIG. 1 shows a partial top view of a memory structure 50 according to Comparative Example A1 of the present invention. Figure 5B Draw Figure 5A A partial cross-sectional view of the memory structure 50 is shown. A major difference between the memory structure 50 and the memory structure 40 is that the memory structure 50 further includes a third gate structure 516, and the first gate structure 512, the second gate structure 514, and the third gate structure 516 all surround all channel bodies 120. Other identical parts will not be described in detail.

[0100] like Figure 4A and Figure 5A As shown, the first gate structure 412 and the second gate structure 414 of the memory structure 40, and the first gate structure 512, the second gate structure 514, and the third gate structure 516 of the memory structure 50 have the same length (e.g., 90 nm) and spacing (e.g., 25 nm) in the first direction D1. The unit memory cell area of ​​the memory structure 40 can be 10F2, and the unit memory cell area of ​​the memory structure 50 can be 14F2, where F represents the feature size, such as the minimum half-pitch of the memory cell. It can be seen that the dual-gate memory structure 40 has a smaller unit area than the triple-gate memory structure 50, which better meets the requirements of miniaturization of memory structures.

[0101] Figure 6A and Figure 6B Different voltages are applied to the embodiment A1 (such as Figure 4A and Figure 4B As shown) and Comparative Example A1 (as shown Figure 5A and Figure 5B Schematic diagram of the current-voltage relationship curve of the memory cell with a gate structure as shown). Figure 6A In FIG, -1.5V is applied to the first gate structure 412 of the memory structure 40, and 1.5V is applied to the second gate structure 414 of the memory structure 40; -1.5V is applied to the first gate structure 512 of the memory structure 50, 1.5V is applied to the second gate structure 514 of the memory structure 50, and 1.5V is applied to the third gate structure 516 of the memory structure 50. Figure 6B, -1V is applied to the first gate structure 412 of the memory structure 40, and 1V is applied to the second gate structure 414 of the memory structure 40; -1V is applied to the first gate structure 512 of the memory structure 50, 1V is applied to the second gate structure 514 of the memory structure 50, and 1V is applied to the third gate structure 516 of the memory structure 50. Figure 6A and Figure 6B In the figure, the X-axis represents the bit line bias (V BL ), the unit is volts (V); the Y axis represents the bit line current (I BL ), the unit is ampere (A). The solid line curve represents the forward bias (e.g., scanning from the left to the right), and the dashed line curve represents the reverse bias (e.g., scanning from the right to the left).

[0102] The operating mechanisms of Example A1 and Comparative Example A1 are both based on thyristors, and the current-voltage curve of the memory cell is highly nonlinear, also known as a hysteresis curve. When the memory cell performs a program operation (i.e., a write operation) to write a logical value "1", the memory cell is in a programmed state ("1"). When the memory cell performs an erase operation to erase the logical value to "0", the memory cell is in an erased state ("0"). The drain-source voltage difference of the memory cell is the voltage difference between the bit line voltage and the source line voltage. When the drain-source voltage difference is less than the inherent built-in potential barrier of the PN junction of the memory cell, the memory cell is in an erased state ("0"), and the memory cell stores a logical value "0". On the other hand, when the drain-source voltage difference is greater than the forward breakdown voltage of the forward bias (e.g., Figure 6A When the drain-source voltage difference is within the programming bias range, the positive feedback of the memory cell can be triggered to perform a write operation. In addition, when the drain-source voltage difference of the memory cell is between the inherent built-in barrier of the PN junction and the forward breakdown voltage (such as Figure 6A When the drain-source voltage difference is between VFB1 or VFB2 (as shown), it is within the read bias range. Within the read bias range, the on-to-off current ratio of the memory cell has a large value. More specifically, the on-to-off current ratio is defined as the ratio of the bit line current value in the programmed state ("1") to the bit line current value in the erased state ("0"). Because the on-to-off current ratio is very large, it is clear within the read bias range whether the memory cell is in the programmed state ("1"), storing a logical value of "1", or in the erased state ("0"), storing a logical value of "0".

[0103] Please refer to Figure 6A The breakdown voltage VFB1 of Example A1 is not much different from the breakdown voltage VFB2 of Comparative Example A1, but the on-current of Example A1 is significantly higher than that of Comparative Example A1, as shown by arrow W1. Figure 6B The breakdown voltage VFB3 of Example A1 is not much different from the breakdown voltage VFB4 of Comparative Example A1, while the on-current of Example A1 is significantly increased compared with that of Comparative Example A1, as indicated by arrow W2.

[0104] It can be seen that compared to the triple-gate memory structure 50, the dual-gate memory structure 40 does not significantly reduce the breakdown voltage (e.g., VFB1 and VFB3), and can also increase the on-state current, providing a larger current range, thereby enlarging the window between the programmed state ("1") and the erased state ("0").

[0105] Figure 7A and Figure 7B 1 and 2 illustrate time-bias waveforms of the first gate structure 412 , the second gate structure 414 and the bit line (BL) of a memory cell in the memory structure 40 according to embodiment A1 under different operating states, where the X-axis represents time (μs) and the Y-axis represents bias (V).

[0106] exist Figure 7A In the memory structure 40, one of the memory cells performs an erase operation, first writing a logic value "0" (abbreviated as Write "0"), then performing a hold operation (abbreviated as Hold), and then performing a read operation (abbreviated as Read).

[0107] exist Figure 7B In the memory structure 40, one of the memory cells performs a programming operation, first writing a logic value "1" (abbreviated as Write "1"), then performs a holding operation (abbreviated as Hold), and then performs a reading operation (abbreviated as Read).

[0108] Figure 7CA current-hold time relationship graph for Example A1 and Comparative Example A1 is shown. The X-axis represents hold time (seconds), and the Y-axis represents current (microamperes) during a read operation (abbreviated as Read). Both Example A1 and Comparative Example A1 include curves corresponding to a low current state (corresponding to Write "0") and a high current state (corresponding to Write "1"). In the high current state (corresponding to Write "1"), the current for Example A1 reaches approximately 9.4 microamperes, while the current for Comparative Example A1 is approximately 3.7 microamperes. This shows that the dual-gate structure of Example A1 can achieve a higher current than the triple-gate structure of Comparative Example A1. At a hold time of approximately 5 seconds, the current of both Example A1 and Comparative Example A1 rapidly increases from a low current state (corresponding to Write "0") to a high current state (corresponding to Write "1"), indicating that the hold time of the dual-gate structure of Example A1 is comparable to that of the triple-gate structure of Comparative Example A1, demonstrating comparable hold time.

[0109] Figure 8A The bit line current (I BL )(A)-bit line voltage (V BL (V) Relationship curve diagram. Example A1 is as follows Figure 4A-4B In the memory structure 40 shown, the length of the first gate structure 412 in the first direction D1 is, for example, 90 nm. The lengths of the second gate structures in the first direction D1 of embodiments A2 to A4 are all the same as the length of the second gate structure 414 in the first direction D1 of embodiment A1, for example, all are 90 nm. The difference between embodiments A2 to A4 and embodiment A1 is that the lengths of the first gate structures in the first direction D1 are different (other identical parts will not be described again). For example, the length of the first gate structure in the first direction D1 of embodiment A2 is 70 nm, the length of the first gate structure in the first direction D1 of embodiment A3 is 50 nm, and the length of the first gate structure in the first direction D1 of embodiment A4 is 30 nm. The first gate structures of embodiments A1 to A4 are all given -1.5 V, and the second gate structures are all given 1.5 V.

[0110] like Figure 8A As shown, the breakdown voltages of Examples A1 to A4 remain virtually unchanged. In the high-current state (corresponding to Write "1"), the on-current of Example A4 is greater than that of Example A3, which in turn is greater than that of Example A2, which in turn is greater than that of Example A1. This indicates that as the length of the first gate structure in the first direction D1 decreases, the on-current can increase, as indicated by arrow W3, and the window for reading current can also increase.

[0111] Figure 8B The bit line current (I BL )(A)-bit line voltage (V BL (V) Relationship curve diagram. Example A1 is as follows Figure 4A-4B In the memory structure 40 shown, the length of the second gate structure 414 in the first direction D1 is, for example, 90 nm. The lengths of the first gate structures in the first direction D1 of embodiments B2 to B4 are all the same as the length of the first gate structure 412 in the first direction D1 of embodiment A1, for example, all are 90 nm. The difference between embodiments B2 to B4 and embodiment A1 lies in the different lengths of the second gate structures in the first direction D1 (other identical parts will not be described again). For example, the length of the second gate structure in the first direction D1 of embodiment B2 is 70 nm, the length of the second gate structure in the first direction D1 of embodiment B3 is 50 nm, and the length of the second gate structure in the first direction D1 of embodiment B4 is 30 nm. The first gate structures of embodiments A1 and B2 to B4 are all given -1.5 V, and the second gate structures are all given 1.5 V.

[0112] like Figure 8B As shown, the breakdown voltages of Examples B2-B4 vary, as indicated by arrow W4. The breakdown voltages of Examples B2-B4 are all lower than that of Example A1. For example, the breakdown voltage of Example B4 is lower than that of Example B3, which is lower than that of Example B2, which is lower than that of Example A1. As can be seen, as the length of the second gate structure in the first direction D1 decreases, the breakdown voltage decreases. Because the memory cell operates by applying a bias to the bit line (BL), the bit line bias, which serves as a hole source, induces positive feedback. Therefore, the breakdown voltage depends on the potential barrier of the second gate structure, which is closer to the bit line (BL), rather than the potential barrier of the first gate structure, which is farther away from the bit line. Therefore, changes in the length of the second gate structure in the first direction can affect the breakdown voltage. For example, when the length of the second gate structure in the first direction decreases, the potential barrier to holes decreases, resulting in a significant decrease in the breakdown voltage. However, changes in the length of the first gate structure in the first direction have little effect on the breakdown voltage. That is, reducing the length of the first gate structure in the first direction will increase the on-current but will not affect the hysteresis loop.

[0113] In one embodiment, the size of the memory cell can be reduced by significantly shortening the length of the first gate structure in the first direction. Since the size of the first gate structure hardly affects the hysteresis cycle, it has greater room for reduction than the size of the second gate structure.

[0114] In one embodiment, the breakdown voltage can be reduced by reducing the length of the second gate structure in the first direction. This can also reduce the operating voltage, thereby reducing the power consumption of the memory structure.

[0115] Therefore, in the memory structure of the present invention, the dimensions of the first gate structure and the second gate structure in the first direction can be adjusted according to actual needs. For example, when the memory size of the memory structure is expected to be reduced to a greater extent, the length of the first gate structure in the first direction can be selected to be greater than the length of the second gate structure in the first direction (e.g., Figure 1B Alternatively, when it is desired to reduce the operating energy consumption of the memory structure, the length of the second gate structure in the first direction may be greater than the length of the first gate structure in the first direction.

[0116] Figure 9A A partial cross-sectional view of the memory structure of Example A4 is shown. The length of the second gate structure in the first direction (eg, 90 nm) is greater than the length of the first gate structure in the first direction (eg, 30 nm).

[0117] Figure 9B FIG. 1 is a schematic diagram illustrating a relationship curve between a bit line current and a bit line voltage of a memory cell in the memory structure of Example A4. Figure 9C The variation of bias voltage (V) and current (µA) over time (µs) for different operating states of Example A4 is shown. The erase operation is abbreviated as "ERS," the read operation is abbreviated as "Read," and the program operation is abbreviated as "PGM."

[0118] exist Figure 9B In the figure, the X-axis represents the bit line bias (V BL ), the unit is volts (V); the Y axis represents the bit line current (I BL ), the unit is ampere (A), the solid line curve represents the forward bias FWD, and the dotted line curve represents the reverse bias REV.

[0119] exist Figure 9CIn FIG, the memory cell sequentially performs the "PGM", "Read", "ERS" and "Read" operations. The bit line (BL) bias voltages are 2.5V, 1.5V, 0V and 1.5V in the "PGM", "Read", "ERS" and "Read" states, respectively. The first gate structure 112 is biased at -1.5V in "PGM" and "Read". In "ERS", the bias is pulled back to 0V for a short time and then returns to -1.5V. Thereafter, it remains at -1.5V in "Read". The second gate structure 114 is biased at 1.5V in "PGM" and "Read". In "ERS", the bias is pulled back to 0V for a short time and then returns to 1.5V. Thereafter, it remains at 1.5V in "Read". As can be seen from the waveform of the bit line (BL) current, it can have a current window of approximately 62 microamperes, as indicated by the interval of the double arrow WS.

[0120] By applying a set of appropriate bias voltages (for example, the bit line bias voltages are 2.5V, 1.5V and 0V in the "PGM", "Read" and "ERS" states, respectively), a Figure 9B The DC hysteresis loop shown can help produce Figure 9C The appropriate operating results are shown.

[0121] Figure 10 A memory structure according to an embodiment of the present invention is shown (corresponding to the present invention Figure 1A-1B An equivalent circuit diagram of the embodiment shown or other embodiments).

[0122] Please also refer to Figure 1A and Figure 10 , Figure 10 Exemplary illustration Figure 1A Each intersection of the four adjacent channel bodies 220, for example, the channel body 120, the portion 1121 in the first gate structure 112, and the portion 1141 in the second gate structure 114, forms a transistor. Figure 10As shown, transistors TA1 and TA2 connected through the same channel body 120 together form a memory cell CA; transistors TB1 and TB2 connected through the same channel body 120 together form a memory cell CB; transistors TC1 and TC2 connected through the same channel body 120 together form a memory cell CC; and transistors TD1 and TD2 connected through the same channel body 120 together form a memory cell CD. The first end 120a of the channel body 120 is connected to a corresponding first-side pad CP. The first-side pads CP on different layers electrically contact a first-side plug 140 and are electrically connected to the source line. Therefore, the memory cells CA-CD are connected to the common source line CSL (i.e., at the same potential). The second ends 120 b of the channel bodies 220 are connected to corresponding second side plugs 150. That is, the channel bodies 120 that overlap each other in the third direction D3 are connected to the same second side plug 150. The second side plug 150 can serve as a bit line. For example, the memory cells CA and CC are electrically connected to the first bit line BL1, and the memory cells CB and CD are electrically connected to the second bit line BL2.

[0123] In this embodiment, the memory cell CA is a memory cell to be selected, and the other memory cells CB to CD are unselected memory cells (for example, suppressed memory cells). Different bias voltages can be applied to the portion 1121 of the first gate structure 112, the portion 1122 of the first gate structure 112, the portion 1141 of the second gate structure 114, the portion 1142 of the second gate 114, the first bit line BL1, the second bit line BL2 and the common source line CSL according to the following Tables 1 to 3 to perform different operating modes, for example, "Read disturb", "PGM disturb", "ERSdisturb", or other operating modes similar to those described in the relevant paragraphs of the following Tables 1 to 3 (details will be described later).

[0124] In one embodiment, when the memory structure performs a read operation, since the memory cells AC and CC share the same first bit line BL1, in order to prevent the unselected memory cell CC from generating leakage current when the selected memory cell AC is operated, a larger voltage (e.g., |2.5|V) may be applied to the word line connecting the memory cell CC (i.e., the portion 1122 of the first gate structure 112 and the portion 1142 of the second gate structure 114) to shut down the leakage current of the memory cell CC. Furthermore, it is necessary to confirm the bit line current of the memory cell CC through a simulation experiment (e.g., TCAD), as shown in FIG. Figure 11The operation of applying a larger voltage to the bit line connected to the memory cell CC represents an interruption state during the read operation (abbreviated as "Read") (i.e., the original state is restored after the interruption state), which can be called a read interrupt, or "Read disturb" for short. The operating voltage during the "Readdisturb" state can be referred to in Table 1 below.

[0125] [Table 1]

[0126] Operation Mode Read disturb Portion 1121 (V) of the first gate structure 112 -1.5 Portion 1122 (V) of the first gate structure 112 -2.5 Portion 1141 (V) of the second gate structure 114 1.5 Portion 1142 (V) of the second gate structure 114 2.5 First bit line BL1 (V) 1.5 Second bit line BL2 (V) 0 Common source line CSL(V) 0

[0127] Figure 11 The simulation results of the read operation of the memory cell CC are shown, for example, the bias voltage (V) applied to the first bit line BL1, the bias voltage (V) applied to the portion 1122 of the first gate structure 112, the bias voltage (V) applied to the portion 1142 of the second gate structure 114, and the first bit line current (μA) are shown as a function of time (μs) under the operating states "PGM", "Read", "Read disturb" and "Read". Please also refer to Table 1 and Figure 11 , 0V can be applied to the unselected second bit line BL2 to shut down the current from the memory cell CB and the memory cell CD. Figure 11 The simulation results show that in the "Read disturb" state, the memory cell CC has no bit line current, as shown by the arrow W5. It can be seen that by increasing the voltage of the word line (i.e., the gate structure) of the memory cell CC (for example, from |1.5|V to |2.5|V), the bit line current of the memory cell CC is indeed completely shut down. In addition, the read current (read current) of the memory cell CC in the "Read" state before the "Read disturb" state and the "Read" state after the "Read disturb" state does not change (as shown by the arrow WT), indicating that the memory cell CC remains in a good state and is not affected by the "Read disturb".

[0128] In one embodiment, the memory structure performs a programming operation, that is, changes from a "0" state to a "1" state. When the memory cell CA is selected for programming, in order to prevent the unselected memory cells CC and CD from being programmed, a larger voltage (e.g., 3V) is applied to the portion 1142 of the second gate structure 114 to increase the PNPN barrier to inhibit programming. Simulation experiments are also required to confirm the bit line current of the memory cells CC and CD, as shown in FIG. Figures 12A to 12DThe operation of applying a relatively large voltage (e.g., 3V) to the portion 1142 of the second gate structure 114 represents an interruption state during a programming operation (abbreviated as "PGM") (i.e., the original state is restored after the interruption state), which can be referred to as a programming interrupt, or "PGM disturb" for short. The operating voltage during the "PGM disturb" state can be referred to in Table 2 shown below.

[0129] [Table 2]

[0130] Operation Mode Programming interrupt (PGM disturb) Portion 1121 (V) of the first gate structure 112 -1.5 Portion 1122 (V) of the first gate structure 112 -1.5 Portion 1141 (V) of the second gate structure 114 1.5 Portion 1142 (V) of the second gate structure 114 3 First bit line BL1 (V) 2.5 Second bit line BL2 (V) 1.5 Common source line CSL(V) 0

[0131] Figure 12A The simulation results of the programming operation of the memory cell CC in the "0" state are shown, for example, the bias voltage (V) applied to the first bit line BL1, the bias voltage (V) applied to the portion 1122 of the first gate structure 112, the bias voltage (V) applied to the portion 1142 of the second gate structure 114, and the first bit line current (microamperes) are shown as a function of time (microseconds) under the operating states "ERS", "Read", "PGMdisturb" and "Read". Please refer to Figure 12A , the first bit line current before and after “PGM disturb” is the same, as shown by arrow W6.

[0132] Figure 12B The simulation results of the programming operation of the memory cell CC in the "1" state are shown, for example, the bias voltage (V) applied to the first bit line BL1, the bias voltage (V) applied to the portion 1122 of the first gate structure 112, the bias voltage (V) applied to the portion 1142 of the second gate structure 114, and the first bit line current (microamperes) are shown as a function of time (microseconds) under the operating states "PGM", "Read", "PGMdisturb" and "Read". Please refer to Figure 12B , the first bit line current before and after “PGM disturb” is the same, as shown by arrow W7.

[0133] Figure 12C The simulation results of the programming operation of the memory cell CD in the "0" state are shown, for example, the bias voltage (V) applied to the second bit line BL2, the bias voltage (V) applied to the portion 1122 of the first gate structure 112, the bias voltage (V) applied to the portion 1142 of the second gate structure 114, and the second bit line current (μA) are shown as a function of time (μs) under the operating states "ERS", "Read", "PGMdisturb" and "Read". Please refer to Figure 12C , the second bit line current before “PGM disturb” and after “Read” is the same, as shown by arrow W8.

[0134] Figure 12D The simulation results of the programming operation of the memory cell CD in the "1" state are shown, for example, the bias voltage (V) applied to the second bit line BL2, the bias voltage (V) applied to the portion 1122 of the first gate structure 112, the bias voltage (V) applied to the portion 1142 of the second gate structure 114, and the second bit line current (μA) are shown as a function of time (μs) under the operating states "PGM", "Read", "PGMdisturb" and "Read". Please refer to Figure 12D , the second bit line current before “PGM disturb” and after “Read” is the same, as shown by arrow W9.

[0135] Depend on Figures 12A to 12D The simulation results show that by increasing the voltage applied to the unselected portion 1142 of the second gate structure 114 to 3V, programming of the memory cells CC and CD is successfully inhibited regardless of whether they are in the “0” state or the “1” state.

[0136] In one embodiment, the memory structure performs an erase operation, that is, enters a "0" state from a "1" state. When the memory cell CA is selected for the erase operation, a word line bias reset-up step is performed on the gate structure connected to the memory cell CA (e.g., portion 1121 of the first gate structure 112 and portion 1141 of the second gate structure 114), and the memory cells CA and CB are erased simultaneously in a page manner. In order to prevent the unselected memory cells CC and CD from being erased, the word line bias reset-up step is not performed on the gate structure connected to the memory cells CC and CD (e.g., portion 1122 of the first gate structure 112 and portion 1142 of the second gate structure 114), and the bit line current of the memory cells CC and CD needs to be confirmed through simulation experiments, such as Figures 13A to 13D The word line bias reset step is achieved, for example, by temporarily returning the operating voltage to 0V, such as sequentially applying operating voltages of -1.5V, 0V, and -1.5V to portion 1121 of the first gate structure 112, and sequentially applying operating voltages of 1.5V, 0V, and 1.5V to portion 1141 of the second gate structure 114. The above-mentioned operation of not performing the word line bias reset step on the gate structures connected to the memory cells CC and CD (e.g., portion 1122 of the first gate structure 112 and portion 1142 of the second gate structure 114) indicates an interruption state during the erase operation (abbreviated as "ERS") (i.e., the original state is restored after the interruption state), which can be referred to as erase interruption, abbreviated as "ERS disturb". The operating voltage during the "ERS disturb" state can be referred to as shown in Table 3 below.

[0137] [Table 3]

[0138] Operation Mode Erase interrupt (ERS disturb) Portion 1121 (V) of the first gate structure 112 -1.5→0→1.5 Portion 1122 (V) of the first gate structure 112 -1.5 Portion 1141 (V) of the second gate structure 114 1.5→0→1.5 Portion 1142 (V) of the second gate structure 114 1.5 First bit line BL1 (V) 0 Second bit line BL2 (V) 0 Common source line CSL(V) 0

[0139] Figure 13A The simulation results of the erase operation of the memory cell CC in the "0" state are shown, for example, the bias voltage (V) applied to the first bit line BL1, the bias voltage (V) applied to the portion 1122 of the first gate structure 112, the bias voltage (V) applied to the portion 1142 of the second gate structure 114, and the first bit line current (microamperes) are shown as a function of time (microseconds) under the operating states "ERS", "Read", "ERSdisturb" and "Read". Please refer to Figure 13A , the first bit line current before and after “ERS disturb” is the same, as shown by arrow W10.

[0140] Figure 13B The simulation results of the erase operation of the memory cell CC in the "1" state are shown, for example, the bias voltage (V) applied to the first bit line BL1, the bias voltage (V) applied to the portion 1122 of the first gate structure 112, the bias voltage (V) applied to the portion 1142 of the second gate structure 114, and the first bit line current (microamperes) are shown as a function of time (microseconds) under the operating states "PGM", "Read", "ERSdisturb" and "Read". Please refer to Figure 13B , the first bit line current before and after “ERS disturb” is the same, as shown by arrow W11.

[0141] Figure 13C The simulation results of the erase operation of the memory cell CD in the "0" state are shown, for example, the bias voltage (V) applied to the second bit line BL2, the bias voltage (V) applied to the portion 1122 of the first gate structure 112, the bias voltage (V) applied to the portion 1142 of the second gate structure 114, and the second bit line current (microamperes) are shown as a function of time (microseconds) under the operating states "ERS", "Read", "ERSdisturb" and "Read". Please refer to Figure 13C , the second bit line current before and after “ERS disturb” is the same, as shown by arrow W12.

[0142] Figure 13DThe simulation results of the erase operation of the memory cell CD in the "1" state are shown, for example, the bias voltage (V) applied to the second bit line BL2, the bias voltage (V) applied to the portion 1122 of the first gate structure 112, the bias voltage (V) applied to the portion 1142 of the second gate structure 114, and the second bit line current (μA) are shown as a function of time (μs) under the operation states "PGM", "Read", "ERSdisturb" and "Read". Please refer to Figure 13D , the second bit line current before and after “ERS disturb” is the same, as shown by arrow W13.

[0143] Depend on Figures 13A to 13D The simulation results show that by not performing the word line bias reset step on the gate structures connected to the memory cells CC and CD (e.g., portion 1122 of the first gate structure 112 and portion 1142 of the second gate structure 114), the erasure of the memory cells CC and CD is successfully suppressed regardless of whether they are in the "0" state or the "1" state.

[0144] Depend on Figures 11 to 13D It can be seen from the simulation results that the memory structure according to an embodiment of the present invention is feasible in all operations of “Read”, “PGM” or “ERS”.

[0145] According to one embodiment of the present invention, a memory structure includes a substrate, a first gate structure, a second gate structure, and a plurality of channel bodies. The substrate has an upper surface. The first gate structure and the second gate structure are disposed on the substrate, separated from each other in a first direction and extending along a second direction. The channel bodies are separated from each other in a second direction and a third direction and pass through the first gate structure and the second gate structure along the first direction, respectively. The first, second, and third directions intersect with each other, the upper surface is parallel to the first and second directions, and a normal to the upper surface is parallel to the third direction. A first length of the first gate structure in the first direction is different from a second length of the second gate structure in the first direction. Compared to a comparative example in which the first length of the first gate structure in the first direction and the second length of the second gate structure in the first direction are the same, the first gate structure or the second gate structure of the present invention can have a smaller length in the first direction. Thus, the first gate structure or the second gate structure can occupy a smaller volume, thereby reducing the size of the memory structure and meeting miniaturization requirements. Furthermore, the memory structure of the present invention can also have a lower operating voltage, thereby reducing the energy consumption of operating the memory structure. Furthermore, the memory structure of the present invention is a memory structure based on the operation mechanism of thyristors and still has the advantages of high scalability and fast operation speed.

[0146] In summary, although the present invention has been disclosed above with reference to the embodiments, these are not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations can be made without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A memory structure comprising: a substrate having an upper surface; A first gate structure and a second gate structure are disposed on the substrate, separated from each other in a first direction and respectively extend along a second direction; as well as A plurality of channel bodies are separated from each other in the second direction and a third direction and pass through the first gate structure and the second gate structure respectively along the first direction. The first direction, the second direction, and the third direction intersect with each other, the upper surface is parallel to the first direction and the second direction, and the normal direction of the upper surface is parallel to the third direction. A first length of the first gate structure in the first direction and a second length of the second gate structure in the first direction are different from each other.

2. The memory structure according to claim 1 , further comprising: a plurality of pads, the pads being stacked along the third direction and separated from each other along the third direction, each of the pads being connected to a corresponding first end of the channel bodies; a first side plug extending along the third direction and connecting the pads; as well as A plurality of second side plugs extend respectively along the third direction and are separated from each other in the second direction. Each of the second side plugs is connected to a corresponding second end of the channel bodies, the second end being opposite to the first end, wherein the first gate structure is closer to the first end than the second gate structure. The memory structure according to claim 2 , wherein the first length is smaller than the second length. The memory structure according to claim 2 , wherein the second length is smaller than the first length.

5. The memory structure according to claim 2 , wherein the first gate structure includes a plurality of parts, the second gate structure includes a plurality of parts, the parts of the first gate structure extend respectively along the second direction and are separated from each other along the third direction, and the parts of the second gate structure extend respectively along the second direction and are separated from each other along the third direction. 6 . The memory structure according to claim 5 , wherein the lengths of the portions of the first gate structure in the second direction are different from each other, and the lengths of the portions of the second gate structure in the second direction are different from each other.

7. The memory structure according to claim 5, further comprising: a plurality of first contacts, separated from each other along the second direction, respectively extending along the third direction to electrically contact a plurality of first landing areas on the portions of the first gate structure, the first landing areas forming a stepped structure; as well as A plurality of second contacts are separated from each other along the second direction and extend along the third direction to electrically contact a plurality of second landing areas on the portions of the second gate structure, wherein the second landing areas form another stepped structure.

8. The memory structure according to claim 2, wherein the first gate structure is a continuous structure in the third direction, and the second gate structure includes a plurality of parts, wherein the parts of the second gate structure extend along the second direction and are separated from each other along the third direction. 9 . The memory structure according to claim 8 , wherein the first gate structure corresponds to all of the channel bodies, and the portions of the second gate structure respectively correspond to portions of the channel bodies.

10. The memory structure according to claim 8 further includes a plurality of contacts, which are separated from each other along the second direction and extend along the third direction to electrically contact a plurality of landing areas on these parts of the second gate structure, and the landing areas form a stepped structure.

11. The memory structure according to claim 2, wherein the first gate structure comprises a plurality of portions, the portions of the first gate structure respectively extending along the second direction and separated from each other along the third direction, and the second gate structure is a continuous structure in the third direction. 12 . The memory structure according to claim 11 , wherein the portions of the first gate structure respectively correspond to portions of the channel bodies, and the second gate structure corresponds to all of the channel bodies.

13. The memory structure according to claim 12 further includes a plurality of contacts, which are separated from each other along the second direction and extend along the third direction to electrically contact a plurality of landing areas on these parts of the first gate structure, and the landing areas form a stepped structure. 14 . The memory structure according to claim 1 , further comprising a plurality of dielectric films disposed between the first gate structure and the channel bodies and between the second gate structure and the channel bodies. 15 . The memory structure of claim 2 , wherein the first end comprises a first conductivity type dopant, and the second end comprises a second conductivity type dopant, the second conductivity type dopant being different from the first conductivity type dopant.

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