Semiconductor structure and manufacturing method thereof

Abstract

In one embodiment, a method includes forming a stack over a substrate, the stack including channel layers interleaved by sacrificial layers, patterning the stack to form a fin-shaped structure, forming a dummy gate stack across the fin-shaped structure, recessing source / drain regions of the fin-shaped structure, selectively removing the sacrificial layers in the channel regions to release the channel layers as channel members, and forming a dummy gate stack across the dummy gate stack. Depositing a dummy layer in a space between the channel members, selectively and partially recessing the dummy layer to form an internal spacer recess, depositing a first dielectric layer in the internal spacer recess, etching back the first dielectric layer, depositing a second dielectric layer over the first dielectric layer, and forming a second dielectric layer over the second dielectric layer. The method further includes etching the second dielectric layer back to form an internal spacer in the internal spacer recess, forming a source / drain feature over the source / drain region, removing the dummy gate stack and the dummy layer, and forming a gate structure to enclose the channel member. The embodiment of the invention also relates to a semiconductor structure and a manufacturing method thereof.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to semiconductor structures and methods of manufacturing the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous one. Over the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. However, this scaling down also increases the complexity of processing and manufacturing ICs.

[0003] For example, as integrated circuit (IC) technology moves towards smaller technology nodes, multi-gate metal oxide semiconductor field effect transistors (multi-gate MOSFETs or multi-gate devices) have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short channel effect (SCE). A multi-gate device generally refers to a device having a gate structure or portion thereof disposed above more than one side of a channel region. A gate-all-around (GAA) transistor is an example of a multi-gate device, which has become a popular and promising candidate for high performance and low leakage applications. A GAA transistor has a gate structure that wraps around the channel region to provide access to the channel region on four sides. The scaling down of the size of the GAA transistor increases the complexity of the semiconductor manufacturing process. As the minimum component size decreases, additional problems arise that should be addressed. Summary of the Invention

[0004] An embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, comprising: forming a stack above a substrate, the stack comprising a channel layer interleaved by a sacrificial layer; patterning the stack to form a fin-shaped structure; forming a dummy gate stack above a channel region of the fin-shaped structure; depositing a gate spacer layer above the dummy gate stack; recessing a source / drain region of the fin-shaped structure after depositing the gate spacer layer; selectively removing the sacrificial layer in the channel region to release the channel layer as a channel member; depositing a dummy layer in a space between the channel members; and recessing the dummy gate stack. The dummy layer is selectively and partially recessed to form an inner spacer recess; a first dielectric layer is deposited in the inner spacer recess; the first dielectric layer is etched back; after etching back the first dielectric layer, a second dielectric layer is deposited over the first dielectric layer; the second dielectric layer is etched back to form an inner spacer in the inner spacer recess, the inner spacer comprising at least the first dielectric layer and the second dielectric layer; a source / drain component is formed over the source / drain region; the dummy gate stack is removed; the dummy layer is removed; and a gate structure is formed to wrap each of the channel components.

[0005] Another embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, comprising: forming a fin-shaped structure protruding from a substrate; forming a dummy gate stack across the fin-shaped structure; depositing a gate spacer layer above the dummy gate stack; after depositing the gate spacer layer, recessing an area of ​​the fin-shaped structure to form a trench; forming an internal spacer groove on the sidewall of the fin-shaped structure facing the trench; depositing a first dielectric layer in the internal spacer groove; etching back the first dielectric layer; forming a first epitaxial component in a bottom portion of the trench; after forming the first epitaxial component, depositing a second dielectric layer on the first dielectric layer; etching back the second dielectric layer to form an internal spacer in the internal spacer groove; after etching back the second dielectric layer, forming a second epitaxial component in a top portion of the trench; and replacing the dummy gate stack with a metal gate structure, the internal spacer being interposed between the metal gate structure and the second epitaxial component.

[0006] Yet another embodiment of the present disclosure provides a semiconductor structure, comprising:

[0007] a base fin positioned above the substrate;

[0008] a first source / drain feature and a second source / drain feature, the first source / drain feature and the second source / drain feature being located over the substrate fin;

[0009] a plurality of nanostructures extending between the first source / drain feature and the second source / drain feature;

[0010] a gate structure, the gate structure wrapping each of the nanostructures; and

[0011] a plurality of internal spacers interlaced with the nanostructures,

[0012] wherein each of the inner spacers comprises a liner and a bulk dielectric portion surrounded by the liner, and wherein the bulk dielectric portion comprises a first sub-layer and a second sub-layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The present disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are used for illustrative purposes only. In fact, the dimensions of the various components may be increased or decreased as desired for clarity of discussion.

[0014] Figure 1 A flow chart of a method for forming a semiconductor device according to one or more aspects of the present disclosure is shown.

[0015] Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 、 Figure 8 、 Figure 9 、 Figure 10 、 Figure 11 、 Figure 12 、 Figure 13 、 Figure 14 、 Figure 15 、 Figure 16 、 Figure 20 、 Figure 21 、 Figure 22 、 Figure 23 、 Figure 24 、 Figure 25 and Figure 26 According to one or more aspects of the present disclosure, Figure 1 A partial cross-sectional view of a work-in-progress (WIP) structure during the manufacturing process of the method.

[0016] Figure 17A 、 Figure 17B 、 Figure 17C 、 Figure 17D 、 Figure 17E 、 Figure 17F and Figure 17G According to one or more embodiments of the present disclosure, Figure 1 An enlarged cross-sectional view of a region containing an internal spacer during the manufacturing process of the method.

[0017] Figure 18A、 Figure 18B 、 Figure 18C 、 Figure 18D and Figure 18E According to one or more embodiments of the present disclosure, Figure 1 An enlarged cross-sectional view of a region containing an internal spacer during the manufacturing process of the method.

[0018] Figure 19A 、 Figure 19B 、 Figure 19C 、 Figure 19D and Figure 19E According to one or more embodiments of the present disclosure, Figure 1 An enlarged cross-sectional view of a region containing an internal spacer during the manufacturing process of the method.

[0019] Figure 27A 、 Figure 27B 、 Figure 27C and Figure 27D According to one or more embodiments of the present disclosure, Figure 1 An enlarged cross-sectional view of a region containing an inner spacer after a replacement gate process of the method.

[0020] Figure 28A 、 Figure 28B 、 Figure 28C and Figure 28D According to one or more embodiments of the present disclosure, Figure 1 An enlarged cross-sectional view of a region containing an inner spacer after a replacement gate process of the method.

[0021] Figure 29 According to one or more embodiments of the present disclosure, Figure 1 A partial cross-sectional view of a work-in-progress (WIP) structure with different source / drain region widths after a replacement gate process according to the method. DETAILED DESCRIPTION

[0022] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are formed in direct contact, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the embodiments and / or configurations discussed.

[0023] For ease of description, spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0024] Additionally, when "about," "approximately," or the like is used to describe a value or range of values, the term is intended to encompass values ​​within a reasonable range, taking into account variations inherent in manufacturing as understood by one of ordinary skill in the art. For example, based on known manufacturing tolerances associated with manufacturing components having the characteristics associated with the value, the value or range of values ​​encompasses a reasonable range that includes the described value, such as within + / - 10% of the described value. For example, a material layer having a thickness of "about 5 nm" may encompass a range of sizes from 4.25 nm to 5.75 nm, where manufacturing tolerances associated with depositing material layers are known to one of ordinary skill in the art to be + / - 15%.

[0025] The present disclosure generally relates to GAA transistors and methods for manufacturing the same. GAA transistors can be manufactured using a replacement gate process, in which a dummy gate stack is first formed as a placeholder and subsequently replaced with a functional gate structure. In some replacement gate processes, sacrificial material in the nanostructure of the GAA transistor is removed after forming the epitaxial source / drain components. During the removal of the sacrificial material, internal spacers are used to contain an etching process to define the outline of the gate structure and to separate the epitaxial source / drain components from contacting the gate structure. The internal spacers can be formed by first forming an internal spacer recess and then depositing a dielectric material in the internal spacer recess using a conformal deposition process (such as chemical vapor deposition (CVD), atomic layer deposition (ALD), etc.). During conformal deposition, the dielectric material enters the internal spacer recess to form the internal spacer, but may create gaps within the internal spacer and associated depressions on the outer surface of the internal spacer. When the etch selectivity between the internal spacer and the sacrificial material is unsatisfactory, particularly when gaps remain in the internal spacer, the internal spacer can be significantly consumed due to the accelerated etch rate near the gaps. Etch loss of the internal spacers results in thinner-than-expected internal spacer thickness, leading to poor parasitic capacitance performance. In some cases, short circuits may also occur between the gate structure and the epitaxial source / drain components. Embodiments of the present disclosure advantageously perform processes during the formation of the internal spacers to reduce or eliminate gaps that may form within the internal spacers and reduce or eliminate recesses in the internal spacers.

[0026] This process is also called "de-gap process"

[0027] Various aspects of the present disclosure will now be described in more detail with reference to the accompanying drawings. In this regard, Figure 1 1 is a flow chart illustrating a method 100 for forming a semiconductor structure from a work-in-progress (WIP) structure according to an embodiment of the present disclosure. The method 100 is merely an example and is not intended to limit the present disclosure to what is explicitly shown in the method 100. Additional steps may be provided before, during, and after the method 100, and some of the steps described may be replaced, eliminated, or rearranged for additional embodiments of the method. For simplicity, not all steps are described in detail. Figures 2 to 29 Describing method 100, Figures 2 to 29 is based on Figure 1 FIG1 is a partial cross-sectional view of a WIP structure 200 at different manufacturing stages of an embodiment of the method 100 in FIG1. ​​Because the WIP structure 200 will be manufactured into a semiconductor structure or a semiconductor device, the WIP structure 200 may be referred to herein as a semiconductor structure 200 or a semiconductor device 200 depending on the context. For the avoidance of doubt, Figures 2 to 29 The X, Y and Z directions are perpendicular to each other. In the present disclosure, unless otherwise explicitly described, the same reference numerals represent the same components or steps.

[0028] refer to Figure 1 and Figure 2 , the method 100 includes block 102, where a stack 204 of alternating semiconductor layers is formed over the WIP structure 200. Figure 2 As shown, WIP structure 200 includes substrate 202. In some embodiments, substrate 202 may be a semiconductor substrate, such as a silicon (Si) substrate. Depending on design requirements known in the art, substrate 202 may include various doping configurations. In embodiments where the semiconductor device is p-type, an n-type doping profile (i.e., an n-type well or n-well) may be formed on substrate 202. In some embodiments, the n-type dopant used to form the n-type well may include phosphorus (P), arsenic (As), or antimony (Sb). In embodiments where the semiconductor device is n-type, a p-type doping profile (i.e., a p-type well or p-well) may be formed on substrate 202. In some embodiments, the p-type dopant used to form the p-type well may include boron (B) or gallium (Ga). Suitable doping may include ion implantation and / or diffusion processes of the dopant. Substrate 202 may also include other semiconductors, such as germanium (Ge), silicon carbide (SiC), silicon germanium (SiGe), germanium tin (GeSn), or diamond. Alternatively, substrate 202 may include a compound semiconductor and / or an alloy semiconductor. Additionally, the substrate 202 may optionally include an epitaxial layer (epi layer), may be strained for performance enhancement, may include a silicon-on-insulator (SOI) or germanium-on-insulator (GeOI) structure, and / or may have other suitable enhancement features.

[0029] In some embodiments, the stack 204 above the substrate 202 includes channel layers 208 of a first semiconductor composition interleaved with sacrificial layers 206 of a second semiconductor composition. Alternatively, the sacrificial layers 206 may be interleaved with the channel layers 208. The first semiconductor composition and the second semiconductor composition may be different. In some embodiments, the sacrificial layers 206 include silicon germanium (SiGe) or germanium tin (GeSn), and the channel layers 208 include silicon (Si). It should be noted that, as Figure 2 As shown, three (3) layers of sacrificial layers 206 and three (3) layers of channel layers 208 are arranged alternately. This is for illustrative purposes only and is not intended to limit the specific contents recited in the claims. It is understood that any number of epitaxial layers can be formed in the stack 204. The number of layers depends on the desired number of channel components for the semiconductor device 200. In some embodiments, the number of channel layers 208 is between 2 and 10.

[0030] The sacrificial layer 206 and the channel layer 208 in the stack 204 may be deposited using a molecular beam epitaxy (MBE) process, a vapor phase epitaxy (VPE) process, and / or other suitable epitaxial growth processes. As described above, in at least some examples, the sacrificial layer 206 comprises an epitaxially grown silicon germanium (SiGe) layer, and the channel layer 208 comprises an epitaxially grown silicon (Si) layer. In some embodiments, the sacrificial layer 206 and the channel layer 208 are substantially free of dopants (i.e., have a dopant density of from about 0 atoms / cm 3 to about 1x10 17 atoms / cm 3 extrinsic dopant concentration), wherein, for example, no intentional doping is performed during the epitaxial growth process of the stack 204.

[0031] refer to Figure 1 and Figure 3 , method 100 includes box 104, in which a fin structure 212 is formed from the stack 204 and the substrate 202. In order to pattern the stack 204, a hard mask layer can be deposited over the stack 204 to form an etch mask. The hard mask layer can be a single layer or a multilayer. For example, the hard mask layer can include a pad oxide layer and a pad nitride layer disposed over the pad oxide layer. The fin structure 212 can be patterned from the stack 204 and the substrate 202 using a photolithography process and an etching process. The photolithography process can include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable photolithography techniques and / or combinations thereof. In some embodiments, the etching process can include dry etching (e.g., RIE etching), wet etching, and / or other etching methods. As Figure 3As shown, the etching process at box 104 forms a trench that extends vertically through the stack 204 and a portion of the substrate 202. The trench defines a fin structure 212. In some embodiments, a double patterning or multiple patterning process can be used to define the fin structure, the pitch of the fin structure being, for example, smaller than that obtainable using a single direct photolithography process. For example, in one embodiment, a material layer is formed above the substrate and the material layer is patterned using a photolithography process. Spacers are formed next to the patterned material layer using a self-aligned process. The material layer is then removed, and the remaining spacers or mandrels can then be used to pattern the fin structure 212 by etching portions of the stack 204 and the substrate 202. As shown Figure 3 As shown, the fin structure 212 including the sacrificial layer 206 and the channel layer 208 extends vertically along the Z direction and longitudinally along the X direction. Figure 3 As shown, the fin structure 212 includes a base fin structure 212B patterned from the substrate 202 and a patterned stack 204 disposed directly over the base fin structure 212B.

[0032] refer to Figure 1 and Figure 3 , the method 100 includes block 106 , in which an isolation feature 214 is formed around the base fin structure 212B of the fin-shaped structure 212 . Figure 3 In some embodiments shown, the isolation feature 214 is disposed on the sidewalls of the base fin structure 212B. In some embodiments, the isolation feature 214 can be formed in a trench to isolate the fin structure 212 from an adjacent fin structure. The isolation feature 214 can also be referred to as a shallow trench isolation (STI) feature 214. For example, in some embodiments, a dielectric layer is first deposited over the substrate 202 to fill the trench with the dielectric layer. In some embodiments, the dielectric layer can include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics, combinations thereof, and / or other suitable materials. In various examples, the dielectric layer can be deposited by a CVD process, a sub-atmospheric CVD (SACVD) process, a flowable CVD process, a spin coating process, and / or other suitable processes. The deposited dielectric material is then thinned and planarized, for example, by a chemical mechanical polishing (CMP) process. The planarized dielectric layer is further recessed or pulled back by a dry etching process, a wet etching process, and / or a combination thereof to form Figure 3 STI features 214 are shown. After recessing, the fin structures 212 are raised above the STI features 214 , while the base fin structures 212B are embedded or buried in the isolation features 214 .

[0033] refer to Figure 1 and Figure 4, method 100 includes block 108, where a semiconductor liner 207 is deposited over the fin structure 212. After forming the isolation features 214, the semiconductor liner 207 can be deposited over the WIP structure 200, including over the isolation features 214, over the top surface of the fin structure 212, and along the sidewalls of the fin structure 212. The semiconductor liner 207 is used to protect the sidewalls of the sacrificial layer 206, as they may be subject to undesirable damage during the manufacturing process. In some embodiments, the semiconductor liner 207 can include silicon (Si). In some implementations, the semiconductor liner 207 can be deposited using PVD, CVD, or atomic layer deposition (ALD).

[0034] refer to Figure 1 、 Figure 5 and Figure 6 , the method 100 includes block 110 where a dummy gate stack 220 is formed over the channel region 212C of the fin structure 212. The dummy gate stack 220 serves as a placeholder to undergo various processes and will be removed and replaced by a functional gate structure. Other processes and configurations are possible. Figure 6 In some embodiments shown, the dummy gate stack 220 is formed above the fin structure 212, and the fin structure 112 can be divided into a channel region 212C below the dummy gate stack 220 and a source / drain region 212SD not located below the dummy gate stack 210. The channel region 212C is adjacent to the source / drain region 212SD. Figure 6 As shown, the channel region 2120C is disposed between the two source / drain regions 212SD along the X direction.

[0035] The formation of the dummy gate stack 220 may include depositing layers in the dummy gate stack 220 and patterning the layers. Figure 5 , a dummy dielectric layer 216, a dummy electrode layer 218, and a gate top hard mask layer 222 can be blanket deposited over the WIP structure 200. The dummy dielectric layer 216 can be formed on the fin structure 212 using a chemical vapor deposition (CVD) process, an ALD process, an oxygen plasma oxidation process, or other suitable process. In the depicted embodiment, the dummy dielectric layer 216 is formed using an oxygen plasma oxidation process, which essentially oxidizes the semiconductor liner 207 to form the dummy dielectric layer 216. In some cases, the dummy dielectric layer 216 can include silicon oxide. Thereafter, a dummy electrode layer 218 can be deposited over the dummy dielectric layer 216 using a CVD process, an ALD process, or other suitable process. In some cases, the dummy electrode layer 218 can include polysilicon. For patterning purposes, a gate top hard mask layer 222 can be deposited on the dummy electrode layer 218 using a CVD process, an ALD process, or other suitable process. As Figure 6As shown, the gate top hard mask layer 222, the dummy electrode layer 218, and the dummy dielectric layer 216 can then be patterned to form a dummy gate stack 220. For example, the patterning process may include a photolithography process (e.g., photolithography or electron beam lithography) and an etching process. The photolithography process may also include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable photolithography techniques and / or combinations thereof. The photolithography process forms a patterned photoresist layer. The patterned photoresist layer is then used as an etching mask in an etching process to pattern the gate top hard mask layer 222, the dummy electrode layer 218, and the dummy dielectric layer 216. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching, and / or other etching methods. In some embodiments, the gate top hard mask layer 222 may include a silicon oxide layer 223 and a silicon nitride layer 224 located above the silicon oxide layer 223. As Figure 6 As shown, the dummy gate stack 220 is patterned such that it is disposed only over the channel region 212C and not over the source / drain regions 212SD.

[0036] refer to Figure 1 and Figure 7 , the method 100 includes block 112, in which a gate spacer layer 226 is deposited over the WIP structure 200 (including over the dummy gate stack 220). In some embodiments, the gate spacer layer 226 is conformally deposited over the WIP structure 200, including over the top surface and sidewalls of the dummy gate stack 220. To facilitate describing a layer having a substantially uniform thickness over various regions, the term "conformal" may be used herein. The gate spacer layer 226 may be a single layer or multiple layers. At least one layer of the gate spacer layer 226 may include silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, or silicon nitride. The gate spacer layer 226 may be deposited over the dummy gate stack 220 using a process such as a CVD process, a sub-atmospheric pressure CVD (SACVD) process, an ALD process, or other suitable process.

[0037] refer to Figure 1 、 Figure 8 and Figure 9, method 100 includes block 114, in which the source / drain region 212SD of the fin structure 212 is anisotropically recessed to form a source / drain trench 228. The anisotropic etching may include dry etching or a suitable etching process that etches the source / drain region 212SD and a portion of the substrate 202. The resulting source / drain trench 228 extends vertically through the depth of the stack 204 and partially into the substrate 202. An example dry etching process for block 114 may employ an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4 and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBr3), an iodine-containing gas, other suitable gases and / or plasmas and / or combinations thereof. As Figure 8 As shown, the source / drain region 212SD of the fin structure 212 is recessed to expose the sidewalls of the sacrificial layer 206 and the channel layer 208. Because the source / drain trench 228 extends below the stack 204 into the substrate 202, the source / drain trench 228 includes a bottom surface and lower sidewalls defined in the substrate 202. Figure 9 , Figure 9 A partial cross-sectional view spanning two adjacent source / drain regions 212SD is included. Figure 9 As shown, a majority of the fin structure 212 is etched away above the source / drain regions 212SD, and the top surface of the base fin structure 212B is exposed in the source / drain regions 212SD. Since the etching rate of the gate spacer layer 226 is slower than that of the fin structure 212, the gate spacer layer 226 in the source / drain regions 212SD rises above the top surface of the base fin structure 212B.

[0038] refer to Figure 1 、 Figure 10 and Figure 11 , the method 100 includes block 116, wherein the plurality of channel layers 208 in the channel region are released as channel members 2080. Depending on the design, the channel members 2080 may take the form of nanowires, nanosheets, or other nanostructures. After forming the source / drain trenches 228, the sacrificial layers 206 interleaved with the channel layers 208 in the channel region 212C are selectively removed. The selective removal of the sacrificial layers 206 releases the channel layers 208 (e.g., Figure 8 shown), to form Figure 10The channel members 2080 are shown. The selective removal of the sacrificial layer 206 forms spaces between and around adjacent channel members 2080. The selective removal of the sacrificial layer 206 can be achieved by selective dry etching, selective wet etching, or other selective etching processes. An example selective dry etching process can include using one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. An example selective wet etching process can include APM etching (e.g., an ammonium hydroxide-hydrogen peroxide-water mixture). Figure 11 , Figure 11 A partial cross-sectional view spanning two adjacent source / drain regions 212SD is included. Figure 11 As shown, at block 116 , the base fin structure 212B in the source / drain region 212SD is substantially unetched.

[0039] refer to Figure 1 、 Figure 12 and Figure 13 , the method 100 includes block 118, where a dummy layer 230 is deposited around the channel member 2080 and over the source / drain trenches 228. The dummy layer 230 may include silicon oxide and may be deposited using plasma enhanced chemical vapor deposition (PECVD) or ALD. Figure 12 As shown, the dummy layer 230 fills the space between the channel members 2080 and covers the end sidewalls of the channel members 2080. In addition, the dummy layer 230 is in direct contact with the sidewalls of the gate spacer layer 226 and the top surface of the substrate 202. Figure 13 , Figure 13 A partial cross-sectional view spanning two adjacent source / drain regions 212SD is included. Figure 13 As shown, the dummy layer 230 conformally extends over the isolation features 214 , sidewalls of the gate spacer layer 226 , and a top surface of the gate spacer layer 226 .

[0040] refer to Figure 1 and Figure 14 , the method 100 includes block 120, in which an inner spacer recess 232 is formed. The dummy layer 230 is selectively and partially recessed to form the inner spacer recess 232, while the gate spacer layer 226, the dummy gate stack 220, the exposed portion of the substrate 202, and the channel layer 208 are substantially unetched. In embodiments where the channel layer 208 consists essentially of silicon (Si) and the dummy layer 230 is formed of silicon oxide, the selective recessing of the dummy layer 230 may be performed using a selective wet etching process or a selective dry etching process. Example selective dry etching processes may include using carbon tetrafluoride (CF4), nitrogen trifluoride (NF3), hydrogen (H2), or mixtures thereof. Example selective wet etching processes may include using hydrofluoric acid, ammonium fluoride, or mixtures thereof.

[0041] refer to Figure 1 and Figure 15 , method 100 includes block 122, in which a first inner spacer layer 234 is conformally deposited over the exposed surfaces of the source / drain trenches 228 (including the surfaces of the inner spacer recesses 232). The thickness of the first inner spacer layer 234 can be between about 0.5 nm and about 3 nm. In some embodiments, the first inner spacer layer 234 is formed of a material having a high etching contrast relative to the dummy layer 230, which allows the dummy layer 230 to be selectively removed later. In some embodiments, the first inner spacer layer 234 includes a metal oxide, such as polycrystalline aluminum oxide. Since the dummy layer 230 is formed of silicon oxide, the removal of the dummy layer 230 in subsequent steps may include the use of hydrofluoric acid or hydrogen fluoride. It has been observed that crystalline or polycrystalline aluminum oxide undergoes slow etching by hydrofluoric acid. When the first inner spacer layer 234 includes polycrystalline aluminum oxide, atomic layer deposition (ALD) can be used to deposit the first inner spacer layer 234. In some embodiments, an annealing process can be performed after depositing the first inner spacer layer 234 to improve the crystallinity of the first inner spacer layer 234. Since the source / drain features and gate structure have not yet been formed at this point, the annealing process is less likely to cause any undesirable side effects, such as changes in the doping profile or threshold voltage shift. In some cases, the annealing process can include an annealing temperature between about 200° C. and about 500° C. When the first inner spacer layer 234 comprises polycrystalline aluminum oxide, it has a dielectric constant between about 8 and about 9.5.

[0042] In some optional embodiments, the first inner spacer layer 234 includes a polymer material, such as polyethylene (PE) or polypropylene (PP). Although polymer materials may be susceptible to dry etching (involving the use of plasma), they have strong resistance to acids (such as hydrofluoric acid used to etch the dummy layer 230). In these embodiments, in order to deposit the polymer material above the WIP structure 200, the surface of the WIP structure 200 can be subjected to a plasma treatment to increase the number of hydroxyl bonds hanging on the surface. In some cases, the plasma treatment can include the use of oxygen plasma. After the surface plasma treatment, monomers of the polymer material (such as ethylene or propylene) are allowed to contact and react with the dangling bonds in the presence of at least one catalyst. In an exemplary process, a first catalyst is first used to promote the reaction between the monomer and the dangling bond, and then a second catalyst is used to promote the polymerization of the monomer. When the first inner spacer layer 234 includes PE or PP, it has a dielectric constant between about 2.2 and about 2.6.

[0043] In yet other optional embodiments, the first inner spacer layer 234 includes a boron-containing dielectric material, such as boron carbon oxynitride (BCNO) or boron-doped silicon carbon oxynitride (B-SiOCN). In these embodiments, the boron content allows the boron-containing dielectric material to resist the chemistry used to etch the dummy layer 230. In addition, boron carbon oxynitride (BCNO) can have a dielectric constant between about 1.2 and about 3.7, which is beneficial for reducing parasitic capacitance. In some optional embodiments, the first inner spacer layer 234 includes an oxide-based dielectric or a nitride-based dielectric, such as silicon nitride, silicon oxide, silicon oxycarbide, silicon carbonitride, silicon carbon oxynitride, or silicon oxynitride. In some embodiments, the first inner spacer layer 234 can be deposited using chemical vapor deposition (CVD) or atomic layer deposition. Notably, in some optional embodiments, block 122 is optional and the method 100 can skip block 122 and proceed to block 124 without forming the first inner spacer layer 234.

[0044] refer to Figure 1 and Figure 16 , the method 100 includes block 124, in which a second inner spacer layer 236 is deposited over the inner spacer recess 232. The second inner spacer layer 236 may be deposited by a conformal deposition process such as CVD, ALD, or the like. The conformality of the deposition may be between about 50% and about 99%. The second inner spacer layer 236 may include a material such as silicon nitride, silicon oxide, silicon oxycarbide, silicon carbonitride, silicon carbon oxynitride, or silicon oxynitride, but any suitable material may be utilized. In some embodiments, the second inner spacer layer 236 is a low-k dielectric layer, which may be deposited using a precursor such as SiH x Cl y R z (R=CH3,NCH3),SiH x Cl y 、SiH x (R1) y Cl x (R2) z (R1=CH, R2=NCH3), C x H y 、N x / O y / H z, and is deposited at a temperature between about 23° C. and about 700° C. In the deposited state, the second inner spacer layer 236 may include an elemental composition wherein, by atomic ratio, C is 5%-20%, N is 10%-30%, O is 20%-50%, and Si is 30%-50%. The second inner spacer layer 236 may be a low-k dielectric layer having a k value (dielectric constant) of from about 3.0 to about 7.0. The composition of the second inner spacer layer 236 is selected to be different from that of the first inner spacer layer 234. Typically, when the first inner spacer layer 234 comprises polycrystalline aluminum oxide, the dielectric constant of the second inner spacer layer 236 is less than the dielectric constant of the first inner spacer layer 234; however, when the first inner spacer layer 234 comprises boron carbon oxynitride, PE, PP, or other polymer materials, the dielectric constant of the second inner spacer layer 236 is greater than the dielectric constant of the first inner spacer layer 234; when the first inner spacer layer 234 comprises boron-doped silicon carbon oxynitride, the dielectric constant of the second inner spacer layer 236 can be substantially similar to the dielectric constant of the first inner spacer layer 234. Depending on the composition, the density of the second inner spacer layer 236 can be from about 2 g / cm 3 To approximately 7g / cm 3 For example, in some embodiments, such as when the material is silicon oxycarbonitride, in the deposited state, the second inner spacer layer 236 may have a dielectric constant between about 4.9 and 5.4, and may have a dielectric constant at about 2.5 g / cm 3 and about 2.7g / cm 3 Furthermore, the second inner spacer layer 236 may include trace amounts of precursor materials (in addition to the main material), such as Cl and / or H.

[0045] exist Figure 17A , according to some embodiments, during the conformal deposition process of the second inner spacer layer 236 is shown. Figure 16 2080 . The deposition process of the second inner spacer layer 236 can result in the formation of a lateral or horizontal gap 236S or bird's beak opening between the upper portion 236U of the second inner spacer layer 236 and the lower portion 236L of the second inner spacer layer 236, and having gap terminations corresponding to the sides 236I of the second inner spacer layer 236. The upper portion 236U of the second inner spacer layer 236 is produced by the conformal deposition of the dielectric material on the exposed bottom surface of the corresponding upper channel member 2080. The lower portion 236L of the second inner spacer layer 236 is produced by the conformal deposition of the dielectric material on the exposed upper surface of the corresponding lower channel member 2080. The side 236I of the second inner spacer layer 236 is produced by the conformal deposition of the dielectric material on the sidewalls of the inner spacer recess 232. As shown in FIG. Figure 17AAs shown, the slot 236S has a beaked opening.

[0046] like Figure 17B As shown, as conformal deposition continues, the thickness of the upper portion 236U and the lower portion 236L of the second inner spacer layer 236 continues to grow, and eventually closes the beak-shaped opening and seals the gap 236S. In some embodiments, the lateral length Ls of the gap 236S can be between 25% and 75% of the lateral thickness L0 of the first inner spacer layer 234 and the second inner spacer layer 236, such as about 5 nm to about 6 nm; the thickness L1 (as the additional thickness of the first inner spacer layer 234 and the second inner spacer layer 236 covering the sidewalls of the channel member 2080) can be in the range from about 4 nm to about 6 nm; the depth Ld of the concave profile of the sidewall of the second inner spacer layer 236 can be between about 1 nm and about 2 nm; and the lateral distance Lt between the gap 236S and the apex of the concave (also the thickness of the second inner spacer layer 236 that seals the gap 236S) can be between about 0.5 nm and about 1 nm.

[0047] refer to Figure 1 and Figure 17C , method 100 includes block 126, wherein the second inner spacer layer 236 is etched back in a first etch-back process (also referred to as a first trimming process). In some embodiments, the first etch-back process at block 126 may include a dry etching process, such as a plasma-assisted reactive ion etching (RIE) process. Example dry etching processes may include using boron trichloride (BCl3), chlorine (Cl2), hydrogen chloride (HCl), methane (CH4), nitrogen trifluoride (NF3), carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), nitrogen (N2), or a combination thereof. In some embodiments, the dry etching process is anisotropic to some extent. In the illustrated embodiment, the second inner spacer layer 236 is etched back to expose the first inner spacer layer 234. Optionally, the second inner spacer layer 236 and the first inner spacer layer 234 are etched back to expose the sidewalls of the channel member 2080. The first etch-back process opens the gap 236S. The lateral length Ls of the gap 236S is reduced to about 0.2nm to about 1.2nm. At the end of frame 126, the recessed second inner spacer layer 236 has sidewalls 236W that face somewhat laterally outward. The sidewalls 236W can resemble a V-shape with an opening on one side.

[0048] In some embodiments, at the end of block 126, method 100 may optionally include a cleaning process to clean the surface of WIP structure 200. The cleaning process may include dry cleaning, wet cleaning, or a combination thereof. In some examples, wet cleaning may include using deionized (DI) water, a mixture of ammonium hydroxide and hydrogen peroxide, a mixture of DI water, hydrochloric acid and hydrogen peroxide, SPM (sulfuric acid peroxide mixture), and / or hydrofluoric acid for oxide removal. The dry cleaning process may include helium (He) and hydrogen (H2) treatment. The cleaning process may further expand the volume of the remaining portion of the opening and gap 236S.

[0049] refer to Figure 1 and Figure 17D , the method 100 includes a frame 128, in which a third inner spacer layer 238 is deposited over the sidewalls 236W of the second inner spacer layer 236. The third inner spacer layer 238 seals the gap 236S. The third inner spacer layer 238 can be deposited by a conformal deposition process (such as CVD, ALD, etc.). The conformality of the deposition can be between about 50% and about 99%. Unlike the deposition of the second inner spacer layer 236, which occurs in a narrow area within the inner spacer groove 232, the deposition of the third inner spacer layer 238 starts from the sidewalls 236W facing laterally outward and grows toward the relatively open space in the source / drain trench 228. Therefore, the third inner spacer layer 238 is substantially seamless. The ranges of thickness L0, thickness L1 and recess depth Ld can be similar to those of reference 1. Figure 17B The lateral length Ls of the slit 236S is significantly reduced, and the lateral distance Lt is significantly increased. The reduced length Ls of the slit 236S and the increased distance Lt between the slit 236S and the apex of the recess protect the slit 236S from accidental exposure during subsequent etching and / or cleaning processes. Otherwise, if the slit 236S is opened during a subsequent etching and / or cleaning process, the etchant chemicals and / or cleaning solvent will flow into the slit 236S, and the etching rate near the slit 236S will be significantly accelerated. As a result, the resulting internal spacer will be much thinner than expected. If the thin internal spacer is broken down during the gate replacement process, the insufficient thickness of the internal spacer may result in higher parasitic capacitance and even cause a short circuit between the gate structure and the epitaxial source / drain components. The gate replacement process will be discussed in further detail later with reference to box 134.

[0050] The third inner spacer layer 238 may include a material such as silicon nitride, silicon oxide, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride, or silicon oxynitride, but any suitable material may be utilized. In some embodiments, the composition of the third inner spacer layer 238 is selected to be different from that of the first inner spacer layer 234. The composition of the third inner spacer layer 238 may be the same as or different from that of the second inner spacer layer 236. When the third inner spacer layer 238 and the second inner spacer layer 236 have different material compositions, the sidewalls 236W as the interface between the third inner spacer layer 238 and the second inner spacer layer 236 may be discernible. When the third inner spacer layer 238 and the second inner spacer layer 236 have the same material composition, the sidewalls 236W as the interface between the third inner spacer layer 238 and the second inner spacer layer 236 may be discernible or not, depending on the specific deposition parameters applied at block 128. In some embodiments, the composition of the third inner spacer layer 238 is selected to be the same as that of the first inner spacer layer 234, but different from that of the second inner spacer layer 236. For example, the third inner spacer layer 238 can have a higher dielectric constant and / or higher etch resistance than the second inner spacer layer 236, which helps resist attack by etchants from the direction of the source / drain trenches 228 in subsequent steps.

[0051] refer to Figure 1 and Figure 17E , method 100 includes block 130, wherein the third inner spacer layer 238 is etched back in a second etch-back process (also referred to as a second trimming process). In some embodiments, the second etch-back process at block 130 may include a dry etching process, such as a plasma-assisted reactive ion etching (RIE) process. Example dry etching processes may include using boron trichloride (BCl3), chlorine (Cl2), hydrogen chloride (HCl), methane (CH4), nitrogen trifluoride (NF3), carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), nitrogen (N2), or a combination thereof. In some embodiments, the dry etching process is anisotropic to some extent. If, after the first etch-back process, the first inner spacer layer 234 has not yet been etched back to expose the sidewalls of the channel member 2080, then during the second etch-back process, the first inner spacer layer 234 will also be etched back together with the third inner spacer layer 238 to expose the sidewalls of the channel member 2080.

[0052] The remaining portions of the first inner spacer layer 234, the second inner spacer layer 236, and the third inner spacer layer 238 collectively define an inner spacer 242. The inner spacer 242 can be considered to have the first inner spacer layer 234 (also referred to as the liner 234) as a liner, and the second inner spacer layer 236 and the third inner spacer layer 238 as a bulk dielectric portion 240 surrounded by the liner 234. The bulk dielectric portion 240 includes the second inner spacer layer 236 (also referred to as the first sub-layer 236) as a first sub-layer and the third inner spacer layer 238 (also referred to as the second sub-layer 238) as a second sub-layer, which is surrounded by (embedded in) the first sub-layer 236. Depending on the material composition of the second inner spacer layer 236 and the third inner spacer layer 238 and their respective deposition methods, sidewalls 236W at the interface between them may or may not be discernible. In some examples, if the inner spacer layers 236 and 238 have the same material composition, the bulk dielectric portion 240 is considered to have a single dielectric material. In further examples, the liner 234 also has the same material composition, and the entire inner spacer 242 is considered to have a single dielectric material. In the depicted embodiment, the inner spacer 242 has a hat-shaped profile that includes a dome-shaped portion vertically stacked between two adjacent channel members 2080 and an edge-shaped portion (primarily the liner 234) partially disposed vertically on the sidewalls of the channel members 2080.

[0053] Still refer to Figure 17E , gap 236S is defined in the second inner spacer layer 236, but is laterally covered (or sealed) by the third inner spacer layer 238. In some embodiments, the thickness L0 of the inner spacer 242 is reduced to about 1 nm to about 10 nm; the length Ls of the gap 236S is reduced to about 0.2 nm to about 1.2 nm; the recess depth Ld is reduced to between about 0.01 nm and about 1 nm; and the lateral distance Lt between the gap 236S and the apex of the recess (also the thickness of the third inner spacer layer 238 that seals the gap 236S) is expanded to between 1 nm and about 5 nm. The now shallower recess depth Ld reduces the amount of etchant chemicals and / or cleaning solvents that accumulate in the recess during subsequent etching and / or cleaning processes; the now thicker lateral distance Lt also effectively prevents the gap 236S from accidentally opening during subsequent etching and / or cleaning processes.

[0054] In some embodiments, at the end of block 130, method 100 may optionally include a cleaning process to clean the surface of WIP structure 200. The cleaning process may include dry cleaning, wet cleaning, or a combination thereof. In some examples, wet cleaning may include using deionized (DI) water, a mixture of ammonium hydroxide and hydrogen peroxide, a mixture of DI water, hydrochloric acid and hydrogen peroxide, SPM (sulfuric acid peroxide mixture), and / or hydrofluoric acid for oxide removal. The dry cleaning process may include helium (He) and hydrogen (H2) treatments.

[0055] Now refer to Figure 17F and Figure 17G , Figure 17F and Figure 17G The region 300 is shown after forming source / drain features 250 in the source / drain trenches 228. The formation of the source / drain features 250 will be explained in further detail later with reference to box 132. Figure 17F and Figure 17G Each of the electrodes 240 and 241 shows a void 246 trapped between the inner spacer 242 and the source / drain feature 250 due to the recessed profile. Figure 17F , the sidewalls of the source / drain features 250 in the gap 246 have a convex profile, curving toward the third inner spacer layer 238. Alternatively, as Figure 17G As shown, the sidewalls of the source / drain features 250 in the void 246 can have a concave profile, curving away from the third inner spacer layer 238. This variation depends on the growth rate of the source / drain features 250 during their formation, and in particular, on the speed at which the portions of the source / drain features 250 grown from the sidewalls of two adjacent channel members 2080 merge. As discussed above, the recess depth Ld has been reduced to a range of about 0.01 nm to about 1 nm, and the size of the void 246 is approximately the same scale. In other words, by 17A to 17E In the "de-gap" process shown, the size of the gap 246 is significantly reduced.

[0056] 18A to 18E An optional "de-gap" process is shown in FIG. Figure 18A and Figure 17A In a substantially similar manner, the deposition process of the second inner spacer layer 236 results in the formation of a lateral or horizontal gap 236S or bird's beak opening between the upper portion 236U of the second inner spacer layer 236 and the lower portion 236L of the second inner spacer layer 236, with gap terminations corresponding to the sides 236I of the second inner spacer layer 236. However, the deposition of the second inner spacer layer 236 Figure 18A This is before closing the beak-shaped opening, and the method 100 proceeds to block 126 to etch back the second inner spacer layer 236 in a first etch-back process (also referred to as a first trim process), as shown. Figure 18B As shown. The first etch back process opens the bird's beak opening to form sidewalls 236W that face laterally outward to a certain extent. The method 100 may optionally perform a cleaning process to clean the surface of the WIP structure 200. Subsequently, the method 100 proceeds to block 128 to deposit a third inner spacer layer 238. Since the opening of the bird's beak reduces the gap 236S, as shown Figure 18C As shown, no gaps remain in the second inner spacer layer 236 and the third inner spacer layer 238. The method 100 then proceeds to block 130 to etch back the third inner spacer layer 238 in a second etch back process (also referred to as a second trimming process), as shown in FIG. Figure 18D As shown. If the first inner spacer layer 234 has not been etched back to expose the sidewalls of the channel member 2080 after the first etch back process, the first inner spacer layer 234 will also be etched back together with the third inner spacer layer 238 during the second etch back process to expose the sidewalls of the channel member 2080. Thereafter, the method 100 may optionally perform a cleaning process to clean the surface of the WIP structure 200. At the end of block 130, the remaining portions of the first inner spacer layer 234, the second inner spacer layer 236, and the third inner spacer layer 238 together define the inner spacer 242. Figure 18D In the depicted embodiment shown, the inner spacer 242 has a hat-shaped profile including a dome-shaped portion vertically stacked between two adjacent channel members 2080 and an edge-shaped portion partially disposed vertically on the sidewalls of the channel member 2080. In some embodiments, the sidewalls of the inner spacer 242 have a concave profile with a concave depth ranging from about 0.01 nm to about 1 nm. Figure 18E Further shown is the region 300 after forming source / drain features 250 in the source / drain trenches 228. The formation of the source / drain features 250 will be explained in further detail later with reference to box 132. Figure 17F or Figure 17G One difference compared to the embodiment depicted in Figure 18E In the embodiment, the inner spacer 242 is seamless, and no voids are trapped between the inner spacer 242 and the source / drain features 250 due to the early enlargement of the aperture of the bird's beak opening.

[0057] Figures 19A to 19E An optional "de-gap" process is shown in FIG. Figure 19A and Figure 17BIn a substantially similar manner, as conformal deposition continues, the thickness of the upper portion 236U and the lower portion 236L of the second inner spacer layer 236 continues to grow, and eventually closes the beak-shaped opening and seals the gap 236S. The method 100 proceeds to block 126 to etch back the second inner spacer layer 236 in a first etch-back process (also referred to as a first trimming process), as shown in FIG. Figure 19B As shown. The first etch-back process shortens the length of the gap 236S and creates an outward-facing sidewall 236W. Thereafter, the method 100 may optionally perform a cleaning process to clean the surface of the WIP structure 200. Subsequently, a third inner spacer layer 238 is formed. Figure 17D or Figure 18C Unlike the depicted embodiment, the third inner spacer layer 238 may be formed after forming the bottom epitaxial feature of the source / drain feature 250 in the bottom of the source / drain trench 228. The formation of the bottom epitaxial feature of the source / drain feature 250 will be explained in further detail later with reference to block 132. The third inner spacer layer 238 covers the gap 236S and also captures the void 236V between the second inner spacer layer 236 and the third inner spacer layer 238, as shown in FIG. Figure 19C Then, the method 100 proceeds to block 130 to etch back the third inner spacer layer 238 in a second etch back process (also referred to as a second trimming process), as shown. Figure 19D As shown. If the first inner spacer layer 234 has not been etched back to expose the sidewalls of the channel member 2080 after the first etch back process, the first inner spacer layer 234 will also be etched back together with the third inner spacer layer 238 during the second etch back process to expose the sidewalls of the channel member 2080. Thereafter, the method 100 may optionally perform a cleaning process to clean the surface of the WIP structure 200. At the end of block 130, the remaining portions of the first inner spacer layer 234, the second inner spacer layer 236, and the third inner spacer layer 238 together define the inner spacer 242. Figure 19D In the depicted embodiment shown, the inner spacer 242 has a hat-shaped profile including a dome-shaped portion vertically stacked between two adjacent channel members 2080 and an edge-shaped portion partially disposed vertically on the sidewalls of the channel member 2080. In some embodiments, the sidewalls of the inner spacer 242 have a concave profile with a concave depth ranging from about 0.01 nm to about 1 nm. Figure 19E Further shown is a region 300 after forming the main epitaxial features of the source / drain features 250 in the source / drain trenches 228. The formation of the main epitaxial features of the source / drain features 250 will be explained in further detail later with reference to box 132. Figure 17F Compared to the depicted embodiment, one difference is that in Figure 19E, the inner spacer 242 includes a slit 236S having a reduced length and a void 236V adjacent to the slit 236S, while no void exists between the inner spacer 242 and the source / drain feature 250. Since the third inner spacer layer 238 is formed after portions of the source / drain feature 250 have been formed, the third inner spacer layer 238 avoids being subjected to some etching and cleaning processes associated with the formation of the source / drain feature 250, and thus the entire inner spacer 242 has a lower risk of being etched through even though the slit 236S and the void 236V exist therein.

[0058] refer to Figure 1 、 Figure 20 and Figure 21 , method 100 includes block 132, wherein at the end of block 130, a Figure 17E 、 Figure 18D or Figure 19D After the internal spacers 242 are shown, source / drain features 250 are formed over the source / drain regions 212SD. Although not explicitly shown, before forming any epitaxial layers, method 100 may include a cleaning process for cleaning the surface of the WIP structure 200. The cleaning process may include dry cleaning, wet cleaning, or a combination thereof. In some examples, wet cleaning may include using deionized (DI) water, a mixture of ammonium hydroxide and hydrogen peroxide, DI water, a mixture of hydrochloric acid and hydrogen peroxide, SPM (sulfuric acid peroxide mixture), and / or hydrofluoric acid for oxide removal. The dry cleaning process may include helium (He) and hydrogen (H2) treatment. The hydrogen treatment may convert the silicon on the surface into silane (SiH4), which may be extracted and removed.

[0059] refer to Figure 20. In some embodiments, the source / drain feature 250 includes a bottom epitaxial feature 252 and a main epitaxial feature 254 located above the bottom epitaxial feature 252. The source / drain feature 250 can be n-type or p-type. When the source / drain feature 250 is n-type, the bottom epitaxial feature 252 can include undoped silicon (Si) or undoped silicon germanium (SiGe), and the main epitaxial feature 254 can include silicon (Si) and an n-type dopant, such as phosphorus (P), arsenic (As), antimony (Sb), or a combination thereof. When the source / drain feature 250 is p-type, the bottom epitaxial feature 252 can include undoped silicon (Si) or undoped silicon germanium (SiGe), and the main epitaxial feature 254 can include silicon germanium (SiGe) and a p-type dopant, such as boron (B), boron difluoride (BF2), or a combination thereof. As used herein, an undoped semiconductor material is considered undoped when it is not intentionally doped. In some optional embodiments, the bottom epitaxial feature 252 may include an anti-dopant to reduce leakage into the bulk substrate 202. For example, the bottom epitaxial feature 252 in the n-type source / drain feature 250 may include a p-type dopant, such as boron (B). For another example, the bottom epitaxial feature 252 in the p-type source / drain feature 250 may include an n-type dopant, such as phosphorus (p), arsenic (As), or antimony (Sb). The source / drain feature 250 may be formed using vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), or molecular beam epitaxy (MBE). Doping of the source / drain feature 250 may be achieved by in-situ doping.

[0060] refer to Figure 21 , Figure 21 Includes a partial cross-sectional view across two adjacent source / drain regions 212SD. Figure 21 In some of the depicted embodiments, n-type source / drain features 250N can be adjacent to p-type source / drain features 250P. The n-type source / drain features 250N include a bottom epitaxial feature 252 and an n-type main epitaxial feature 254N. The n-type main epitaxial feature 254N can include silicon (Si) and an n-type dopant, such as phosphorus (P), arsenic (As), or antimony (Sb). The p-type source / drain features 250P include a bottom epitaxial feature 252 and a p-type main epitaxial feature 254P. The p-type main epitaxial feature 254P can include silicon germanium (SiGe) and a p-type dopant, such as boron (B). Each of the n-type source / drain features 250N and the p-type source / drain structure 250P can be in direct contact with a top surface of the base fin structure 212B and sidewalls of the gate spacer layer 226. For ease of illustration and description, the n-type source / drain features 250N and the p-type source / drain features 250 may be collectively referred to as source / drain features 250 (e.g., in FIG. Figure 20 (in Chinese). Figure 21As shown, the etch back at the previous block 130 may not completely remove the sidewall portions 2340 of the first inner spacer layer 234 along the sidewalls of the isolation features 214 .

[0061] At the end of block 132, the Figure 17F 、 Figure 17G 、 Figure 18E or Figure 19E As discussed above, in some embodiments, the formation of the source / drain features 250 can be performed after forming all dielectric layers (the inner spacer layers 234, 236, and 238) in the inner spacer 242; alternatively, in some embodiments, the formation of the bottom epitaxial feature 252 is performed after the formation of the first inner spacer layer 234 and the second inner spacer layer 236, the formation of the third inner spacer layer 238 is performed after the formation of the bottom epitaxial feature 252, and the formation of the main epitaxial feature 254 is performed after the formation of the third inner spacer layer 238.

[0062] refer to Figure 1 and Figures 22 to 26 , the method 100 includes block 134, where the dummy gate stack 220 and the dummy layer 230 are replaced with a gate structure 260 (also referred to as a metal gate structure 260). Operations at block 134 may include depositing a contact etch stop layer (CESL) 256 (e.g., a metal gate structure) over the source / drain features 250. Figure 22 ), an interlayer dielectric layer 258 is deposited over the CESL 256 (as shown in FIG. Figure 22 As shown), remove the dummy gate stack 220 (as shown Figure 23 As shown), remove the dummy layer 230 (as shown Figure 24 and Figure 25 ) and depositing a gate structure 260 to wrap each channel member 2080 (as shown Figure 26 Reference Figure 22CESL 256 is deposited over WIP structure 200, including over source / drain features 250. CESL 256 may include silicon nitride or aluminum nitride. In some embodiments, CESL 256 may be deposited using CVD or atomic layer deposition (ALD). An ILD layer 258 is then deposited over CESL 256. In some embodiments, ILD layer 258 includes a material such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silica glass (BSG), and / or other suitable dielectric materials. ILD layer 258 may be deposited using CVD, flowable CVD (FCVD), spin coating, or other suitable deposition techniques. After depositing ILD layer 258, WIP structure 200 may be planarized using a planarization process to expose dummy gate stack 220. For example, the planarization process may include a chemical mechanical planarization (CMP) process. The exposure of the dummy gate stack 220 allows for removal of the dummy gate stack 220. Removal of the dummy gate stack 220 may include one or more etching processes that are selective to the material of the dummy gate stack 200. For example, removal of the dummy gate stack 220 may be performed using a selective wet etch that is selective to the dummy gate stack 220, a selective dry etch, or a combination thereof.

[0063] After removing the dummy gate stack 220, the dummy layer 230 in the channel region 212C is exposed. A separate etching process may be performed to selectively remove the dummy layer 230 in the channel region 212C. For example, a selective wet etching process or a selective dry etching process may be performed to remove the dummy layer 230. An example selective wet etching process may include using diluted hydrofluoric acid (DHF) or a mixture of hydrofluoric acid (HF) and ammonium fluoride (NH4F). An example selective dry etching process may include using anhydrous hydrogen fluoride (HF) vapor, trifluoromethane (CHF3), nitrogen trifluoride (NF3), hydrogen (H2), ammonia (NH3), carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), or a combination thereof. As described above, the selective etching of the dummy layer 230 etches the first inner spacer layer 234 at a much smaller rate. After selectively removing the dummy layer 230, as Figure 24 and Figure 25 As shown, the channel member 2080 in the channel region 212C is exposed again.

[0064] like Figure 26 As shown, after the channel members 2080 are released, a gate structure 260 is formed to wrap around each channel member 2080 . 27A to 27D It further shows the Figure 17F 、 Figure 17G 、 Figure 18Eand Figure 19E Various embodiments of the region 300 of the intermediate structure after the gate replacement process are depicted in FIG. Figure 26 Not explicitly shown (but 27A to 27D ), the gate structure 260 includes an interface layer 262 that interfaces with the channel member 2080 and the substrate 202 in the channel region 212C, a gate dielectric layer 264 located above the interface layer 262, and a gate electrode layer 266 located above the gate dielectric layer 264. The interface layer 262 may include a dielectric material such as silicon oxide, hafnium silicate, or silicon oxynitride. The interface layer 262 may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. If the interface layer 262 is formed in the oxidation process, the interface layer 262 may be selectively formed on the exposed semiconductor surface but not on the dielectric surface. In other words, the interface layer 262 may not contact the sidewalls of the internal spacer 242 (except for the end portion of the interface layer 262 in the corner region where the channel member 2080 intersects the internal spacer 242).

[0065] The gate dielectric layer 264 may include a high-k dielectric material such as hafnium oxide. Alternatively, the gate dielectric layer 264 may include other high-k dielectric materials such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), combinations thereof, or other suitable materials. The gate dielectric layer 264 may be formed by ALD, physical vapor deposition (PVD), CVD, oxidation, and / or other suitable methods. The gate dielectric layer 264 also covers the sidewalls of the inner spacer 242.

[0066] The gate electrode layer 266 of the gate structure 260 may include a multilayer structure, such as a metal layer having a selected work function to enhance device performance (work function metal layer), a liner layer, a wetting layer, an adhesion layer, a metal alloy, or various combinations of metal silicides. For example, the gate electrode layer 266 may include titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals, or other suitable metal materials, or combinations thereof. In various embodiments, the gate electrode layer 266 may be formed by ALD, PVD, CVD, electron beam evaporation, or other suitable processes. In various embodiments, a CMP process can be performed to remove excess metal, thereby providing a substantially flat top surface of the gate structure 260. The gate structure 260 includes a portion between the channel members 2080 in the channel region 212C. In some embodiments, the gate structure 260 can include a p-type gate structure portion and an n-type gate structure portion. The p-type gate structure portion includes a p-type work function metal layer disposed closer to the channel member 2080. The n-type gate structure portion includes an n-type work function metal layer disposed closer to the channel member 2080.

[0067] refer to 28A to 28D , 28A to 28D Shows the Figure 17F 、 Figure 17G 、 Figure 18E and Figure 19E, assumes that the internal spacer 242 suffers etch loss during the removal of the dummy layer 230. In some embodiments, if the dielectric material selected for the first internal spacer layer 234 exhibits limited etch contrast relative to the dummy layer 230, or the dielectric material selected for the first internal spacer layer 234 is similar or identical to the second internal spacer layer 236, or the formation of the first internal spacer layer 234 is skipped, then the removal of the dummy layer 230 may penetrate the first internal spacer layer 234 and etch into the second internal spacer layer 236. However, due to the "seam removal" process discussed above, the size of the seam 236S has been significantly reduced or even eliminated, which leaves a sufficiently thick internal spacer between the source / drain features 250 and the gate structure 260, even if the internal spacer 242 suffers further etch loss during the gate replacement process. Additionally, the reduced recess depth of the recess profile of the sidewalls of the third inner spacer layer 238 also helps to reduce and eliminate the voids trapped between the sidewalls of the third inner spacer layer 238 and the corresponding source / drain features 250. It is worth noting that the angle θ formed between the two edges of the recess may vary due to the loading effect during the etch-back of the inner spacer layer 238. Figure 29 As shown, Figure 29 In the WIP structure 200 shown, which has a dense region (having narrower source / drain regions 212SD) and a sparse region (having wider source / drain regions 212SD), more etchant will accumulate in the wider source / drain regions 212SD, resulting in a smaller angle θ. In other words, the angle θ in region 300a located in the dense region can be larger than another angle θ in region 300b located in the sparse region.

[0068] Embodiments of the present disclosure advantageously include a "de-gap process" during the formation of the internal spacers. By reducing or eliminating gaps within the internal spacers, this process prevents accelerated etch rates near the gaps, thereby maintaining sufficient thickness of the internal spacers. This reduces the risk of gate protrusion and avoids short circuits between the gate structure and the epitaxial source / drain components. Due to the sufficient thickness of the internal spacers, parasitic capacitance in the resulting device is also suppressed.

[0069] In one exemplary aspect, the present disclosure is directed to a method comprising forming a stack over a substrate, the stack comprising a channel layer interleaved by sacrificial layers, patterning the stack to form a fin structure, forming a dummy gate stack over a channel region of the fin structure, depositing a gate spacer layer over the dummy gate stack, recessing a source / drain region of the fin structure after depositing the gate spacer layer, selectively removing the sacrificial layer in the channel region to release the channel layer for use as a channel member, depositing a dummy layer in spaces between the channel members, selectively and partially recessing the dummy layer to form inner spacer recesses, depositing a first dielectric layer in the inner spacer recesses, etching back the first dielectric layer, depositing a second dielectric layer over the first dielectric layer after etching back the first dielectric layer, etching back the second dielectric layer to form inner spacers in the inner spacer recesses, the inner spacers comprising at least a first dielectric layer and a second dielectric layer, forming source / drain features over the source / drain region, removing the dummy gate stack, removing the dummy layer, and forming a gate structure to encapsulate each channel member. In some embodiments, the deposition of the first dielectric layer captures gaps within the first dielectric layer. In some embodiments, the etch back of the first dielectric layer opens the gaps. In some embodiments, the deposition of the second dielectric layer seals the gaps. In some embodiments, the deposition of the first dielectric layer forms a beak-shaped opening, and the etch back of the first dielectric layer expands the aperture of the beak-shaped opening. In some embodiments, the deposition of the second dielectric layer completely fills the expanded beak-shaped opening with the second dielectric layer, wherein no gaps are captured. In some embodiments, after the etch back of the second dielectric layer, the sidewalls of the second dielectric layer have a recess, and the formation of the source / drain component captures a void between the sidewalls of the second dielectric layer and the source / drain component. In some embodiments, after the etch back of the second dielectric layer, the sidewalls of the second dielectric layer have a recess, and the formation of the source / drain component completely fills the recess, and no voids are captured between the sidewalls of the second dielectric layer and the source / drain component. In some embodiments, the method further comprises depositing a dielectric liner in the internal spacer recess prior to depositing the first dielectric layer. A first dielectric layer is deposited on the dielectric liner, and the inner spacer includes the dielectric liner, the first dielectric layer, and the second dielectric layer. In some embodiments, forming the source / drain features includes forming a bottom portion of the source / drain features before depositing the second dielectric layer, and forming a top portion of the source / drain features after etching back the second dielectric layer.

[0070] In another exemplary aspect, the present disclosure is directed to a method. The method includes forming a fin structure protruding from a substrate, forming a dummy gate stack across the fin structure, depositing a gate spacer layer over the dummy gate stack, recessing a region of the fin structure to form a trench after depositing the gate spacer layer, forming an inner spacer recess on a sidewall of the fin structure facing the trench, depositing a first dielectric layer in the inner spacer recess, etching back the first dielectric layer, forming a first epitaxial feature in a bottom portion of the trench, depositing a second dielectric layer over the first dielectric layer after forming the first epitaxial feature, etching back the second dielectric layer to form an inner spacer in the inner spacer recess, forming a second epitaxial feature in a top portion of the trench after etching back the second dielectric layer, and replacing the dummy gate stack with a metal gate structure with the inner spacer interposed between the metal gate structure and the second epitaxial feature. In some embodiments, the deposition of the first dielectric layer traps a gap within the first dielectric layer, and the etching back of the first dielectric layer opens the gap. In some embodiments, the deposition of the second dielectric layer traps a void between the first dielectric layer and the second dielectric layer. In some embodiments, the void is connected to the gap. In some embodiments, after the second dielectric layer is etched back, the sidewall of the second dielectric layer has a recess, and the formation of the second epitaxial component completely fills the recess, and no void is trapped between the sidewall of the second dielectric layer and the second epitaxial component. In some embodiments, the method further includes depositing a dielectric liner in the inner spacer groove before depositing the first dielectric layer. The dielectric liner and the first dielectric layer include different material compositions. In some embodiments, the replacement of the dummy gate stack penetrates the dielectric liner so that the metal gate structure contacts the first dielectric layer.

[0071] In yet another exemplary aspect, the present disclosure is directed to a semiconductor structure. The semiconductor structure includes: a base fin located above a substrate; a first source / drain component and a second source / drain component located above the base fin; a nanostructure extending between the first source / drain component and the second source / drain component; a gate structure wrapping each nanostructure; and a plurality of internal spacers interlaced with the nanostructures. Each internal spacer includes a liner and a bulk dielectric portion surrounded by the liner, and the bulk dielectric portion includes a first sublayer and a second sublayer. In some embodiments, the bulk dielectric portion further includes a gap located within the first sublayer and covered by the second sublayer. In some embodiments, the interface between the first sublayer and the second sublayer has a V-shape. In some embodiments, the sidewall of the bulk dielectric portion has a recessed profile, and one of the first source / drain component and the second source / drain component captures a void between the sidewall of the bulk dielectric portion and the one of the first source / drain component and the second source / drain component.

[0072] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use this disclosure as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments described herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor structure, comprising: forming a stack over a substrate, the stack comprising channel layers interleaved by sacrificial layers; patterning the stack to form a fin structure; forming a dummy gate stack above the channel region of the fin structure; depositing a gate spacer layer over the dummy gate stack; After depositing the gate spacer layer, recessing the source / drain regions of the fin structure; selectively removing the sacrificial layer in the channel region to release the channel layer as a channel member; depositing a dummy layer in the space between the channel members; selectively and partially recessing the dummy layer to form an inner spacer recess; depositing a first dielectric layer in the inner spacer recess; etching back the first dielectric layer; After etching back the first dielectric layer, depositing a second dielectric layer over the first dielectric layer; etching back the second dielectric layer to form an inner spacer in the inner spacer groove, the inner spacer comprising at least the first dielectric layer and the second dielectric layer; forming a source / drain feature over the source / drain region; removing the dummy gate stack; removing the dummy layer; as well as A gate structure is formed to wrap around each of the channel components.

2. The method according to claim 1, wherein The depositing of the first dielectric layer captures gaps within the first dielectric layer.

3. The method according to claim 2, wherein: The etching back of the first dielectric layer opens the gap.

4. The method according to claim 3, wherein: The depositing of the second dielectric layer seals the gap.

5. The method according to claim 1, wherein The depositing of the first dielectric layer forms a beak-shaped opening, and the etching back of the first dielectric layer enlarges an aperture of the beak-shaped opening.

6. The method according to claim 5, wherein: The depositing of the second dielectric layer completely fills the enlarged beak-shaped opening with the second dielectric layer, with no gaps trapped therein.

7. The method according to claim 1, wherein After said etching back the second dielectric layer, sidewalls of the second dielectric layer have a recess, and wherein said forming of the source / drain features traps a void between the sidewalls of the second dielectric layer and the source / drain features.

8. The method according to claim 1, wherein After said etching back the second dielectric layer, sidewalls of the second dielectric layer have a recess, and wherein said forming of the source / drain features completely fills the recess without trapping voids between the sidewalls of the second dielectric layer and the source / drain features.

9. A method of manufacturing a semiconductor structure, comprising: forming a fin-shaped structure protruding from a substrate; forming a dummy gate stack across the fin structure; depositing a gate spacer layer over the dummy gate stack; After depositing the gate spacer layer, recessing a region of the fin structure to form a trench; forming an inner spacer recess on a sidewall of the fin structure facing the trench; depositing a first dielectric layer in the inner spacer recess; etching back the first dielectric layer; forming a first epitaxial feature in a bottom portion of the trench; After forming the first epitaxial feature, depositing a second dielectric layer on the first dielectric layer; etching back the second dielectric layer to form an inner spacer in the inner spacer groove; forming a second epitaxial feature in a top portion of the trench after etching back the second dielectric layer; as well as The dummy gate stack is replaced with a metal gate structure, with the inner spacer interposed between the metal gate structure and the second epitaxial feature.

10. A semiconductor structure comprising: basal fin, located above the substrate; a first source / drain feature and a second source / drain feature located above the substrate fin; a plurality of nanostructures extending between the first source / drain feature and the second source / drain feature; a gate structure wrapping each of the nanostructures; as well as a plurality of internal spacers interlaced with the nanostructures, wherein each of the inner spacers comprises a liner and a bulk dielectric portion surrounded by the liner, and wherein the bulk dielectric portion comprises a first sub-layer and a second sub-layer.

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