HEMT device and preparation method thereof
By adopting a single-layer or multi-layer field plate layer design in HEMT devices, a patterned field plate layer is formed and through-holes are used to connect the metal layer, which solves the layout area waste and etching problems in traditional HEMT devices and achieves efficient device preparation and large-scale production.
Patent Information
- Application Number
- CN202510880323.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-27
- Publication Date
- 2025-09-16
AI Technical Summary
The traditional HEMT device has problems such as wasted layout area, too small a through-hole etching process window, and difficulty in achieving large-scale mass production due to the multi-layer source/drain field plate structure.
A single-layer or multi-layer source field plate layer and drain field plate layer design is adopted. By forming a patterned field plate layer on the semiconductor structure and forming through holes in the passivation layer to connect the source and drain metal layers, the etching process is simplified and uniform coverage of the metal layer is ensured.
It solves the problems of layout area waste and too small etching process window, improves the power density (GDPW) of the device and reduces the FOM value, thus achieving large-scale mass production.
Smart Images
Figure CN120659351A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor preparation, and in particular to a HEMT device and a preparation method thereof. Background Art
[0002] In traditional HEMT device design, layout design is usually limited by the multi-layer source / drain field plate structure. First, due to the existence of the multi-layer field plate, the through-holes need to be arranged outside the active area, which leads to a waste of layout area. This area waste directly affects the figure of merit (FOM) of the device, which is specifically manifested as a high value of FOM = Ron * Area. Among them, Ron is the on-resistance of the device, and Area is the area of the device. A higher FOM value means that under the same on-resistance, the device needs to occupy a larger area, which runs counter to the trend of modern electronic devices to pursue miniaturization and high performance. In addition, this area waste also limits the power density (GDPW) of the device. A lower power density means that the device cannot output enough power in the same area, thereby affecting its performance in high-power applications.
[0003] In addition, due to the height difference between the source / drain field plates and the gate / source / drain electrodes, the process window for through-hole etching becomes smaller. Therefore, the etching depth and etching rate need to be controlled very precisely during the etching process to avoid damage to the electrodes or other important structures. This high requirement for process accuracy makes large-scale mass production extremely difficult, especially in the case of multi-layer field plate structures. The problem is more prominent. The multi-layer field plate structure further increases the complexity of etching because each layer needs to be precisely aligned and etched. Any slight deviation may cause device performance degradation or failure. Summary of the Invention
[0004] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a HEMT device and a method for manufacturing the same, which are used to solve the problems in the prior art caused by the multi-layer source field plate and drain field plate structure, such as wasted layout area, too small a through-hole etching process window, and difficulty in achieving large-scale mass production.
[0005] To achieve the above-mentioned and other related objectives, the present invention provides a method for preparing a HEMT device, the method comprising:
[0006] A semiconductor structure is provided, comprising, from bottom to top, a semiconductor substrate, a HEMT device channel layer, a HEMT device barrier layer, and a HEMT device source, drain, and gate formed on the barrier layer, wherein the source, drain, and gate are electrically isolated by an insulating layer;
[0007] forming a first passivation layer covering the upper surface of the semiconductor structure;
[0008] forming a patterned source field plate layer and / or a patterned drain field plate layer on the first passivation layer; wherein the source field plate layer is formed at least above the source electrode, and the drain field plate layer is formed at least above the drain electrode;
[0009] forming a second passivation layer covering the first passivation layer, the source field plate layer and / or the drain field plate layer;
[0010] forming a first through hole and a second through hole; wherein the first through hole penetrates downward from the upper surface of the obtained structure until the source electrode is exposed, and the second through hole penetrates downward from the upper surface of the obtained structure until the drain electrode is exposed;
[0011] A source metal layer and a drain metal layer are formed; wherein the source metal layer at least fills the first through hole to be in contact with the source, and the drain metal layer at least fills the second through hole to be in contact with the drain.
[0012] Optionally, after forming the second passivation layer, the step also includes forming at least one upper source field plate layer and / or at least one upper drain field plate layer on the second passivation layer, and the two upper and lower adjacent upper source field plate layers and / or the two upper and lower adjacent upper drain field plate layers are isolated by a dielectric layer; the first through hole also penetrates all the upper source field plate layers, and the second through hole also penetrates all the upper drain field plate layers.
[0013] Furthermore, the aspect ratio of the first through hole is less than 3:1, and the aspect ratio of the second through hole is less than 3:1.
[0014] Optionally, the HEMT device is a D-Mode GaN HEMT device or an E-Mode GaN HEMT device.
[0015] Optionally, the material of the source field plate layer includes one or more of Ti, TiN, AlCu and AlSi, and the material of the drain field plate layer includes one or more of Ti, TiN, AlCu and AlSi.
[0016] Optionally, the thickness of the source field plate layer does not exceed 1000 nm, and the thickness of the drain field plate layer does not exceed 1000 nm.
[0017] Optionally, a nucleation layer is formed between the semiconductor substrate and the channel layer, and a material of the nucleation layer includes AlN.
[0018] Optionally, the material of the semiconductor substrate includes one of silicon, GaN, GaO, SiC, diamond, SOI and sapphire, the material of the channel layer includes GaN, and the material of the barrier layer includes AlGaN.
[0019] Optionally, the first through hole is formed by a single through hole etching process or a multiple through hole etching process; and the second through hole is formed by a single through hole etching process or a multiple through hole etching process.
[0020] The present invention also provides a HEMT device, which is prepared using any one of the above methods for preparing a HEMT device.
[0021] As described above, the HEMT device and the method for manufacturing the same of the present invention have the following beneficial effects: first, a semiconductor structure having a semiconductor substrate, a channel layer, a barrier layer, a source electrode, a drain electrode, and a gate electrode of the HEMT device is provided; a first passivation layer is formed on the semiconductor structure; and a patterned source field plate layer and / or drain field plate layer is formed on the first passivation layer, wherein the source field plate layer is at least formed above the source electrode, and the drain field plate layer is at least formed above the drain electrode; then, a second passivation layer is formed covering the first passivation layer, the source field plate layer, and / or the drain field plate layer, and penetrates downward from the upper surface of the obtained structure until the gate electrode is exposed. A first through hole is formed at the source electrode, and a second through hole is formed downwardly through the upper surface of the obtained structure until the drain electrode is exposed. Then, a source metal layer and a drain metal layer are formed. The source metal layer at least fills the first through hole to be in contact with the source electrode, and the drain metal layer at least fills the second through hole to be in contact with the drain electrode. Both the source metal layer and the drain metal layer are located in the active area of the device. Through the above steps, the problems of layout area waste, too small through-hole etching process window, and difficulty in large-scale mass production caused by the through-hole structure connected to the multi-layer source / drain field plate in the prior art are solved, thereby improving the GDPW of the device and reducing the FOM value. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] Figure 1 It is a schematic flow chart of the method for preparing a HEMT device according to the present invention.
[0023] Figures 2 to 6 Shown are schematic cross-sectional structures of various steps in the method for preparing a HEMT device according to the present invention.
[0024] Figure 7 It is a schematic diagram of the top view of the HEMT device of the present invention.
[0025] Description of element reference numerals
[0026] 1 Semiconductor structure
[0027] 2 Source-drain pre-structure
[0028] 10. Semiconductor substrate
[0029] 11 Nucleation layer
[0030] 12 Channel layer
[0031] 13 Barrier layer
[0032] 14 Source
[0033] 15 Drain
[0034] 16 First insulation layer
[0035] 17 Second insulation layer
[0036] 18 Gate trench
[0037] 19 Gate
[0038] 20 First passivation layer
[0039] 21 Source field plate layer
[0040] 22 Drain field plate layer
[0041] 23 Second passivation layer
[0042] 24 First through hole
[0043] 25 Second through hole
[0044] 26 Source metal layer
[0045] 27 Drain metal layer
[0046] 28 active area
[0047] 29 Quarantine Zone
[0048] 30 Gate metal layer
[0049] 40 Insulation layer
[0050] Steps S1 to S6 DETAILED DESCRIPTION
[0051] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.
[0052] See also Figures 1 to 7It should be noted that the diagrams provided in this embodiment are merely schematic illustrations of the basic concept of the present invention. Therefore, the diagrams only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be changed arbitrarily, and the component layout may also be more complex.
[0053] This embodiment provides a method for preparing a HEMT device, such as Figure 1 As shown, the preparation method comprises:
[0054] S1. Providing a semiconductor structure, wherein the semiconductor structure comprises, from bottom to top, a semiconductor substrate, a HEMT device channel layer, a HEMT device barrier layer, and a HEMT device source, drain, and gate formed on the barrier layer, wherein the source, drain, and gate are electrically isolated by an insulating layer;
[0055] S2, forming a first passivation layer covering the upper surface of the semiconductor structure;
[0056] S3, forming a patterned source field plate layer and / or a patterned drain field plate layer on the first passivation layer; wherein the source field plate layer is formed at least above the source electrode, and the drain field plate layer is formed at least above the drain electrode;
[0057] S4, forming a second passivation layer covering the first passivation layer, the source field plate layer and / or the drain field plate layer;
[0058] S5, forming a first through hole and a second through hole, wherein the first through hole penetrates downward from the upper surface of the obtained structure until the source electrode is exposed, and the second through hole penetrates downward from the upper surface of the obtained structure until the drain electrode is exposed;
[0059] S6, forming a source metal layer and a drain metal layer; wherein the source metal layer at least fills the first through hole to be in contact with the source, and the drain metal layer at least fills the second through hole to be in contact with the drain.
[0060] The method for preparing the HEMT device of this embodiment comprises first providing a semiconductor structure having a semiconductor substrate, a channel layer, a barrier layer, a source electrode, a drain electrode, and a gate electrode of the HEMT device, and then forming a first passivation layer on the semiconductor structure, and then forming a patterned source field plate layer and / or drain field plate layer on the first passivation layer, wherein the source field plate layer is formed at least above the source electrode, and the drain field plate layer is formed at least above the drain electrode, and then forming a second passivation layer covering the first passivation layer, the source field plate layer, and / or the drain field plate layer, and then penetrating downward from the upper surface of the obtained structure until the source electrode is exposed to form a first passivation layer. A hole is formed, and a second through hole is formed downwardly from the upper surface of the obtained structure until the drain electrode is exposed, and then a source metal layer and a drain metal layer are formed. The source metal layer at least fills the first through hole to be in contact with the source electrode, and the drain metal layer at least fills the second through hole to be in contact with the drain electrode. The source metal layer and the drain metal layer are both located in the active area of the device. Through the above steps, the problems of layout area waste, too small through-hole etching process window and difficulty in large-scale mass production caused by the through-hole structure connected to the multi-layer source / drain field plate in the prior art are solved, thereby improving the GDPW of the device and reducing the FOM value.
[0061] The method for preparing the HEMT device of this embodiment will be described in detail below with reference to the accompanying drawings.
[0062] like Figure 3 As shown, first perform step S1,
[0063] A semiconductor structure 1 is provided. The semiconductor structure 1 includes, from bottom to top, a semiconductor substrate 10, a HEMT device channel layer 12, a HEMT device barrier layer 13, and a HEMT device source 14, a drain 15, and a gate 19 formed on the barrier layer 13. The source 14, the drain 15, and the gate 19 are electrically isolated by an insulating layer 40.
[0064] As an example, the material of the semiconductor substrate 10 includes one of silicon (Si), gallium nitride (GaN), gallium oxide (GaO), silicon carbide (SiC), diamond, silicon on insulator (SOI), and sapphire.
[0065] As an example, the HEMT device type can be selected as needed, and can be, for example, a D-Mode GaN HEMT device (depletion-mode gallium nitride high electron mobility transistor device) or an E-Mode GaN HEMT device (enhancement-mode gallium nitride high electron mobility transistor device), both of which are compatible with existing manufacturing processes. This embodiment uses the D-Mode GaN HEMT device as an example for illustration.
[0066] Furthermore, the semiconductor structure 1 can be formed based on a gate-first process or a gate-last process. In this embodiment, the semiconductor structure 1 formed based on a gate-last process is used as an example for description. Figure 2 and Figure 3 As shown, the method for preparing the semiconductor structure 1 includes:
[0067] S11, such as Figure 2 As shown, a source-drain pre-structure 2 is provided, which includes the semiconductor substrate 10, the channel layer 12, the barrier layer 13, the source 14 and the drain 15 from bottom to top, and the source 14 and the drain 15 are electrically isolated by a first insulating layer 16.
[0068] S12, such as Figure 3 As shown, a second insulating layer 17 is formed to cover the source 14 , the drain 15 and the first insulating layer 16 .
[0069] S13, such as Figure 3 As shown, a gate trench 18 penetrating the second insulating layer 17 and the first insulating layer 16 is formed in a predetermined gate region, and the gate 19 is formed to at least fill the gate trench 18 .
[0070] As an example, other film layers are formed between the semiconductor substrate 10 and the channel layer 12, which can be designed according to actual needs. For example, Figure 2 As shown, a nucleation layer 11 is further formed between the semiconductor substrate 10 and the channel layer 12. The channel layer 12 and the barrier layer 13 are made of different materials. A two-dimensional electron gas is formed at the interface between the channel layer 12 and the barrier layer 13. The two-dimensional electron gas serves as the channel of the HEMT device, providing a conductive channel between the source and drain of the device.
[0071] As an example, the material of the channel layer 12 includes the more commonly used gallium nitride (GaN), the material of the barrier layer 13 includes the more commonly used aluminum gallium nitride (AlGaN), the material of the channel layer 12 also includes one of gallium arsenide (GaAs), silicon carbide (SiC), gallium oxide (GaO), aluminum nitride (AlN) and AlGaN, the material of the barrier layer 13 also includes one of GaN, GaAs, SiC, GaO and AlN, and the material of the channel layer 12 is different from the material of the barrier layer 13; the material of the nucleation layer 11 includes AlN, the material of the channel layer 12, the material of the barrier layer 13 and the material of the nucleation layer 11 can be selected according to needs, and no excessive restrictions are made here.
[0072] like Figure 4As shown, step S2 is then performed to form a first passivation layer 20 covering the upper surface of the semiconductor structure 1 .
[0073] like Figure 4 As shown, step S3 is then performed to form a patterned source field plate layer 21 and / or a patterned drain field plate layer 22 on the first passivation layer 20; wherein the source field plate layer 21 is formed at least above the source 14, and the drain field plate layer 22 is formed at least above the drain 15.
[0074] In this embodiment, the formation of the source field plate layer 21 and the drain field plate layer 22 is taken as an example for description. In other embodiments, only the source field plate layer 21 or only the drain field plate layer 22 may be formed to simultaneously meet the switching speed and electric field distribution requirements of the HEMT device.
[0075] As an example, the material of the source field plate layer 21 includes one or more of titanium (Ti), titanium nitride (TiN), aluminum-copper alloy (AlCu) and aluminum-silicon alloy (AlSi), and the material of the drain field plate layer 22 includes one or more of titanium (Ti), titanium nitride (TiN), aluminum-copper alloy (AlCu) and aluminum-silicon alloy (AlSi). The materials of the source field plate layer 21 and the drain field plate layer 22 can be selected according to needs and are not overly restricted here.
[0076] As an example, the thickness of the source field plate layer 21 does not exceed 1000 nm, preferably 100 nm, and the thickness of the drain field plate layer 22 does not exceed 1000 nm, preferably 100 nm, so as to effectively optimize the electrical performance of the device, improve process feasibility and production efficiency, and reduce costs. In addition, the thickness of the source field plate layer 21 and the thickness of the drain field plate layer 22 are not limited to the above thicknesses and can be designed according to the needs of actual products. No excessive restrictions are made here.
[0077] like Figure 5 As shown, step S4 is then performed to form a second passivation layer 23 covering the first passivation layer 20 , the source field plate layer 21 and / or the drain field plate layer 22 .
[0078] like Figure 5 As shown, step S5 is then performed to form a first through hole 24 and a second through hole 25; wherein the first through hole 24 penetrates downward from the upper surface of the obtained structure (for example, the structure obtained after step S4) until the source 14 is exposed, and the second through hole 25 penetrates downward from the upper surface of the obtained structure until the drain 15 is exposed.
[0079] As an example, the first through-hole 24 may be formed by a single through-hole etching process or a multiple through-hole etching process, and the second through-hole 25 may be formed by a single through-hole etching process or a multiple through-hole etching process.
[0080] Specifically, such as Figure 5 As shown, a single through-hole etching process or a multiple through-hole etching process can be used to sequentially etch the second passivation layer 23, the source field plate layer 21, the first passivation layer 20 and the insulating layer 40 from the upper surface of the second passivation layer 23 downward to form the first through-hole 24; a single through-hole etching process or a multiple through-hole etching process can be used to sequentially etch the second passivation layer 23, the drain field plate layer 22, the first passivation layer 20 and the insulating layer 40 from the upper surface of the second passivation layer 23 downward to form the second through-hole 25.
[0081] It should be noted here that the multiple through-hole etching process involves etching of multiple layers of dielectrics (the second passivation layer 23, the first passivation layer 20 and the insulating layer 40) and metal layers (the source field plate layer 21 or the drain field plate layer 22) during the etching process, and the etching menus (including etching gas, power, pressure and other process parameters) for etching dielectrics and metals are usually different. Therefore, in order to ensure the etching effect and accuracy of each layer, multiple etchings will be used. At the same time, when etching deep holes, etching by-products are easily generated and attached to the side walls, resulting in a slower etching rate. Multiple etchings help to remove by-products in time and maintain the etching rate and quality. Of course, according to the characteristics of the etching material, by optimizing the etching menu, a single etching can also be used in one step. Therefore, this embodiment provides a flexible choice of a single through-hole etching process or a multiple through-hole etching process to meet the needs of different materials and process conditions.
[0082] like Figure 6 As shown, step S6 is then performed to form a source metal layer 26 and a drain metal layer 27. The source metal layer 26 at least fills the first through-hole 24 to contact and connect with the source electrode 14, and the drain metal layer 27 at least fills the second through-hole 25 to contact and connect with the drain electrode 15. Therefore, the source field plate layer 21 is interconnected with the source metal layer 26 through the sidewall of the first through-hole 24, and the drain field plate layer 22 is interconnected with the drain metal layer 27 through the sidewall of the second through-hole 25, thereby increasing the etching process window.
[0083] As described above, this embodiment is described by taking only one source / drain field plate layer (the source field plate layer 21 and the drain field plate layer 22) as an example. In fact, the source / drain field plate layer can also be multi-layered. When the source / drain field plate layer is multi-layered, the preparation method further includes the step of forming at least one upper source field plate layer and / or at least one upper drain field plate layer (not shown) on the second passivation layer 23 after forming the second passivation layer 23. The upper and lower adjacent layers of the upper source field plate layers and / or the upper and lower adjacent layers of the upper drain field plate layers are isolated by a dielectric layer (not shown).
[0084] At this time, the first through hole 24 also penetrates all the upper source field plate layers, and the second through hole 25 also penetrates all the upper drain field plate layers, so that the subsequently formed source metal layer is in contact and connected with each layer of the upper source field plate layer, and the drain metal layer is in contact and connected with each layer of the upper drain field plate layer.
[0085] As an example, regardless of whether a single source / drain field plate layer or multiple source / drain field plate layers are formed in the HEMT device, the aspect ratio of the first through hole 24 is preferably less than 3:1, and the aspect ratio of the second through hole 25 is also preferably less than 3:1, to ensure that the source metal layer 26 uniformly covers the sidewalls and bottom of the first through hole 24, and the drain metal layer 27 uniformly covers the sidewalls and bottom of the second through hole 25, thereby reducing the possibility of voids or discontinuous deposition, thereby improving the quality of the contact connection between the source metal layer 26 and the source field plate layer 21 and the source 14, and the quality of the contact connection between the drain metal layer 27 and the drain field plate layer 22 and the drain 15.
[0086] As an example, Figure 7 As shown, when the HEMT device further includes a gate field plate structure, the preparation method further includes forming a gate field plate layer, and forming a gate metal layer 30 (which penetrates the gate field plate layer and is in contact with the gate) Figures 2 to 6 (step not shown), and the gate metal layer 30 can be placed in the isolation region 29 outside the active region 28.
[0087] This embodiment further provides a HEMT device, which is manufactured using the method for manufacturing the HEMT device in the above embodiment. The beneficial effects that can be achieved can be found in the detailed description of the manufacturing method, which will not be repeated here.
[0088] In summary, the HEMT device and its preparation method of the present invention are as follows: first, a semiconductor structure having a semiconductor substrate, a channel layer, a barrier layer, a source electrode, a drain electrode, and a gate electrode of the HEMT device is provided; a first passivation layer is formed on the semiconductor structure; and a patterned source field plate layer and / or drain field plate layer is formed on the first passivation layer, wherein the source field plate layer is at least formed above the source electrode, and the drain field plate layer is at least formed above the drain electrode; then, a second passivation layer is formed covering the first passivation layer, the source field plate layer, and / or the drain field plate layer, and penetrates downward from the upper surface of the obtained structure until the second passivation layer is exposed. A first through-hole is formed at the source electrode, which is then penetrated until the drain electrode is exposed to form a second through-hole. Subsequently, a source metal layer and a drain metal layer are formed. The source metal layer at least fills the first through-hole to contact and connect with the source electrode, and the drain metal layer at least fills the second through-hole to contact and connect with the drain electrode. Both the source metal layer and the drain metal layer are located in the device active area. Through these steps, the problems of the prior art caused by the through-hole structure connected to the multi-layer source / drain field plate, the small through-hole etching process window, and the difficulty in achieving large-scale mass production are solved, thereby improving the device's GDPW and reducing the FOM value. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial utilization value.
[0089] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.
Claims
1. A method for preparing a HEMT device, characterized in that: The preparation method comprises: A semiconductor structure is provided, comprising, from bottom to top, a semiconductor substrate, a HEMT device channel layer, a HEMT device barrier layer, and a HEMT device source, drain, and gate formed on the barrier layer, wherein the source, drain, and gate are electrically isolated by an insulating layer; forming a first passivation layer covering the upper surface of the semiconductor structure; forming a patterned source field plate layer and / or a patterned drain field plate layer on the first passivation layer; wherein the source field plate layer is formed at least above the source electrode, and the drain field plate layer is formed at least above the drain electrode; forming a second passivation layer covering the first passivation layer, the source field plate layer and / or the drain field plate layer; forming a first through hole and a second through hole; wherein the first through hole penetrates downward from the upper surface of the obtained structure until the source electrode is exposed, and the second through hole penetrates downward from the upper surface of the obtained structure until the drain electrode is exposed; A source metal layer and a drain metal layer are formed; wherein the source metal layer at least fills the first through hole to be in contact with the source, and the drain metal layer at least fills the second through hole to be in contact with the drain.
2. The method for preparing a HEMT device according to claim 1, wherein: After forming the second passivation layer, the method also includes the step of forming at least one upper source field plate layer and / or at least one upper drain field plate layer on the second passivation layer, wherein the upper and lower adjacent layers of the upper source field plate layers and / or the upper and lower adjacent layers of the upper drain field plate layers are isolated by a dielectric layer; the first through hole also penetrates all the upper source field plate layers, and the second through hole also penetrates all the upper drain field plate layers.
3. The method for preparing a HEMT device according to any one of claims 1 to 2, wherein: The aspect ratio of the first through hole is less than 3:1, and the aspect ratio of the second through hole is less than 3:
1.
4. The method for preparing a HEMT device according to claim 1, wherein: The HEMT device is a D-Mode GaN HEMT device or an E-Mode GaN HEMT device.
5. The method for preparing a HEMT device according to claim 1, wherein: The material of the source field plate layer includes one or more of Ti, TiN, AlCu and AlSi, and the material of the drain field plate layer includes one or more of Ti, TiN, AlCu and AlSi.
6. The method for preparing a HEMT device according to claim 1, wherein: The thickness of the source field plate layer does not exceed 1000 nm, and the thickness of the drain field plate layer does not exceed 1000 nm.
7. The method for preparing a HEMT device according to claim 1, wherein: A nucleation layer is formed between the semiconductor substrate and the channel layer, and the material of the nucleation layer includes AlN.
8. The method for preparing a HEMT device according to claim 1, wherein: The material of the semiconductor substrate includes one of Si, GaN, GaO, SiC, diamond, SOI and sapphire, the material of the channel layer includes GaN, and the material of the barrier layer includes AlGaN.
9. The method for preparing a HEMT device according to claim 1, wherein: The first through hole is formed by a single through hole etching process or a multiple through hole etching process; the second through hole is formed by a single through hole etching process or a multiple through hole etching process.
10. A HEMT device, characterized in that: The HEMT device is prepared by the preparation method of any one of claims 1 to 9.