Chip packaging body packaging method, chip packaging body and power grid configuration method

Abstract

The invention provides a chip packaging body packaging method, a chip packaging body and a power grid configuration method, and the chip packaging body packaging method comprises the steps: carrying out the function division of a to-be-packaged chip set, and obtaining a plurality of function modules; integrating a plurality of functional modules into a plurality of functional layers based on the functional types of the functional modules; integrating a plurality of functional modules into different areas of the functional layer based on the signal processing types of the functional modules; and realizing communication interconnection between different functional layers based on a preset vertical interconnection strategy to obtain the chip packaging body. The plurality of functional modules are integrated into different areas of the functional layer, so that the mutual influence generated when the functional models of different signal processing types process signals subsequently is reduced, and the signal integrity in the subsequent signal transmission process is improved; through vertical interconnection, three-dimensional stacking of a plurality of functional modules is realized, and the integration density and the interconnection efficiency of the chip are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip package packaging, and in particular to a chip package packaging method, a chip package, and a power grid configuration method. Background Art

[0002] With the expansion of smart grids and the prevalence of distributed energy, chips need to be able to integrate multiple computing capabilities to support real-time data processing, multi-service collaboration, and high security requirements. Traditional chip architectures use a discrete design, which has problems such as dispersed computing power, high communication latency, and high power consumption. Although existing technologies have improved computing power flexibility through heterogeneous multi-core architectures, due to the limitations of planar packaging processes, the integration density and interconnection efficiency of functional modules of different chips (such as computing cores, security cores, and power-specific modules) are low, making it difficult to meet the needs of high-density, low-latency power systems.

[0003] Smart grids have extremely high requirements for the real-time performance and reliability of chips, and an innovative SiP packaging method is urgently needed to meet the smart grid's demand for high efficiency. Summary of the Invention

[0004] The present invention aims to provide a chip package packaging method, a chip package and a power grid configuration method to solve the above technical problems, improve the integration density and interconnection efficiency of the chip package, and further improve the efficiency of configuring the power grid.

[0005] In order to solve the above technical problems, the present invention provides a chip package packaging method, comprising the following steps:

[0006] Perform functional division on the chip set to be packaged to obtain multiple functional modules;

[0007] Integrating a plurality of the functional modules into a plurality of functional layers based on the functional types of the functional modules;

[0008] Integrating a plurality of the functional modules into different areas of the functional layer based on the signal processing types of the functional modules;

[0009] Based on a preset vertical interconnection strategy, communication and interconnection between different functional layers are achieved to obtain a chip package.

[0010] In the above case, the chip set to be packaged is functionally divided to obtain multiple functional modules, thereby realizing the classification and induction of multiple chips in the chip set to be packaged; based on the functional type of the functional module, multiple functional modules are integrated into multiple functional layers, and functional modules of different functional types are integrated into different functional layers, thereby ensuring the smoothness and efficiency of data processing; based on the signal processing type of the functional module, multiple functional modules are integrated into different areas of the functional layer, thereby reducing the mutual influence when functional models of different signal processing types subsequently process the signal, and improving the signal integrity in the subsequent signal transmission process; based on the preset vertical interconnection strategy, communication interconnection between different functional layers is realized to obtain a chip package body, and through vertical interconnection, three-dimensional stacking of multiple functional modules is realized, which improves the integration density and interconnection efficiency of the chip compared to the existing planar packaging process.

[0011] Furthermore, the chip set to be packaged includes a plurality of chips to be packaged, and the communication interconnection between different functional layers is achieved based on a preset vertical interconnection strategy to obtain a chip package, including:

[0012] placing the plurality of functional modules on the plurality of functional layers respectively;

[0013] Etching on the functional layer to obtain a through hole, and filling the through hole with a conductive material;

[0014] The chips to be packaged are aligned between any two adjacent functional layers so that the functional layers communicate with each other through the conductive material in the through-holes.

[0015] In the above scheme, through holes are etched on each functional layer, and conductive material is filled in the through holes. The chips to be packaged between any two adjacent functional layers are aligned to achieve communication between different functional layers. Vertical interconnection is achieved by using through holes, and then stacking between different functional layers is achieved, thereby increasing the interconnection density and improving communication efficiency.

[0016] Furthermore, aligning the chips to be packaged between any two adjacent functional layers so that the functional layers communicate with each other through the conductive material in the through-holes includes:

[0017] Depositing metal on the chip to be packaged on the functional layer, and performing photolithography and etching on the deposited metal to form bumps;

[0018] The chips to be packaged are aligned between any two adjacent functional layers so that the functional layers communicate with each other based on the bumps and the conductive materials in the through holes.

[0019] In the above solution, the electrical connection between different functional layers is achieved by combining the bumps, thereby shortening the communication path and improving the communication efficiency.

[0020] Furthermore, the communication interconnection between the different functional layers is achieved based on a preset vertical interconnection strategy to obtain a chip package, including:

[0021] A micro-channel device is provided between the functional layers, so that the micro-channel device can dissipate heat between the functional layers based on circulating cooling liquid.

[0022] In the above solution, the heat dissipation of the functional layer is achieved through the microfluidic device.

[0023] Furthermore, the communication interconnection between the different functional layers is achieved based on a preset vertical interconnection strategy to obtain a chip package, including:

[0024] Thermally conductive silicone grease is applied between the chip to be packaged and the microfluidic channel device.

[0025] In the above solution, heat dissipation of the functional layer is further achieved through thermal grease.

[0026] The present invention also provides a chip package, which is obtained by packaging based on the chip package packaging method as described above.

[0027] In this solution, functional modules of different types are integrated into different functional layers to ensure smooth and efficient data processing. Multiple functional modules are integrated into different areas of the functional layer, reducing the impact of subsequent signal processing by functional models of different signal processing types, thereby improving signal integrity during subsequent signal transmission. The chip package is based on a vertical interconnection strategy, enabling three-dimensional stacking of multiple functional modules. Compared to existing planar packaging processes, this improves chip integration density and interconnection efficiency.

[0028] The present invention also provides a power grid configuration method, which configures a processing power grid based on the chip package as described above, wherein the chip package includes multiple functional layers, and the multiple functional layers include a substrate layer and a computing layer. The power grid configuration method specifically includes the following steps:

[0029] collecting target data from the power grid to be processed through the substrate layer;

[0030] The target data is checked for faults by the computing layer to obtain a check result, so that the substrate layer configures the power grid to be processed based on the check result.

[0031] In the above scheme, the chip package includes multiple functional layers, each corresponding to a different functional type. The functional layers include a substrate layer and a computing layer. The substrate layer is used to collect target data from the target power grid, enabling the computing layer to perform fault detection on the target data and obtain inspection results, thereby facilitating subsequent configuration of the target power grid based on the inspection results. The functional layer division by function type helps to improve data processing efficiency and avoid duplicate data transmission. Because the chips in the chip package have high-density and high-efficiency interconnection characteristics, the configuration process of the target power grid based on the chip package can also improve the efficiency of the power grid configuration.

[0032] Furthermore, the substrate layer includes an AD control module and a network storm processing module, the target data includes grid parameters and compliance data, and the target data is collected from the grid to be processed through the substrate layer, including:

[0033] Collecting the grid parameters from the grid to be processed through the AD control module;

[0034] The flow data in the to-be-processed power grid is acquired through the network storm processing module, and the flow data is filtered based on preset rules to obtain the compliance data in the flow data.

[0035] In the above solution, the grid parameters are collected through the AD control module, and the compliance data in the traffic data is obtained through the network storm processing module, providing more data for calculation and processing by the computing layer.

[0036] Furthermore, the computing layer includes a security module, a business module, and a computing module, and the substrate layer also includes a control module. The computing layer performs a fault check on the target data to obtain a check result, so that the substrate layer configures the power grid to be processed based on the check result, including:

[0037] Acquiring the target data from the substrate layer through the security module, and encrypting the target data to obtain encrypted data;

[0038] The business module is used to perform data identification on the encrypted data to obtain abnormal event data;

[0039] The calculation module analyzes the abnormal event data based on a preset fault model, generates a control instruction, and sends the control instruction to the substrate layer, so that the control module in the substrate layer isolates the fault of the power grid to be processed based on the control instruction.

[0040] In the above scheme, the target data is encrypted through the security module to improve security; the encrypted data is identified through the business module to obtain abnormal event data, thereby achieving accurate screening of abnormal event data; the abnormal event data is analyzed by the calculation module based on the preset fault model to generate control instructions. Due to the high-density interconnection of chips between functional layers, efficient configuration of the processed power grid is achieved.

[0041] Furthermore, the substrate layer further includes a B-code timing module, and the target data is collected from the power grid to be processed through the substrate layer, including:

[0042] The B-code timing module in the substrate layer receives an optical pulse signal from the power grid to be processed, so that the B-code timing module parses the optical pulse signal based on an internal protocol to obtain a synchronous clock signal, and then the B-code timing module transmits the synchronous clock signal to the computing layer, so that the substrate layer and the computing layer perform data processing based on the synchronous clock signal.

[0043] In the above solution, clock synchronization between functional layers is achieved through the B-code timing module, thereby reducing timing delays. No complex cross-clock domain processing is required between functional layers and functional modules, and data transmission delays can be significantly reduced, thereby improving overall efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 A schematic flow chart of a chip package packaging method according to an embodiment of the present invention;

[0045] Figure 2 A schematic diagram of the architecture of a chip package provided by one embodiment of the present invention;

[0046] Figure 3 A schematic diagram of the structure of a substrate layer provided by one embodiment of the present invention;

[0047] Figure 4 A schematic diagram of the architecture of the computing layer provided in one embodiment of the present invention;

[0048] Figure 5 A coaxial shielding structure provided by an embodiment of the present invention;

[0049] Figure 6 A schematic diagram of a power grid configuration method provided by one embodiment of the present invention. DETAILED DESCRIPTION

[0050] The following will provide a clear and complete description of the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0051] See Figure 1 This embodiment provides a chip package packaging method, comprising the following steps:

[0052] Step S11: functionally dividing the chipset to be packaged to obtain multiple functional modules;

[0053] Step S12: Integrate multiple functional modules into multiple functional layers based on the functional types of the functional modules;

[0054] Step S13: Integrate multiple functional modules into different areas of the functional layer based on the signal processing types of the functional modules;

[0055] Step S14: realizing communication interconnection between different functional layers based on a preset vertical interconnection strategy to obtain a chip package.

[0056] In the above case, the chip set to be packaged is functionally divided to obtain multiple functional modules, thereby realizing the classification and induction of multiple chips in the chip set to be packaged; based on the functional type of the functional module, multiple functional modules are integrated into multiple functional layers, and functional modules of different functional types are integrated into different functional layers, thereby ensuring the smoothness and efficiency of data processing; based on the signal processing type of the functional module, multiple functional modules are integrated into different areas of the functional layer, thereby reducing the mutual influence of subsequent functional models of different signal processing types on the signal, and improving the signal integrity in the subsequent signal transmission process; based on the preset vertical interconnection strategy, communication interconnection between different functional layers is realized to obtain a chip package. Through vertical interconnection, three-dimensional stacking of multiple functional modules is realized, which improves the integration density and interconnection efficiency of the chip compared with the existing planar packaging process.

[0057] Furthermore, based on the functional types of the functional modules, multiple functional modules are integrated into multiple functional layers. For example, if the chipset to be packaged is divided into power, computing, storage, and interface functions, the power function is correspondingly integrated into the substrate layer within the functional layer, the computing function into the computing layer within the functional layer, the storage function into the storage layer within the functional layer, and the interface function into the interface layer within the functional layer. This allows for the organization and summary of functional modules with different functions, facilitates data transmission and processing, and avoids long-distance and overly frequent back-and-forth data transmission.

[0058] Furthermore, based on the signal processing type of the functional modules, multiple functional modules are integrated into different areas of the functional layer. For example, the functional layer includes a substrate layer, which includes an AD control module, a B-code timing module, and a network storm processing module. The AD control module is used to process analog signals, while the B-code timing module and the network storm processing module both process digital signals. Therefore, the AD control module is distributed to the analog area of ​​the substrate layer, close to the analog power plane, while the B-code timing module and the network storm processing module are distributed to the digital area of ​​the substrate layer. This reduces the mutual influence of subsequent functional models of different signal processing types on the signal processing, and improves the signal integrity during the subsequent signal transmission process.

[0059] In another embodiment, a chip set to be packaged includes a plurality of chips to be packaged, and communication interconnection between different functional layers is achieved based on a preset vertical interconnection strategy to obtain a chip package, including:

[0060] Place multiple functional modules on multiple functional layers;

[0061] Etching on the functional layer to obtain a through hole, and filling the through hole with a conductive material;

[0062] Align the chips to be packaged between any two adjacent functional layers so that the functional layers communicate with each other through the conductive material in the through-holes.

[0063] In another embodiment, aligning the chips to be packaged between any two adjacent functional layers so that the functional layers communicate with each other through the conductive material in the through-holes includes:

[0064] Depositing metal on the chip to be packaged on the functional layer, and performing photolithography and etching on the deposited metal to form bumps;

[0065] Align the chips to be packaged between any two adjacent functional layers so that the functional layers communicate with each other based on the conductive materials in the bumps and through-holes.

[0066] It should be noted that the vertical interconnection strategy uses through silicon via (TSV) technology to achieve vertical interconnection of each functional layer, stacking multiple functional layers in three-dimensional space. TSV adopts a high aspect ratio structural design, combined with low-impedance metal filling materials, which significantly shortens the signal transmission path between layers and reduces communication delays. An insulating isolation layer is set around TSV to effectively prevent signal crosstalk and leakage problems. Different functional layers are connected through TSV, and different chips in the same functional layer are also connected through TSV, thereby realizing the stacking of different functional layers and the stacking of different functional modules in the same layer to achieve high-density interconnection. For example, refer to Figure 4The functional layer includes the computing layer, which includes a shared cache, a security module, a business module, and a computing module. The security module is also called the security core, the business module is also called the security core, and the computing module is also called the computing core. Specifically:

[0067] Through-silicon via (TSV) preparation: Vertical through-holes are etched on the wafers of the computing core (CPU / FPGA), security core, and business core, and filled with conductive materials to form low-impedance interconnect channels.

[0068] Temporary bonding and alignment: Use temporary bonding glue to stack multi-core chips onto the computing layer substrate, and use optical alignment technology to ensure the precise alignment of TSVs between layers.

[0069] Stacking process: TSV preparation: Vertical through-hole vias (TSVs) are etched on the wafer of each core and filled with conductive material (such as copper).

[0070] Chip thinning: Grind the back of the wafer to 50-100μm to expose the TSV.

[0071] Alignment and stacking: Use a high-precision placement machine to align and temporarily fix them in order (security core → computing core, shared cache, shared cache → business core).

[0072] ±0.5μm alignment accuracy is ensured by optical markings.

[0073] Permanent bonding: Thermal compression bonding (200-250°C) interconnects TSVs or microbumps to form electrical connections.

[0074] Filling and reinforcement: Inject thermal conductive adhesive to fill the gaps between layers to optimize heat dissipation and mechanical strength.

[0075] The stacking process of the shared cache and the computing core is as follows: the shared cache and the computing core are flip-chip bonded to the same silicon interposer via microbumps; the silicon interposer is embedded with high-density copper wiring (line width ≤ 2μm), directly connecting the I / O interface of the cache and the core; high-bandwidth interconnection; and the use of through-silicon vias (TSVs) vertically penetrating the interposer to shorten the data transmission path (delay <1ns).

[0076] The process for connecting different functional layers via TSVs is similar: through-holes are etched into the wafer corresponding to the functional modules on each functional layer and filled with conductive material. The chips are then thinned to expose the TSVs. The chips between the functional layers are aligned and stacked, and the TSVs are interconnected through thermocompression bonding to form an electrical connection, which is then reinforced with filler. Vertical interconnection technology enables vertical signal transmission between different functional layers, shortens signal transmission paths, reduces communication latency, and increases packaging density while reducing package volume.

[0077] Furthermore, refer to Figure 4 To further ensure the reliability of electrical connections, a layer of conductive material, such as copper, can be deposited on the surface of the chips to be packaged during the alignment of the chips between any two adjacent functional layers. Tiny bumps are formed by etching, and any shape is allowed to form contact points that connect the chips or modules between different functional layers. This provides a higher density of electrical connections, ensuring reliability, reducing signal transmission paths, and lowering signal latency.

[0078] In another embodiment, communication interconnection between different functional layers is achieved based on a preset vertical interconnection strategy to obtain a chip package, including:

[0079] A microfluidic channel device is provided between the functional layers, so that the microfluidic channel device can dissipate heat between the functional layers based on circulating cooling liquid.

[0080] It should be noted that active heat dissipation is achieved through microchannels: a microchannel structure is embedded between different functional layers, and heat is quickly removed through circulating coolant. The flow channel design uses a multi-branch network to ensure that heat is evenly distributed within the package to avoid local overheating. Furthermore, the functional layer includes the substrate layer and the computing layer. There is more interaction between the two, and their respective power consumption is also high, so the heat generated is also more. Therefore, compared with other functional layers, it is more necessary to embed a microchannel structure between the computing layer and the substrate layer.

[0081] In another embodiment, communication interconnection between different functional layers is achieved based on a preset vertical interconnection strategy to obtain a chip package, including: coating thermal grease between the chip to be packaged and the microfluidic device.

[0082] It should be noted that thermal management can also be achieved by applying thermal interface material (TIM). Specifically, high thermal conductivity silicone grease is applied between the chip to be packaged and the heat dissipation structure, i.e., the microchannel structure, to reduce the contact thermal resistance and improve the overall heat dissipation efficiency.

[0083] Furthermore, corresponding to the functional layer where high-power consumption modules exist, thermoelectric cooling (TEC) units are deployed to achieve active temperature control of hot spots through the Peltier effect, thereby maintaining a stable operating temperature of the chip.

[0084] Furthermore, illustratively, reference is made to Figure 2 The functional layer includes substrate layer, computing layer, storage layer and interface layer. The following provides the specific packaging process of the chip package:

[0085] (1) Substrate layer module integration:

[0086] Substrate preparation: Use high thermal conductivity ceramic substrate, and the surface is precisely polished and cleaned to ensure no impurities remain.

[0087] Power module mounting:

[0088] Before mounting, isolation grooves are processed in advance. During processing, the space required for the functional modules is reserved in advance according to the module position. Then, the AD control module, B code timing module and network storm processing module are positioned to the preset area of ​​the substrate through a high-precision placement machine.

[0089] Bonding process: Gold wire bonding technology is used to connect the electrical interface of the module and the substrate. The bonding process adopts closed-loop control to ensure connection strength and signal integrity.

[0090] Signal routing optimization: Complete differential signal line routing, use a multi-layer stacking design for power and ground planes, and combine high-frequency decoupling capacitors to suppress noise.

[0091] (2) Computing layer stacking and interconnection: through silicon via (TSV) preparation; temporary bonding and alignment; stacking process: TSV preparation, chip thinning; alignment stacking; permanent bonding; filling and reinforcement.

[0092] (3) Storage layer encapsulation:

[0093] Memory mounting: High-bandwidth dynamic memory and non-volatile memory are integrated into the storage layer substrate through flip-chip technology, and the solder ball array layout ensures high-density interconnection.

[0094] Microbump and TSV interconnection: Microbump technology and TSV technology are used to connect the storage layer and the computing layer. A stable electrical connection is formed through the reflow process. Glue is filled between the storage layer substrate and the computing layer to enhance mechanical reliability.

[0095] Data channel optimization: Design the shortest data path between the storage layer and the computing layer to reduce access latency, and integrate error correction mechanisms to improve data integrity.

[0096] (4) Interface layer encapsulation and anti-interference design:

[0097] High-speed interface integration: Redundant communication interfaces (such as HSR / PRP) and universal expansion interfaces are mounted on the interface layer substrate, and signal pin alignment is ensured through precision welding.

[0098] Shielding cover installation: Cover the interface area with a metal shielding cover, fixed with laser welding technology, and use a grounding design to reduce electromagnetic radiation interference.

[0099] Coaxial signal protection: A coaxial shielding structure is implemented for high-frequency signal lines (such as Gigabit Ethernet and clock lines), and the outer layer is wrapped with absorbing material to suppress signal crosstalk.

[0100] (5) Thermal management system integration

[0101] Microchannel embedding: A microchannel heat dissipation structure is embedded between the computing layer and the substrate layer. The channel network covers the high-power consumption area, and the coolant circulation is driven by an external pump to dissipate heat.

[0102] Thermoelectric cooling (TEC) deployment: A thermoelectric cooling module is attached to the back of high-heat-density areas (such as FPGAs and security cores) to achieve local temperature control using the Peltier effect.

[0103] Thermal Interface Material (TIM) coating: Apply high thermal conductivity silicone grease between the chip and the heat dissipation structure to reduce contact thermal resistance and improve overall heat dissipation efficiency.

[0104] (6) Security and reliability reinforcement

[0105] Physical isolation implementation: deep trenches are etched in the substrate layer to isolate the security core and the power module. The trenches are filled with insulating materials and the surface is covered with a metal shielding layer to block electromagnetic leakage.

[0106] Redundant wiring design: Dual-path redundant wiring is implemented for key paths such as clock synchronization lines and power lines, integrating fault detection circuits and automatic switching logic.

[0107] Encryption module integration: Embed a hardware encryption engine in the secure core area and directly connect it to the interface layer encryption communication unit through through-silicon vias (Through-Silicon Via).

[0108] (7) Overall packaging and testing

[0109] Plastic sealing protection: Epoxy molding compound (EMC) is used to seal the entire package. The temperature and pressure are controlled during the sealing process to avoid deformation of the internal structure.

[0110] Aging test: Long-term aging test in high temperature and high humidity environment to simulate extreme working conditions and screen potential defects.

[0111] Functional Verification:

[0112] Electrical testing: Verify signal integrity, power supply stability, and redundant switching functions between layers.

[0113] Security testing: Detects encrypted communications, permission control, and anti-interference performance to ensure compliance with national encryption standards.

[0114] Thermal performance testing: Monitors the temperature distribution of the chip under different loads to verify the effectiveness of the cooling system.

[0115] (8) Final inspection and packaging

[0116] Appearance inspection: Use optical inspection equipment to check the surface integrity of the package to ensure there are no cracks, bubbles or contamination.

[0117] Performance calibration: Comprehensively calibrate the chip computing power, communication bandwidth, and security level, and generate a test report.

[0118] Anti-static packaging: Use anti-static materials to package the finished chips to avoid static damage during transportation and storage.

[0119] This embodiment further provides a chip package, which is packaged based on the above-mentioned chip package packaging method.

[0120] This approach integrates functional modules of different types into distinct functional layers, ensuring smooth and efficient data processing. Multiple functional modules are integrated into different regions of the functional layer, minimizing the impact of subsequent signal processing by functional models of different signal processing types, thereby improving signal integrity during subsequent signal transmission. The chip package is based on a vertical interconnection strategy, enabling three-dimensional stacking of multiple functional modules. Compared to existing planar packaging processes, this improves chip integration density and interconnection efficiency.

[0121] refer to Figure 6 This embodiment further provides a power grid configuration method, which configures a power grid to be processed based on the chip package as described above. The chip package includes multiple functional layers, and the multiple functional layers include a substrate layer and a computing layer. The power grid configuration method specifically includes the following steps:

[0122] Step S21: collecting target data from the power grid to be processed through the substrate layer;

[0123] Step S22: Performing a fault check on the target data through the computing layer to obtain a check result, so that the substrate layer can configure the power grid to be processed based on the check result.

[0124] In the above scheme, the chip package includes multiple functional layers, each corresponding to a different functional type. The functional layers include a substrate layer and a computing layer. The substrate layer is used to collect target data from the target power grid, enabling the computing layer to perform fault detection on the target data and obtain inspection results, thereby facilitating subsequent configuration of the target power grid based on the inspection results. The functional layer division by function type helps to improve data processing efficiency and avoid duplicate data transmission. Because the chips in the chip package have high-density and high-efficiency interconnection characteristics, the configuration process of the target power grid based on the chip package can also improve the efficiency of the power grid configuration.

[0125] In another embodiment, the substrate layer includes an AD control module and a network storm processing module. The target data includes grid parameters and compliance data. The target data is collected from the grid to be processed through the substrate layer, including:

[0126] Collect grid parameters from the power grid to be processed through the AD control module;

[0127] The network storm processing module obtains the flow data in the power grid to be processed, and filters the flow data based on preset rules to obtain the compliant data in the flow data.

[0128] It should be noted that the substrate layer can be made of a high thermal conductivity substrate material. For example, a ceramic substrate with thermal conductivity is selected to ensure that the heat generated by the power-dedicated module can be quickly conducted to the outside of the package while providing high mechanical strength and electrical insulation.

[0129] The power-specific modules include: AD control module and network storm processing module, etc. Among them:

[0130] AD control module:

[0131] It integrates high-precision analog signal acquisition and digital processing functions, supports dynamic range expansion and noise suppression, and is used for real-time monitoring of grid parameters of the power grid to be processed. Specifically, the core functional units include: High-precision ADC chip: realizes multi-channel analog signal acquisition and digitization, and supports programmable gain and sampling rate adjustment. Signal conditioning circuit: contains differential amplifiers and anti-aliasing filters to ensure signal quality. Reference voltage source: provides a highly stable reference voltage. Among them, the AD control module is used to process analog signals, while the network storm processing module is used to process digital signals. Therefore, the AD control module is distributed in the analog area of ​​the substrate layer, close to the analog power plane. The analog power supply is used to provide power for the AD control module to perform corresponding operations, while the network storm processing module is distributed in the digital area of ​​the substrate layer. The analog input is connected to the external interface through a shielded line, and the digitized digital output is connected to the main processor through a differential pair.

[0132] Network storm processing module:

[0133] Through intelligent traffic data monitoring and priority management algorithms, redundant packets are dynamically suppressed, ensuring stable utilization of communication bandwidth. Compliant data is also captured and sent to the computing layer. Specifically, the core functional units include: A network traffic processor: This implements line-speed packet processing and traffic data monitoring. A physical layer interface chip: This supports access to multiple network protocols, enabling interaction with the power grid being processed. A policy execution unit: This dynamically adjusts network policies based on traffic analysis results, suppressing redundant packets and filtering out compliant data.

[0134] Substrate Integration: Placed in the center of the substrate, close to the high-speed interconnect. Connected to the main processor via a high-speed serial interface, with the network interface extended outside the package.

[0135] It is understandable that, in addition to this, some special modules can be added to the substrate layer based on actual needs.

[0136] In another embodiment, the computing layer includes a security module, a business module, and a computing module, and the substrate layer also includes a control module. The computing layer performs a fault check on the target data to obtain a check result, so that the substrate layer configures the target power grid based on the check result, including:

[0137] Obtaining target data from the substrate layer through the security module and encrypting the target data to obtain encrypted data;

[0138] The business module is used to identify encrypted data and obtain abnormal event data;

[0139] The calculation module analyzes the abnormal event data based on the preset fault model, generates control instructions, and sends the control instructions to the substrate layer, so that the control module in the substrate layer can isolate the fault of the processed power grid based on the control instructions.

[0140] It should be noted that the reference Figure 4 ,The heterogeneous core clusters in the computing layer include:

[0141] Computing core (i.e. computing module): includes a general-purpose processor and a programmable logic unit, supporting dynamic computing power allocation and multi-task parallel processing.

[0142] Security core (i.e. security module): An independently designed security processing unit with an integrated hardware-accelerated encryption engine that provides end-to-end data encryption and rights management capabilities.

[0143] Business core (i.e. business module): A real-time processing unit optimized for smart grid protocols (such as GOOSE / SV), supporting fast task switching and low-latency response.

[0144] Vertical interconnection technology: Through silicon vias (TSVs) enable vertical stacking of computing cores, security cores, and business cores, minimizing inter-layer signal transmission paths and significantly reducing communication latency.

[0145] Shared Cache Mechanism: Utilizing high-bandwidth shared memory and silicon interposer technology, this technology enables rapid data interaction and sharing among multiple cores, improving task collaboration efficiency. The silicon interposer temporarily stores task parameters assigned by the business cores, intermediate results from the compute cores, and pre- and post-encryption data from the security cores, thus preventing frequent direct communication between cores.

[0146] The order of interaction between cores varies depending on their functions. The following takes smart grid fault detection as an example:

[0147] Data Acquisition: The substrate layer collects target data and transmits it to the security core via differential pair wiring. This includes grid parameters, such as current signals, collected by the substrate AD module, and compliance data collected from stray data used to monitor the grid by the network storm processing module.

[0148] Security processing: The security core signs and encrypts the original target data to obtain the encrypted data → the result is written to the shared cache.

[0149] Task allocation: The business core reads data from the cache and allocates abnormal event data related to the "fault event" to the computing core for fault analysis.

[0150] Feedback control: The computing core detects abnormal event data. For example, an overload is detected → a control instruction is sent to the substrate layer through the silicon interposer. For example, the control instruction is used to represent a relay disconnect instruction. It is understandable that the substrate layer also includes a control module, and the control module includes a reset controller. When an abnormality is detected, the reset controller on the substrate automatically triggers a software and hardware reset, so that the substrate layer disconnects the relay in the processing power grid based on the control instruction, achieving fault isolation and system self-recovery. Furthermore, the control module in the substrate layer may also include a resource allocation management chip. When the computing layer feedback control instruction is used to represent a resource allocation abnormality, the resource allocation management chip is used to reallocate resources to the processing power grid.

[0151] In another embodiment, the substrate layer further includes a B-code timing module, which collects target data from the power grid to be processed through the substrate layer, including:

[0152] The B-code timing module in the substrate layer receives the optical pulse signal from the power grid to be processed, so that the B-code timing module parses the optical pulse signal based on the internal protocol to obtain a synchronous clock signal, and then the B-code timing module transmits the synchronous clock signal to the computing layer, so that the substrate layer and the computing layer perform data processing based on the synchronous clock signal.

[0153] It should be noted that the substrate layer also includes a B-code timing module, which is located in the digital area along with the network storm processing module. The B-code timing module has a built-in time synchronization protocol processing unit that supports optical signal input and output, enabling high-precision clock synchronization for all network devices. Specifically, the core functional units of the B-code timing module include: a high-precision clock source that supports satellite-synchronized timing and provides a nanosecond-level time reference; an optical signal interface that enables the transmission and reception of optical pulse signals; and a protocol processing unit that parses the time synchronization protocol and generates a synchronized clock signal.

[0154] The B-code timing module is integrated into the baseboard in the digital area, close to the high-speed signal routing area. It connects to the main processor via differential signals, with a separate optical interface leading out of the package.

[0155] Furthermore, for the substrate layer, a differential signal routing design is used to optimize signal integrity, reducing signal reflections and crosstalk during transmission. A multi-layer stacked layout is used for the power and ground planes, combined with high-frequency decoupling capacitors to effectively suppress power supply noise.

[0156] refer to Figure 3 , the substrate layer partition design is as follows: simulation area ( Figure 3 Left side): AD control module, analog power plane;

[0157] Digital Area( Figure 3 Right side): B-code timing module, network storm processing module, and digital power plane.

[0158] Isolation measures: The analog and digital areas are separated by a 2mm wide isolation groove, and the groove is filled with ferrite beads to suppress high-frequency noise coupling. It is understandable that in addition to this, some dedicated modules can be added to the substrate layer based on actual needs, and other dedicated modules are placed in the digital area, such as Figure 3 shown.

[0159] Differential signal wiring specifications:

[0160] (1) Connection between AD module and B code module:

[0161] 2 pairs of differential signal lines:

[0162] Clock synchronization line: transmits sampling clock reference; status feedback line: transmits module working status.

[0163] Wiring parameters: Line width / spacing: designed according to impedance control requirements; length matching: intra-group deviation ≤5mil; reference plane: complete ground plane.

[0164] (2) The network storm processing module is connected to the main processor:

[0165] 4 pairs of high-speed differential lines: data transmission channel; data receiving channel; clock channel; control channel.

[0166] Furthermore, refer to Figure 2 , the functional layer also includes a storage layer and an interface layer, where:

[0167] Storage layer:

[0168] The storage layer integrates high-bandwidth memory (such as LPDDR5) and non-volatile memory (NOR Flash), directly interconnecting the computing layer via microbumps or TSVs to reduce data access latency. The storage layer primarily stores data processed by the computing layer.

[0169] Interface layer:

[0170] It can send data in the storage layer to the power grid to be processed, and can also receive instructions output by the power grid to be processed. The core functional units include: Multi-protocol high-speed interface: integrated redundant communication interface (such as HSR / PRP), supporting dual-path data transmission and automatic fault switching to ensure communication reliability. And add a high-speed signal interface. Extension interface: provides a variety of general interfaces, compatible with the connection requirements of smart grid terminal equipment (such as smart meters, sensors). Electromagnetic shielding is also provided: the key communication area is covered with a metal shielding cover to suppress external electromagnetic interference. Reference Figure 5 , using a coaxial shielding structure to protect high-frequency signal lines and ensure signal integrity. Key high-speed signal lines (such as Gigabit Ethernet and clock lines) use a coaxial shielding structure, with the outer layer covered with electromagnetic shielding material to suppress external interference. The outer layer of the coaxial shielding structure is the outer conductor of the shielding layer, partially using a metal shielding cover, with the shielding layer in the middle and the center conductor in the middle, which is the protected part. The signal routing layout follows strict impedance matching rules to reduce signal reflection and attenuation.

[0171] Furthermore, the physical security protection of the chip package is improved based on the preset physical security rules. For example:

[0172] Partition isolation technology: The security core, power-dedicated module, and computing core are divided into independent physical areas. Deep trench isolation (such as silicon dioxide-filled trenches) and shielding layers (metal shielding covers) are used to achieve electrical and electromagnetic isolation to prevent side-channel attacks and data leakage.

[0173] Redundant interconnect design: Critical functional paths (such as clock synchronization lines and power supply lines) use dual-path redundant wiring. Critical paths (such as clock lines and power lines) use physically separated dual channels, with the primary and backup paths having the same length and impedance. Automatic switching logic is also configured. Monitoring circuits are deployed on each critical path. The switching logic triggers conditions including: loss of signal on the primary path (such as a voltage drop to 0V); signal quality degradation (such as clock jitter >1ns); and external forced switching commands (such as fault isolation initiated by the security core). In the event of a primary path failure, the backup path seamlessly takes over, ensuring continuous system operation.

[0174] Furthermore, based on the preset data security rules, the data security of the chip package is improved, exemplarily:

[0175] Hardware-level encryption engine: The security core integrates a dedicated encryption module, supports national secret algorithm acceleration, and realizes hardware acceleration of data encryption, decryption and signature verification, avoiding performance bottlenecks and potential vulnerabilities caused by software processing.

[0176] Permission Control and Access Isolation: Dynamically manage and control the operational permissions of different business cores through hardware firewalls and memory protection units (MPUs). Sensitive data storage areas utilize independent encrypted memory, accessible only to the security core to prevent unauthorized read and write access.

[0177] Furthermore, based on the preset communication security and protocol reinforcement rules, the communication security and protocol reinforcement of the chip package are improved. For example:

[0178] Encrypted communication protocol: The interface layer integrates a hardware encryption engine to perform link layer encryption on all external communication data (such as Ethernet and RS-485), support dynamic key negotiation and update, and resist replay attacks and man-in-the-middle attacks.

[0179] Protocol anomaly detection: Built-in intelligent protocol parsing unit monitors the format and behavior pattern of communication data packets in real time, automatically filters and issues alarms for abnormal messages (such as illegal instructions and excessive data volume) to prevent network storms and malicious injections.

[0180] Furthermore, the reliability of the chip package is improved based on the preset reliability enhancement rules, exemplarily:

[0181] Fault self-healing mechanism: The chip has a built-in health monitoring unit that monitors the operating status of each module (such as voltage, temperature, and signal integrity) in real time. When an anomaly is detected, the reset controller and resource allocation management chip on the substrate automatically trigger a software or hardware reset or resource reallocation, achieving fault isolation and system self-recovery. Interaction with the target module is achieved through TSVs or microbumps.

[0182] Aging and Environmental Adaptability Design: The packaging material is made of high-temperature and moisture-resistant epoxy molding compound (EMC), combined with a sealing process to ensure the long-term stability of the chip in harsh environments (such as high humidity and temperature fluctuations). Key interconnect nodes use high-reliability solder and bonding processes to enhance mechanical strength and fatigue resistance.

[0183] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A chip package packaging method, characterized in that: include: Perform functional division on the chip set to be packaged to obtain multiple functional modules; Integrating a plurality of the functional modules into a plurality of functional layers based on the functional types of the functional modules; Integrating a plurality of the functional modules into different areas of the functional layer based on the signal processing types of the functional modules; Based on a preset vertical interconnection strategy, communication and interconnection between different functional layers are achieved to obtain a chip package.

2. The chip package packaging method according to claim 1, wherein: The chip set to be packaged includes a plurality of chips to be packaged, and the communication interconnection between different functional layers is achieved based on a preset vertical interconnection strategy to obtain a chip package, including: placing the plurality of functional modules on the plurality of functional layers respectively; Etching on the functional layer to obtain a through hole, and filling the through hole with a conductive material; The chips to be packaged are aligned between any two adjacent functional layers so that the functional layers communicate with each other through the conductive material in the through-holes.

3. The chip package packaging method according to claim 2, wherein: The step of aligning the chips to be packaged between any two adjacent functional layers so that the functional layers communicate with each other through the conductive material in the through-holes comprises: Depositing metal on the chip to be packaged on the functional layer, and performing photolithography and etching on the deposited metal to form bumps; The chips to be packaged are aligned between any two adjacent functional layers so that the functional layers communicate with each other based on the bumps and the conductive materials in the through holes.

4. The chip package packaging method according to claim 1, wherein: The communication interconnection between the different functional layers is realized based on a preset vertical interconnection strategy to obtain a chip package, including: A micro-channel device is provided between the functional layers, so that the micro-channel device can dissipate heat between the functional layers based on circulating cooling liquid.

5. The chip package packaging method according to claim 4, characterized in that: The communication interconnection between the different functional layers is realized based on a preset vertical interconnection strategy to obtain a chip package, including: Thermally conductive silicone grease is applied between the chip to be packaged and the microfluidic channel device.

6. A chip package, characterized in that: The chip package is obtained by packaging based on the chip package packaging method according to any one of claims 1 to 5.

7. A power grid configuration method, characterized in that: The power grid to be processed is configured based on the chip package according to claim 6, wherein the chip package includes multiple functional layers, and the multiple functional layers include a substrate layer and a computing layer. The power grid configuration method specifically includes the following steps: collecting target data from the power grid to be processed through the substrate layer; The target data is checked for faults by the computing layer to obtain a check result, so that the substrate layer configures the power grid to be processed based on the check result.

8. A power grid configuration method according to claim 7, characterized in that: The substrate layer includes an AD control module and a network storm processing module. The target data includes grid parameters and compliance data. The target data is collected from the grid to be processed through the substrate layer, including: Collecting the grid parameters from the grid to be processed through the AD control module; The flow data in the to-be-processed power grid is acquired through the network storm processing module, and the flow data is filtered based on preset rules to obtain the compliance data in the flow data.

9. A power grid configuration method according to claim 7, characterized in that: The computing layer includes a security module, a business module, and a computing module. The substrate layer also includes a control module. The computing layer performs a fault check on the target data to obtain a check result, so that the substrate layer configures the power grid to be processed based on the check result, including: Acquiring the target data from the substrate layer through the security module, and encrypting the target data to obtain encrypted data; The business module is used to perform data identification on the encrypted data to obtain abnormal event data; The calculation module analyzes the abnormal event data based on a preset fault model, generates a control instruction, and sends the control instruction to the substrate layer, so that the control module in the substrate layer isolates the fault of the power grid to be processed based on the control instruction.

10. A power grid configuration method according to claim 7, characterized in that: The substrate layer further includes a B-code timing module. The target data collected from the power grid to be processed through the substrate layer includes: The B-code timing module in the substrate layer receives an optical pulse signal from the power grid to be processed, so that the B-code timing module parses the optical pulse signal based on an internal protocol to obtain a synchronous clock signal, and then the B-code timing module transmits the synchronous clock signal to the computing layer, so that the substrate layer and the computing layer perform data processing based on the synchronous clock signal.

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