Display device and method of manufacturing same

Abstract

A display device and a method of manufacturing the same are provided. The display device includes a first barrier layer disposed on a substrate, a lower metal layer disposed on the first barrier layer, and a semiconductor layer disposed on the lower metal layer. In a cross-sectional view, the lower metal layer includes a first portion spaced apart from the semiconductor layer and a second portion close to the semiconductor layer, in a planar view, an area of the second portion is smaller than an area of the first portion, and a side of the semiconductor layer and a side of the second portion adjacent to the semiconductor layer are parallel to each other.

Description

Technical Field

[0001] The present disclosure relates to a display device configured to control an excimer laser annealing process and a method of manufacturing the display device by controlling the excimer laser annealing process. Background Art

[0002] Excimer laser annealing is used to convert the amorphous silicon in thin-film transistors into low-temperature polysilicon (LTPS). LTPS has a more regular silicon composition than amorphous silicon. Therefore, electrons can move more easily in LTPS than in amorphous silicon. In other words, electron mobility is higher in LTPS than in amorphous silicon. Because high electron mobility facilitates the movement of power and data, LTPS facilitates the realization of high-resolution displays with thin bezels and low power consumption. Summary of the Invention

[0003] Embodiments relate to a display device configured to control an excimer laser annealing process and a method of manufacturing the display device by controlling the excimer laser annealing process.

[0004] A display device according to an embodiment of the present disclosure may include a first barrier layer disposed on a substrate, a lower metal layer disposed on the first barrier layer, and a semiconductor layer disposed on the lower metal layer. In a cross-sectional view, the lower metal layer may include a first portion spaced apart from the semiconductor layer and a second portion adjacent to the semiconductor layer. In a plan view, an area of ​​the second portion may be smaller than an area of ​​the first portion, and a side of the semiconductor layer and a side of the second portion adjacent to the semiconductor layer may be parallel to each other.

[0005] The display device may further include a buffer layer disposed between the semiconductor layer and the lower metal layer.

[0006] The display device may further include a second barrier layer disposed between the lower metal layer and the buffer layer.

[0007] In a cross-sectional view, the buffer layer may have a thickness of about 1 to about 4 times that of the lower metal layer.

[0008] In plan view, the second portion may have an additional area.

[0009] In a cross-sectional view, the first portion and the second portion may be continuous.

[0010] In a cross-sectional view, the second portion may include an inclined surface at the end.

[0011] The angle of the inclined surface may be in the range of about 30 degrees to about 60 degrees.

[0012] In a cross-sectional view, the first portion and the second portion may be spaced apart from each other.

[0013] The display device may further include a third barrier layer disposed between the first portion and the second portion.

[0014] A method for manufacturing a display device according to an embodiment of the present disclosure may include forming a first barrier layer on a substrate, forming a lower metal layer on the first barrier layer, and forming a semiconductor layer on the lower metal layer. Forming the semiconductor layer on the lower metal layer may include applying the semiconductor layer on the lower metal layer and simultaneously irradiating a flat surface and an inclined surface of the semiconductor layer with laser light.

[0015] The incident angle of the laser light may be in the range of about 0 degrees to about 80 degrees.

[0016] The inclined surface may have a higher height than the flat surface.

[0017] In a cross-sectional view, the lower metal layer includes a first portion spaced apart from the semiconductor layer and a second portion close to the semiconductor layer, and in a plan view, an area of ​​the second portion may be smaller than an area of ​​the first portion.

[0018] One side of the semiconductor layer and a side of the second portion adjacent to the semiconductor layer may be parallel to each other.

[0019] Forming the lower metal layer may include forming a step in the lower metal layer using a photoresist.

[0020] The photoresist may include steps.

[0021] The method may further include forming a buffer layer between the semiconductor layer and the lower metal layer.

[0022] The method may further include forming a second barrier layer between the lower metal layer and the buffer layer.

[0023] In a cross-sectional view, the buffer layer may have a thickness of about 1 to about 4 times that of the lower metal layer.

[0024] According to an embodiment, an inclined surface may be formed in a semiconductor layer using a stepped lower metal layer.

[0025] By performing the excimer laser annealing process using the inclined surface of the semiconductor layer, the regularity of silicon particles can be improved at specific positions of the semiconductor layer.

[0026] As a result, electron mobility at a specific position in the semiconductor layer can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 Schematic diagram showing an excimer laser annealing process of a comparative example.

[0028] Figure 2 is a schematic cross-sectional view illustrating the creation of an inclined surface in a semiconductor layer by a lower metal layer.

[0029] Figure 3 is a schematic cross-sectional view illustrating an excimer laser annealing process performed on a semiconductor layer having an inclined surface.

[0030] Figures 4 to 8 This is a photo of the semiconductor layer.

[0031] Figure 9 is an enlarged schematic cross-sectional view showing the shape of the lower metal layer.

[0032] Figure 10 is a flow chart of a method of manufacturing a display device including a lower metal layer and a semiconductor layer on a substrate.

[0033] Figure 11A 、 Figure 11B 、 Figure 11C and Figure 11D are schematic cross-sectional views sequentially illustrating a method of manufacturing a stepped lower metal layer according to an embodiment.

[0034] Figure 12A 、 Figure 12B 、 Figure 12C 、 Figure 12D and Figure 12E are schematic cross-sectional views sequentially illustrating a method of manufacturing a stepped lower metal layer according to another embodiment.

[0035] Figure 13 is a schematic cross-sectional view showing a portion of a display device including a plurality of lower metal layers.

[0036] Figure 14 Is manufactured based on Figure 13 Flowchart of a method for displaying a device according to an embodiment of the present invention.

[0037] Figure 15 is a schematic diagram of an equivalent circuit of a pixel according to an embodiment.

[0038] Figure 16 is a schematic timing diagram of signals applied to one pixel according to an embodiment.

[0039] Figure 17 is a plan view showing a partial configuration of a display device according to an embodiment.

[0040] Figure 18 It is along Figure 17 Schematic cross-sectional view taken along line AA'.

[0041] Figure 19 is a plan view of a display device including only a semiconductor layer and a lower metal layer according to an embodiment.

[0042] Figure 20 yes Figure 19An enlarged plan view of a portion of the .

[0043] Figure 21 is a schematic cross-sectional view illustrating a method of manufacturing a semiconductor layer after an excimer laser annealing process.

[0044] Figure 22 is a plan view of a display device including only a semiconductor layer and a lower metal layer according to another embodiment.

[0045] Figure 23 is a plan view of a display device including only a semiconductor layer and a lower metal layer according to another embodiment.

[0046] Figure 24 is a plan view of a display device including only a semiconductor layer and a lower metal layer according to another embodiment. DETAILED DESCRIPTION

[0047] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement them. The present disclosure can be implemented in many different forms and is not limited to the embodiments described herein.

[0048] In order to clearly explain the present disclosure, parts that are irrelevant to the description are omitted, and the same or similar components are given the same reference numerals throughout the specification.

[0049] The use of cross hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Thus, unless otherwise stated, the presence or absence of cross hatching or shading does not convey or indicate a preference or requirement for a particular material, material properties, size, proportion, commonality between the elements shown, and / or any other characteristics, attributes, properties, etc. of the elements. In addition, in the drawings, the size and relative sizes of the elements may be exaggerated for clarity and / or descriptive purposes. When embodiments can be implemented differently, the specific process sequence may be performed differently from the described sequence. For example, two consecutively described processes may be performed substantially simultaneously or in an order opposite to the described sequence.

[0050] When an element, such as a layer, is referred to as being "on," "connected to," or "coupled to" another element or layer, it can be directly on, directly connected to, or coupled to the other element or layer, or there can be intervening elements or layers. However, when an element or layer is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there can be no intervening elements or layers. For this purpose, the term "connected" can refer to physical, electrical, and / or fluid connections, with or without intervening elements. Furthermore, when an element is referred to as being "in contact" or "contacted" with another element, or similar expressions, the element can be "electrically in contact" or "physically in contact" with the other element; or "indirectly in contact" or "directly in contact" with the other element.

[0051] Spatially relative terms, such as "below," "beneath," "below," "above," "upper," "upper," "higher," "side" (e.g., as in "sidewall"), and the like, may be used herein for descriptive purposes and thereby describe the relationship of one element to another element(s) as shown in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientations depicted in the accompanying drawings. For example, if the device in the drawings is turned over, an element described as being "below" or "beneath" other elements or features would subsequently be oriented "above" the other elements or features. Thus, the exemplary term "below" is capable of encompassing both above and below orientations. Furthermore, the device may be oriented in other ways (e.g., rotated 90 degrees or at other orientations), and thus, the spatially relative descriptors used herein are to be interpreted accordingly.

[0052] The technical terms used herein are for the purpose of describing particular embodiments and are not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. In addition, the terms "comprises," "comprising," "includes," and / or "including," when used in this specification, specify the presence of stated features, wholes, steps, operations, elements, components, and / or clusters thereof, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or clusters thereof.

[0053] Throughout the specification and claims, for purposes of its meaning and interpretation, the phrase "at least one of" is intended to include the meaning of "at least one selected from the group of." For example, "at least one of A and B" is understood to mean "A, B, or A and B." Throughout the specification and claims, for purposes of its meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or." For example, "A and / or B" is understood to mean "A, B, or A and B." The terms "and" and "or" may be used in conjunction or disjunction and are understood to be equivalent to "and / or."

[0054] Furthermore, throughout the specification, when “in a plan view” is mentioned, this means when the target portion is viewed from above, and when “in a sectional view” is mentioned, this means when the cross section of the target portion is cut vertically and viewed from the side.

[0055] As used herein, "about" or "approximately" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the measurements in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0056] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used have the same meaning as commonly understood by those skilled in the art to which this disclosure pertains. It will also be understood that, unless clearly defined otherwise in the specification, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense.

[0057] Figure 1 Schematic diagram showing an excimer laser annealing process of a comparative example.

[0058] Excimer laser annealing (ELA) is a laser process used to create low-temperature polycrystalline silicon (LTPS) electronic circuit layers. Using ELA, amorphous silicon can be converted into LTPS. Amorphous silicon is referred to as a-Si, and LTPS is referred to as Poly-Si. Applying ELA to thin-film transistors (TFTs) can improve their performance.

[0059] The excimer laser annealing process may be performed by irradiating laser light to the semiconductor layer ACT. Figure 1 Schematically shows the laser irradiation to the semiconductor layer ACT. Figure 1In the figure, the arrow located at the boundary between amorphous silicon a-Si and low-temperature polycrystalline silicon (Poly-Si) indicates that laser light is being applied. The arrow moving from left to right indicates the direction of laser light movement. The direction of laser light movement can indicate the relative movement between the laser light and the semiconductor layer ACT. As the laser light moves to the right, the amorphous silicon a-Si can be transformed into low-temperature polycrystalline silicon (Poly-Si).

[0060] Compared to amorphous silicon (a-Si), the silicon particles in low-temperature polycrystalline silicon (Poly-Si) can have a more regular arrangement. Therefore, electrons can move more easily in low-temperature polycrystalline silicon (Poly-Si) than in amorphous silicon (a-Si). This is referred to as high electron mobility. Because high electron mobility facilitates the movement of power and data, low-temperature polycrystalline silicon can facilitate the realization of high-resolution, thin-frame, and low-power display devices.

[0061] Figure 2 is a schematic cross-sectional view illustrating the creation of an inclined surface in a semiconductor layer by a lower metal layer. Figure 2 is an enlarged view of a portion of a display device 10 according to an embodiment. In an embodiment, the display device 10 may include a substrate SUB, a first barrier layer BL1, a lower metal layer BML, a second barrier layer BL2, a buffer layer BF, and a semiconductor layer ACT. The buffer layer BF may include a first buffer layer BFL1 and a second buffer layer BFL2. In an embodiment, the display device 10 may exclude some of the substrate SUB, the first barrier layer BL1, the lower metal layer BML, the second barrier layer BL2, the buffer layer BF, and the semiconductor layer ACT, and may include other layers.

[0062] A first barrier layer BL1 may be disposed on the substrate SUB, and a lower metal layer BML may be disposed on the first barrier layer BL1. A second barrier layer BL2 may be disposed on the first barrier layer BL1 and the lower metal layer BML, a first buffer layer BFL1 may be disposed on the second barrier layer BL2, the first buffer layer BFL1 may be disposed on the first barrier layer BL1 and the lower metal layer BML, and the second buffer layer BFL2 may be disposed on the first buffer layer BFL1. Furthermore, a semiconductor layer ACT may be disposed on the second buffer layer BFL2.

[0063] The substrate SUB may be made of a rigid material such as glass. In another embodiment, the substrate SUB may be made of a flexible material such as plastic or polyimide. When the substrate SUB includes a flexible material, the substrate SUB may have a two-layer structure of polyimide and a barrier layer formed of an inorganic insulating material on the polyimide.

[0064] The first barrier layer BL1, the second barrier layer BL2 and the buffer layer BF may be made of an inorganic material (such as silicon oxide SiO x , silicon nitride SiN x、Silicon Oxynitride SiO x N y or aluminum oxide AlO x and the like) and may form an inorganic layer, and may also include an organic insulating material such as polyimide and polyacrylic acid (with epoxy resin added).

[0065] The buffer layer BF can block impurities from being transferred from the substrate SUB to the upper layer of the buffer layer BF (particularly the semiconductor layer ACT), prevent the degradation of the characteristics of the semiconductor layer ACT, and relieve stress. When an excimer laser annealing process is performed on the semiconductor layer ACT, a large amount of heat may be generated, and when the heat is transferred to the lower metal layer BML, peeling of the lower metal layer BML may occur. Therefore, the buffer layer BF disposed between the semiconductor layer ACT and the lower metal layer BML may need to be sufficiently thick. For example, the thickness of the buffer layer BF may be about 1 to about 4 times the thickness of the lower metal layer BML.

[0066] The lower metal layer BML may include a metal such as copper (Cu), molybdenum (Mo), aluminum (Al), titanium (Ti), or an alloy thereof. The lower metal layer BML may additionally include amorphous silicon (a-Si) and may have a single layer or multiple layers. The lower metal layer BML may include a light-blocking material and may prevent light from entering the semiconductor layer ACT.

[0067] The semiconductor layer ACT may include a plurality of doped regions doped with impurities and a channel region between the doped regions. The semiconductor layer ACT may include at least one of polycrystalline silicon and an oxide semiconductor. When the semiconductor layer ACT is made of an oxide semiconductor, a separate protective layer may be added to protect the oxide semiconductor material, which is susceptible to environmental factors (such as high temperature).

[0068] Figure 2 The schematic diagram shows the formation of steps in the semiconductor layer ACT when the lower metal layer BML is disposed on the first barrier layer BL1. The formation of steps in the semiconductor layer ACT may mean that a low-height portion and a high-height portion appear in the semiconductor layer ACT. A sloped surface may be formed between the low-height portion and the high-height portion of the semiconductor layer ACT. The sloped surface of the semiconductor layer ACT may have an angle. For example, based on the flat surface of the low-height portion of the semiconductor layer ACT, the angle of the slope may be greater than 0 degrees and less than 90 degrees. Since the lower metal layer BML has a certain thickness or greater to block light and is only disposed on a portion of the first barrier layer BL1, the second barrier layer BL2 disposed on the lower metal layer BML may have a stepped shape. As the second barrier layer BL2 has a stepped shape, the buffer layer BF may also have a stepped shape, and the semiconductor layer ACT may also have a stepped shape. The steps may have a shape in which a portion of the layer is raised in a cross-sectional view.

[0069] Figure 3 is a schematic cross-sectional view illustrating an excimer laser annealing process performed on a semiconductor layer having an inclined surface.

[0070] Figure 3 The schematic diagram shows an excimer laser annealing process performed by irradiating a semiconductor layer ACT on a buffer layer BF with a laser. The laser can simultaneously irradiate the inclined surface and the flat surface of the semiconductor layer ACT. When the laser irradiates the inclined surface and the flat surface simultaneously, the inclined surface may have a height higher than the flat surface. In other words, the flat surface may be a portion having a height lower than the inclined surface. This is because, as will be described below, the excimer laser annealing process can be performed using interference between incident light from the laser incident on the flat surface and reflected light from the laser reflected from the inclined surface. Amorphous silicon a-Si can be converted into low-temperature polycrystalline silicon Poly-Si through the excimer laser annealing process.

[0071] This is performed by irradiating a flat semiconductor layer ACT with laser light. Figure 1 The excimer laser annealing process of the comparative example shown in FIG. Figure 1 In the excimer laser annealing process of the comparative example shown in , the laser is irradiated in a direction perpendicular to the flat semiconductor layer ACT. However, Figure 3 The excimer laser annealing process of the embodiment shown in can use the inclined surface of the semiconductor layer ACT formed by the lower metal layer BML. The laser can be irradiated at an incident angle according to the angle formed by the inclined surface of the semiconductor layer ACT, and may not be irradiated in a direction perpendicular to the surface of the semiconductor layer ACT. In another embodiment, Figure 3 The laser in the embodiment shown in the figure may be irradiated in a direction perpendicular to the surface of the semiconductor layer ACT. The angle of incidence of the laser in the embodiment of the present disclosure is not limited. In an embodiment, the angle of incidence of the laser may be in the range of about 0 degrees to about 80 degrees.

[0072] The laser light irradiated to the semiconductor layer ACT to perform the excimer laser annealing process can be divided into incident light ( Figure 3 ①) and the reflected light generated by the inclined surface of the semiconductor layer ACT ( Figure 3 ② in the figure). The location where the low-temperature polysilicon Poly-Si is to be formed may be the flat surface of the semiconductor layer ACT. Figure 3 The incident light and reflected light of the laser in are shown as thick arrows. The incident light is represented as a dotted line, and the reflected light is represented as a solid line. Figure 3In the diagram, thin lines drawn perpendicular to the directions of travel of incident and reflected light represent the same phase in both incident and reflected light. For example, the thin lines may indicate where the phase of the laser light is at a peak. The peaks of the incident and reflected light may interfere, producing constructive interference that allows the silicon particles to achieve regularity.

[0073] By using the inclined surface generated by the lower metal layer BML in the semiconductor layer ACT, low-temperature polysilicon (Poly-Si) can be formed at a specific position of the semiconductor layer ACT. For example, in a plan view, the second portion BML2 ( Figure 9 ) can be formed adjacent to the location where low-temperature polycrystalline silicon (Poly-Si) is to be formed. A second portion BML2 of the lower metal layer BML may be close to the semiconductor layer ACT in a cross-sectional view, and a step in the lower metal layer BML may be caused by the second portion BML2. By performing an excimer laser annealing process using the inclined surface of the semiconductor layer ACT resulting from the step of the lower metal layer BML, low-temperature polycrystalline silicon (Poly-Si) can be formed at a specific location in the semiconductor layer ACT. This will be explained in detail below.

[0074] The low-temperature polysilicon (Poly-Si) formed using the steps in the semiconductor layer ACT can have superior electron mobility compared to low-temperature polysilicon (Poly-Si) formed on a flat semiconductor layer ACT. This means that when the low-temperature polysilicon (Poly-Si) is formed using the steps in the semiconductor layer ACT, the silicon particles will have better regularity than the low-temperature polysilicon (Poly-Si) of the comparative example.

[0075] Hereinafter, it will be explained that the low-temperature polysilicon (Poly-Si) particles formed using the step have better regularity than the comparative example.

[0076] Figures 4 to 8 This is a photo of the semiconductor layer.

[0077] Figure 4 is a photograph showing that the silicon of the semiconductor layer ACT has a lattice-like periodicity by the excimer laser annealing process, and Figure 5 3 is a photograph showing that silicon of the semiconductor layer ACT has linear periodicity through an excimer laser annealing process.

[0078] Figure 4 and Figure 5 An enlarged view of a semiconductor layer ACT is shown, in which amorphous silicon a-Si has been converted to low-temperature polycrystalline silicon Poly-Si through an excimer laser annealing process. Thus, the purpose of the excimer laser annealing process can be to improve electron mobility by ensuring that the silicon particles in the semiconductor layer ACT have a regular periodicity. By enhancing the regularity of the silicon particles, electron mobility can be improved.

[0079] Figure 6 3 is a photograph showing that the semiconductor layer ACT of the comparative example includes both periodic portions and non-periodic portions.

[0080] As in Figure 1 In the comparative example of , in the case of performing the excimer laser annealing process by irradiating laser light to the flat surface of the semiconductor layer ACT without using an inclined surface, silicon particles of the semiconductor layer ACT may have both periodic and non-periodic regions. Figure 6 This is an enlarged photograph of the semiconductor layer ACT of the comparative example. Figure 6 A in represents the periodic part of the silicon particle, and Figure 6 The B in the figure represents the non-periodic portion of the silicon particle.

[0081] Although excimer laser annealing (ELA) is performed on the semiconductor layer ACT, irregularities may still appear in certain parts of the semiconductor layer ACT. The excimer laser annealing process can induce regularity in the silicon particles due to interference between the incident light entering the semiconductor layer ACT and the reflected light and scattered light from the surface of the semiconductor layer ACT. For example, as in the comparative example, the case where laser light is irradiated onto a flat semiconductor layer ACT is explained. Although it appears to be a flat semiconductor layer ACT, in an enlarged view, the surface may not be smooth but may have an uneven shape. Because the surface of the semiconductor layer ACT has an irregular shape, the laser light may be scattered or reflected. The excimer laser annealing process can use the interference between the incident light, reflected light, and scattered light to regularly arrange the silicon particles. However, the irregularity of the shape on the surface of the semiconductor layer ACT may be irregular and may not be a controllable factor. Therefore, when the excimer laser annealing process is performed, the silicon particles may have periodicity at one position of the semiconductor layer ACT, but the silicon particles may have non-periodicity at another position of the semiconductor layer ACT. Controlling such periodicity and non-periodicity may be difficult when performing an excimer laser annealing process.

[0082] In the case where the semiconductor layer ACT has such a non-periodicity, the electron mobility of the semiconductor layer ACT can be approximately 60 cm 2 / V·s to about 90cm 2 / V·s range.

[0083] Figure 7 3 is a photograph showing that silicon of the semiconductor layer ACT changes its characteristics due to its non-periodicity and appears as streaks.

[0084] Figure 8 3 is a photograph showing that arrangement of silicon crystals has periodicity at specific positions in the semiconductor layer ACT.

[0085] When an excimer laser annealing process is performed on a flat semiconductor layer ACT as in the comparative example, it may be difficult to control the arrangement of silicon particles so that they have periodicity at specific positions. This is because the shape of the surface of the semiconductor layer ACT is irregular and cannot be controlled. However, in the embodiment of the present disclosure, since the excimer laser annealing process is controlled using the inclined surface of the semiconductor layer ACT, the reflected light that interferes with the incident light can be controlled. The reflected light generated using the inclined surface of the semiconductor layer ACT may have greater energy than the reflected light and scattered light generated by the unevenness of the semiconductor layer ACT. Therefore, if the excimer laser annealing process is performed using steps in the semiconductor layer ACT, an array of silicon particles with better regularity can be formed.

[0086] Figure 8 The P in the figure is low-temperature polysilicon (Poly-Si), which is formed by the curved periodicity of silicon particles formed by the inclined surface of the semiconductor layer ACT. In this way, by using the steps of the lower metal layer BML, a semiconductor layer ACT with a specific shape and excellent properties can be formed at a specific location.

[0087] Figure 9 is an enlarged schematic cross-sectional view showing the shape of the lower metal layer.

[0088] A first barrier layer BL1 may be formed on the substrate SUB, and a lower metal layer BML may be formed on the first barrier layer BL1. Figure 9 Although not shown in the drawings, the buffer layer BF and the barrier layer may be formed on the lower metal layer BML, and the semiconductor layer ACT may be formed on the lower metal layer BML.

[0089] Figure 9 The lower metal layer BML in the embodiment may have a stepped single-layer structure in a cross-sectional view. The lower metal layer BML may include an inclined surface. The shape of the lower metal layer BML will be described in detail. The stepped lower metal layer BML may mean that the lower metal layer BML is divided into a high-height region and a low-height region in a cross-sectional view. The high-height region may be the upper surface of the second portion BML2, and the low-height region may be the exposed upper surface of the first portion BML1. An inclined surface may be formed between the high-height region and the low-height region in the lower metal layer BML. The inclined surface may be a plane. Figure 9 The angle a in FIG. 1 represents the angle of the inclined surface. The angle of the slope is not limited. For example, the angle of the inclined surface can be approximately 90 degrees. In a cross-sectional view, the lower metal layer BML can include a first portion BML1 away from the semiconductor layer ACT and a second portion BML2 closer to the semiconductor layer ACT. Figure 9The diagram schematically illustrates a first portion BML1 and a second portion BML2 of the lower metal layer BML. The first portion BML1 may be close to the substrate SUB, while the second portion BML2 may be farther from the substrate SUB. For example, in a cross-sectional view, a region of the lower metal layer BML below a certain height from the first barrier layer BL1 may be the first portion BML1, and a region of the lower metal layer BML above a certain height from the first barrier layer BL1 may be the second portion BML2.

[0090] The second portion BML2 can be controlled to form a step in the semiconductor layer ACT. By controlling the position of the second portion BML2 on the first portion BML1, better low-temperature polysilicon (Poly-Si) can be formed at a specific position of the semiconductor layer ACT.

[0091] The first portion BML1 may be provided to prevent light from being incident on the semiconductor layer ACT.

[0092] Therefore, in a plan view, an area of ​​the second portion BML2 may be smaller than an area of ​​the first portion BML1 .

[0093] In a cross-sectional view, the lower metal layer BML may be stepped, and the second portion BML2 may include an inclined surface at an end portion. Figure 9 As seen in FIG, the end portion of the second portion BML2 may be a portion where the second portion BML2 no longer extends to the left. Figure 9 , the right end portion of the second portion BML2 is not shown, but the second portion BML2 may have a right end portion. The end portion of the second portion BML2 may mean only one end or both ends. According to the angle of the inclined surface at the end portion of the second portion BML2, the angle of the inclined surface of the semiconductor layer ACT can be controlled. In an embodiment, the angle a of the inclined surface of the second portion BML2 may be in the range of about 15 degrees to about 75 degrees. For example, the angle a of the inclined surface of the second portion BML2 may be in the range of about 30 degrees to about 60 degrees. If the angle of the inclined surface of the second portion BML2 is close to 0 degrees, a step may not be formed in the lower metal layer BML, or only a step of minimum height may be formed. If the angle of the inclined surface of the second portion BML2 is close to 90 degrees, it may be difficult to form the reflected light of the laser required in the excimer laser annealing process.

[0094] exist Figure 9 , the flat surface b may be a portion of the first portion BML1 that does not overlap with the second portion BML2 in a cross-sectional view. Figure 9 The flat surface b in may be a portion of the first portion BML1 that is not covered by the second portion BML2. Figure 9The flat surface b in the first portion BML1 may be a flat surface adjacent to the inclined surface of the second portion BML2. An excimer laser annealing process using the inclined surface of the semiconductor layer ACT may be performed on a region of the semiconductor layer ACT that overlaps the inclined surface of the second portion BML2 and the adjacent flat surface b of the first portion BML1. Since the semiconductor layer ACT can be formed in its final form after the excimer laser annealing process is performed on the applied semiconductor layer ACT, the flat surface b of the first portion BML1 adjacent to the inclined surface of the second portion BML2 can have an appropriate length that is neither too short nor too long.

[0095] In a cross-sectional view, a length of a flat surface b of the first portion BML1 adjacent to the inclined surface of the second portion BML2 may be determined according to an angle a of the inclined surface of the second portion BML2 .

[0096] A length of the flat surface b of the first portion BML1 adjacent to the inclined surface of the second portion BML2 may be determined according to the shape of the semiconductor layer ACT.

[0097] Figure 10 is a flow chart of a method of manufacturing a display device including a lower metal layer and a semiconductor layer on a substrate.

[0098] Figure 10 Part of a process for manufacturing the display device 10 is shown. First, step S10 of forming a first barrier layer BL1 on a substrate SUB may be performed. Step S20 may be performed to form a lower metal layer BML on the first barrier layer BL1, and step S30 may be performed to form a second barrier layer BL2 on the lower metal layer BML and the first barrier layer BL1. Step S40 of forming a first buffer layer BFL1 on the second barrier layer BL2 may be performed, and step S50 of forming a second buffer layer BFL2 on the first buffer layer BFL1 may be performed. Step S60 of forming a semiconductor layer ACT on the second buffer layer BFL2 may be performed. Stacking a plurality of conductive layers, insulating layers, and light emitting layers EML (on the semiconductor layer ACT) may be performed. Figure 17 and Figure 18 ).

[0099] Each step may be omitted as needed, and a step of forming a new layer may be performed as needed.

[0100] The order of the steps can be changed as desired.

[0101] 11A to 11D are schematic cross-sectional views sequentially illustrating a method of manufacturing a stepped lower metal layer according to an embodiment.

[0102] about Figure 10In step S20 of forming the lower metal layer BML, a process of forming the stepped lower metal layer BML will be explained in detail.

[0103] like Figure 9 As shown in FIG, the lower metal layer BML may be composed of a single layer including a first portion BML1 and a second portion BML2. In a plan view, the second portion BML2 may have a smaller area than the first portion BML1. Therefore, in a cross-sectional view, the lower metal layer BML may be shaped such that the second portion BML2 protrudes above the first portion BML1.

[0104] As an embodiment of forming a step in the lower metal layer BML, a half-tone mask may be applied. The half-tone mask may consist of a portion that blocks most light, a portion that blocks only some light, and a portion that transmits most light.

[0105] 11A to 11D The method of manufacturing the stepped lower metal layer BML using the stepped photoresist PR is sequentially shown. The stepped photoresist PR can be manufactured using a technique using a half-tone mask. 11A to 11D First, a lower metal layer BML may be applied on the first barrier layer BL1, and a step-shaped photoresist PR may be placed on the applied lower metal layer BML ( Figure 11A Afterwards, primary development and etching can be performed ( Figure 11B Because of this, a portion of the lower metal layer BML may be removed. Ashing may be performed on a portion of the step-shaped photoresist PR ( Figure 11C ). As a result, only part of the photoresist PR may remain, resulting in a non-step-shaped photoresist PR. The remaining part of the photoresist PR may be used to manufacture a stepped lower metal layer BML. This may be performed by secondary development and etching ( Figure 11D ).

[0106] 12A to 12E are schematic cross-sectional views sequentially illustrating a method of manufacturing a stepped lower metal layer according to another embodiment.

[0107] 12A to 12E A method of manufacturing a stepped lower metal layer BML without using a stepped photoresist PR is shown. The stepped lower metal layer BML can be manufactured by repeatedly using a non-stepped photoresist PR. 12A to 12E First, a lower metal layer BML may be applied on the first barrier layer BL1, and a photoresist PR may be placed on the applied lower metal layer BML ( Figure 12A Afterwards, primary development and etching can be performed ( Figure 12B Because of this, part of the lower metal layer BML can be removed. The entire photoresist PR formed on the lower metal layer BML can be removed by ashing ( Figure 12CA new non-step photoresist PR can be formed on the lower metal layer BML ( Figure 12D ), and secondary development and etching can be performed ( Figure 12E ).

[0108] Manufacturing the stepped lower metal layer BML using the stepped photoresist PR may have an advantage in that the steps of removing the existing photoresist PR and forming a new photoresist PR on the lower metal layer BML may be omitted.

[0109] In the case of manufacturing the lower metal layer BML using the non-step-shaped photoresist PR, there may be an advantage in that a separate step-shaped photoresist PR is not required.

[0110] Figure 13 is a schematic cross-sectional view showing a portion of a display device including a plurality of lower metal layers.

[0111] Figure 13 Another embodiment of a lower metal layer BML for forming a semiconductor layer ACT having an inclined surface is schematically illustrated. For example, the inclined surface can be formed in the semiconductor layer ACT by using multiple lower metal layers BML. The lower metal layer BML can be formed into multiple layers and can include a first portion BML1 and a second portion BML2. In a cross-sectional view, the first portion BML1 and the second portion BML2 can be separated from each other. For example, the first portion BML1 can be a lower metal layer away from the semiconductor layer ACT, and the second portion BML2 can be a lower metal layer closer to the semiconductor layer ACT. In addition, in a cross-sectional view, the lower metal layer BML below a certain height from the first barrier layer BL1 can be the first portion BML1, and the lower metal layer BML above a certain height from the first barrier layer BL1 can be the second portion BML2.

[0112] Will describe Figure 13The display device 20 is shown in FIG. A first barrier layer BL1 may be disposed on a substrate SUB, and a first portion BML1 may be disposed on the first barrier layer BL1. The first portion BML1 disposed on the first barrier layer BL1 may be a lower metal layer BML away from the semiconductor layer ACT. A third barrier layer BL3 may be disposed on the first barrier layer BL1 and the first portion BML1, and a third buffer layer BFL3 may be disposed on the third barrier layer BL3. A fourth barrier layer BL4 may be disposed on the third buffer layer BFL3. A second portion BML2 may be disposed on the fourth barrier layer BL4. A second portion BML2 disposed on the fourth barrier layer BL4 may be a lower metal layer BML close to the semiconductor layer ACT. A second barrier layer BL2 may be disposed on the fourth barrier layer BL4 and the second portion BML2. The first buffer layer BFL1 may be disposed on the second barrier layer BL2, and the second buffer layer BFL2 may be disposed on the first buffer layer BFL1. The first buffer layer BFL1 and the second buffer layer BFL2 may form a buffer layer BF. The semiconductor layer ACT may be disposed on the buffer layer BF, and the stepped semiconductor layer ACT is caused by the second portion BML2 .

[0113] In this manner, by using a plurality of lower metal layers BML, the inclined surface position of the semiconductor layer ACT can be controlled by disposing the second portion BML2 at a specific position. Therefore, the semiconductor layer ACT having an inclined surface at a specific position can be manufactured without manufacturing a stepped single-layer lower metal layer BML.

[0114] Figure 14 Is manufactured based on Figure 13Flowchart of a method for forming a display device according to an embodiment of the present invention. First, step S100 of forming a first barrier layer BL1 on a substrate SUB may be performed. Subsequently, step S200 of forming a first portion BML1 on the first barrier layer BL1 may be performed, and step S300 of forming a third barrier layer BL3 on the first barrier layer BL1 and the first portion BML1 may be performed. Thereafter, step S400 of forming a third buffer layer BFL3 on top of the third barrier layer BL3 may be performed, and step S500 of forming a fourth barrier layer BL4 on top of the third buffer layer BFL3 may be performed. Subsequently, step S600 of forming a second portion BML2 on the fourth barrier layer BL4 may be performed, and step S700 of forming a second barrier layer BL2 on the fourth barrier layer BL4 and the second portion BML2 may be performed. Step S800 of forming a first buffer layer BFL1 on the second barrier layer BL2 may be performed, and step S900 of forming a second buffer layer BFL2 on the first buffer layer BFL1 may be performed. The first buffer layer BFL1 and the second buffer layer BFL2 may form a buffer layer BF. Subsequently, step S1000 of forming a semiconductor layer ACT on the second buffer layer BFL2 may be performed. The stepped semiconductor layer ACT may include an inclined surface. A plurality of conductive layers, an insulating layer, and a light emitting layer EML may be stacked on the semiconductor layer ACT.

[0115] Figure 15 is a schematic diagram of an equivalent circuit of a pixel according to an embodiment.

[0116] Reference Figure 15 According to an embodiment, a display device may include a plurality of pixels PX capable of displaying an image and a plurality of signal lines 127, 151, 152, 154, 155, 171, and 172. The pixel PX may include a plurality of transistors T1, T2, T3, T4, T5, T6, and T7, and a capacitor Cst connected to the plurality of signal lines 127, 151, 152, 154, 155, 171, and 172, and may include at least one light emitting diode ED. The description will be based on an embodiment in which the pixel PX includes one light emitting diode ED.

[0117] The signal lines 127 , 151 , 152 , 154 , 155 , 171 , and 172 may include an initialization voltage line 127 , a plurality of scan lines 151 , 152 , and 154 , a light emitting control line 155 , a data line 171 , and a driving voltage line 172 .

[0118] Initialization voltage line 127 can transmit initialization voltage Vint. Scan lines 151, 152, and 154 can transmit scan signals GWn, GIn, and PB, respectively. Scan signals GWn, GIn, and PB can transmit gate-on voltages and gate-off voltages that can turn on / off transistors T2, T3, T4, and T7 included in pixel PX.

[0119] The scan lines 151, 152, and 154 connected to one pixel PX may include a first scan line 151 capable of transmitting a scan signal GWn, a second scan line 152 capable of transmitting a scan signal GIn having a different gate-on timing than the first scan line 151, and a third scan line 154 capable of transmitting a bypass signal PB. An embodiment will be described in which the second scan line 152 transmits a gate-on voltage at an earlier timing than the first scan line 151. For example, if the scan signal GWn is the nth scan signal Sn (n is a natural number of 1 or greater) among the scan signals applied during one frame, the scan signal GIn may be the n-1th scan signal, which is a front-end scan signal such as S(n-1), and the bypass signal PB may be the n-1th scan signal S(n-1). However, the present disclosure is not limited thereto, and the bypass signal PB may be a scan signal different from the n-1th scan signal S(n-1).

[0120] The light emission control line 155 may transmit a control signal. For example, the light emission control signal EM may control the light emission of the light emitting diode ED included in the pixel PX. The control signal transmitted by the light emission control line 155 may transmit a gate-on voltage and a gate-off voltage and may have a different waveform from the scan signal transmitted by the scan lines 151, 152, and 154.

[0121] The data line 171 may transmit a data signal Dm, and the driving voltage line 172 may transmit a driving voltage ELVDD. The data signal Dm may have different voltage levels according to an image signal input to the display device, and the driving voltage ELVDD may have a substantially constant level.

[0122] Although not shown, the display device may further include a driver that transmits signals to the signal lines 127 , 151 , 152 , 154 , 155 , 171 , and 172 .

[0123] The transistors T1 , T2 , T3 , T4 , T5 , T6 , and T7 included in the pixel PX may include a driving transistor T1 , a second transistor T2 , a third transistor T3 , a fourth transistor T4 , a fifth transistor T5 , a sixth transistor T6 , and a seventh transistor T7 .

[0124] The first scan line 151 can transmit the scan signal GWn to the second transistor T2 and the third transistor T3, the second scan line 152 can transmit the scan signal GIn to the fourth transistor T4, the third scan line 154 can transmit the bypass signal PB to the seventh transistor T7, and the light emitting control line 155 can transmit the light emitting control signal EM to the fifth transistor T5 and the sixth transistor T6.

[0125] The gate electrode G1 of the driving transistor T1 can be connected to one end of the capacitor Cst (e.g., the second storage electrode E2) via the driving gate node GN, the first electrode Ea1 of the driving transistor T1 can be connected to the driving voltage line 172 via the fifth transistor T5, and the second electrode Eb1 of the driving transistor T1 can be connected to the anode of the light emitting diode ED via the sixth transistor T6. The driving transistor T1 can receive the data signal Dm transmitted by the data line 171 according to the switching operation of the second transistor T2 and supply the driving current Id to the light emitting diode ED.

[0126] A gate electrode G2 of the second transistor T2 may be connected to the first scan line 151, a first electrode Ea2 of the second transistor T2 may be connected to the data line 171, and a second electrode Eb2 of the second transistor T2 may be connected to the first electrode Ea1 of the driving transistor T1 and may be connected to the driving voltage line 172 via the fifth transistor T5. The second transistor T2 may be turned on according to the scan signal GWn received through the first scan line 151 and may transfer the data signal Dm transmitted from the data line 171 to the first electrode Ea1 of the driving transistor T1.

[0127] The gate electrode G3 of the third transistor T3 may be connected to the first scan line 151, and the first electrode Ea3 of the third transistor T3 may be connected to the second electrode Eb1 of the driving transistor T1 and may be connected to the anode of the light emitting diode ED via the sixth transistor T6. The second electrode Eb3 of the third transistor T3 may be connected to the second electrode Eb4 of the fourth transistor T4, one end of the capacitor Cst (e.g., the second storage electrode E2), and the gate electrode G1 of the driving transistor T1. The third transistor T3 may be turned on according to the scan signal GWn received through the first scan line 151 to connect the gate electrode G1 and the second electrode Eb1 of the driving transistor T1 to each other, thereby diode-connecting the driving transistor T1.

[0128] A gate electrode G4 of the fourth transistor T4 may be connected to the second scan line 152, a first electrode Ea4 of the fourth transistor T4 may be connected to the initialization voltage line 127, and a second electrode Eb4 of the fourth transistor T4 may be connected to one end of the capacitor Cst (e.g., the second storage electrode E2) and the gate electrode G1 of the driving transistor T1 via the second electrode Eb3 of the third transistor T3. The fourth transistor T4 may be turned on by a scan signal GIn received through the second scan line 152 and perform an initialization operation of transferring an initialization voltage Vint to the gate electrode G1 of the driving transistor T1 and resetting the voltage of the gate electrode G1 of the driving transistor T1.

[0129] The gate electrode G5 of the fifth transistor T5 can be connected to the light emission control line 155, the first electrode Ea5 of the fifth transistor T5 can be connected to the driving voltage line 172, and the second electrode Eb5 of the fifth transistor T5 can be connected to the first electrode Ea1 of the driving transistor T1 and the second electrode Eb2 of the second transistor T2.

[0130] A gate electrode G6 of the sixth transistor T6 may be connected to the light emission control line 155, a first electrode Ea6 of the sixth transistor T6 may be connected to the second electrode Eb1 of the driving transistor T1 and the first electrode Ea3 of the third transistor T3, and a second electrode Eb6 of the sixth transistor T6 may be electrically connected to the anode of the light emitting diode ED. The fifth transistor T5 and the sixth transistor T6 may be simultaneously turned on according to the light emission control signal EM received through the light emission control line 155, allowing the driving voltage ELVDD to be compensated and transmitted to the light emitting diode ED via the driving transistor T1.

[0131] A gate electrode G7 of the seventh transistor T7 can be connected to the third scan line 154, a first electrode Ea7 of the seventh transistor T7 can be connected to the second electrode Eb6 of the sixth transistor T6 and the anode of the light emitting diode ED, and a second electrode Eb7 of the seventh transistor T7 can be connected to the initialization voltage line 127 and the first electrode Ea4 of the fourth transistor T4.

[0132] Transistors T1, T2, T3, T4, T5, T6, and T7 may be P-type channel transistors, such as PMOS, but not limited thereto, and among the transistors T1, T2, T3, T4, T5, T6, and T7, at least one may be an N-type channel transistor, or may include P-type channel transistors and N-type channel transistors.

[0133] As described above, one end of the capacitor Cst (e.g., the second storage electrode E2) may be connected to the gate electrode G1 of the driving transistor T1, and the other end (e.g., the first storage electrode E1) may be connected to the driving voltage line 172. The cathode of the light emitting diode ED may be connected to the common voltage ELVSS terminal transmitting the common voltage ELVSS and may receive the common voltage ELVSS.

[0134] Although a structure in which one pixel includes 7 transistors and 1 capacitor has been described above, the present disclosure is not limited thereto, and in one pixel PX of the display device, the number of transistors and capacitors and the connection relationship between the transistors and capacitors may vary.

[0135] Figure 16 is a schematic timing diagram of signals applied to one pixel according to an embodiment.

[0136] During the initialization period, a low-level front-end scan signal S(n-1) may be supplied to the pixel PX via the second scan line 152. The second scan line 152 may be a front-end scan line. The fourth transistor T4 may be turned on by the scan signal S(n-1), and the initialization voltage Vint may be applied to the gate electrode G1 of the drive transistor T1 and the second storage electrode E2 of the capacitor Cst via the fourth transistor T4. As a result, the drive transistor T1 and the capacitor Cst may be initialized. Since the voltage of the initialization voltage Vint is low, the drive transistor T1 may be turned on.

[0137] During the initialization period, the low-level bypass signal PB may also be applied to the seventh transistor T7. The seventh transistor T7 may be turned on, so that the initialization voltage Vint is applied to the anode of the light emitting diode ED through the seventh transistor T7. As a result, the anode of the light emitting diode ED may also be initialized.

[0138] Thereafter, during a data input period, a low-level scan signal Sn may be supplied to the pixel PX through the scan line 151. The second transistor T2 and the third transistor T3 may be turned on by the low-level scan signal Sn.

[0139] In a case where the second transistor T2 is turned on, the data voltage Dm may pass through the second transistor T2 and may be input to the first electrode Ea1 of the driving transistor T1 .

[0140] During the data input period, the third transistor T3 may be turned on, and as a result, the second electrode Eb1 of the driving transistor T1 may be electrically connected to the gate electrode G1 and the second storage electrode E2 of the capacitor Cst. The gate electrode G1 and the second electrode Eb1 of the driving transistor T1 may be connected to form a diode. The driving transistor T1 may be turned on because a low voltage (initialization voltage Vint) is applied to the gate electrode G1 during the initialization period. As a result, the data voltage Dm input to the first electrode Ea1 of the driving transistor T1 may pass through the channel of the driving transistor T1, may be output from the second electrode Eb1, may pass through the third transistor T3, and may be stored in the second storage electrode E2 of the capacitor Cst.

[0141] The voltage applied to the second storage electrode E2 may vary depending on the threshold voltage Vth of the driving transistor T1. When the data voltage Dm is applied to the first electrode Ea1 of the driving transistor T1 and the initialization voltage Vint is applied to the gate electrode G1 of the driving transistor T1, the voltage output to the second electrode Eb1 may have a value of Vgs+Vth. Here, Vgs may be the difference between the voltages applied to the gate electrode G1 and the first electrode Ea1 of the driving transistor T1 and may have a value of Dm-Vint. Therefore, the voltage output from the second electrode Eb1 and stored in the second storage electrode E2 may have a value of Dm-Vint+Vth.

[0142] Thereafter, during the light emission period, the light emission control signal EM supplied from the light emission control line 155 may have a low level value, and the fifth transistor T5 and the sixth transistor T6 may be turned on. As a result, the driving voltage ELVDD may be applied to the first electrode Ea1 of the driving transistor T1, and the second electrode Eb1 of the driving transistor T1 may be connected to the light-emitting diode ED. The driving transistor T1 may generate a driving current Id based on the voltage difference between the voltage of the gate electrode G1 and the voltage of the first electrode Ea1 (e.g., the driving voltage ELVDD). The driving current Id of the driving transistor T1 may have a value proportional to the square of Vgs-Vth. Here, the value of Vgs may be equal to the voltage difference across the capacitor Cst, and the value of Vgs may be the value of Vg-Vs, which is Dm-Vint+Vth-ELVDD. The value of Vgs-Vth may be the value of Dm-Vint-ELVDD obtained by subtracting Vth. For example, the driving current Id of the driving transistor T1 may have an output current that is independent of the threshold voltage Vth of the driving transistor T1.

[0143] Therefore, even if the driving transistor T1 positioned in each pixel PX has a different threshold voltage Vth due to process distribution, the output current of the driving transistor T1 may be maintained constant, thereby improving characteristic non-uniformity.

[0144] In the above calculation formula, in the case of a P-channel transistor using a polycrystalline semiconductor, the Vth value may have a value slightly greater than 0 or a negative value. The expressions of + and - may change depending on the direction in which the voltage is calculated. However, the fact that the drive current Id as the output current of the drive transistor T1 can have a value that is independent of the threshold voltage Vth does not change.

[0145] In the case where the above-mentioned light emission period ends, the initialization period may start again, and the same operation may be repeated from the beginning.

[0146] In the above, the third transistor T3 may be a switching transistor. Hereinafter, the planar shape and cross-sectional shape of the display device according to the embodiment will be further described, focusing on the driving transistor T1, the third transistor T3 and the capacitor Cst.

[0147] Figure 17 is a plan view showing a partial configuration of a display device according to an embodiment. Figure 18 It is along Figure 17 Schematic cross-sectional view taken along line AA'. Figure 17This is a plan view showing only the lower metal layer BML, semiconductor layer ACT, first gate conductive layer, second gate conductive layer, and data conductive layer among the components of a display device. Other components of the display device are omitted. In the cross-sectional view, the lower metal layer BML is shown as a first portion BML1 away from the semiconductor layer ACT and a second portion BML2 closer to the semiconductor layer ACT.

[0148] Figure 18 It is along Figure 17 , taken along line AA', schematically illustrates a cross-sectional view of a display device, including a lower metal layer BML, a semiconductor layer ACT, a first gate conductive layer, a second gate conductive layer, a data conductive layer, and other components. Other components include a substrate SUB, a first barrier layer BL1, a second barrier layer BL2, a buffer layer BF, a first gate insulating layer GIL1, a second gate insulating layer GIL2, a first insulating layer IL1, a second insulating layer IL2, barrier ribs IL3, a first storage electrode E1, a second storage electrode E2, and an emission layer EML. Thus, the vertical stacking relationship between the components of the display device can be identified.

[0149] Reference Figure 17 and Figure 18 , we will look at each layer in more detail.

[0150] The substrate SUB may be made of a material having rigid characteristics or a material having flexibility. In the case of a flexible substrate SUB, the substrate SUB may have a two-layer structure of polyimide and a barrier layer formed of an inorganic insulating material on the polyimide.

[0151] The first barrier layer BL1 may be disposed on the substrate SUB. The first barrier layer BL1 may include an inorganic material and may form an inorganic layer. In another embodiment, the first barrier layer BL1 may include an organic insulating material.

[0152] The lower metal layer BML may be disposed on the first barrier layer BL1. The lower metal layer BML may include a light-blocking material and may be disposed on a portion of the first barrier layer BL1 to prevent light from entering the semiconductor layer ACT. The lower metal layer BML may include a metal such as copper (Cu), molybdenum (Mo), aluminum (Al), titanium (Ti), or an alloy thereof. The lower metal layer BML may have a single layer. The lower metal layer BML may include a first portion BML1 and a second portion BML2.

[0153] The second barrier layer BL2 may be disposed on portions of the lower metal layer BML and the first barrier layer BL1. A buffer layer BF may be disposed on the second barrier layer BL2. The second barrier layer BL2 and the buffer layer BF may include an inorganic material and may form an inorganic layer. In another embodiment, the second barrier layer BL2 and the buffer layer BF may include an organic insulating material. The second barrier layer BL2 and the buffer layer BF may have a step equal to the thickness of the lower metal layer BML.

[0154] The channel 1132, the first region 1131, and the second region 1133 of the driving transistor T1 and the channel 3132, the first region 3131, and the second region 3133 of the third transistor T3 may be disposed on the buffer layer BF. The semiconductor layer ACT may include not only the driving transistor T1 and the third transistor T3, but also the channel, the first region, and the second region of each of the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7.

[0155] The channel 1132, first region 1131, and second region 1133 of the driving transistor T1 and the channel 3132, first region 3131, and second region 3133 of the third transistor T3 may be connected to each other and formed as a whole. The second region 1133 of the driving transistor T1 may extend from the first region 3131 of the third transistor T3.

[0156] To prevent light from being incident on the driving transistor T1, the lower metal layer BML may overlap, in a plan view, the channel 1132, the first region 1131, and the second region 1133 of the driving transistor T1. For example, a first portion BML1 of the lower metal layer BML may overlap the channel 1132, the first region 1131, and the second region 1133 of the driving transistor T1.

[0157] The second portion BML2 of the lower metal layer BML may be disposed on a portion of the first portion BML1 of the lower metal layer BML so as to perform an excimer laser annealing process using an inclined surface. The region of the semiconductor layer ACT overlapping the second portion BML2 may bulge upward by the thickness of the second portion BML2.

[0158] The channel 1132 of the driving transistor T1 may have a curved shape in a plan view. However, the shape of the channel 1132 of the driving transistor T1 is not limited thereto and may be modified in various ways. For example, the channel 1132 of the driving transistor T1 may be bent into a different shape or may be shaped like a rod. The first region 1131 and the second region 1133 of the driving transistor T1 may be disposed on both sides of the channel 1132 of the driving transistor T1.

[0159] The second region 1133 of the driving transistor T1 may extend up and down in a plan view such that a downwardly extending portion may be connected to the first region of the sixth transistor T6 and an upwardly extending portion may be connected to the first region 3131 of the third transistor T3 .

[0160] The first and second regions 3131 and 3133 of the third transistor T3 may be disposed on both sides of the channel 3132 of the third transistor T3. One end of the third transistor T3 may be connected to the second region 1133 of the driving transistor T1, and the other end may be connected to the second region of the fourth transistor T4.

[0161] The first gate insulating layer GIL1 may be disposed on the substrate SUB and the semiconductor layer ACT. At least a portion of the first gate insulating layer GIL1 may be disposed directly on the buffer layer BF. For example, at least a portion of the first gate insulating layer GIL1 may be in contact with the buffer layer BF.

[0162] A first gate conductive layer may be disposed on the first gate insulating layer GIL1. The first gate conductive layer may include a first scan line 151, a second scan line 152, and a light emission control line 155. The first scan line 151, the second scan line 152, and the light emission control line 155 may extend substantially in the row direction. Each of the first scan line 151, the second scan line 152, and the light emission control line 155 may be connected to multiple pixels. For example, multiple pixels arranged in the same row may be connected to the same first scan line 151, the second scan line 152, and the light emission control line 155. The first scan line 151 may be connected to the gate electrode of the second transistor T2 and the gate electrode 3151 of the third transistor T3. The first scan line 151 may be integrated with the gate electrode 3151 of the second transistor T2 and the gate electrode 3151 of the third transistor T3. The second scan line 152 may be connected to the gate electrode of the fourth transistor T4. The second scan line 152 may be integrated with the gate electrode of the fourth transistor T4. The second scan line 152 may be connected to the gate electrode of the seventh transistor T7 located in the pixel of the previous stage. For example, the third scan line 154 connected to the seventh transistor T7 may be formed by the second scan line 152 at the rear end. The light emission control line 155 may be connected to the gate electrode of the fifth transistor T5 and the gate electrode of the sixth transistor T6. The light emission control line 155 may be integrated with the gate electrode of the fifth transistor T5 and the gate electrode of the sixth transistor T6.

[0163] The first gate conductive layer may further include a gate electrode 1151 of the driving transistor T1. Figure 18 As shown in FIG, in a plan view, the gate electrode 1151 of the driving transistor T1 may overlap with the channel 1132 of the driving transistor T1.

[0164] like Figure 18As shown in FIG, the second gate insulating layer GIL2 may be disposed on the first gate conductive layer and the first gate insulating layer GIL1. At least a portion of the second gate insulating layer GIL2 may be disposed directly over the first gate insulating layer GIL1.

[0165] The second gate conductive layer may be disposed on the second gate insulating layer GIL2. The second gate conductive layer may include a storage electrode 1153. The storage electrode 1153 may overlap with the first gate electrode 1151 in a plan view to form a capacitor Cst. Figure 18 As shown in FIG, an opening 1152 may be formed in the storage electrode 1153 of the capacitor Cst. In a plan view, the opening 1152 of the storage electrode 1153 of the capacitor Cst may overlap with the gate electrode 1151 of the driving transistor T1. In a plan view, the first connection electrode 1175 may overlap with the gate electrode 1151 of the driving transistor T1. Although Figure 18 Although not shown, the first connection electrode 1175 may be connected to the gate electrode 1151 of the driving transistor T1 through the opening 1152 .

[0166] The second gate conductive layer may further include an initialization voltage line 127. The initialization voltage line 127 may extend substantially in the row direction. The initialization voltage line 127 may be connected to a plurality of pixels. For example, a plurality of pixels arranged in the same row may be connected to the same initialization voltage line 127.

[0167] The first insulating layer IL1 may be disposed on the second gate conductive layer and the second gate insulating layer GIL2. A data conductive layer including the data line 171, the driving voltage line 172, and the connection electrode 1175 may be disposed on the first insulating layer IL1. The data conductive layer may include the data line 171, the driving voltage line 172, and the connection electrode 1175.

[0168] The data line 171 and the driving voltage line 172 may extend substantially in the column direction. The data line 171 may be connected to the second transistor T2. The driving voltage line 172 may be connected to the fifth transistor T5. Figure 18 As shown in FIG, the driving voltage line 172 may be connected to the storage electrode 1153 through the contact hole 165. The driving voltage ELVDD may be transmitted to the storage electrode 1153.

[0169] Although Figure 18 Not shown, the connection electrode 1175 may be connected to the gate electrode 1151 of the driving transistor T1 through the opening 1152 of the storage electrode 1153. The connection electrode 1175 may be connected to the third transistor T3 and the fourth transistor T4. The connection electrode 1175 may be connected to the second region of the third transistor T3 and the second region of the fourth transistor T4.

[0170] The data conductive layer may additionally include other connection electrodes. The first region of the fourth transistor T4 and the second region of the seventh transistor T7 may be connected to the initialization voltage line 127 through such connection electrodes. A connection electrode may exist that overlaps with the sixth transistor T6 and may be connected to the second region of the sixth transistor T6.

[0171] like Figure 18 As shown in , the driving voltage line 172 may be connected to the storage electrode 1153 through the contact hole 165 .

[0172] The driving voltage line 172 may be connected to the fifth transistor T5 through the contact hole C11. One end portion of the connection electrode 1175 may be connected to the gate electrode 1151 of the driving transistor T1 through the contact hole C13.

[0173] As mentioned earlier, over the data conductive layer and the first insulating layer IL1 , there may be sequentially positioned the second insulating layer IL2 , the first storage electrode E1 , the barrier rib IL3 , the light emitting layer EML, and the second storage electrode E2 .

[0174] A buffer layer BF may be disposed between the substrate SUB and the semiconductor layer ACT.

[0175] Figure 19 is a plan view of a display device including only a semiconductor layer and a lower metal layer according to an embodiment.

[0176] The lower metal layer BML may include a first portion BML1 and a second portion BML2. The second portion BML2 may be disposed between the semiconductor layer ACT and the first portion BML1. The first portion BML1 may prevent light from entering the semiconductor layer ACT. Therefore, the first portion BML1 may be arranged to overlap the region of the driving transistor T1 in a plan view. The first portion BML1 may be arranged to partially overlap the region of the driving transistor T1 in a plan view. The second portion BML2 may be used to form a step in the semiconductor layer ACT. Therefore, one side of the semiconductor layer ACT and one side of the second portion BML2 adjacent to the semiconductor layer may be parallel to each other. Here, the side of the semiconductor layer ACT and one side of the second portion BML2 that are parallel to each other may be referred to as corresponding sides, and the corresponding sides of the semiconductor layer ACT and the second portion BML2 may be parallel to each other in a plan view. This may mean that, in a plan view, the sides forming the semiconductor layer ACT and the sides forming the second portion BML2 that are close to each other may extend in the same direction while maintaining a certain distance. The adjacent sides of the semiconductor layer ACT and the second portion BML2 may include straight lines and curved lines. If the side of the semiconductor layer ACT and the side of the second portion BML2 are curved, the space (horizontal space) between the two corresponding curves may be constant. In another embodiment, the side of the semiconductor layer ACT and the side of the second portion BML2 may be formed only by straight lines or curves.

[0177] The semiconductor layer ACT may include not only the driving transistor T1 and the third transistor T3 , but also a channel, a first region, and a second region of each of the second transistor T2 , the fourth transistor T4 , the fifth transistor T5 , the sixth transistor T6 , and the seventh transistor T7 .

[0178] Figure 20 yes Figure 19 An enlarged plan view of a portion of the .

[0179] Figure 20 By zooming in Figure 19 , schematically illustrating an embodiment of an arrangement of the semiconductor layer ACT and the first and second portions BML1 and BML2 of the driving transistor T1 portion. Figure 21 The figure shows the Figure 20 Schematic cross-sectional view of an embodiment cut by the dotted line in FIG.

[0180] Figure 21 is a schematic cross-sectional view illustrating a method of manufacturing a semiconductor layer after an excimer laser annealing process.

[0181] Figure 21It is schematically shown that the second portion BML2 is disposed on the first portion BML1 and the semiconductor layer ACT is disposed on the second portion BML2 . Figure 21 The schematic diagram shows a shape in which steps and inclined surfaces are generated in the semiconductor layer ACT by the first portion BML1 and the second portion BML2. In a cross-sectional view, low-temperature polycrystalline silicon (Poly-Si) may be formed in the semiconductor layer ACT overlapping with the region of the first portion BML1 that does not overlap with the second portion BML2. In other words, low-temperature polycrystalline silicon (Poly-Si) may be formed in the semiconductor layer ACT overlapping with the first portion BML1 not covered by the second portion BML2. In other words, low-temperature polycrystalline silicon (Poly-Si) may be formed on a flat surface of the semiconductor layer ACT that is lower in height than the inclined surface on which light is reflected.

[0182] In an embodiment of the present disclosure, the semiconductor layer ACT may partially include low-temperature polycrystalline silicon Poly-Si formed using an inclined surface. The semiconductor layer ACT may be shaped according to design. In other words, the semiconductor layer ACT may be etched after the excimer laser annealing process is performed, leaving only a portion of the applied semiconductor layer ACT. Therefore, in an embodiment of the present disclosure, a portion of the semiconductor layer ACT may be low-temperature polycrystalline silicon Poly-Si in which the excimer laser annealing process is performed using an inclined surface, and another portion of the semiconductor layer ACT may be low-temperature polycrystalline silicon Poly-Si in which the excimer laser annealing process of the comparative example is performed without using an inclined surface. According to an embodiment of the present disclosure, the electron mobility of the semiconductor layer ACT may have a value greater than or equal to about 200 cm 2 / V·s average value.

[0183] Figure 21 The semiconductor layer ACT is schematically shown as being formed by irradiating the applied semiconductor layer ACT with laser and performing an excimer laser annealing process to form low-temperature polysilicon Poly-Si, followed by an etching process.

[0184] As described above, in the case where the excimer laser annealing process is performed using the inclined surface of the applied semiconductor layer ACT, the regularity of silicon particles may be improved compared to the case where the excimer laser annealing process of the comparative example is performed.

[0185] Figure 22 is a plan view of a display device including only a semiconductor layer and a lower metal layer according to another embodiment.

[0186] Figure 22 Another embodiment of the second part BML2 is schematically shown. Figure 20 Compared with the second part BML2, the part not required for the excimer laser annealing process can be removed from the Figure 22The second part of BML2 is excluded.

[0187] Figure 22 The second part BML2 can be used with Figure 20 The second portion BML2 is similar to the first portion BML2, and in a plan view, one side of the semiconductor layer ACT and one side of the second portion BML2 may be parallel to each other.

[0188] Figure 23 is a plan view of a display device including only a semiconductor layer and a lower metal layer according to another embodiment.

[0189] Figure 23 A further embodiment of the second part BML2 is schematically shown. Figure 20 The second portion BML2 in the embodiment may be disposed on one side of a region of the semiconductor layer ACT where an excimer laser annealing process is to be performed using an inclined surface, and Figure 23 The second portion BML2 may be placed on the other side of the semiconductor layer ACT region where the excimer laser annealing process is to be performed. Figure 20 The second part of BML2 and Figure 23 The second portion BML2 in FIG. 5 is disposed at a different position, but the excimer laser annealing process may be performed on the semiconductor layer ACT at the same position.

[0190] exist Figure 23 In the second portion BML2, one side of the semiconductor layer ACT may be parallel to one side of the second portion BML2 in a plan view.

[0191] Figure 24 is a plan view of a display device including only a semiconductor layer and a lower metal layer according to another embodiment.

[0192] Figure 24 Another embodiment of the second part BML2 is schematically shown. For example, in a plan view, the second part BML2 may have one or more areas. In a plan view, the second part BML2 may have additional areas. Figure 24 The second part BML2 may include Figure 22 The second part of BML2 and Figure 23 As a result, reflected light can be generated in the second portion from both sides of the semiconductor layer ACT region where the excimer laser annealing process is to be performed using the inclined surface. Therefore, the excimer laser annealing process can be performed using stronger reflected light. This further improves the regularity of the silicon particles.

[0193] The above description is an example of the technical features of the present disclosure, and those skilled in the art to which the present disclosure pertains will be able to make various modifications and variations. Therefore, the embodiments of the present disclosure described above may be implemented individually or in combination with each other.

[0194] Therefore, the embodiments disclosed in this disclosure are not intended to limit the technical spirit of this disclosure, but to describe the technical spirit of this disclosure, and the scope of the technical spirit of this disclosure is not limited by these embodiments. The scope of protection of this disclosure should be interpreted by the appended claims, and it should be interpreted that all technical spirits within the equivalent scope are included within the scope of this disclosure.

Claims

1. A display device comprising: a first barrier layer disposed on a substrate; a lower metal layer, the lower metal layer being disposed on the first barrier layer; as well as a semiconductor layer, the semiconductor layer being disposed on the lower metal layer, Wherein, in a cross-sectional view, the lower metal layer includes a first portion spaced apart from the semiconductor layer and a second portion close to the semiconductor layer, In plan view, the area of ​​the second portion is smaller than the area of ​​the first portion, and One side of the semiconductor layer and a side of the second portion adjacent to the semiconductor layer are parallel to each other.

2. The display device according to claim 1, further comprising: A buffer layer is provided between the semiconductor layer and the lower metal layer.

3. The display device according to claim 2, further comprising: A second barrier layer is disposed between the lower metal layer and the buffer layer.

4. The display device according to claim 2, wherein In the cross-sectional view, the thickness of the buffer layer is 1 to 4 times the thickness of the lower metal layer.

5. The display device according to claim 1, wherein In plan view, the second portion has an additional area. The display device according to claim 1 , wherein: In a cross-sectional view, the first portion and the second portion are continuous.

7. The display device according to claim 1, wherein In cross-sectional view, the second portion includes an inclined surface at an end.

8. The display device according to claim 7, wherein: The angle of the inclined surface is in the range of 30 degrees to 60 degrees.

9. The display device according to claim 1, wherein In a cross-sectional view, the first portion and the second portion are spaced apart from each other.

10. The display device according to claim 9, further comprising: A third barrier layer is disposed between the first portion and the second portion.

11. A method for manufacturing a display device, comprising: forming a first barrier layer on the substrate; forming a lower metal layer on the first barrier layer; as well as forming a semiconductor layer on the lower metal layer, The forming of the semiconductor layer on the lower metal layer includes applying the semiconductor layer on the lower metal layer, and simultaneously irradiating a laser onto a flat surface and an inclined surface of the semiconductor layer.

12. The method for manufacturing a display device according to claim 11, wherein: The incident angle of the laser is in the range of 0 degrees to 80 degrees.

13. The method for manufacturing a display device according to claim 11, wherein: The inclined surface has a height higher than that of the flat surface.

14. The method for manufacturing a display device according to claim 11, wherein: In a cross-sectional view, the lower metal layer includes a first portion spaced apart from the semiconductor layer and a second portion close to the semiconductor layer, and In a plan view, an area of ​​the second portion is smaller than an area of ​​the first portion.

15. The method for manufacturing a display device according to claim 14, wherein: One side of the semiconductor layer and a side of the second portion adjacent to the semiconductor layer are parallel to each other.

16. The method for manufacturing a display device according to claim 11, wherein: Forming the lower metal layer includes forming a step in the lower metal layer using a photoresist.

17. The method for manufacturing a display device according to claim 16, wherein: The photoresist includes steps.

18. The method for manufacturing a display device according to claim 11, further comprising: A buffer layer is formed between the semiconductor layer and the lower metal layer.

19. The method for manufacturing a display device according to claim 18, further comprising: A second barrier layer is formed between the lower metal layer and the buffer layer.

20. The method for manufacturing a display device according to claim 18, wherein: In the cross-sectional view, the thickness of the buffer layer is 1 to 4 times the thickness of the lower metal layer.

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