Thin film transistor substrate and display device including the same

Abstract

Provided is a thin film transistor substrate including: a substrate; a first thin film transistor on the substrate; and a second thin film transistor on the substrate, in which the first thin film transistor includes a first active layer having a first channel portion, a first gate insulating layer on the first active layer, a first gate on the first gate insulating layer, a first source connected to the first active layer, and a second source connected to the second channel portion, and a first drain spaced apart from the first source and connected to the first active layer, the second thin film transistor including a conductive material layer on the substrate, a first buffer layer on the conductive material layer, a second active layer having a second channel portion on the first buffer layer, a second gate insulating layer on the second active layer, and a second gate insulating layer on the second active layer, a second gate on the second gate insulating layer, a second source connected to the second active layer, and a second drain spaced apart from the second source and connected to the second active layer, and a conductive material layer connected to the second source and overlapping the second channel portion. In addition, a display device including the thin film transistor substrate is provided.

Description

[0001] This application is a divisional application, and its parent application is an application with an application date of May 31, 2022, application number 202210607527.5, and invention name “Thin film transistor substrate and display device comprising the thin film transistor substrate”.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims the benefit of Korean Patent Application No. 10-2021-0075690, filed on June 10, 2021, which is hereby incorporated by reference as if fully set forth herein. Technical Field

[0004] The present disclosure relates to a thin film transistor substrate and a display device including the thin film transistor substrate. Background Art

[0005] Transistors are widely used as switching devices or driving devices in the field of electronic devices. In particular, since thin film transistors can be manufactured on glass substrates or plastic substrates, they are widely used as switching devices in display devices such as liquid crystal displays or organic light emitting devices.

[0006] For example, a display device may include a switching thin film transistor and a driving thin film transistor. Generally, it is advantageous that the switching thin film transistor has a smaller s factor to improve switching characteristics, and the driving thin film transistor has a larger s factor to represent grayscale.

[0007] However, since a thin film transistor generally has a small s factor to ensure switching characteristics, it is difficult to express grayscale when such a thin film transistor is applied to a driving thin film transistor of a display device.

[0008] Therefore, a thin film transistor having a large s-factor is required in order to easily express grayscales through a driving thin film transistor applied to a display device. Summary of the Invention

[0009] The present disclosure is made in view of the above problems, and one object of the present disclosure is to provide a thin film transistor substrate including a thin film transistor having a large s-factor.

[0010] Another object of the present disclosure is to provide a thin film transistor designed to have a large s-factor by including a conductive material layer disposed between a substrate and an active layer and connected to a source electrode, and a thin film transistor substrate including the thin film transistor.

[0011] Yet another object of the present disclosure is to provide a thin film transistor substrate including a first thin film transistor having a relatively small s-factor and a second thin film transistor having a relatively large s-factor.

[0012] Still another object of the present disclosure is to provide a display device having excellent grayscale representation capability by including a driving thin film transistor having a large s-factor.

[0013] In addition to the objects of the present disclosure as described above, those skilled in the art will clearly understand other objects and features of the present disclosure from the following description of the present disclosure.

[0014] According to one aspect of the present disclosure, the above and other purposes can be achieved by providing a thin film transistor substrate, which includes: a substrate; a first thin film transistor on the substrate; and a second thin film transistor on the substrate, wherein the first thin film transistor includes a first active layer having a first channel portion, a first gate insulating layer on the first active layer, a first gate on the first gate insulating layer, a first source connected to the first active layer, and a first drain spaced apart from the first source and connected to the first active layer, and the second thin film transistor includes a conductive material layer on the substrate, a first buffer layer on the conductive material layer, a second active layer having a second channel portion on the first buffer layer, a second gate insulating layer on the second active layer, a second gate on the second gate insulating layer, a second source connected to the second active layer, and a second drain spaced apart from the second source and connected to the second active layer, wherein the conductive material layer is connected to the second source and overlaps with the second channel portion.

[0015] The s-factor of the second thin film transistor is greater than the s-factor of the first thin film transistor.

[0016] The conductive material layer may have light-shielding properties.

[0017] The conductive material layer does not overlap with the first channel portion.

[0018] A first buffer layer may be disposed between the substrate and the first active layer and between the substrate and the second active layer.

[0019] The first buffer layer may have a thickness of 50 nm to 300 nm.

[0020] The thickness of the second gate insulating layer may be 0.75 to 5 times the thickness of the first buffer layer.

[0021] The first buffer layer may include a hydrogen barrier layer on the conductive material layer and a buffer insulating layer on the hydrogen barrier layer.

[0022] The hydrogen barrier layer may comprise silicon nitride (SiN x ).

[0023] The hydrogen barrier layer may have a thickness of 10 nm to 100 nm.

[0024] The first gate insulating layer and the second gate insulating layer have the same thickness.

[0025] The first gate insulating layer and the second gate insulating layer may be integrally formed.

[0026] At least one of the first gate insulating layer or the second gate insulating layer may include a gate insulating portion and an interface layer on the gate insulating portion, and the interface layer may be disposed closer to any one of the first channel portion and the second channel portion than the gate insulating portion.

[0027] The interface layer may be formed by a metal organic chemical vapor deposition (MOCVD) method.

[0028] The interfacial layer may comprise silicon oxide (SiO x ), silicon nitride (SiN x ) or at least one of metal oxides.

[0029] The interfacial layer may comprise SiO2.

[0030] The interface layer may have a thickness of 1 nm to 10 nm.

[0031] The thin film transistor substrate may further include a first pad layer disposed between the substrate and the first buffer layer and overlapping the first channel portion.

[0032] The first pad layer does not overlap with the second channel portion.

[0033] The first pad layer may have electrical conductivity and light shielding properties.

[0034] The first pad layer may be connected to the first gate.

[0035] The thin film transistor substrate may further include a second buffer layer disposed between the substrate and the first buffer layer.

[0036] The conductive material layer is disposed between the first buffer layer and the second buffer layer.

[0037] The first pad layer may be disposed between the substrate and the second buffer layer.

[0038] The first pad layer may be connected to the first source electrode.

[0039] The first pad layer may be connected to the first gate.

[0040] The first pad layer may be disposed between the first buffer layer and the second buffer layer.

[0041] The first pad layer may be connected to the first gate.

[0042] At least one of the first active layer or the second active layer may include an oxide semiconductor material.

[0043] The oxide semiconductor material may include at least one of an IZO (InZnO)-based, IGO (InGaO)-based, ITO (InSnO)-based, IGZO (InGaZnO)-based, IGZTO (InGaZnSnO)-based, GZTO (GaZnSnO)-based, GZO (GaZnO)-based, ITZO (InSnZnO)-based, or FIZO (FeInZnO)-based oxide semiconductor material.

[0044] At least one of the first active layer or the second active layer may include a first oxide semiconductor layer and a second oxide semiconductor layer on the first oxide semiconductor layer.

[0045] At least one of the first active layer or the second active layer may further include a third oxide semiconductor layer on the second oxide semiconductor layer.

[0046] According to another aspect of the present disclosure, the above and other objects can be achieved by providing a display device including a thin film transistor substrate and a display element of a second thin film transistor connected to the thin film transistor substrate.

[0047] The display element may include an organic light emitting diode. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The above and other objects, features and other advantages of the present disclosure will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0049] Figure 1A and Figure 1B is a cross-sectional view showing a thin film transistor substrate according to one embodiment of the present disclosure;

[0050] Figure 2A and Figure 2B is a cross-sectional view illustrating a thin film transistor substrate according to another embodiment of the present disclosure;

[0051] Figure 3A and Figure 3B is a cross-sectional view showing a thin film transistor substrate according to yet another embodiment of the present disclosure;

[0052] Figure 4 is a cross-sectional view showing a thin film transistor substrate according to yet another embodiment of the present disclosure;

[0053] Figure 5 is a cross-sectional view showing a thin film transistor substrate according to yet another embodiment of the present disclosure;

[0054] Figure 6 is a cross-sectional view showing a thin film transistor substrate according to yet another embodiment of the present disclosure;

[0055] Figure 7 is a cross-sectional view showing a thin film transistor substrate according to yet another embodiment of the present disclosure;

[0056] Figures 8A to 8E is a graph showing a threshold voltage of a thin film transistor;

[0057] Figure 9A and Figure 9B is a graph showing a threshold voltage of a thin film transistor;

[0058] Figure 10 is a graph showing the relationship between the s-factor and the thickness ratio of the first buffer layer and the gate insulating layer;

[0059] Figure 11A and Figure 11B is a schematic diagram showing an effective gate voltage of a first thin film transistor according to one embodiment of the present disclosure;

[0060] Figure 12A and Figure 12B is a schematic diagram showing an effective gate voltage of a second thin film transistor according to one embodiment of the present disclosure;

[0061] Figure 13A and Figure 13B is a schematic diagram illustrating an effective gate voltage of a first thin film transistor according to another embodiment of the present disclosure;

[0062] Figure 14 is a schematic diagram showing a display device according to another embodiment of the present disclosure;

[0063] Figure 15 It shows Figure 14 The circuit diagram of any pixel;

[0064] Figure 16 It shows Figure 15 A plan view of pixels;

[0065] Figure 17 It is along Figure 16 A cross-sectional view taken along line II';

[0066] Figure 18 is a plan view showing an arbitrary pixel of a display device according to another embodiment of the present disclosure;

[0067] Figure 19 It is along Figure 18 A cross-sectional view taken along line II-II';

[0068] Figure 20 It is along Figure 18A cross-sectional view taken along line III-III';

[0069] Figure 21 is a plan view showing any one pixel of a display device according to yet another embodiment of the present disclosure;

[0070] Figure 22 It is along Figure 21 A cross-sectional view taken along line IV-IV';

[0071] Figure 23 It is along Figure 21 A cross-sectional view taken along line V-V';

[0072] Figure 24 is a plan view showing an arbitrary pixel of a display device according to still another embodiment of the present disclosure;

[0073] Figure 25 It is along Figure 24 A cross-sectional view taken along line VI-VI';

[0074] Figure 26 It is along Figure 24 A cross-sectional view taken along line VII-VII';

[0075] Figure 27 is a circuit diagram showing any one pixel of a display device according to yet another embodiment of the present disclosure; and

[0076] Figure 28 is a circuit diagram showing any one pixel of a display device according to still another embodiment of the present disclosure. DETAILED DESCRIPTION

[0077] The advantages and features of the present disclosure and their implementation methods will be illustrated by the following embodiments described with reference to the accompanying drawings. However, the present disclosure may be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be complete and comprehensive and will fully convey the scope of the present disclosure to those skilled in the art. Furthermore, the present disclosure is limited only by the scope of the claims.

[0078] The shapes, sizes, ratios, angles, and quantities disclosed in the drawings used to describe the embodiments of the present disclosure are merely examples, and therefore, the present disclosure is not limited to the details shown. Throughout the specification, like reference numerals refer to like elements. In the following description, when it is determined that a detailed description of a related known function or configuration unnecessarily obscures the key points of the present disclosure, the detailed description will be omitted.

[0079] In the case where “including,” “having,” and “comprising” described in this specification are used, another component may be added unless “only…” is used. Terms in the singular form may include plural forms unless the contrary meaning is mentioned.

[0080] When explaining an element, although there is no explicit description, the element is interpreted as including a range of error.

[0081] When describing a positional relationship, for example, when the positional relationship is described as “on,” “above,” “below,” and “beside,” one or more parts may be set between the two parts unless “only” or “directly” is used.

[0082] Spatially relative terms such as "under," "beneath," "beneath," "above," and "above" may be used herein to readily describe the relationship of one or more elements to another or other elements as illustrated in the accompanying drawings. It should be understood that these terms are intended to encompass different orientations of the device in addition to the orientation shown in the accompanying drawings. For example, if the device shown in the accompanying drawings were turned over, a device described as being disposed "under" or "beneath" another device could be disposed "above" the other device. Thus, the exemplary terms "under or beneath" could encompass orientations of "under or beneath" as well as "above." Similarly, the exemplary terms "above" or "above" could encompass orientations of "above" as well as "under or beneath."

[0083] When describing a temporal relationship, for example, when a temporal order is described as "after," "followed by," "next to," and "before," discontinuous cases may be included unless "only" or "directly" is used.

[0084] It should be understood that although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of the present invention.

[0085] The term "at least one" should be understood to include any or all combinations of one or more of the related listed items. For example, "at least one of the first, second, and third items" means a combination of two or more of the first, second, and third items, as well as all items proposed in the first, second, or third item.

[0086] The features of the various embodiments of the present disclosure may be coupled or combined with each other in part or in whole, and may interoperate and be driven technically in different ways as will be fully understood by those skilled in the art. The embodiments of the present disclosure may be performed independently of each other, or may be performed together in a mutually dependent relationship.

[0087] In the drawings, the same or similar elements are denoted by the same reference numerals even though they are shown in different drawings.

[0088] In the embodiments of the present disclosure, for ease of description, the source and drain are distinguished from each other. However, the source and drain can be used interchangeably. The source can be a drain, and the drain can be a source. In addition, the source in any embodiment of the present disclosure can be a drain in another embodiment of the present disclosure, and the drain in any embodiment of the present disclosure can be a source in another embodiment of the present disclosure.

[0089] In the embodiments of the present disclosure, the source and drain are not subject to the above limitations. The source region in any embodiment of the present disclosure can be a source, and the drain region in any embodiment of the present disclosure can be a drain. The source region in any embodiment of the present disclosure can be a drain, and the drain region in any embodiment of the present disclosure can be a source.

[0090] Figure 1A and Figure 1B is a cross-sectional view illustrating a thin film transistor substrate 100 according to one embodiment of the present disclosure.

[0091] The thin film transistor substrate 100 according to one embodiment of the present disclosure includes a substrate 110 , a first thin film transistor TR1 on the substrate 110 , and a second thin film transistor TR2 on the substrate 110 .

[0092] The first thin film transistor TR1 includes a first active layer A1 having a first channel portion 131, a first gate insulating layer GI1 on the first active layer A1, a first gate G1 on the first gate insulating layer GI1, a first source electrode S1 connected to the first active layer A1, and a first drain electrode D1 spaced apart from the first source electrode S1 and connected to the first active layer A1.

[0093] The second thin film transistor TR2 includes a conductive material layer 215 on the substrate 110, a first buffer layer 120 on the conductive material layer 215, a second active layer A2 having a second channel portion 231 on the first buffer layer 120, a second gate insulating layer GI2 on the second active layer A2, a second gate G2 on the second gate insulating layer GI2, a second source electrode S2 connected to the second active layer A2, and a second drain electrode D2 spaced apart from the second source electrode S2 and connected to the second active layer A2.

[0094] In the second thin film transistor TR2 , the conductive material layer 215 is connected to the second source electrode S2 and overlaps the second channel portion 231 .

[0095] The second thin film transistor TR2 having the conductive material layer 215 overlapping the second channel portion 231 and connected to the second source electrode S2 has an s factor greater than that of the first thin film transistor TR1. The second thin film transistor TR2 may be used as a driving thin film transistor of a display device.

[0096] In the following, reference will be made to Figure 1A and Figure 1B The thin film transistor substrate 100 according to one embodiment of the present disclosure is described in more detail.

[0097] The substrate 110 may be formed of glass or plastic. A transparent plastic having flexible properties (eg, polyimide) may be used to form the substrate 110. When polyimide is used to form the substrate 110, heat-resistant polyimide capable of withstanding high temperatures may be used to form the substrate 110.

[0098] The conductive material layer 215 is disposed on the substrate 110 . The conductive material layer 215 overlaps the second channel portion 231 .

[0099] The conductive material layer 215 has electrical conductivity. The conductive material layer 215 may include at least one of an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a silver-based metal such as silver (Ag) or a silver alloy, a copper-based metal such as copper (Cu) or a copper alloy, a molybdenum-based metal such as molybdenum (Mo) or a molybdenum alloy, chromium (Cr), tantalum (Ta), neodymium (Nd), titanium (Ti), or iron (Fe). The conductive material layer 215 may have a multilayer structure including at least two conductive material layers having different physical properties.

[0100] According to one embodiment of the present disclosure, the conductive material layer 215 is connected to the second source S2. Therefore, the voltage applied to the conductive material layer 215 may be the same as that of the second source S2.

[0101] According to one embodiment of the present disclosure, the conductive material layer 215 overlaps the second channel portion 231. When the same voltage as the second source S2 is applied to the conductive material layer 215, the conductive material layer 215 may affect the electrical characteristics of the second channel portion 231. Due to the influence of the conductive material layer 215 on the electrical characteristics, the influence of the electric field applied by the second gate G2 to the second channel portion 231 may be reduced.

[0102] According to one embodiment of the present disclosure, the conductive material layer 215 does not overlap with the first channel portion 131. Therefore, a voltage applied to the conductive material layer 215 does not directly affect the first channel portion 131 and the first active layer A1.

[0103] According to one embodiment of the present disclosure, the conductive material layer 215 may have light-shielding properties. Therefore, the conductive material layer 215 may serve as a light-shielding layer. The conductive material layer 215 may block light incident on the substrate 110 to protect the second channel portion 231 and the second active layer A2.

[0104] The first buffer layer 120 is disposed on the conductive material layer 215. The first buffer layer 120 may include at least one of silicon oxide, silicon nitride, or a metal-based oxide. According to one embodiment of the present disclosure, the first buffer layer 120 may include at least one of silicon oxide or silicon nitride. The first buffer layer 120 may have a single-layer structure or a multi-layer structure.

[0105] The first buffer layer 120 protects the first active layer A1 and the second active layer A2. In addition, the first buffer layer 120 can maintain a uniform surface on the upper portion of the substrate 110.

[0106] The first buffer layer 120 spaces the conductive material layer 215 and the second channel portion 231 apart from each other.

[0107] According to one embodiment of the present disclosure, the first buffer layer 120 may be provided between the substrate 110 and the first active layer A1 and between the substrate 110 and the second active layer A2. Figure 1A and Figure 1B , the first buffer layer 120 may be provided on the entire surface of the substrate 110 . The conductive material layer 215 and the second channel portion 231 are spaced apart from each other and insulated from each other by the first buffer layer 120 .

[0108] According to an embodiment of the present disclosure, the first buffer layer 120 may have a thickness t1 of 50 nm to 300 nm. According to an embodiment of the present disclosure, the thickness t1 of the first buffer layer 120 is defined as the distance between the upper surface of the conductive material layer 215 and the lower surface of the second channel portion 231 .

[0109] When the thickness t1 of the first buffer layer 120 is less than 50 nm, the first buffer layer 120 may not be able to prevent hydrogen (H) or oxygen (O) from penetrating into the first and second thin film transistors TR1 and TR2, and thus the functions of the first and second thin film transistors TR1 and TR2 may be degraded. For example, when the thickness t1 of the first buffer layer 120 is less than 50 nm, the first and second channel portions 131 and 231 may become conductive due to hydrogen (H) penetrating from outside the first and second thin film transistors TR1 and TR2, and thus the transistor functions of the first and second thin film transistors TR1 and TR2 may be lost.

[0110] When the thickness t1 of the first buffer layer 120 exceeds 300 nm, the distance between the conductive material layer 215 and the second channel portion 231 may increase, and thus the capacitance Cap between the conductive material layer 215 and the second channel portion 231 may become very small. Therefore, even if the same voltage as the second source electrode S2 is applied to the conductive material layer 215, the effect of the conductive material layer 215 on the electrical characteristics of the second channel portion 231 may be very small. When the effect of the conductive material layer 215 on the electrical characteristics of the second channel portion 231 is reduced, the effect of reducing the influence of the electric field applied to the second channel portion 231 by the second gate electrode G2 is almost not achieved.

[0111] The first active layer A1 and the second active layer A2 are disposed on the first buffer layer 120 .

[0112] The first active layer A1 and the second active layer A2 may be formed of a semiconductor material. The first active layer A1 of the first thin-film transistor TR1 may have the same or different composition as the second active layer A2 of the second thin-film transistor TR2. For example, the first active layer A1 and the second active layer A2 may include one of an amorphous silicon semiconductor material, a polycrystalline silicon semiconductor material, and an oxide semiconductor.

[0113] According to one embodiment of the present disclosure, at least one of the first active layer A1 or the second active layer A2 may include an oxide semiconductor material. For example, the oxide semiconductor material may include at least one of an IZO (InZnO)-based, IGO (InGaO)-based, ITO (InSnO)-based, IGZO (InGaZnO)-based, IGZTO (InGaZnSnO)-based, GZTO (GaZnSnO)-based, GZO (GaZnO)-based, ITZO (InSnZnO)-based, or FIZO (FeInZnO)-based oxide semiconductor material, but one embodiment of the present disclosure is not limited thereto. The first active layer A1 and the second active layer A2 may be made of other oxide semiconductor materials known in the art.

[0114] The first active layer A1 may include a first channel portion 131, a first conductor portion 132, and a second conductor portion 133. The first channel portion 131 overlaps the first gate G1. The first conductor portion 132 and the second conductor portion 133 of the first active layer A1 do not overlap the first gate G1. The first conductor portion 132 and the second conductor portion 133 may be formed by selectively conducting a semiconductor material.

[0115] According to one embodiment of the present disclosure, the first conductor portion 132 of the first active layer A1 may be a source region, and the second conductor portion 133 may be a drain region. According to one embodiment of the present disclosure, the first conductor portion 132 may be referred to as a source, and the second conductor portion 133 may be referred to as a drain, but the present disclosure is not limited thereto. The first conductor portion 132 may be a drain region, and the second conductor portion 133 may be a source region. Furthermore, the first conductor portion 132 may be referred to as a drain, and the second conductor portion 133 may be referred to as a source.

[0116] The second active layer A2 may include a second channel portion 231, a first conductor portion 232, and a second conductor portion 233. The second channel portion 231 overlaps with the second gate G2. The first conductor portion 232 and the second conductor portion 233 of the second active layer A2 do not overlap with the second gate G2. The first conductor portion 232 and the second conductor portion 233 may be formed by selectively conducting a semiconductor material.

[0117] According to one embodiment of the present disclosure, the first conductor portion 232 of the second active layer A2 may be a source region, and the second conductor portion 233 may be a drain region. According to one embodiment of the present disclosure, the first conductor portion 232 may be referred to as a source, and the second conductor portion 233 may be referred to as a drain, but the present disclosure is not limited thereto. The first conductor portion 232 may be a drain region, and the second conductor portion 233 may be a source region. Furthermore, the first conductor portion 232 may be referred to as a drain, and the second conductor portion 233 may be referred to as a source.

[0118] The first gate insulating layer GI1 is disposed on the first active layer A1, and the second gate insulating layer GI2 is disposed on the second active layer A2. More specifically, the first gate insulating layer GI1 is disposed on the first channel portion 131, and the second gate insulating layer GI2 is disposed on the second channel portion 231. The first gate insulating layer GI1 and the second gate insulating layer GI2 may be formed in separate patterns to be distinguished from each other ( Figure 1B ), and can be formed integrally without being distinguishable from each other ( Figure 1A ).

[0119] Each of the first and second gate insulating layers GI1 and GI2 may include at least one of silicon oxide, silicon nitride, or metal-based oxide. Each of the first and second gate insulating layers GI1 and GI2 may have a single layer structure or a multi-layer structure.

[0120] The first gate insulating layer GI1 of the first thin film transistor TR1 and the second gate insulating layer GI2 of the second thin film transistor TR2 may have the same composition and may be formed by the same process. According to one embodiment of the present disclosure, the thickness t21 of the first gate insulating layer GI1 and the thickness t22 of the second gate insulating layer GI2 may be the same as each other.

[0121] refer to Figure 1A , the first gate insulating layer GI1 and the second gate insulating layer GI2 may be integrally formed on the entire surface of the substrate 110 without being patterned. Figure 1A The first gate insulating layer GI1 and the second gate insulating layer GI2 are integrally formed, so the first gate insulating layer GI1 and the second gate insulating layer GI2 may be collectively referred to as a gate insulating layer 140 .

[0122] refer to Figure 1B , the first gate insulating layer GI1 and the second gate insulating layer GI2 can be formed separately by patterning. Figure 1B In the thin film transistor shown, a thickness t21 of the first gate insulating layer GI1 and a thickness t22 of the second gate insulating layer GI2 may be the same as each other ( t21 = t22 ).

[0123] The first gate insulating layer GI1 and the second gate insulating layer GI2 protect the first channel portion 131 and the second channel portion 231 , respectively.

[0124] The first gate electrode G1 of the first thin film transistor TR1 is disposed on the first gate insulating layer GI1 and overlaps the first channel portion 131 of the first active layer A1.

[0125] The second gate electrode G2 of the second thin film transistor TR2 is disposed on the second gate insulating layer GI2 and overlaps with the second channel portion 231 of the second active layer A2.

[0126] Each of the first gate G1 and the second gate G2 may include at least one of an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a silver-based metal such as silver (Ag) or a silver alloy, a copper-based metal such as copper (Cu) or a copper alloy, a molybdenum-based metal such as molybdenum (Mo) or a molybdenum alloy, chromium (Cr), tantalum (Ta), neodymium (Nd), or titanium (Ti). The first gate G1 and the second gate G2 may have a multilayer structure including at least two conductive material layers having different physical properties from each other.

[0127] The interlayer insulating layer 160 is provided on the first gate electrode G1 and the second gate electrode G2. The interlayer insulating layer 160 is an insulating layer made of an insulating material. The interlayer insulating layer 160 may be made of an organic material, an inorganic material, or a stacked structure of organic and inorganic layers.

[0128] The first source electrode S1 , the first drain electrode D1 , the second source electrode S2 , and the second drain electrode D2 are disposed on the interlayer insulating layer 160 .

[0129] The first source electrode S1 is connected to the first active layer A1 through a contact hole. The first drain electrode D1 is spaced apart from the first source electrode S1 and connected to the first active layer A1 through a contact hole.

[0130] The second source electrode S2 is connected to the second active layer A2 through a contact hole. The second drain electrode D2 is spaced apart from the second source electrode S2 and connected to the second active layer A2 through a contact hole.

[0131] Each of the first source electrode S1, the first drain electrode D1, the second source electrode S2, and the second drain electrode D2 may include at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or alloys thereof. Each of the first source electrode S1, the first drain electrode D1, the second source electrode S2, and the second drain electrode D2 may be formed of a single layer made of a metal or an alloy thereof, or may be formed of a multilayer of two or more layers.

[0132] refer to Figure 1A and Figure 1B The bridge portion 171 may be provided on the interlayer insulating layer 160 . The bridge portion 171 is connected to the second source electrode S2 . The bridge portion 171 may extend from the second source electrode S2 , and a portion of the second source electrode S2 may be the bridge portion 171 .

[0133] The bridge portion 171 is connected to the conductive material layer 215 through a contact hole H21. The contact hole H21 is formed through the interlayer insulating layer 160 and the first buffer layer 120.

[0134] The second source electrode S2 of the second thin film transistor TR2 and the conductive material layer 215 may be connected to each other through the bridge 171 .

[0135] When the first conductor portion 132 of the first active layer A1 is used as the first source electrode and the second conductor portion 133 is used as the first drain electrode, the first source electrode S1 and the first drain electrode D1 on the interlayer insulating layer 160 may be omitted.

[0136] In addition, when the first conductor portion 232 of the second active layer A2 is used as the second drain electrode and the second conductor portion 233 is used as the second source electrode, the second source electrode S2 and the second drain electrode D2 on the interlayer insulating layer 160 can be omitted. In this case, the second source electrode S2 on the interlayer insulating layer 160 can be part of the bridge portion 171.

[0137] refer to Figure 1A and Figure 1BThe bridge portion 171 can connect the second conductor portion 233 of the second active layer A2 to the conductive material layer 215 through the two contact holes H21 and H22. When the second conductor portion 233 of the second active layer A2 serves as the second drain, the bridge portion 171 can connect the conductive material layer 215 to the second drain through the two contact holes H21 and H22.

[0138] According to one embodiment of the present disclosure, the s-factor of the second thin film transistor TR2 having the conductive material layer 215 connected to the second source electrode S2 is greater than the s-factor of the first thin film transistor TR1 .

[0139] Hereinafter, the s factor will be described in detail.

[0140] The s-factor (subthreshold swing) is defined as the reciprocal value of the slope of the drain-source current curve relative to the gate voltage of the thin-film transistors TR1 and TR2 near the threshold voltage Vth. For example, the s-factor can be an indicator of the magnitude of the change in the drain-source current relative to the gate voltage near the threshold voltage Vth of the thin-film transistors TR1 and TR2.

[0141] When the s factor becomes larger, the drain-source current I with respect to the gate voltage near the threshold voltage Vth becomes larger. DS The rate of change slows down.

[0142] For example, the s factor can be obtained by Figures 8A to 8E The current variation diagram is shown to describe it. Figures 8A to 8E are graphs showing the threshold voltage of a thin film transistor. Specifically, Figures 8A to 8E shows the gate voltage V GS The drain-source current I DS .exist Figures 8A to 8E The threshold voltage Vth of the graph shown is close to the gate voltage V GS The drain-source current I DS The reciprocal of the curve is the s factor. When the slope of the curve is steeper, the s factor is smaller, and when the slope of the curve is gentler, the s factor is larger. When the s factor is larger, the drain-source current I with respect to the gate voltage near the threshold voltage Vth is DS The rate of change is slow.

[0143] When the s factor becomes larger, the drain-source current I with respect to the gate voltage near the threshold voltage Vth increases. DS The rate of change slows down, so it is easy to adjust the gate voltage V GS Adjust the drain-source current I DS size.

[0144] In a current-driven display device, for example, an organic light-emitting display device, the drain-source current I of the driving thin film transistor can be adjusted. DS The grayscale of the pixel is controlled by the size of the drain-source current I DS The size of is determined by the gate voltage. Therefore, in an organic light-emitting display device driven by current, as the s factor of the driving TFT becomes larger, it is easier to adjust the grayscale of the pixel.

[0145] According to one embodiment of the present disclosure, because the conductive material layer 215 overlaps with the second channel portion 231, when the same voltage as the second source electrode S2 is applied to the conductive material layer 215, the conductive material layer 215 can affect the electrical characteristics of the second channel portion 231. Due to the influence of the conductive material layer 215 on the electrical characteristics, the influence of the electric field applied to the second channel portion 231 by the second gate electrode G2 can be reduced. Therefore, the s-factor of the second thin film transistor TR2 including the conductive material layer 215 can be greater than the s-factor of the first thin film transistor TR1 not including the conductive material layer 215.

[0146] The influence of the conductive material layer 215 on the s-factor of the second thin film transistor TR2 can be Figure 11A 、 Figure 11B 、 Figure 12A and Figure 12B To describe.

[0147] Figure 11A and Figure 11B is a graph showing the effective gate voltage V of the first thin film transistor TR1 according to one embodiment of the present disclosure. eff Schematic diagram of .

[0148] Figure 11A Schematically shows that when the gate voltage V GS When the gate voltage V is applied to the first thin film transistor TR1, a capacitance Cap may be generated. GS is the voltage between the first source S1 and the first gate G1. Figure 11A , the relationship of the capacitance Cap at a voltage near the threshold voltage Vth before the first thin film transistor TR1 is completely turned on is schematically shown.

[0149] like Figure 11A As shown, when the gate voltage V GS When applied to the first thin film transistor TR1, a capacitor C may be formed between the first channel portion 131 of the first active layer A1 and the first gate G1. GI1 and a capacitor C may be formed between the first channel portion 131 and the first source S1 CH .

[0150] according to Figure 11AThe relationship between the voltage and capacitance can be expressed as Figure 11B Reference Figure 11B , due to the capacitance C between the first channel portion 131 and the first source S1 CH , a gate voltage V applied between the first source S1 and the first gate G1 GS It may not be applied between the first channel portion 131 and the first gate G1. Therefore, a voltage loss may occur.

[0151] refer to Figure 11B , when the voltage applied between the first channel portion 131 and the first gate G1 during driving of the first thin film transistor TR1 is referred to as the effective gate voltage V eff When the effective gate voltage V eff It can be obtained by the following formula 1.

[0152] [Formula 1]

[0153] V eff =[C GI1 / (C GI1 +C CH )]×V Gs

[0154] Figure 12A and Figure 12B is a graph showing the effective gate voltage V of the second thin film transistor TR2 according to one embodiment of the present disclosure. eff Schematic diagram of .

[0155] Figure 12A Schematically shows that when the gate voltage V GS When applied to the second thin film transistor TR2, a capacitance Cap can be generated. Figure 12A , the relationship of the capacitance Cap at a voltage near the threshold voltage Vth before the second thin film transistor TR2 is completely turned on is schematically shown.

[0156] like Figure 12A As shown, when the gate voltage V GS When applied to the second thin film transistor TR2, a capacitor C may be formed between the second channel portion 231 of the second active layer A2 and the second gate G2. GI2 , a capacitor C may be formed between the second channel portion 231 and the second source S2 CH , a capacitor C may be formed between the second channel portion 231 and the conductive material layer 215 BUF .exist Figure 12A and Figure 12B In the embodiment, since the conductive material layer 215 may be used as a light shielding layer, the reference numeral of the conductive material layer 215 may be LS (light shielding layer).

[0157] according to Figure 12A The relationship between the voltage and capacitance Cap can be expressed as Figure 12B Reference Figure 12B , due to the capacitance C between the second channel portion 231 and the second source S2 CH and the capacitance C between the second channel portion 231 and the conductive material layer 215 BUF , a gate voltage V applied between the second source S2 and the second gate G2 GS The voltage may not be applied between the second channel portion 231 and the second gate G2. Therefore, a voltage loss may occur.

[0158] According to one embodiment of the present disclosure, the conductive material layer 215 and the second source electrode S2 are electrically connected to each other. Therefore, a capacitance C is generated between the second channel portion 231 and the conductive material layer 215. BUF , thereby increasing the capacitance Cap of the lower portion of the second channel portion 231 that generates voltage loss (C CH +C BUF ). Therefore, refer to Figure 12B , when the voltage applied between the second channel portion 231 and the second gate G2 during the driving of the second thin film transistor TR2 is referred to as the effective gate voltage V eff When the effective gate voltage V eff It can be obtained by the following formula 2.

[0159] [Formula 2]

[0160] V eff =[C GI2 / (C GI2 +C CH +C BUF )]×V GS

[0161] Referring to Formula 2, the denominator of Formula 2 is due to the capacitance C between the second channel portion 231 and the conductive material layer 215. BUF Therefore, the effective gate voltage V eff The decrease is greater than the gate voltage V actually applied between the second source S2 and the second gate G2 GS Therefore, when the same voltage is applied, the drain-source current I DS is smaller than the drain-source current I of the first thin film transistor TR1 DS , and the drain-source current I DS The range of change is also smaller.

[0162] Thus, due to the drain-source current I DSThe change of is smaller than that of the first thin film transistor TR1, so the s-factor of the second thin film transistor TR2 is greater than the s-factor of the first thin film transistor TR1.

[0163] According to one embodiment of the present disclosure, the second channel portion 231 and the conductive material layer 215 are spaced apart from each other with the first buffer layer 120 interposed therebetween. Therefore, when the thickness of the first buffer layer 120 increases, the distance between the conductive material layer 215 and the second channel portion 231 increases, thereby increasing the capacitance C between the second channel portion 231 and the conductive material layer 215. BUF When the capacitance C between the second channel portion 231 and the conductive material layer 215 decreases. BUF When it decreases, the s-factor of the second thin film transistor TR2 will become smaller.

[0164] Therefore, in order to make the s factor of the second thin film transistor TR2 have a relatively large value, the first buffer layer 120 may have a thickness less than or equal to a predetermined value. According to one embodiment of the present disclosure, the first buffer layer 120 may have a thickness t1 of 300 nm or less. When the thickness t1 of the first buffer layer 120 exceeds 300 nm, the distance between the conductive material layer 215 and the second channel portion 231 may increase, thereby increasing the capacitance C between the conductive material layer 215 and the second channel portion 231. BUF Therefore, the s-factor of the second thin film transistor TR2 may become small.

[0165] As described above, when the thickness t1 of the first buffer layer 120 is less than 50 nm, the function of the first buffer layer 120 to block hydrogen (H) or oxygen (O) may be deteriorated, and thus the first and second channel portions 131 and 231 may be damaged or conductive.

[0166] Therefore, according to one embodiment of the present disclosure, the first buffer layer 120 may have a thickness t1 of 50 nm to 300 nm. More specifically, the first buffer layer 120 may have a thickness t1 of 50 nm to 250 nm, a thickness t1 of 80 nm to 250 nm, a thickness t1 of 80 nm to 200 nm, a thickness t1 of 100 nm to 200 nm, or a thickness t1 of 120 nm to 300 nm.

[0167] Referring to Formula 2, when the second thin film transistor TR2 is driven, the effective gate voltage V eff Affected by the capacitance C between the second channel portion 231 and the second gate G2 GI2 In addition, the capacitance C between the second channel portion 231 and the second gate G2 GI2 Affected by the thickness t22 of the second gate insulating layer GI2.

[0168] According to one embodiment of the present disclosure, the thickness of the second gate insulating layer GI2 may be 0.75 to 5 times the thickness of the first buffer layer 120, so that the second thin film transistor TR2 has a large s factor and can simultaneously turn on and off the flow of current. For example, the thickness t1 of the first buffer layer 120 and the thickness t22 of the second gate insulating layer GI2 may satisfy the following formula 3.

[0169] [Formula 3]

[0170] 0.75≤t22 / t1≤5

[0171] When the thickness t22 of the second gate insulating layer GI2 is less than 0.75 times the thickness t1 of the first buffer layer 120 (0.75>t22 / t1), most of the gate voltage V GS is applied between the second channel portion 231 and the second gate G2 , and the influence of the conductive material layer 215 is reduced, whereby the slope of the threshold voltage graph may increase and the s-factor of the second thin film transistor TR2 may decrease.

[0172] On the other hand, when the thickness t22 of the second gate insulating layer GI2 exceeds 5 times the thickness t1 of the first buffer layer 120 (t22 / t1>5), the s-factor of the second thin film transistor TR2 may become too large. When the s-factor of the second thin film transistor TR2 becomes too large, excessive power may be consumed to drive the second thin film transistor TR2.

[0173] According to one embodiment of the present disclosure, the thickness of the second gate insulating layer GI2 may be 1 to 3.5 times or 1.5 to 3 times the thickness of the first buffer layer 120 .

[0174] According to one embodiment of the present disclosure, for example, the second thin film transistor TR2 may have an s-factor greater than or equal to 0.28. When the second thin film transistor TR2 has an s-factor greater than or equal to 0.28, the grayscale of the pixel may be easily adjusted.

[0175] According to one embodiment of the present disclosure, the second thin-film transistor TR2 may have an s-factor of 0.3 or greater, taking into account ease of grayscale adjustment. When the s-factor of the second thin-film transistor TR2 becomes too large, the power consumption required to drive the second thin-film transistor TR2 increases. Taking these characteristics into account, the s-factor of the second thin-film transistor TR2 according to one embodiment of the present disclosure may be in the range of 0.3 to 0.7. Therefore, the second thin-film transistor TR2 can be used as a drive transistor for a display device.

[0176] On the other hand, the s-factor of the first thin film transistor TR1 is smaller than that of the second thin film transistor TR2. The first thin film transistor TR1 with a smaller s-factor has excellent switching characteristics. Therefore, the first thin film transistor TR1 can be used as a switching transistor of a display device.

[0177] Figure 2A and 2B is a cross-sectional view illustrating a thin film transistor substrate 200 according to another embodiment of the present disclosure. Hereinafter, descriptions of elements that have already been described will be omitted to avoid redundancy.

[0178] refer to Figure 2A The first buffer layer 120 may have a multi-layer structure. When the first buffer layer 120 is thin, the first channel portion 131 and the second channel portion 231 may be conductive due to the influence of hydrogen (H) present in the insulating layer, etc., so that the first thin film transistor TR1 and the second thin film transistor TR2 may lose their transistor functions.

[0179] In order to prevent the first channel portion 131 and the second channel portion 231 from being conductive, the first buffer layer 120 may include a hydrogen barrier layer 122. The hydrogen barrier layer 122 may be disposed on the conductive material layer 215.

[0180] Specifically, in the thin film transistor substrate 200 according to another embodiment of the present disclosure, the first buffer layer 120 may include a hydrogen barrier layer 122 on the conductive material layer 215 and a buffer insulating layer 121 on the hydrogen barrier layer 122. Hydrogen (H) is blocked by the hydrogen barrier layer 122, thereby effectively preventing the first channel portion 131 and the second channel portion 231 from being conductive.

[0181] The hydrogen barrier layer 122 may include silicon nitride (SiN x ). Silicon nitride (SiN x ) is considered to be a material with excellent hydrogen (H) barrier capability.

[0182] The hydrogen barrier layer 122 may have a thickness of 10 nm to 100 nm in consideration of the film stability and electrical insulation properties of the first buffer layer 120. When the thickness of the hydrogen barrier layer 122 is less than 10 nm, the hydrogen barrier capability may be degraded, and when the thickness of the hydrogen barrier layer 122 exceeds 100 nm, the thickness of the buffer insulating layer 121 becomes relatively small, thereby possibly degrading the film stability and electrical insulation properties of the first buffer layer 120.

[0183] The buffer insulating layer 121 may be used to improve the film stability and electrical insulation characteristics of the first buffer layer 120. The buffer insulating layer 121 may include silicon oxide (SiO xThe buffer insulating layer 121 may have a thickness of 40 nm to 250 nm. When the thickness of the buffer insulating layer 121 is less than 40 nm, the film stability and electrical insulation characteristics of the first buffer layer 120 may be deteriorated. When the thickness of the buffer insulating layer 121 exceeds 250 nm, the thickness of the first buffer layer 120 may be greater than necessary. The buffer insulating layer 121 may have a thickness of 40 nm to 250 nm.

[0184] When the first buffer layer 120 includes the hydrogen barrier layer 122 and the buffer insulating layer 121, even if the first buffer layer 120 has a thin thickness t1 of about 50 nm, the first channel portion 131 and the second channel portion 231 can be effectively prevented from being conductive, and the first buffer layer 120 can have excellent film stability and electrical insulation characteristics.

[0185] refer to Figure 2A , the first gate insulating layer GI1 and the second gate insulating layer GI2 are formed integrally. According to another embodiment of the present disclosure, the first gate insulating layer GI1 and the second gate insulating layer GI2 may be collectively referred to as the gate insulating layer 140. According to another embodiment of the present disclosure, the gate insulating layer 140 may be provided on the entire surface of the substrate 110. In this case, the first gate insulating layer GI1 and the second gate insulating layer GI2 do not need to be distinguished from each other. For convenience, the gate insulating layer 140 between the first channel portion 131 and the first gate G1 is referred to as the first gate insulating layer GI1, and the gate insulating layer 140 between the second channel portion 231 and the second gate G2 is referred to as the second gate insulating layer GI2.

[0186] refer to Figure 2A Since the first gate insulating layer GI1 and the second gate insulating layer GI2 are integrally formed, a thickness t21 of the first gate insulating layer GI1 and a thickness t22 of the second gate insulating layer GI2 are the same as each other ( t21 = t22 ).

[0187] According to another embodiment of the present disclosure, at least one of the first gate insulating layer GI1 or the second gate insulating layer GI2 may include an interface layer 141 and a gate insulating portion 142 on the interface layer 141. The interface layer 141 may be disposed closer to one of the first channel portion 131 and the second channel portion 231 than the gate insulating portion 142. The interface layer 141 may be disposed in contact with the first channel portion 131 and the second channel portion 231.

[0188] refer to Figure 2B The gate insulating layer 140 includes an interface layer 141 and a gate insulating portion 142 on the interface layer 141. The interface layer 141 is disposed closer to the first channel portion 131 and the second channel portion 231 than the gate insulating portion 142. According to another embodiment of the present disclosure, Figure 2BAs shown, the interface layer 141 contacts each of the first channel portion 131 and the second channel portion 231 .

[0189] The interface layer 141 protects the first channel portion 131 and the second channel portion 231. According to another embodiment of the present disclosure, the interface layer 141 can be formed by a metal organic chemical vapor deposition (MOCVD) method. The interface layer 141 formed by the MOCVD method has a dense and uniform atomic arrangement structure, thereby effectively blocking hydrogen (H), oxygen (O), etc. that penetrate from the outside of the gate insulating layer 140. Therefore, the first channel portion 131 and the second channel portion 231 can be effectively protected.

[0190] The interface layer 141 may be made of an insulating material. For example, the interface layer 141 may include a material having insulating properties and applicable to the MOCVD method. According to one embodiment of the present disclosure, the interface layer 141 may include silicon oxide (SiO x ), silicon nitride (SiN x ) or at least one of metal oxides. Specifically, the interface layer 141 may include SiO2, SiN x Or at least one of Al2O3. More specifically, the interface layer 141 may include SiO2 as silicon oxide (SiO x ), but one embodiment of the present disclosure is not limited thereto. The interface layer 141 may be formed of other materials having insulating properties.

[0191] According to another embodiment of the present disclosure, the interface layer 141 may have a thickness of 1 nm to 10 nm. When the thickness of the interface layer 141 is less than 1 nm, the effect of the interface layer 141 in blocking hydrogen (H) and oxygen (O) may be reduced. When the thickness of the interface layer 141 exceeds 10 nm, it may take a long time to form the interface layer 141, and the overall thickness of the gate insulating layer 140 may be greater than necessary.

[0192] The gate insulating portion 142 is a main body of the gate insulating layer 140. Due to the gate insulating portion 142, the gate insulating layer 140 may have excellent mechanical stability and electrical insulating properties, and may have dielectric properties required for driving the thin film transistors TR1 and TR2.

[0193] Figure 3A and Figure 3B is a cross-sectional view illustrating a thin film transistor substrate 300 according to yet another embodiment of the present disclosure.

[0194] and Figure 2B Compared with the thin film transistor substrate 200, Figure 3A The thin film transistor substrate 300 includes a first active layer A1 and a second active layer A2 of a multi-layer structure.

[0195] Specifically, at least one of the first active layer A1 or the second active layer A2 may include first oxide semiconductor layers 130a and 230a on the substrate 110, and second oxide semiconductor layers 130b and 230b on the first oxide semiconductor layers 130a and 230a. The first oxide semiconductor layers 130a and 230a and the second oxide semiconductor layers 130b and 230b may include the same semiconductor material, or may include different semiconductor materials.

[0196] The first oxide semiconductor layers 130a and 230a support the second oxide semiconductor layers 130b and 230b. Therefore, the first oxide semiconductor layers 130a and 230a are referred to as "support layers." The first channel portion 131 and the second channel portion 231 may be formed in the second oxide semiconductor layers 130b and 230b, respectively. Therefore, the second oxide semiconductor layers 130b and 230b are referred to as "channel layers," but one embodiment of the present disclosure is not limited thereto. The first channel portion 131 and the second channel portion 231 may be formed in the first oxide semiconductor layers 130a and 230a.

[0197] The first oxide semiconductor layers 130a and 230a and the second oxide semiconductor layers 130b and 230b may be formed by deposition, metal organic chemical vapor deposition (MOCVD), etc. The first oxide semiconductor layers 130a and 230a and the second oxide semiconductor layers 130b and 230b may be formed by a continuous process.

[0198] The structure in which the first active layer A1 and the second active layer A2 include the first oxide semiconductor layers 130a and 230a and the second oxide semiconductor layers 130b and 230b is referred to as a double-layer structure, but another embodiment of the present disclosure is not limited thereto. At least one of the first active layer A1 or the second active layer A2 may further include a third oxide semiconductor layer on the second oxide semiconductor layers 130b and 230b.

[0199] According to yet another embodiment of the present disclosure, at least one of the first gate insulating layer GI1 or the second gate insulating layer GI2 may include a gate insulating portion 142 and a passivation layer 143 on the gate insulating portion 142. The passivation layer 143 may be disposed closer to one of the first gate G1 and the second gate G2 than the gate insulating portion 142.

[0200] refer to Figure 3B The gate insulating layer 140 includes a gate insulating portion 142 and a passivation layer 143 on the gate insulating portion 142. The passivation layer 143 may be in contact with the first gate G1 and the second gate G2, respectively.

[0201] The passivation layer 143 improves the surface characteristics of the gate insulating layer 140. According to another embodiment of the present disclosure, the passivation layer 143 can be formed by an MOCVD method. The passivation layer 143 formed by the MOCVD method has a dense and uniform atomic arrangement structure, thereby effectively blocking hydrogen (H), oxygen (O), etc. that penetrate from the outside of the gate insulating layer 140. Therefore, the channel portions 131 and 132 can be effectively protected.

[0202] The passivation layer 143 may be made of an insulating material. For example, the passivation layer 143 may include a material having insulating properties and applicable to the MOCVD method. According to one embodiment of the present disclosure, the passivation layer 143 may include silicon oxide (SiO x ), silicon nitride (SiN x ) or at least one of metal oxides. Specifically, the passivation layer 143 may include SiO2, SiN x Or at least one of Al2O3.

[0203] According to another embodiment of the present disclosure, the passivation layer 143 may have a thickness of 1 nm to 10 nm. When the thickness of the passivation layer 143 is less than 1 nm, the passivation layer 143 may not be effective in blocking hydrogen (H) and oxygen (O). When the thickness of the passivation layer 143 exceeds 10 nm, it may take a long time to form the passivation layer 143, and the overall thickness of the gate insulating layer 140 may be greater than necessary.

[0204] Figure 4 is a cross-sectional view illustrating a thin film transistor substrate 400 according to yet another embodiment of the present disclosure.

[0205] and Figure 2B Compared with the TFT substrate 200, Figure 4 The thin film transistor substrate 400 further includes a first pad layer 115 overlapping the first channel portion 131 .

[0206] refer to Figure 4 The first pad layer 115 is disposed between the substrate 110 and the first buffer layer 120 and overlaps the first channel portion 131 . The first pad layer 115 does not overlap the second channel portion 231 .

[0207] The first pad layer 115 may have electrical conductivity and light shielding properties. The first pad layer 115 may be a light shielding layer.

[0208] According to another embodiment of the present disclosure, the first buffer layer 120 is disposed on the first pad layer 115. The first pad layer 115 and the first channel portion 131 are spaced apart from each other by the first buffer layer 120. Figure 4, the gap distance t3 between the first pad layer 115 and the first channel portion 131 is substantially the same as the thickness t1 of the first buffer layer 120. Therefore, the gap distance t3 between the first pad layer 115 and the first channel portion 131 may be equal to the gap distance t1 between the conductive material layer 215 and the second channel portion 231.

[0209] According to another embodiment of the present disclosure, the first pad layer 115 is connected to the first gate G1. Figure 4 The bridge portion 172 is disposed on the interlayer insulating layer 160 , and the first pad layer 115 and the first gate G1 are connected to each other through the bridge portion 172 .

[0210] refer to Figure 4 The first conductor portion 132 of the first active layer A1 functions as the first source S1, and the second conductor portion 133 functions as the first drain D1. In addition, the first conductor portion 232 of the second active layer A2 functions as the second drain D2, and the second conductor portion 233 functions as the second source S2.

[0211] The bridge 172 connects the first gate G1 to the first pad layer 115 through contact holes H11 and H12. One of the contact holes H11 and H12 is formed by passing through the interlayer insulating layer 160, and the other contact hole H21 is formed by passing through the interlayer insulating layer 160, the gate insulating layer 140, and the first buffer layer 120.

[0212] refer to Figure 4 , since the first pad layer 115 is connected to the first gate G1, Figure 4 The first thin film transistor TR1 may have a double gate structure. Due to the double gate structure, Figure 4 The first thin film transistor TR1 may have a very small s-factor.

[0213] The effective gate voltage V of the first pad layer 115 eff You can refer to Figure 13A and Figure 13B describe.

[0214] Figure 13A and 13B is a graph showing the effective gate voltage V of the first thin film transistor according to another embodiment of the present disclosure. eff Schematic diagram of .

[0215] Figure 13A Schematically shows that when the gate voltage V GS Applied to Figure 4 The first thin film transistor TR1 can generate a capacitance Cap. Figure 13A, the relationship of the capacitance Cap at a voltage near the threshold voltage Vth before the first thin film transistor TR1 is completely turned on is schematically shown.

[0216] like Figure 13A As shown, when the gate voltage V GS When applied to the second thin film transistor TR2, a capacitor C may be formed between the first channel portion 131 and the first gate G1. GI1 , a capacitor C may be formed between the first channel portion 131 and the first source S1 CH , and a capacitor C may be formed between the first channel portion 131 and the first pad layer 115 BUF .

[0217] according to Figure 13A The relationship between the voltage and capacitance Cap can be expressed as Figure 13B shown.

[0218] According to one embodiment of the present disclosure, the first pad layer 115 and the first gate G1 are electrically connected to each other. Therefore, a gate voltage is applied to the first channel portion through the first pad layer 115. Therefore, the capacitance C between the first channel portion 131 and the first pad layer 115 is BUF The corresponding effective gate voltage V eff Increase.

[0219] refer to Figure 13B , when the voltage applied between the first channel portion 131 and the first gate G1 during driving of the first thin film transistor TR1 is referred to as the effective gate voltage V eff When the effective gate voltage V eff It can be obtained by the following formula 4.

[0220] [Formula 4]

[0221] V eff =[C GI1 +C BUF ) / (C GI1 +C CH +C BUF )]×V GS

[0222] Referring to Formula 4, due to the capacitance C between the first channel portion 131 and the first pad layer 115 BUF , compared with Formula 2, the numerator of Formula 4 increases. Therefore, the gate voltage V actually applied between the first source S1 and the first gate G1 is GS Compared to the effective gate voltage V eff Therefore, when the same voltage is applied, the drain-source current I DSGreater than the drain-source current I of the second thin film transistor TR2 DS , and the drain-source current I DS The range of change is also large.

[0223] As described above, due to the drain-source current I DS The change of is greater than that of the second thin film transistor TR2, so the s-factor of the first thin film transistor TR1 is smaller than the s-factor of the second thin film transistor TR2.

[0224] Therefore, in Figure 4 In the illustrated thin film transistor substrate 400 , the first thin film transistor TR1 having a very small s-factor can be used as a switching transistor, and the second thin film transistor TR2 having a relatively large s-factor can be used as a driving transistor of a display device.

[0225] Figure 5 is a cross-sectional view illustrating a thin film transistor substrate 500 according to yet another embodiment of the present disclosure.

[0226] refer to Figure 5 The thin film transistor substrate 500 according to another embodiment of the present disclosure further includes a second buffer layer 220 between the substrate 110 and the first buffer layer 120. The second buffer layer 220 has an insulating property and can prevent the penetration of moisture and oxygen.

[0227] The second buffer layer 220 may include at least one of silicon oxide, silicon nitride, or a metal-based oxide. The second buffer layer 220 may have a single-layer structure, or may have a multi-layer structure.

[0228] According to one embodiment of the present disclosure, the second buffer layer 220 may have the same thickness as the first buffer layer 120, or may have a thickness greater than that of the first buffer layer 120. For example, the thickness of the second buffer layer 220 may be at least 1.5 times the thickness of the first buffer layer 120. The thickness of the second buffer layer 220 may be at least 2 times or 3 times the thickness of the first buffer layer 120.

[0229] refer to Figure 5 The conductive material layer 215 may be disposed between the first buffer layer 120 and the second buffer layer 220 . The first pad layer 115 may also be disposed between the first buffer layer 120 and the second buffer layer 220 .

[0230] exist Figure 5 In the thin film transistor substrate 500 according to another embodiment of the present disclosure, the first pad layer 115 is connected to the substrate 500. Figure 4 The first pad layer 115 is electrically connected to the first gate G1 through the bridge portion 172 and the contact holes H11 and H12.

[0231] Figure 6 is a cross-sectional view illustrating a thin film transistor substrate 600 according to yet another embodiment of the present disclosure.

[0232] refer to Figure 6 , a first pad layer 115 may be provided between the substrate 110 and the second buffer layer 220. The first pad layer 115 is connected to the first source electrode S1 of the first thin film transistor TR1.

[0233] refer to Figure 6 The bridge 173 is disposed on the interlayer insulating layer 160 , so the first pad layer 115 and the first source S1 are connected to each other through the bridge 173 . The bridge 173 may extend from the first source S1 , and a portion of the first source S1 may serve as the bridge 173 .

[0234] The bridge portion 173 is connected to the first pad layer 115 through the contact hole H12. The contact hole H21 is formed by passing through the interlayer insulating layer 160, the gate insulating layer 140, the first buffer layer 120, and the second buffer layer 220.

[0235] When the first conductor portion 132 of the first active layer A1 serves as the first source S1 and the second conductor portion 133 serves as the first drain D1, the first source S1 and the first drain D1 on the interlayer insulating layer 160 may be omitted. In this case, the first source S1 on the interlayer insulating layer 160 may be part of the bridge 173.

[0236] refer to Figure 6 , the bridge portion 173 may connect the first conductor portion 132 of the first active layer A1 to the first pad layer 115 through the two contact holes H11 and H12 .

[0237] exist Figure 6 In the thin film transistor substrate 600, since the first pad layer 115 is connected to the first source electrode S1, a capacitor Cap may be formed between the first pad layer 115 and the first channel portion 131. However, since the distance between the first pad layer 115 and the first channel portion 131 is long, the capacitance between the first pad layer 115 and the first channel portion 131 is very small. Therefore, the capacitance Cap between the first pad layer 115 and the first channel portion 131 has little effect on the gate voltage V GS and the effective gate voltage V eff .

[0238] According to one embodiment of the present disclosure, the distance t4 between the first pad layer 115 and the first channel portion 131 is greater than the distance t1 between the conductive material layer 215 and the second channel portion 231. For example, the distance t4 between the first pad layer 115 and the first channel portion 131 may be at least twice the distance t1 between the conductive material layer 215 and the second channel portion 231 (t4 ≥ 2xt1). More specifically, the distance t4 between the first pad layer 115 and the first channel portion 131 may be at least 2.5 times the distance t1 between the conductive material layer 215 and the second channel portion 231.

[0239] As described above, even though the first pad layer 115 is provided under the first channel portion 131 of the first thin film transistor TR1 and the first pad layer 115 is connected to the first source electrode S1, the s-factor of the first thin film transistor TR1 is hardly increased due to the long distance between the first pad layer 115 and the first channel portion 131. Therefore, the first thin film transistor TR1 can maintain excellent switching characteristics.

[0240] Figure 7 is a cross-sectional view illustrating a thin film transistor substrate 700 according to yet another embodiment of the present disclosure.

[0241] refer to Figure 7 , the first pad layer 115 is connected to the first gate G1 . Specifically, the bridge portion 174 is provided on the interlayer insulating layer 160 , and the first pad layer 115 and the first gate G1 are connected to each other through the bridge portion 174 .

[0242] refer to Figure 7 The first conductor portion 132 of the first active layer A1 functions as the first source S1, and the second conductor portion 133 functions as the first drain D1. In addition, the first conductor portion 232 of the second active layer A2 functions as the second drain D2, and the second conductor portion 233 functions as the second source S2.

[0243] The bridge 174 connects the first gate G1 to the first pad layer 115 through contact holes H11 and H12. One of the contact holes H11 and H12 is formed by passing through the interlayer insulating layer 160, and the other contact hole H21 is formed by passing through the interlayer insulating layer 160, the gate insulating layer 140, the first buffer layer 120, and the second buffer layer 220.

[0244] refer to Figure 7 , since the first pad layer 115 is connected to the first gate G1, Figure 7 The first thin film transistor TR1 may have a double gate structure.

[0245] However, since the distance between the first pad layer 115 and the first channel portion 131 is long, the capacitance Cap between the first pad layer 115 and the first channel portion 131 is very small. Therefore, the capacitance Cap between the first pad layer 115 and the first channel portion 131 hardly affects the gate voltage V GS and the effective gate voltage V eff .

[0246] Figures 8A to 8E is a graph showing the threshold voltage of a thin film transistor. Figures 8A to 8E As shown, the gate voltage V GS The drain-source current I DS The curve graph represents the threshold voltage diagram of the thin film transistor.

[0247] Specifically, Figures 8A to 8E The thin film transistor to be measured in FIG has the same structure as the thin film transistor TR2 shown in FIG. 1A .

[0248] Figure 8A 、 Figure 8B 、 Figure 8C and Figure 8D The measured thin film transistors in include a gate insulating layer having a thickness of 250 nm, and include first buffer layers 120 having thicknesses of 82 nm, 120 nm, 182 nm, and 232 nm, respectively. Figure 8E The thin film transistor includes a gate insulating layer with a thickness of 150 nm and a first buffer layer 120 with a thickness of 400 nm.

[0249] Confirmation basis Figure 8A 、 Figure 8B 、 Figure 8C and Figure 8D The s factors of the thin film transistor including the first buffer layer 120 thinner than the gate insulating layer are 0.38 V / dec, 0.36 V / dec, 0.31 V / dec, and 0.31 V / dec, respectively.

[0250] Confirmation basis Figure 8E The s-factor of the thin film transistor including the first buffer layer 120 thicker than the gate insulating layer is 0.19 V / dec.

[0251] refer to Figures 8A to 8E When the thickness t1 of the first buffer layer 120 and the thickness t22 of the gate insulating layer (the second gate insulating layer GI2) satisfy the relationship of Formula 3, it can be confirmed that the thin film transistor has an s factor of 0.3 V / dec or more.

[0252] [Formula 3]

[0253] 0.75≤t22 / t1≤5

[0254] Figure 9A and Figure 9B is a graph showing the threshold voltage of a thin film transistor. GS The drain-source current I DS The curve graph represents the threshold voltage diagram of the thin film transistor.

[0255] Figure 9A and Figure 9B The thin film transistor being measured has Figure 2A The thin film transistor TR2 shown has the same structure. Figure 9A and Figure 9B The measured thin film transistor in includes a gate insulating layer 140 having a thickness of 350 nm, and includes a first buffer layer 120 having thicknesses of 110 nm and 130 nm, respectively.

[0256] Specifically, Figure 9A The first buffer layer 120 of the thin film transistor under test includes a hydrogen barrier layer 122 with a thickness of 10 nm and a buffer insulating layer 121 with a thickness of 100 nm. Figure 9B The first buffer layer 120 of the thin film transistor to be measured includes a hydrogen barrier layer 122 with a thickness of 30 nm and a buffer insulating layer 121 with a thickness of 100 nm. The hydrogen barrier layer 122 is made of silicon nitride (SiN x ), the buffer insulating layer 121 is made of silicon oxide (SiO x ) is made.

[0257] confirm Figure 9A The s-factor of the thin film transistor shown is 0.51V / dec. Figure 9B The s-factor of the thin film transistor is 0.49 V / dec. Thus, according to one embodiment of the present disclosure, the thin film transistor can have an s-factor of 0.45 V / dec or more.

[0258] Figure 10 is a graph showing the relationship between the s-factor and the thickness ratio of the first buffer layer to the gate insulating layer.

[0259] Specifically, Figure 10 Shows that when having Figure 2A The gate insulating layer GI ( Figure 2A When the thickness of the second gate insulating layer (of the first buffer layer 120) is 150 nm, 250 nm and 350 nm respectively, the s factor is calculated according to the thickness ratio of the first buffer layer 120 to the gate insulating layer GI (GI / first buffer layer).

[0260] refer to Figure 10When the thickness of the gate insulating layer GI is greater than 250 nm, and when the thickness ratio of the gate insulating layer GI to the first buffer layer 120 (GI / first buffer layer) is greater than 0.75, the thin film transistor can have an s factor greater than 0.3.

[0261] Still another embodiment of the present disclosure provides a display device 800 including thin film transistor substrates 100, 200, 300, 400, 500, 600, and 700, and a display element 710 connected to the second thin film transistor TR2 of the thin film transistor substrates 100, 200, 300, 400, 500, 600, and 700. According to still another embodiment of the present disclosure, the display element 710 may include, for example, an organic light emitting diode.

[0262] Figure 14 FIG. 8 is a schematic diagram illustrating a display device 800 according to yet another embodiment of the present disclosure.

[0263] like Figure 14 As shown, a display device 800 according to yet another embodiment of the present disclosure includes a display panel 310 , a gate driver 320 , a data driver 330 , and a controller 340 .

[0264] The gate lines GL and the data lines DL are provided in the display panel 310, and the pixels P are provided in the intersection area of ​​the gate lines GL and the data lines DL. By driving the pixels P to display an image

[0265] The controller 340 controls the gate driver 320 and the data driver 330 .

[0266] The controller 340 uses a signal supplied from an external system (not shown) to output a gate control signal GCS for controlling the gate driver 320 and a data control signal DCS for controlling the data driver 330. In addition, the controller 340 samples input image data input from the external system, rearranges the sampled input image data, and supplies rearranged digital image data RGB to the data driver 330.

[0267] The gate control signal GCS includes a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, a start signal Vst, and a gate clock GCLK. In addition, a control signal for controlling the shift register may be included in the gate control signal GCS.

[0268] The data control signal DCS includes a source start pulse SSP, a source shift clock signal SSC, a source output enable signal SOE, a polarity control signal POL, and the like.

[0269] The data driver 330 supplies data voltages to the data lines DL of the display panel 310. Specifically, the data driver 330 converts the image data RGB input from the controller 340 into analog data voltages and supplies the data voltages to the data lines DL.

[0270] The gate driver 320 may include a shift register 350 .

[0271] The shift register 350 sequentially supplies gate pulses to the gate lines GL during one frame using a start signal and a gate clock transmitted from the controller 340. In this case, one frame refers to a period of time during which one image is output through the display panel 310. The gate pulse has a turn-on voltage capable of turning on a switching element (thin film transistor) provided in a pixel P.

[0272] In addition, the shift register 350 supplies a gate-off signal to the gate line GL during the remaining period of a frame when no gate pulse is supplied. Hereinafter, the gate pulse and the gate-off signal will be collectively referred to as a scan signal SS or Scan.

[0273] According to one embodiment of the present disclosure, the gate driver 320 may be packaged on the substrate 110. In this way, the structure in which the gate driver 320 is directly packaged on the substrate 110 will be referred to as a gate-in-panel (GIP) structure.

[0274] Figure 15 yes Figure 14 The circuit diagram of any pixel P, Figure 16 It shows Figure 15 The plane diagram of pixel P, Figure 17 It is along Figure 16 A cross-sectional view taken along line II'.

[0275] Figure 15 The circuit diagram of FIG. 8 is an equivalent circuit diagram of a pixel P of a display device 800 including an organic light emitting diode (OLED) as a display element 710 .

[0276] The pixel P includes a display element 710 and a pixel driving circuit PDC for driving the display element 710 .

[0277] Figure 15 The pixel driving circuit PDC includes a first thin film transistor TR1 as a switching transistor and a second thin film transistor TR2 as a driving transistor. The first thin film transistor TR1 and the second thin film transistor TR2 have been described in the description of the thin film transistor substrates 100, 200, 300, 400, 500, 600 and 700.

[0278] The first thin film transistor TR1 is connected to the gate line GL and the data line DL, and is turned on or off by a scan signal SS supplied through the gate line GL.

[0279] The data line DL supplies a data voltage Vdata to the pixel driving circuit PDC, and the first thin film transistor TR1 controls application of the data voltage Vdata.

[0280] The driving power line PL supplies a driving voltage Vdd to the display element 710 , and the second thin film transistor TR2 controls the driving voltage Vdd. The driving voltage Vdd is a pixel driving voltage for driving an organic light emitting diode (OLED) as the display element 710 .

[0281] When the first thin film transistor TR1 is turned on by a scan signal SS applied from the gate driver 320 via the gate line GL, a data voltage Vdata supplied via the data line DL is supplied to the gate electrode G2 of the second thin film transistor TR2 connected to the display element 710. The data voltage Vdata charges a first capacitor C1 formed between the gate electrode G2 and the source electrode S2 of the second thin film transistor TR2. The first capacitor C1 is a storage capacitor Cst.

[0282] The amount of current supplied to the organic light emitting diode (OLED) as the display element 710 is controlled through the second thin film transistor TR2 according to the data voltage Vdata, thereby controlling the grayscale of light output from the display element 710 .

[0283] refer to Figure 16 and Figure 17 , the first thin film transistor TR1 and the second thin film transistor TR2 are disposed on the substrate 110 .

[0284] The substrate 110 may be made of glass or plastic. Plastic having flexible properties, such as polyimide (PI), may be used as the substrate 110 .

[0285] The second buffer layer 220 is disposed on the substrate 110, and the conductive material layer 215 is disposed on the second buffer layer 220. The conductive material layer 215 may have conductivity and light shielding properties. The conductive material layer 215 may protect the active layers A1 and A2 by shielding light incident from the outside.

[0286] The first buffer layer 120 is disposed on the conductive material layer 215. The first buffer layer 120 is made of an insulating material and protects the active layers A1 and A2 from moisture or oxygen introduced from the outside. The first buffer layer 120 may include a hydrogen barrier layer 122 and a buffer insulating layer 121.

[0287] The first active layer A1 of the first thin film transistor TR1 and the second active layer A2 of the second thin film transistor TR2 are disposed on the first buffer layer 120 .

[0288] For example, the first active layer A1 and the second active layer A2 may include an oxide semiconductor material. The first active layer A1 and the second active layer A2 may be formed of an oxide semiconductor layer made of an oxide semiconductor material.

[0289] The first active layer A1 may include a first channel portion 131, a first conductor portion 132, and a second conductor portion 133. The first channel portion 131 overlaps the first gate G1. According to another embodiment of the present disclosure, the first conductor portion 132 may be referred to as a first source S1, and the second conductor portion 133 may be referred to as a first drain D1.

[0290] The second active layer A2 may include a second channel portion 231, a first conductor portion 232, and a second conductor portion 233. The second channel portion 231 overlaps the second gate G2. According to another embodiment of the present disclosure, the first conductor portion 232 may be referred to as a second source S2, and the second conductor portion 233 may be referred to as a second drain D2.

[0291] refer to Figure 16 and Figure 17 , a portion of the first active layer A1 may be conductorized and thus may be the first capacitor electrode C11 of the first capacitor C1.

[0292] A gate insulating layer 140 is disposed on the first active layer A1 and the second active layer A2. The gate insulating layer 140 may cover the entire upper surface of the first active layer A1 and the second active layer A2, or may cover only a portion of the first active layer A1 and the second active layer A2. The gate insulating layer 140 protects the first channel portion 131 and the second channel portion 231.

[0293] The gate insulating layer 140 may include an interface layer 141 and a gate insulating portion 142 on the interface layer 141. The interface layer 141 is disposed closer to the first and second channel portions 131 and 231 than the gate insulating portion 142 is.

[0294] A first gate electrode G1 of the first thin film transistor TR1 and a second gate electrode G2 of the second thin film transistor TR2 are disposed on the gate insulating layer 140 .

[0295] The first gate G1 of the first thin film transistor TR1 overlaps at least a portion of the first active layer A1 of the first thin film transistor TR1 and the second gate G2 of the second thin film transistor TR2 overlaps at least a portion of the second active layer A2 of the second thin film transistor TR2.

[0296] An interlayer insulating layer 160 is disposed on the first gate G1 and the second gate G2 .

[0297] The data lines DL and the driving power lines PL are disposed on the interlayer insulating layer 160 .

[0298] The data line DL contacts the first source electrode S1 formed in the first active layer A1 through the first contact hole H1. According to another embodiment of the present disclosure, a portion of the data line DL overlapping the first active layer A1 may be referred to as the first source electrode S1.

[0299] The driving power line PL contacts the second drain electrode D2 formed in the second active layer A2 through the fifth contact hole H5. According to another embodiment of the present disclosure, a portion of the driving power line PL overlapping the second active layer A2 may be referred to as the second drain electrode D2.

[0300] refer to Figure 16 and Figure 17 , the second capacitor electrode C12 of the first capacitor C1 , and the first and second bridges BR1 and BR2 are disposed on the interlayer insulating layer 160 .

[0301] The second capacitor electrode C12 overlaps the first capacitor electrode C11 to form the first capacitor C1.

[0302] The first bridge BR1 may be integrally formed with the second capacitor electrode C12. The first bridge BR1 is connected to the conductive material layer 215 through the second contact hole H2 and to the second source electrode S2 through the third contact hole H3. Thus, the conductive material layer 215 may be connected to the second source electrode S2 of the second thin film transistor TR2.

[0303] The second bridge portion BR2 is connected to the second gate electrode G2 of the second thin film transistor TR2 through the fourth contact hole H4 and is connected to the first capacitor electrode C11 of the first capacitor C1 through the seventh contact hole H7.

[0304] A planarization layer 175 is disposed on the data line DL, the driving power line PL, the second capacitor electrode C12, the first bridge BR1, and the second bridge BR2. The planarization layer 175 planarizes upper portions of the first and second thin film transistors TR1 and TR2 and protects the first and second thin film transistors TR1 and TR2.

[0305] The first electrode 711 of the display element 710 is disposed on the planarization layer 175. The first electrode 711 of the display element 710 contacts the second capacitor electrode C12 through a sixth contact hole H6 formed in the planarization layer 175. The second capacitor electrode C12 is integrally formed with the first bridge BR1. Thus, the first electrode 711 can be connected to the second source electrode S2 of the second thin film transistor TR2.

[0306] The bank layer 750 is provided at an edge of the first electrode 711. The bank layer 750 defines a light emitting region of the display element 710.

[0307] The organic light emitting layer 712 is provided on the first electrode 711, and the second electrode 713 is provided on the organic light emitting layer 712. Thus, the display element 710 is completed. Figure 17 The display element 710 shown is an organic light emitting diode (OLED). Therefore, the display device 100 according to one embodiment of the present disclosure is an organic light emitting display device.

[0308] According to another embodiment of the present disclosure, the second thin film transistor TR2 may have a relatively large s factor. The second thin film transistor TR2 may be used as a driving transistor to improve the grayscale representation capability of the display device 800.

[0309] The first thin film transistor TR1 has a relatively small s-factor and thus has excellent switching characteristics. The first thin film transistor TR1 can be used as a switching transistor to improve the display quality of the display device 800.

[0310] Figure 18 is a plan view showing any one pixel P of a display device 900 according to another embodiment of the present disclosure, Figure 19 It is along Figure 18 A cross-sectional view taken along line II-II', Figure 20 It is along Figure 18 A cross-sectional view taken along line III-III'.

[0311] and Figures 14 to 17 Compared to the display device 800 shown, Figure 18 The display device 900 further includes a first pad layer 115 overlapping the first active layer A1.

[0312] refer to Figure 19 and Figure 20 , the first pad layer 115 is disposed between the substrate 110 and the first buffer layer 120 . More specifically, the first pad layer 115 is disposed between the first buffer layer 120 and the second buffer layer 220 .

[0313] The first pad layer 115 overlaps the first channel portion 131 of the first active layer A1 , but does not overlap the second channel portion 231 of the second active layer A2 .

[0314] The first pad layer 115 may have electrical conductivity and light shielding properties. The first pad layer 115 may be a light shielding layer.

[0315] refer to Figure 18 and Figure 20, the third bridge portion BR3 is provided on the interlayer insulating layer 160. The third bridge portion BR3 is connected to the gate line GL through the eighth contact hole H8, and is connected to the first pad layer 115 through the ninth contact hole H9. Since the first gate G1 is part of the gate line GL, the first pad layer 115 can be connected to the first gate G1 of the first thin film transistor TR1 through the third bridge portion BR3.

[0316] Figure 21 is a plan view showing an arbitrary pixel P of the display device 1000 according to yet another embodiment of the present disclosure, Figure 22 It is along Figure 21 A cross-sectional view taken along line IV-IV', Figure 23 It is along Figure 21 A cross-sectional view taken along line V-V'.

[0317] and Figures 14 to 17 Compared to the display device 800 shown, Figure 21 The display device 1000 further includes a first pad layer 115 overlapping the first active layer A1.

[0318] refer to Figures 21 to 23 , the first pad layer 115 is disposed between the substrate 110 and the first buffer layer 120 . More specifically, the first pad layer 115 is disposed between the substrate 110 and the second buffer layer 220 .

[0319] refer to Figures 21 to 23 , the third bridge portion BR3 is provided on the interlayer insulating layer 160. The third bridge portion BR3 is connected to the first source electrode S1 of the first thin film transistor TR1 through the eighth contact hole H8, and is connected to the first pad layer 115 through the ninth contact hole H9. Therefore, the first pad layer 115 can be connected to the first source electrode S1 of the first thin film transistor TR1 through the third bridge portion BR3.

[0320] Figure 24 is a plan view showing an arbitrary pixel P of a display device 1100 according to yet another embodiment of the present disclosure, Figure 25 It is along Figure 24 A cross-sectional view taken along line VI-VI', Figure 26 It is along Figure 24 A cross-sectional view taken along line VII-VII'.

[0321] exist Figures 24 to 26 In the display device 1100, Figures 18 to 20 Compared with the display device 900 , the first pad layer 115 is disposed between the substrate 110 and the second buffer layer 220 .

[0322] refer to Figures 24 to 26, the third bridge portion BR3 is provided on the interlayer insulating layer 160. The third bridge portion BR3 is connected to the gate line GL through the eighth contact hole H8, and is connected to the first pad layer 115 through the ninth contact hole H9. Since the first gate G1 is part of the gate line GL, the first pad layer 115 can be connected to the first gate G1 of the first thin film transistor TR1 through the third bridge portion BR3.

[0323] Figure 27 is a circuit diagram illustrating any one pixel P of the display device 1200 according to yet another embodiment of the present disclosure.

[0324] Figure 27 FIG. 1 is an equivalent circuit diagram illustrating a pixel P of an organic light emitting display device.

[0325] Figure 27 The pixel P of the display device 1200 shown includes an organic light emitting diode (OLED) as a display element 710 and a pixel driving circuit PDC for driving the display element 710. The display element 710 is connected to the pixel driving circuit PDC.

[0326] In the pixel P, signal lines DL, GL, PL, RL, and SCL for supplying signals to the pixel driving circuit PDC are provided.

[0327] Data voltage Vdata is supplied to data line DL, scan signal SS is supplied to gate line GL, driving voltage Vdd for driving pixels is supplied to driving power line PL, reference voltage Vref is supplied to reference line RL, and sensing control signal SCS is supplied to sensing control line SCL.

[0328] refer to Figure 27 , assuming that the gate line of the nth pixel P is "GL n ", then the gate line of the n-1th pixel P adjacent to the nth pixel P is "GL n-1 ", and the gate line "GL n-1 ” is used as the sensing control line SCL of the n-th pixel P.

[0329] For example, the pixel driving circuit PDC includes a first thin film transistor TR1 (switching transistor) connected to the gate line GL and the data line DL, a second thin film transistor TR2 (driving transistor) for controlling the magnitude of the current output to the display element 710 according to the data voltage Vdata transmitted through the first thin film transistor TR1, and a third thin film transistor TR3 (reference transistor) for sensing the characteristics of the second thin film transistor TR2.

[0330] The first capacitor C1 is provided between the gate electrode G2 of the second thin film transistor TR2 and the display element 710. The first capacitor C1 is referred to as a storage capacitor Cst.

[0331] The first thin film transistor TR1 is turned on by the scan signal SS supplied to the gate line GL to transfer the data voltage Vdata supplied to the data line DL to the gate electrode G2 of the second thin film transistor TR2 .

[0332] The third thin film transistor TR3 is connected to the first node n1 between the second thin film transistor TR2 and the display element 710 and the reference line RL, thereby being turned on or off by the sensing control signal SCS and sensing characteristics of the second thin film transistor TR2 as a driving transistor during a sensing period.

[0333] A second node n2 connected to the gate electrode G2 of the second thin film transistor TR2 is connected to the first thin film transistor TR1. A first capacitor C1 is formed between the second node n2 and the first node n1.

[0334] When the first thin film transistor TR1 is turned on, the data voltage Vdata supplied through the data line DL is supplied to the gate electrode G2 of the second thin film transistor TR2. The data voltage Vdata charges the first capacitor C1 formed between the gate electrode G2 and the source electrode S2 of the second thin film transistor TR2.

[0335] When the second thin film transistor TR2 is turned on, current is supplied to the display element 710 via the second thin film transistor TR2 according to the driving voltage Vdd for driving the pixel, whereby light is output from the display element 710 .

[0336] Figure 28 is a circuit diagram illustrating any one pixel of the display device 1300 according to yet another embodiment of the present disclosure.

[0337] Figure 28 The pixel P of the display device 1300 shown includes an organic light emitting diode (OLED) as a display element 710 and a pixel driving circuit PDC for driving the display element 710. The display element 710 is connected to the pixel driving circuit PDC.

[0338] The pixel driving circuit PDC includes thin film transistors TR1 , TR2 , TR3 , and TR4 .

[0339] In the pixel P, signal lines DL, EL, GL, PL, SCL, and RL for supplying driving signals to the pixel driving circuit PDC are provided.

[0340] and Figure 27 Compared with the pixel P, Figure 28The pixel P further includes a light emitting control line EL. A light emitting control signal EM is supplied to the light emitting control line EL.

[0341] In addition, with Figure 27 Compared with the pixel driving circuit PDC, Figure 28 The pixel driving circuit PDC further includes a fourth thin film transistor TR4 as a light emission control transistor for controlling the light emission timing of the second thin film transistor TR2.

[0342] refer to Figure 28 , assuming that the gate line of the nth pixel P is "GL n ", then the gate line of the n-1th pixel P adjacent to the nth pixel P is "GL n-1 ", and the gate line "GL n-1 ” is used as the sensing control line SCL of the n-th pixel P.

[0343] The first capacitor C1 is provided between the gate G2 of the second thin film transistor TR2 and the display element 710. The second capacitor C2 is provided between one terminal of the fourth thin film transistor TR4 to which the driving voltage Vdd is supplied and one electrode of the display element 710.

[0344] The first thin film transistor TR1 is turned on by the scan signal SS supplied to the gate line GL to transmit the data voltage Vdata supplied to the data line DL to the gate electrode G2 of the second thin film transistor TR2 .

[0345] The third thin film transistor TR3 is connected to the reference line RL to be turned on or off by the sensing control signal SCS, and senses characteristics of the second thin film transistor TR2 as a driving transistor during a sensing period.

[0346] The fourth thin film transistor TR4 transmits the driving voltage Vdd to the second thin film transistor TR2 or disables the driving voltage Vdd according to the emission control signal EM. When the fourth thin film transistor is turned on, current is supplied to the second thin film transistor TR2, thereby outputting light from the display element 710.

[0347] In addition to the above structure, the pixel driving circuit PDC according to another embodiment of the present disclosure may be formed in various structures. For example, the pixel driving circuit PDC may include more than five thin film transistors.

[0348] According to the present disclosure, the following beneficial effects can be achieved.

[0349] A thin-film transistor substrate according to one embodiment of the present disclosure includes a second thin-film transistor designed to have a large s-factor. Because the second thin-film transistor includes a conductive material layer disposed between the substrate and the active layer and connected to the source electrode, the second thin-film transistor can have a large s-factor. The second thin-film transistor can serve as a driving thin-film transistor for a display device, enabling the display device to easily display grayscale.

[0350] A thin film transistor substrate according to one embodiment of the present disclosure includes a first thin film transistor designed to have a small s-factor and a second thin film transistor designed to have a large s-factor. The first thin film transistor can be used as a switching transistor due to its excellent switching characteristics, and the second thin film transistor can be used as a driving transistor due to its large s-factor. Therefore, a display device with both excellent switching characteristics and excellent driving characteristics can be manufactured using the thin film transistor substrate according to one embodiment of the present disclosure.

[0351] A display device according to another embodiment of the present disclosure includes a second thin film transistor having a relatively large s-factor, thereby having excellent grayscale representation capability.

[0352] It is obvious to those skilled in the art that the present disclosure is not limited to the above embodiments and drawings, and that various substitutions, modifications, and variations may be made in the present disclosure without departing from the spirit or scope of the present disclosure. Therefore, the scope of the present disclosure is defined by the appended claims, and all variations or modifications derived from the meaning, scope, and equivalents of the claims are within the scope of the present disclosure.

Claims

1. A thin film transistor substrate, comprising: Plastic substrates; a switching transistor on the plastic substrate; as well as a driving transistor on the plastic substrate, Wherein, the switching transistor includes: a first light-shielding layer on the plastic substrate; a first buffer layer on the first light-shielding layer; a first semiconductor layer on the first buffer layer, the first semiconductor layer having a first channel portion and comprising an oxide semiconductor material; a first gate overlapping the first channel portion; a first source electrode connected to the first semiconductor layer; and A first drain electrode spaced apart from the first source electrode and connected to the first semiconductor layer, the driving transistor comprising: a second light-shielding layer on the plastic substrate; the first buffer layer on the second light-shielding layer; a second semiconductor layer on the first buffer layer, the second semiconductor layer having a second channel portion and comprising an oxide semiconductor material; a second gate overlapping the second channel portion; a second source electrode connected to the second semiconductor layer; and a second drain electrode spaced apart from the second source electrode and connected to the second semiconductor layer, wherein the second light shielding layer is connected to the second semiconductor layer and overlaps with the second channel portion, The first semiconductor layer and the second semiconductor layer are provided on the same layer, The first light-shielding layer and the second light-shielding layer are each provided on a different layer, and A distance between the first light shielding layer and the first channel portion is different from a distance between the second light shielding layer and the second channel portion.

2. The thin film transistor substrate according to claim 1, wherein: A distance between the first light shielding layer and the first channel portion is greater than a distance between the second light shielding layer and the second channel portion.

3. The thin film transistor substrate according to claim 1, wherein: The second light shielding layer is connected to the second source electrode.

4. The thin film transistor substrate according to claim 1 , further comprising a second buffer layer, wherein the second buffer layer is disposed between the plastic substrate and the first buffer layer. in, The first light shielding layer is disposed between the second buffer layer and the plastic substrate, and Wherein, the second light shielding layer is arranged between the first buffer layer and the second buffer layer.

5. The thin film transistor substrate according to claim 1, wherein The s-factor of the driving transistor is greater than the s-factor of the switching transistor. The thin film transistor substrate according to claim 1 , wherein: The second light shielding layer does not overlap with the first channel portion.

7. The thin film transistor substrate according to claim 1, wherein: The first light shielding layer does not overlap with the second channel portion.

8. The thin film transistor substrate according to claim 1, wherein: The first buffer layer is disposed between the plastic substrate and the first semiconductor layer and between the plastic substrate and the second semiconductor layer.

9. The thin film transistor substrate according to claim 1, wherein: The first buffer layer has a thickness of 50 nm to 300 nm.

10. The thin film transistor substrate according to claim 1, wherein The first buffer layer includes: a hydrogen barrier layer on the second light-shielding layer; and A buffer insulating layer is on the hydrogen barrier layer.

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