Image sensing device

Abstract

The invention relates to an image sensing device. The image sensing device includes: a plurality of color filters; and a grid structure disposed between the color filters and configured to prevent optical crosstalk between adjacent color filters. The grid structure includes: a first cover layer configured to define and cover a space filled with air to form an air layer, and including a plurality of holes; and a second cover layer disposed at an outer surface and an inner surface of the first cover layer and configured to fill the plurality of holes.

Description

Technical Field

[0001] Techniques and embodiments disclosed in this patent document generally relate to image sensing devices. Background Art

[0002] Image sensors are used in electronic devices to convert optical images into electrical signals. With the recent development of the automotive, medical, computer, and communications industries, the demand for highly integrated, higher-performance image sensors has rapidly increased in various electronic devices (such as digital cameras, camcorders, personal communication systems (PCS), video game consoles, surveillance cameras, medical miniature cameras, robots, etc.). Summary of the Invention

[0003] Various embodiments of the disclosed technology relate to an image sensing device capable of improving the stability of a mesh structure including an air layer.

[0004] According to an embodiment of the disclosed technology, an image sensing device may include: a plurality of color filters; and a grid structure, which is arranged between the color filters and configured to prevent optical crosstalk between adjacent color filters, wherein the grid structure includes: a first covering layer, the first covering layer is configured to define and cover a space filled with air to form an air layer, and includes a plurality of holes; and a second covering layer, the second covering layer is arranged at the outer surface and the inner surface of the first covering layer and configured to fill the plurality of holes.

[0005] According to another embodiment of the disclosed technology, an image sensing device may include: a semiconductor substrate, the semiconductor substrate including: a photoelectric conversion element, the photoelectric conversion element being configured to generate photocharges by converting incident light; and a pixel isolation structure, the pixel isolation structure being arranged between the photoelectric conversion elements adjacent to each other; a buffer layer, the buffer layer being arranged above the semiconductor substrate; a grid structure, the grid structure being arranged above the buffer layer to overlap with the pixel isolation structure; and a color filter, the color filter being arranged in an area defined by the grid structure on the buffer layer, wherein the grid structure includes: an area including air and operating as an air layer; a first covering layer, the first covering layer covering the air layer and including a plurality of holes; and a second covering layer, the second covering layer being arranged at the outer surface and the inner surface of the first covering layer and configured to seal the air layer by filling the plurality of holes.

[0006] It is to be understood that both the foregoing general description and the following detailed description of the disclosed technology are exemplary and explanatory and are intended to provide further explanation of the disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The foregoing and other features and advantageous aspects of the disclosed technology will become apparent with reference to the following detailed description when considered in conjunction with the accompanying drawings.

[0008] Figure 1 is a block diagram illustrating an example of an image sensing device based on some embodiments of the disclosed technology.

[0009] Figure 2 The following are some examples of the technology disclosed. Figure 1 A plan view of an example of a grid structure in a pixel area is shown.

[0010] Figure 3A It is shown along Figure 2 The cross-sectional view of an example of the cross-sectional structure taken along the line AA' is shown, and Figure 3B It is shown along Figure 2 A cross-sectional view of an example of a cross-sectional structure taken along line BB' is shown.

[0011] Figures 4A to 4G is a diagram showing some embodiments of the disclosed technology for forming Figure 3A Cross-sectional view of an example of the method of mesh structure. DETAILED DESCRIPTION

[0012] This patent document provides embodiments and examples of image sensing devices that can be used to substantially resolve one or more technical or engineering problems and mitigate limitations or shortcomings encountered in some other image sensing devices. Some embodiments of the disclosed technology provide examples of image sensing devices that can improve the stability of a mesh structure including an air layer. In light of the aforementioned issues, the disclosed technology provides various embodiments of image sensing devices that can improve the stability of a mesh structure including an air layer.

[0013] Reference will now be made in detail to certain embodiments, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings to refer to the same or similar parts. In the following description, detailed descriptions of related known configurations or functions incorporated herein will be omitted to avoid obscuring the subject matter.

[0014] Hereinafter, various embodiments will be described with reference to the accompanying drawings. However, it should be understood that the disclosed technology is not limited to specific embodiments, but includes various modifications, equivalents, and / or alternatives of the embodiments. The embodiments of the disclosed technology can provide various effects that can be directly or indirectly recognized by the disclosed technology.

[0015] Figure 1 is a block diagram illustrating an example of an image sensing device based on some embodiments of the disclosed technology.

[0016] refer to Figure 1 , the image sensing device may include a pixel region 100 , a row driver 200 , a correlated double sampler (CDS) 300 , an analog-to-digital converter (ADC) 400 , an output buffer 500 , a column driver 600 , and a timing controller 700 . Figure 1 The components of the image sensing device shown in the foregoing are discussed by way of example only, and this patent document encompasses many other variations, substitutions, variations, alterations, and modifications. In this patent document, the word "pixel" may be used to refer to an image sensing pixel that is configured to detect incident light to generate an electrical signal that carries an image in the incident light.

[0017] The pixel area 100 may include a plurality of unit pixels arranged continuously in a two-dimensional (2D) structure. The unit pixel may convert incident light into an electrical signal corresponding to the incident light, may generate a pixel signal, and may output the pixel signal to the CDS 300 via a column line. The pixel area 100 may include a grid structure to prevent crosstalk between color filters of adjacent unit pixels. The grid structure may include a structure in which an air layer is covered or covered by a cover layer. In some embodiments, the grid structure may include a structure to prevent the cover layer from collapsing due to the expansion of the air layer during the heat treatment process. This anti-collapse structure will be described in more detail later.

[0018] The pixel region 100 may receive driving signals (eg, row selection signals, reset signals, transfer signals, etc.) from the row driver 200. Upon receiving the driving signals, the unit pixels may be activated to perform operations corresponding to the row selection signals, reset signals, and transfer signals.

[0019] The row driver 200 can activate the pixel area 100 based on a control signal provided by a controller circuit such as the timing controller 700 to perform certain operations on the unit pixels in the corresponding row. In some embodiments, the row driver 200 can select one or more pixel groups arranged in one or more rows of the pixel area 100. The row driver 200 can generate a row select signal to select one or more rows from a plurality of rows. The row driver 200 can sequentially enable a reset signal and a transfer signal for the unit pixels arranged in the selected row. The pixel signals generated by the unit pixels arranged in the selected row can be output to the correlated double sampler (CDS) 300.

[0020] The correlated double sampler (CDS) 300 can use correlated double sampling to remove undesired offset values ​​of unit pixels. In one example, the correlated double sampler (CDS) 300 can remove undesired offset values ​​of unit pixels by comparing the output voltages of the pixel signal (of the unit pixel) obtained before and after the photocharge generated by the incident light accumulates in the sensing node (i.e., the floating diffusion (FD) node). As a result, the CDS 300 can obtain a pixel signal generated only by the incident light without causing noise. In some embodiments, upon receiving a clock signal from the timing controller 700, the CDS 300 can sequentially sample and maintain the voltage levels of the reference signal and the pixel signal, which are provided to each of the multiple column lines from the pixel area 100. That is, the CDS 300 can sample and maintain the voltage levels of the reference signal and the pixel signal corresponding to each of the columns of the pixel area 100. In some embodiments, the CDS 300 may transmit the reference signal and the pixel signal of each of the columns to the ADC 400 as a correlated double sampling (CDS) signal based on a control signal from the timing controller 700 .

[0021] The ADC 400 is used to convert the analog CDS signal received from the CDS 300 into a digital signal. In some embodiments, the ADC 400 may be implemented as a ramp comparison ADC. The analog-to-digital converter (ADC) 400 may compare the ramp signal received from the timing controller 700 with the CDS signal received from the CDS 300, and may therefore output a comparison signal indicating a comparison result between the ramp signal and the CDS signal. The analog-to-digital converter (ADC) 400 may count the level transition time of the comparison signal in response to the ramp signal received from the timing controller 700, and may output a count value indicating the counted level transition time to the output buffer 500.

[0022] The output buffer 500 may temporarily store the column-based image data provided from the ADC 400 based on a control signal of the timing controller 700. The image data received from the ADC 400 may be temporarily stored in the output buffer 500 based on the control signal of the timing controller 700. The output buffer 500 may provide an interface to compensate for a data rate difference or a transmission rate difference between the image sensing device and other devices.

[0023] The column driver 600 may select a column of the output buffer 500 upon receiving a control signal from the timing controller 700, and sequentially output image data temporarily stored in the selected column of the output buffer 500. In some embodiments, upon receiving an address signal from the timing controller 700, the column driver 600 may generate a column selection signal based on the address signal, may select a column of the output buffer 500 using the column selection signal, and may control the image data received from the selected column of the output buffer 500 to be output as an output signal.

[0024] The timing controller 700 may generate signals for controlling the operations of the row driver 200, the ADC 400, the output buffer 500, and the column driver 600. The timing controller 700 may provide the row driver 200, the column driver 600, the ADC 400, and the output buffer 500 with clock signals required for the operations of the corresponding components of the image sensing device, control signals for timing control, and address signals for selecting rows or columns. In some embodiments, the timing controller 700 may include a logic control circuit, a phase-locked loop (PLL) circuit, a timing control circuit, a communication interface circuit, and the like.

[0025] Figure 2 The following are some examples of the technology disclosed. Figure 1 A plan view of an example of a grid structure in a pixel area is shown.

[0026] refer to Figure 2 , the pixel region 100 may include a plurality of unit pixels (PX) continuously arranged in a first direction (eg, an X-axis direction) and a second direction (eg, a Y-axis direction) perpendicular to the first direction.

[0027] The pixel region 100 may include a grid structure 130 disposed between the color filters 140 of adjacent unit pixels (PX) to prevent optical crosstalk between the adjacent color filters 140. The grid structure 130 may include a plurality of first portions extending in a first direction and a plurality of second portions extending in a second direction. Figure 2 In the example shown, the first and second portions of mesh structure 130 may extend across pixel region 100 and be disposed between color filters 140. The first and second portions of mesh structure 130 may be formed to intersect each other and surround each of color filters 140.

[0028] The grid structure 130 may include an air layer and a covering layer covering or shielding the air layer. The covering layer is configured to define a space filled with air to form the air layer. The covering layer may include a multi-layer structure in which a plurality of insulating layers are formed to overlap each other. Figure 3A and Figure 3BAs shown in the example of , the mesh structure 130 can be constructed to include such an air layer 132, a first cover layer 134 having holes 139, a second cover layer 136, and a support layer 138. The cover layer can include an ultra low temperature oxide (ULTO) layer, such as a silicon oxide (SiO2) layer.

[0029] Although the cover layer includes a plurality of insulating layers, the insulating layer of the cover layer may include a plurality of anti-collapse holes 139 through which a portion of the upper surface passes. The anti-collapse holes 139 may be formed to prevent the cover layer from collapsing due to expansion of an air layer during the process of forming the mesh structure 130.

[0030] although Figure 2 The example case where the anti-collapse holes 139 are formed only in some areas where the first and second parts are arranged to cross each other in the grid structure 130 is shown, but other embodiments are possible. It should be noted that the position and number of the anti-collapse holes 139 can be changed in various embodiments.

[0031] Figure 3A It is shown along Figure 2 The cross-sectional view of an example of the cross-sectional structure taken along the line AA' is shown, and Figure 3B It is shown along Figure 2 A cross-sectional view of an example of a cross-sectional structure taken along line BB' is shown.

[0032] refer to Figure 3A and Figure 3B , the pixel region 100 of the image sensing device may include a substrate layer 110 , a buffer layer 120 , a mesh structure 130 , a color filter 140 and a lens layer 150 .

[0033] The substrate layer 110 may include a substrate 112 , a photoelectric conversion element 114 , and a pixel isolation structure 116 .

[0034] The substrate 112 may include a semiconductor substrate having a first surface and a second surface facing the first surface or opposite the first surface. In this example, the first surface is the surface onto which light is incident, and the buffer layer 120, the mesh structure 130, the color filter 140, and the lens layer 150 may be formed thereon. The semiconductor substrate 112 may be in a single crystal state and may include a silicon-containing material. In some embodiments, the semiconductor substrate 112 may include a single crystal silicon-containing material. The semiconductor substrate 112 may include P-type impurities. The semiconductor substrate layer 110 may include a photoelectric conversion element 114.

[0035] The photoelectric conversion element 114 may convert incident light received through the first surface of the semiconductor substrate 112, resulting in the formation of photocharges. The photoelectric conversion element 114 may be formed in the semiconductor substrate 112 to correspond to the unit pixels (PX), respectively. In some embodiments, each of the photoelectric conversion elements 114 may be formed for each unit pixel (PX) in the semiconductor substrate 112. The photoelectric conversion elements 114 may be isolated from each other by a pixel isolation structure 116. Each photoelectric conversion element 114 may include an impurity region vertically stacked within the semiconductor substrate 112. For example, each photoelectric conversion element 114 may include a photodiode in which an N-type impurity region and a P-type impurity region are stacked in a vertical direction.

[0036] A pixel isolation structure 116 may be formed between adjacent photoelectric conversion elements 114 within the semiconductor substrate 112 so that the photoelectric conversion elements 114 can be isolated from each other for each pixel. In some embodiments, the pixel isolation structure 116 may include a trench structure such as back deep trench isolation (BDTI) or front deep trench isolation (FDTI). In some other embodiments, the pixel isolation structure 116 may include a junction isolation structure in which a high concentration of impurities (e.g., P-type impurities) are implanted into the semiconductor substrate 112.

[0037] The buffer layer 120 may be provided between the semiconductor substrate 112 and the color filter 140 on the first surface of the substrate layer 110. The buffer layer 120 may operate as a planarization layer to remove a step difference formed on the first surface of the substrate layer 110. In addition, the buffer layer 120 may operate as an anti-reflection layer to allow incident light to pass through the photoelectric conversion element 114.

[0038] The buffer layer 120 may include a multi-layer structure formed by stacking an oxide layer and a nitride layer. For example, the buffer layer 120 may include a lower buffer layer 120a and an upper buffer layer 120b.

[0039] The lower buffer layer 120a may be formed below the grid structure 130 and the color filter 140 on the substrate layer 110. In some embodiments, the lower buffer layer 120a may be formed entirely below the grid structure 130 and the color filter 140 on the substrate layer 110. The lower buffer layer 120a may include a first buffer layer to a third buffer layer (including 121, 122, 123). The first buffer layer 121 may include a metal oxide layer such as aluminum oxide (Al2O3) or hafnium oxide (HfO2). The second buffer layer 122 may include a silicon oxide (SiO2) layer, and the third buffer layer 123 may include a nitride layer such as a silicon nitride layer or a silicon oxynitride layer.

[0040] The upper buffer layer 120b may be formed between the lower buffer layer 120a and the color filter 140. The upper buffer layer 120b may include a fourth buffer layer 124 and a fifth buffer layer 125. The fourth buffer layer 124 and the fifth buffer layer 125 may be formed of the same material as the first capping layer 134 and the second capping layer 136 of the mesh structure 130, respectively, and may be formed together by the same deposition process. For example, the fourth buffer layer 124 and the fifth buffer layer 125 may be formed such that the first capping layer 134 and the second capping layer 136 extend below the color filter 140. The fourth buffer layer 124 and the fifth buffer layer 125 may include an ultra-low temperature oxide (ULTO) layer.

[0041] The grid structure 130 may be located between the color filters 140 to prevent optical crosstalk between adjacent color filters. The grid structure 130 may be arranged to overlap the pixel isolation structure 116 in a vertical direction. Each of the grid structures 130 may be configured to include a space filled with air as an air layer 132, a first cover layer 134, a second cover layer 136, and a support layer 138.

[0042] In some embodiments, the first cover layer 134 and the second cover layer 136 may cover or obscure the air layer 132. Figure 3A and Figure 3B In the example shown in FIG. 1 , the second cover layer 136 may include an inner cover layer 136a formed over the inner surface of the first cover layer 134 and an outer cover layer 136b formed over the outer surface of the first cover layer 134. In some embodiments, the inner cover layer 136a may surround the air layer 132. The first cover layer 134 may include an anti-collapse hole 139 connecting the inner cover layer 136a and the outer cover layer 136b to each other. The anti-collapse hole 139 is formed on the upper surface of the first cover layer 134 to provide a passage connecting the inner cover layer 136a and the outer cover layer 136b. The inner cover layer 136a and the outer cover layer 136b may be formed over the inner and outer surfaces of the first cover layer 134, respectively, and the air layer 132 may be sealed from external influences by filling the anti-collapse hole 139. Each of the inner cover layer 136a and the outer cover layer 136b may be formed thicker than the first cover layer 134. In some embodiments, the inner cover layer 136a and the outer cover layer 136b may be formed to have the same thickness.Each of the first cover layer 134 and the second cover layer 136 may include an ultra low temperature oxide (ULTO) layer.

[0043] The inner cover layer 136a and the air layer 132 may extend to the inside of the lower buffer layer 120a. For example, the bottom surface of the air layer 132 may extend to a position lower than the upper buffer layer 120b.

[0044] The support layer 138, which serves as a layer for maintaining the shape of the first cover layer 134, can support the first cover layer 134 while the air layer 132 is formed to prevent the first cover layer 134 from collapsing. The support layer 138 can be provided between the upper region of the first cover layer 134 and the inner cover layer 136a. The support layer 138 may include an insulating layer that does not have light absorption properties. For example, the support layer 138 may be or include an insulating layer having an etching selectivity different from that of a spin-on carbon (SOC) layer containing carbon, and may include a silicon oxynitride (SiON) layer.

[0045] Color filter 140 may filter light incident through lens layer 150 according to the color of the incident light and may allow the filtered light to pass through. Color filter 140 may be disposed in an area defined by grid structure 130 on substrate layer 110. Color filter 140 may be positioned to correspond to photoelectric conversion element 114. Color filter 140 may include a plurality of red filters, a plurality of green filters, and / or a plurality of blue filters. Color filters 140 may be arranged in a Bayer pattern.

[0046] The lens layer 150 may be disposed above the mesh structure 130 and the color filter 140 and may focus incident light onto the photoelectric conversion element 114. The lens layer 150 may include an overcoat layer 152 and microlenses 154. The overcoat layer 152 may function as a planarization layer to compensate for (or remove) a step difference formed by the mesh structure 130 and the color filter 140. The overcoat layer 152 may be formed of the same material as the microlenses 154. For example, the overcoat layer 152 may include a photoresist material.

[0047] Figures 4A to 4G is a diagram showing some embodiments of the disclosed technology for forming Figure 3A Cross-sectional view of an example of the method of mesh structure.

[0048] First, refer to Figure 4A , the lower buffer layer 120a can be formed above the substrate layer 110 in which the photoelectric conversion element and the pixel isolation structure are formed in the semiconductor substrate. For example, the first to third buffer layers (including 121, 122, 123) can be sequentially formed above the substrate layer 110. In this case, the first buffer layer 121 may include a metal oxide layer such as aluminum oxide (Al2O3) or hafnium oxide (HfO2). The second buffer layer 122 may include a silicon oxide (SiO2) layer, and the third buffer layer 123 may include a nitride layer such as a silicon nitride layer or a silicon oxynitride layer.

[0049] Subsequently, a trench 162 formed when a region in which the mesh structure 130 is to be formed in the lower buffer layer 120a is etched to a predetermined depth may be formed. The trench 162 may be formed to expose the first buffer layer 121.

[0050] refer to Figure 4B A sacrificial layer 132' may be formed over the lower buffer layer 120a having the trench 162 formed therein, and a support material layer 138' may be formed over the sacrificial layer 132'. In some embodiments, the sacrificial layer 132' may include a spin-on carbon (SOC) layer containing carbon, and the support material layer 138' may include a silicon oxynitride (SiON) layer.

[0051] Subsequently, a mask pattern 164 may be formed over the support material layer 138' to define an area to be covered by the first capping layer 134. For example, a mask pattern 164 may be formed over the support material layer 138' to define an area where the inner capping layer 136a and the air layer 132 of the mesh structure 130 are to be formed. The mask pattern 164 may include a photoresist pattern.

[0052] refer to Figure 4C , the support material layer 138 ′ and the sacrificial layer 132 ′ may be sequentially etched using the mask pattern 164 as an etching mask, so that a support layer pattern 138 ″ and a sacrificial layer pattern 132 ″ may be formed.

[0053] Subsequently, insulating layers 124 , 134 ′ may be formed to cover the lower buffer layer 120 a , the sacrificial layer pattern 132 ″, and the support layer pattern 138 ″. Each of the insulating layers 124 , 134 ′ may include an ultra low temperature oxide (ULTO) layer.

[0054] refer to Figure 4D , a mask pattern 166 may be formed over the insulating layers 124 and 134' defining the region where the anti-collapse holes 139 will be formed. For example, the mask pattern 166 may be formed to expose the insulating layer 134' in a region where the first portion of the mesh structure 130 intersects the second portion of the mesh structure 130. The mask pattern 166 may include a photoresist pattern.

[0055] Subsequently, the insulating layer 134 ′ and the supporting layer pattern 138 ″ are etched using the mask pattern 166 as an etching mask to expose the sacrificial layer pattern 132 ″, so that not only the first capping layer 134 including the collapse preventing hole 139 but also the supporting layer 138 may be formed.

[0056] Reference Figure 4E After removing the mask pattern 166, the sacrificial layer pattern 132" is removed by a plasma process, so that an air layer 132 may be formed where the sacrificial layer pattern 132" is removed. The plasma process may be performed using a gas including at least one of oxygen, nitrogen, or hydrogen (e.g., O2, N2, H2, CO, CO2, or CH4).

[0057] For example, if an O2 plasma process is performed, oxygen radicals (O*) may flow into the sacrificial layer pattern 132″ through the anti-collapse hole 139, and the oxygen radicals (O*) included in the sacrificial layer pattern 132″ may be combined with carbon of the sacrificial layer pattern 132″, resulting in the formation of CO or CO2. The formed CO or CO2 may be discharged to the outside through the anti-collapse hole 139. As a result, the sacrificial layer pattern 132″ may be removed, and an air layer 132 may be formed at the location where the sacrificial layer pattern 132″ is removed.

[0058] When the first covering layer 134 is formed into a thin film, during the O2 plasma process, oxygen radicals (O*) flow into the sacrificial layer pattern 132″ not only through the anti-collapse hole 139 but also through the first covering layer 134, so that the oxygen radicals (O*) can be combined with the carbon of the sacrificial layer pattern 132″. In addition, the formed CO or CO2 can be discharged to the outside not only through the anti-collapse hole 139 but also through the first covering layer 134.

[0059] If the O2 plasma process is performed in a state where the anti-collapse holes 139 are not formed in the first capping layer 134, the first capping layer 134 may collapse during the process of discharging the generated CO or CO2 through the first capping layer 134. However, as in the present embodiment, when the O2 plasma process is performed in a state where the anti-collapse holes 139 are formed in the first capping layer 134, the generated CO or CO2 is discharged through the anti-collapse holes 139, thereby preventing the first capping layer 134 from collapsing. When the sacrificial layer pattern 132″ is removed, the support layer 138 formed above the sacrificial layer pattern 132″ can support the first capping layer 134, so that the support layer 138 can prevent the first capping layer 134 from collapsing.

[0060] refer to Figure 4F The second capping layer 136 and the fifth buffer layer 125 may be formed by depositing an oxide layer on the inner and outer surfaces of the first capping layer 134 having the anti-collapse holes 139 formed therein. For example, an ultra-low temperature oxide (ULTO) layer may be deposited on the inner and outer surfaces of the first capping layer 134 using an atomic layer deposition (ALD) process and / or a chemical vapor deposition (CVD) process. In some embodiments, the second capping layer 136 may be made of the same material as the first capping layer 134 or a different material from the first capping layer 134.

[0061] When the air layer is formed using a plasma process, the thickness of the first capping layer 134 can be formed as thin as possible. As a result, after the air layer is formed, an additional deposition process is required to increase the thickness of the capping layer.

[0062] As in the present embodiment, when an oxide layer deposition process is performed on the first covering layer 134 including the anti-collapse hole 139 using an atomic layer deposition (ALD) process and / or a chemical vapor deposition (CVD) process, an inner covering layer 136a and an outer covering layer 136b are formed at the inner surface and outer surface of the first covering layer 134, respectively, and the anti-collapse hole 139 is also blocked by the oxide layer, resulting in the production of a second covering layer 136 formed to cover the air layer 132.

[0063] Each of the inner cover layer 136 a and the outer cover layer 136 b of the second cover layer 136 may be formed to be thicker than the first cover layer 134 , and the inner cover layer 136 a and the outer cover layer 136 b may be formed to have the same thickness.

[0064] refer to Figure 4G , the color filters 140 may be formed between the mesh structures 130 .

[0065] Subsequently, an overcoat layer 152 and microlenses 154 may be sequentially formed over the mesh structure 130 and the color filter 140 .

[0066] As is apparent from the above description, an image sensing device based on some embodiments of the disclosed technology can improve the stability of a mesh structure including an air layer.

[0067] The embodiments of the disclosed technology can provide various effects that can be directly or indirectly recognized through the above-mentioned patent documents.

[0068] Although a number of illustrative embodiments have been described, it should be understood that various modifications or enhancements of the disclosed embodiments and other embodiments may be devised based on what is described and / or illustrated in this patent document.

[0069] Priority and cross-reference to related applications

[0070] This patent document claims priority to and the benefit of Korean Patent Application No. 10-2024-0035835, filed on March 14, 2024, which is hereby incorporated by reference herein in its entirety as a part of the disclosure of this patent document.

Claims

1. An image sensing device, comprising: Multiple color filters; as well as a grid structure disposed between the color filters and preventing optical crosstalk between adjacent color filters, Wherein, the grid structure includes: a first covering layer defining and covering a space filled with air to form an air layer, the first covering layer including a plurality of holes; and A second covering layer is provided at the outer surface and the inner surface of the first covering layer and fills the plurality of holes.

2. The image sensing device according to claim 1, wherein The second covering layer comprises: an inner cover layer provided at an inner surface of the first cover layer; and An outer cover layer is provided at an outer surface of the first cover layer and is connected to the inner cover layer through the plurality of holes.

3. The image sensing device according to claim 2, wherein: A thickness of each of the inner cover layer and the outer cover layer is greater than a thickness of the first cover layer.

4. The image sensing device according to claim 2, wherein: The inner cover layer and the outer cover layer have the same thickness.

5. The image sensing device according to claim 2, wherein: The first cover layer and the outer cover layer extend to a lower portion of the color filter.

6. The image sensing device according to claim 5, wherein: The air layer extends to a position lower than the bottom surface of the first cover layer.

7. The image sensing device according to claim 2, further comprising: A support layer is provided between the first cover layer and the inner cover layer.

8. The image sensing device according to claim 1, wherein The grid structure includes: a first portion extending in a first direction; and a second portion extending in a second direction intersecting the first direction and intersecting the first portion, The plurality of holes are located in a region where the first portion and the second portion intersect each other.

9. The image sensing device according to claim 1, wherein: Each of the first capping layer and the second capping layer includes an ultra low temperature oxide (ULTO) layer.

10. An image sensing device, comprising: A semiconductor substrate comprising: a photoelectric conversion element that generates photocharges by converting incident light; and a pixel isolation structure disposed between adjacent photoelectric conversion elements; a buffer layer, the buffer layer being disposed above the semiconductor substrate; a grid structure disposed above the buffer layer to overlap the pixel isolation structure; and a color filter disposed in an area defined by the grid structure above the buffer layer, Wherein, the grid structure includes: A region that includes air and operates as an air layer; a first cover layer covering the air layer and including a plurality of holes; and a second cover layer that is provided at the outer surface and the inner surface of the first cover layer and seals the air layer by filling the plurality of holes.

11. The image sensing device according to claim 10, wherein: The second covering layer comprises: an inner cover layer provided at an inner surface of the first cover layer; and An outer cover layer is provided at an outer surface of the first cover layer and is connected to the inner cover layer through the plurality of holes.

12. The image sensing device according to claim 11, wherein A thickness of each of the inner cover layer and the outer cover layer is greater than a thickness of the first cover layer.

13. The image sensing device according to claim 11, wherein The inner cover layer and the outer cover layer have the same thickness.

14. The image sensing device according to claim 11, wherein The buffer layer comprises: a lower buffer layer disposed between the semiconductor substrate and the mesh structure and between the semiconductor substrate and the color filter; and An upper buffer layer is disposed between the lower buffer layer and the color filter.

15. The image sensing device according to claim 14, wherein: The first cover layer and the outer cover layer extend to operate as the upper buffer layer.

16. The image sensing device according to claim 15, wherein: The air layer extends to the interior of the lower buffer layer.

17. The image sensing device according to claim 11, further comprising: A support layer is provided between the first cover layer and the inner cover layer.

18. The image sensing device according to claim 10, wherein: The grid structure includes: a first portion extending in a first direction; and a second portion extending in a second direction intersecting the first direction and intersecting the first portion, The plurality of holes are located in a region where the first portion and the second portion intersect each other.

19. The image sensing device according to claim 10, wherein: Each of the first capping layer and the second capping layer includes an ultra low temperature oxide (ULTO) layer.

Images