Image sensor and electronic equipment thereof

Abstract

The embodiment of the invention provides an image sensor and electronic equipment. The image sensor comprises a first semiconductor structure and a second semiconductor structure which are stacked; the first semiconductor structure comprises a pixel array and a first interconnection layer, and the second semiconductor structure comprises a peripheral circuit and a second interconnection layer; the penetrating structure at least partially penetrates through the first semiconductor structure and is connected to the first interconnection layer or the second interconnection layer; the through structure comprises a main body structure and a stress protection structure, the stress protection structure is arranged around the main body structure, and the main body structure is connected to the first interconnection layer or the second interconnection layer; and the stress protection structure is arranged in the first interconnection layer and / or the second interconnection layer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to an image sensor and electronic equipment thereof. Background Art

[0002] Image sensors are used in a variety of electronic devices, including digital cameras and optical imaging devices, to capture images. Image sensors convert optical images into digital images. Currently, the most commonly used image sensors include complementary metal oxide semiconductor (CMOS) image sensors. CMOS image sensors offer low power consumption, small size, fast data processing capabilities, and low manufacturing costs.

[0003] CMOS image sensors typically feature TSVs (Through Silicon Vias) and BSVs (Back Side Vias), which connect to corresponding interconnect layers for signal connection and transmission. However, due to the mismatch between the stress of the BSVs / TSVs and the stress of the interconnect layers, this can cause deformation of the metal layers in the interconnect layers or cracks between the BSVs / TSVs and the surrounding semiconductor structures. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide an image sensor and an electronic device thereof.

[0005] To achieve the above objectives, the technical solution of the present disclosure is implemented as follows:

[0006] In a first aspect, an embodiment of the present disclosure provides an image sensor, comprising: a first semiconductor structure and a second semiconductor structure arranged in a stack; the first semiconductor structure comprises a pixel array and a first interconnection layer, and the second semiconductor structure comprises a peripheral circuit and a second interconnection layer; a through-structure, wherein the through-structure at least partially penetrates the first semiconductor structure and is connected to the first interconnection layer or the second interconnection layer; the through-structure comprises a main structure and a stress protection structure, wherein the stress protection structure is arranged around the main structure, and the main structure is connected to the first interconnection layer or the second interconnection layer; the stress protection structure is arranged in the first interconnection layer and / or the second interconnection layer.

[0007] In some embodiments, the stress protection structure includes at least one annular structure, each annular structure includes a plurality of protection columns arranged along the circumferential direction of the main structure, and each of the protection columns in the annular structure is equidistant from the main structure.

[0008] In some embodiments, the stress protection structure includes a first annular structure and a second annular structure, the first annular structure surrounds the main structure, and the second annular structure surrounds the first annular structure; the protection columns in the first annular structure and the protection columns in the second annular structure are aligned or staggered along the radial direction of the main structure.

[0009] In some embodiments, the stress protection structure includes at least one ring structure, and the ring structure is a closed figure.

[0010] In some embodiments, the stress protection structure includes a first annular structure and a second annular structure, wherein the first annular structure surrounds the main structure and the second annular structure surrounds the first annular structure; the distance between the first annular structure and the main structure is greater than the distance between the second annular structure and the first annular structure.

[0011] In some embodiments, the first interconnection layer includes multiple pixel metal layers, and the pixel metal layer closest to the second semiconductor structure among the multiple pixel metal layers is the top pixel metal layer; the second interconnection layer includes multiple peripheral metal layers, and the peripheral metal layer closest to the first semiconductor structure among the multiple peripheral metal layers is the top peripheral metal layer; the main structure is connected to the top pixel metal layer or the top peripheral metal layer.

[0012] In some embodiments, the stress protection structure is formed by the first interconnect layer.

[0013] In some embodiments, the first interconnection layer further includes a pixel plug for connecting adjacent pixel metal layers; the stress protection structure is formed by the top pixel metal layer, the pixel plug connected to the top pixel metal layer, and the pixel metal layer adjacent to the top pixel metal layer.

[0014] In some embodiments, the first semiconductor structure further includes a metal mesh structure, and the metal mesh structure is electrically connected to the through structure.

[0015] In some embodiments, the stress protection structure is formed by the first interconnect layer and the second interconnect layer.

[0016] In some embodiments, the first semiconductor structure further includes: a first bonding layer; the second semiconductor structure further includes: a second bonding layer; the first bonding layer and the second bonding layer are bonded and connected, and are located between the top pixel metal layer and the top peripheral metal layer.

[0017] In some embodiments, the main structure includes at least a conductive layer, a dielectric layer, and a filling layer.

[0018] In a second aspect, an embodiment of the present disclosure provides an electronic device, comprising: an image sensor as described in any one of the first aspects.

[0019] The embodiments of the present disclosure provide an image sensor and an electronic device. The image sensor includes: a first semiconductor structure and a second semiconductor structure arranged in a stack; the first semiconductor structure includes a pixel array and a first interconnect layer, and the second semiconductor structure includes a peripheral circuit and a second interconnect layer; a through-structure, the through-structure at least partially penetrates the first semiconductor structure and is connected to the first interconnect layer or the second interconnect layer; the through-structure includes a main structure and a stress protection structure, the stress protection structure is arranged around the main structure, and the main structure is connected to the first interconnect layer or the second interconnect layer; the stress protection structure is arranged in the first interconnect layer and / or the second interconnect layer. The through-structure provided by the embodiments of the present disclosure includes a main structure and a stress protection structure, the stress protection structure is arranged around the main structure, thereby avoiding stress mismatch through the stress protection structure, and can also use the stress protection structure to block the intrusion of water vapor from the external environment. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A schematic structural diagram of an image sensor provided in an embodiment of the present disclosure;

[0021] Figure 2 A top view of a through-structure provided in an embodiment of the present disclosure Figure 1 ;

[0022] Figure 3 A top view of a through-structure provided in an embodiment of the present disclosure Figure 2 ;

[0023] Figure 4 A top view of a through-structure provided in an embodiment of the present disclosure Figure 3 ;

[0024] Figure 5 A top view of a through-structure provided in an embodiment of the present disclosure Figure 4 ;

[0025] Figure 6 A top view of a through-structure provided in an embodiment of the present disclosure Figure 5 ;

[0026] Figure 7 A top view of a through-structure provided in an embodiment of the present disclosure Figure 6 ;

[0027] Figure 8 for Figure 2 Cross-sectional view along AA' direction;

[0028] Figure 9 for Figure 3 Cross-sectional view along AA' direction;

[0029] Figure 10 for Figure 4 Cross-sectional view along AA' direction;

[0030] Figure 11 for Figure 5 Cross-sectional view along AA' direction;

[0031] Figure 12 for Figure 6 Cross-sectional view along AA' direction;

[0032] Figure 13 for Figure 7 Cross-sectional view along AA' direction. DETAILED DESCRIPTION

[0033] The following will clearly and completely describe the technical solutions in the embodiments of the present disclosure in conjunction with the embodiments of the present disclosure and the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0034] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0035] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0036] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. However, when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part exists in the present disclosure.

[0037] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0038] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0039] In order to fully understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below. However, in addition to these detailed descriptions, the present disclosure may also have other implementation methods.

[0040] Image sensors are semiconductor devices that convert optical information into electrical signals. For example, they can convert the variable attenuation of light waves into signals (i.e., small bursts of current that convey information). Such image sensors include charge-coupled device (CCD) image sensors and complementary metal oxide semiconductor (CMOS) image sensors. Based on the differences in the optical path, CMOS image sensors can be further divided into front-side illumination (FSI) image sensors and back-side illumination (BSI) image sensors.

[0041] Please refer to Figure 1 The image sensor includes a pixel area PA and a peripheral area LA, wherein the peripheral area LA is located on at least one side of the pixel area PA. Figure 1The peripheral area LA is shown as being located around the pixel area PA. Of course, the peripheral area LA can also be located on two or three sides of the pixel area PA, and can be specifically arranged as needed. The pixel area PA is the core area of ​​the image sensor, mainly responsible for capturing light and converting light signals into electrical signals. The pixel area PA mainly includes: photodiode (Photodiode), transfer transistor (Transistor), reset transistor (Reset Transistor), source follower (Source Follower) or amplification transistor (Amplification Transistor) and row select transistor (Row Select Transistor). The peripheral area surrounds the pixel area and is mainly responsible for signal processing, control and interface functions. It mainly includes: readout circuitry (Readout Circuitry), control circuitry (Control Circuitry), row / column driver circuits (Row / Column Driver Circuits), timing and logic circuits (Timing and Logic Circuits), interface circuits (Interface Circuits), memory circuits (Memory Circuits), power management circuits (Power Management Circuits), etc. The peripheral area LA usually has TSVs and BSVs, which are connected to the corresponding interconnect layers for signal connection and transmission. However, the mismatch between the stress of the BSV / TSV and the stress of the interconnect layer can cause severe stress effects, leading to deformation of the metal layer in the interconnect layer or cracks between the BSV / TSV and the surrounding semiconductor structure, significantly reducing the performance of the semiconductor structure. Furthermore, deformation and cracks in the metal layer can also lead to moisture intrusion.

[0042] To this end, the present disclosure proposes the following embodiments.

[0043] An embodiment of the present disclosure provides an image sensor, which includes: a first semiconductor structure and a second semiconductor structure arranged in a stacked manner; the first semiconductor structure includes a pixel array and a first interconnect layer, and the second semiconductor structure includes a peripheral circuit and a second interconnect layer; a through-structure, which at least partially penetrates the first semiconductor structure and is connected to the first interconnect layer or the second interconnect layer; the through-structure includes a main structure and a stress protection structure, the stress protection structure is arranged around the main structure, and the main structure is connected to the first interconnect layer or the second interconnect layer; the stress protection structure is arranged in the first interconnect layer and / or the second interconnect layer.

[0044] The through-structure provided by the embodiment of the present disclosure includes a main structure and a stress protection structure. The stress protection structure is arranged around the main structure, thereby avoiding stress mismatch through the stress protection structure, and can also use the stress protection structure to block the intrusion of water vapor in the external environment.

[0045] It should be noted that for ease of description, various directions that may be used in the following description are first defined. The direction perpendicular to the substrate is defined as the vertical direction (Z direction), and the direction parallel to the substrate is defined as the horizontal direction. A first horizontal direction (X direction) and a second horizontal direction (Y direction) that intersect are defined in a plane parallel to the substrate. The X direction, Y direction, and Z direction may be perpendicular to each other.

[0046] The following Figures 2 to 7 The penetration structures are described in detail. Figures 2 to 7 Schematic diagrams of several through-structures provided in the embodiments of the present disclosure, wherein: Figures 2 to 5 In, the structure is as BSV; Figures 6 and 7 In the embodiment, the through-structure is used as TSV.

[0047] In some embodiments, the stress protection structure includes at least one annular structure, each annular structure includes a plurality of protection columns arranged along the circumferential direction of the main structure, and each protection column in the annular structure is at an equal distance from the main structure. Figure 2 As shown, the stress protection structure 220 includes an annular structure comprising eight protection pillars 221 arranged along the circumference of the main structure 210. The eight protection pillars 221 are distributed around the main structure 210, and each protection pillar 221 in the stress protection structure 220 is equidistant from the main structure 210. In one specific example, the distance between the protection pillars and the main structure 210 is greater than 100 nm.

[0048] In some embodiments, the number of protective pillars may be set according to stress requirements. To ensure stress matching between the BSV / TSV stress and the stress of the interconnect layer, there are no less than two protective pillars on each side of the main structure.

[0049] It should be noted that Figure 2 The number of protective columns shown in the figure is only an example, and the number of protective columns in the present disclosure is not limited to Figure 2 Quantity shown.

[0050] In some embodiments, the stress protection structure has two annular structures, namely a first annular structure and a second annular structure. The first annular structure surrounds the main structure, and the second annular structure surrounds the first annular structure. The protective columns in the first annular structure and the protective columns in the second annular structure are aligned or staggered along the radial direction of the main structure.

[0051] like Figure 3 As shown, the stress protection structure 300 includes a first annular structure 310 and a second annular structure 320. The first annular structure 310 surrounds the main structure 210, and the second annular structure 320 surrounds the first annular structure 310. The first annular structure 310 includes eight protective pillars 311 arranged along the circumference of the main structure 210, and the second annular structure 320 includes eight protective pillars 321 arranged along the circumference of the main structure 210. The protective pillars 311 and 321 are aligned in the radial direction (horizontal direction) of the main structure 210. In one specific example, the distance between the protective pillars 311 and the main structure 210 is greater than 100 nm. The distance between the protective pillars 311 and 321 is greater than 60 nm. In other embodiments, the protective pillars in the first annular structure and the protective pillars in the second annular structure are staggered along the radial direction of the main structure. For example, along the radial direction of the main structure, a protective pillar in the second annular structure is located between two adjacent protective pillars in the first annular structure.

[0052] In some embodiments, the material of the stress protection structures 220 and 300 is different from that of the main structure 210, but the material of the stress protection structures 220 and 300 is the same as that of the metal layer in the interconnect layer. As a result, the stress protection structures 220 and 300 can effectively absorb the diffusion stress of the main structure 210, thereby preventing deformation of the metal layer. Furthermore, the stress protection structures 220 and 300 can prevent the diffusion of the metal layer and protect the main structure 210, thereby improving device performance.

[0053] In some embodiments, the stress protection structure includes at least one ring-shaped structure, which is a closed shape. A closed ring structure can effectively block the intrusion of water vapor from the external environment. Furthermore, multiple ring structures can further prevent stress effects and significantly enhance water vapor barrier capabilities.

[0054] like Figure 4 As shown, the stress protection structure 410 includes a closed ring structure, which surrounds the main structure 210. In a specific example, the distance between the closed ring structure and the main structure 210 is greater than 100 nm.

[0055] like Figure 6 As shown, the stress protection structure 620 includes a closed ring structure, which surrounds the main structure 610. In a specific example, the distance between the closed ring structure and the main structure 610 is greater than 100 nm.

[0056] In some embodiments, the stress protection structure includes a first annular structure and a second annular structure, wherein the first annular structure surrounds the main structure and the second annular structure surrounds the first annular structure; the distance between the first annular structure and the main structure is greater than the distance between the second annular structure and the first annular structure.

[0057] In some embodiments, the first annular structure and the second annular structure may form concentric rings around the main structure, for example, circular rings, square rings, rectangular rings, or other desired shapes.

[0058] like Figure 5 As shown, the stress protection structure 500 includes a first ring structure 510 and a second ring structure 520. The first ring structure 510 and the second ring structure 520 are both closed shapes. In one specific example, the distance between the first ring structure 510 and the main structure 210 is greater than 100 nm. The distance between the first ring structure 510 and the second ring structure 520 is greater than 60 nm.

[0059] like Figure 7 As shown, the stress protection structure 700 includes a first ring structure 710 and a second ring structure 720. The first ring structure 710 and the second ring structure 720 are both closed shapes. In one specific example, the distance between the first ring structure 710 and the main structure 610 is greater than 100 nm. The distance between the first ring structure 710 and the second ring structure 720 is greater than 60 nm.

[0060] It should be noted that Figures 2 to 5 In FIG, the main structure 210 is a BSV connected to the first interconnect layer. Figures 6 and 7 In FIG, the main structure 610 is a TSV connected to the second interconnect layer.

[0061] Figures 8 to 13 They are Figures 2 to 7 The cross-sectional view along line AA. Figures 8 to 13As shown, the image sensor provided by the present disclosure can be a back-illuminated image sensor; the first semiconductor structure 100 can be a pixel wafer (Pixel Wafer), which can be a wafer specifically used to manufacture the pixel array in the image sensor, on which a large number of pixel units are integrated, and each pixel unit contains a photodiode, a transfer transistor, a reset transistor, an amplifier transistor and other structures for capturing light and converting it into an electrical signal; the second semiconductor structure 200 can be a logic wafer (Logic Wafer) of an integrated circuit, on which peripheral circuits such as a readout circuit, a control circuit, a row / column drive circuit, a timing and logic circuit, an interface circuit, and a power management circuit are integrated, which are used to process the signal output by the pixel array and realize the readout, processing and transmission of the image. The pixel wafer and the logic wafer are combined by bonding technology to form a complete image sensor.

[0062] In some embodiments, the first semiconductor structure 100 and the second semiconductor structure 200 are stacked in a vertical direction.

[0063] In some embodiments, the first semiconductor structure 100 includes a pixel array, which includes a plurality of pixel units. The plurality of pixel units can be arranged in an array along the X direction and the Y direction. The first semiconductor structure 100 also includes a metal grid structure 101. The metal grid structure 101 can also extend along the X direction and the Y direction. The plurality of pixel units are located between the mutually intersecting metal grid structures 101. The metal grid structure 101 can also be arranged around the array composed of the plurality of pixel units. The metal grid structure can specifically be a backside metal grid (BMG). The function of the BMG is to reduce crosstalk when light is incident from the back side of the first semiconductor structure, thereby improving image quality. In addition to reducing crosstalk and optimizing the optical path, the metal grid structure 101 can also serve as part of the signal transmission path.

[0064] In some embodiments, the metal mesh structure 101 is electrically connected to the through-structure. When the through-structure serves as a BSV, in the embodiments of the present disclosure, the metal mesh structure 101 is electrically connected to the through-structure, so that the image sensor signal can be transmitted from the back side through the first interconnect layer 110 to the analog-to-digital conversion circuit in the first semiconductor structure, thereby achieving an electrical connection between the pixel units in the pixel array and the analog-to-digital conversion circuit, thereby achieving analog-to-digital conversion.

[0065] BSV enables post-positioning of metal wiring in back-side illuminated (BSI) sensors, eliminating light obstruction by metal lines in traditional front-illuminated structures. BSV allows signals or power to be directly connected to circuits on the front of the first semiconductor structure through BSV vias on the back of the first semiconductor structure, thereby reducing signal paths, improving device performance, and facilitating a more compact packaging design.

[0066] It should be noted that the first semiconductor structure 100 includes a front side and a back side, and the front side and the back side are two opposite sides along the vertical direction (Z direction), wherein the back side of the first semiconductor structure 100 is the side away from the second semiconductor structure 200, and the front side of the first semiconductor structure 100 is the side close to the second semiconductor structure 200.

[0067] In some embodiments, the second semiconductor structure 200 includes a substrate 201 and a peripheral circuit 202 located on the substrate 201. The second semiconductor structure 200 also includes a second interconnect layer 203, which is electrically connected to the peripheral circuit 202. The substrate 201 can be made of a semiconductor material, an insulating material, a conductive material, or any combination thereof. The substrate 201 can be a single-layer structure or a multi-layer structure. For example, the substrate 201 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 201 can be a layered substrate including Si / SiGe, Si / SiC, silicon on insulator (SOI), or silicon germanium on insulator.

[0068] In some embodiments, the first semiconductor structure 100 includes a first interconnect layer 110, and the first interconnect layer 110 includes multiple pixel metal layers. Figures 8 to 13 As shown, the first interconnection layer 110 includes at least a first pixel metal layer M1, a second pixel metal layer M2, a third pixel metal layer M3, a fourth pixel metal layer M4, and a fifth pixel metal layer M5, arranged in sequence from top to bottom. The multiple pixel metal layers can be connected by pixel plugs 102 and separated by an interlayer dielectric layer 103. The pixel plugs 102 include a first pixel plug located between the first pixel metal layer M1 and the second pixel metal layer M2, a second pixel plug located between the second pixel metal layer M2 and the third pixel metal layer M3, a third pixel plug located between the third pixel metal layer M3 and the fourth pixel metal layer M4, and a fourth pixel plug located between the fourth pixel metal layer M4 and the fifth pixel metal layer M5.

[0069] The through-hole structure provided in the present disclosure can be used as either a BSV or a TSV, or both. That is, the through-hole structure can implement the BSV function of electrically connecting to the first interconnect layer 110, and can also implement the TSV function of electrically connecting the first semiconductor structure to the second semiconductor structure.

[0070] It should be noted that Figures 8 to 11 In FIG, the main structure 210 is a BSV connected to the top pixel metal layer (M5) in the first interconnect layer. Figures 12 to 13 In FIG. 6 , the main structure 610 is a TSV connected to the top peripheral metal layer M6 in the second interconnect layer 203 .

[0071] In some embodiments, the pixel metal layer closest to the second semiconductor structure 200 among the multiple pixel metal layers is the top pixel metal layer. Figures 8 to 13 As shown, the top pixel metal layer is the fifth pixel metal layer M5.

[0072] In some embodiments, the stress protection structure is formed by the pixel plug connecting the top pixel metal layer and the pixel metal layer adjacent to the top pixel metal layer.

[0073] Combine Figure 2 and Figure 8 As shown, the protection column 221 in the stress protection structure 220 is formed by the fourth pixel metal layer M4 and the fourth pixel plug (102), and the stress protection structure 220 is connected to the top pixel metal layer (M5) through the fourth pixel plug (102). The main structure 210 is also connected to the top pixel metal layer (M5).

[0074] Combine Figure 3 and Figure 9 As shown, the protection columns 311 and 321 in the stress protection structure 300 are both formed by the fourth pixel metal layer M4 and the fourth pixel plug (102), and the stress protection structure is connected to the top pixel metal layer (M5) through the fourth pixel plug (102). The main structure 210 is also connected to the top pixel metal layer (M5).

[0075] In some embodiments, the dimension of the protection pillar ( 221 , 311 , 321 ) along the horizontal direction is greater than the dimension of the pixel plug 102 along the horizontal direction.

[0076] In some embodiments, the stress protection structure is formed by the first interconnect layer. In other words, the stress protection structure can be formed synchronously with the first interconnect layer. Specifically, the stress protection structure and the fourth pixel metal layer M4 and the fourth pixel plug (102) in the first interconnect layer 110 can be formed synchronously. The fourth pixel metal layer M4 is connected to the top pixel metal layer (M5) through the fourth pixel plug (102), which can enhance the bonding effect between the top pixel metal layer (M5) and other metal layers, and prevent deformation or cracks caused by the mismatch between the stress of the BSV (main structure 210) and the stress of the first interconnect layer 110.

[0077] Combine Figure 4 and Figure 10 As shown, the stress protection structure 410 is composed of the first pixel metal layer M1, the first pixel plug, the second pixel metal layer M2, the second pixel plug, the third pixel metal layer M3, the third pixel plug, the fourth pixel metal layer M4, and the fourth pixel plug. The stress protection structure is connected to the top pixel metal layer (M5) through the fourth pixel plug. In other words, the stress protection structure 410 extends from the first pixel metal layer M1 to the top pixel metal layer (M5).

[0078] Combine Figure 5 and Figure 11 As shown, the first ring structure 510 and the second ring structure 520 in the stress protection structure 500 are both formed by the first pixel metal layer M1, the first pixel plug, the second pixel metal layer M2, the second pixel plug, the third pixel metal layer M3, the third pixel plug, the fourth pixel metal layer M4, and the fourth pixel plug. The stress protection structure is connected to the top pixel metal layer (M5) through the fourth pixel plug. In other words, the first ring structure 510 and the second ring structure 520 extend from the first pixel metal layer M1 to the top pixel metal layer (M5).

[0079] In the disclosed embodiment, the stress protection structure can be formed simultaneously with the first pixel metal layer M1, the first pixel plug, the second pixel metal layer M2, the second pixel plug, the third pixel metal layer M3, the third pixel plug, the fourth pixel metal layer M4, and the fourth pixel plug in the first interconnect layer 110. The stress protection structure can enhance the adhesion between the top pixel metal layer (M5) and the other metal layers, preventing deformation or cracks caused by the mismatch between the stress of the BSV (main structure 210) and the stress of the first interconnect layer 110. The stress protection structure can also form a water vapor barrier to prevent the intrusion of water vapor from the external environment.

[0080] In some embodiments, the main structure 210 is connected to the top pixel metal layer (M5). Figure 8 and Figure 11As shown, the main structure 210 in the through-structure penetrates the first semiconductor structure 100 from the back side of the first semiconductor structure 100 and extends to the top pixel metal layer (M5). The main structure is connected to the fifth pixel metal layer M5. Here, the main structure in the through-structure acts as a BSV.

[0081] It should be noted that the main body structure 210 is connected to the fifth pixel metal layer M5, which means that the bottom of the main body structure 210 is in contact with the fifth pixel metal layer M5.

[0082] In some embodiments, the second semiconductor structure includes a second interconnect layer 203, and the second interconnect layer 203 includes multiple peripheral metal layers. Figures 8 to 13 Only the peripheral metal layer closest to the first semiconductor structure 100 in the second interconnect layer 203, ie, the top peripheral metal layer M6, is shown. The second interconnect layer 203 may also include other peripheral metal layers not shown in the figure, which are not limited in the present disclosure.

[0083] In some embodiments, the stress protection structure is formed by the first interconnect layer 110 and the second interconnect layer 203. In other words, the stress protection structure can be formed simultaneously with the first interconnect layer 110 and the second interconnect layer 203.

[0084] Combine Figure 6 and Figure 12 As shown, the stress protection structure 620 includes a first portion 621 located in the first semiconductor structure 100 and a second portion 622 located in the second semiconductor structure 200. The first portion 621 is formed by the first pixel metal layer M1, the first pixel plug, the second pixel metal layer M2, the second pixel plug, the third pixel metal layer M3, the third pixel plug, the fourth pixel metal layer M4, the fourth pixel plug, and the fifth pixel metal layer M5. The second portion 622 is formed by the peripheral plug 204 connected to the top peripheral metal layer M6 and the peripheral metal layer M7 adjacent to the top peripheral metal layer M6. The second portion 622 is connected to the top peripheral metal layer M6 via the peripheral plug 204. The orthographic projections of the first portion 621 and the second portion 622 on the substrate 201 overlap.

[0085] Combine Figure 7 and Figure 13As shown, the first ring structure 710 in the stress protection structure 700 includes a first portion 711 located in the first semiconductor structure 100 and a second portion 712 located in the second semiconductor structure 200. The second ring structure 720 in the stress protection structure 700 includes a first portion 721 located in the first semiconductor structure 100 and a second portion 722 located in the second semiconductor structure 200. The first portions 711 and 721 are both formed by the first pixel metal layer M1, the first pixel plug, the second pixel metal layer M2, the second pixel plug, the third pixel metal layer M3, the third pixel plug, the fourth pixel metal layer M4, the fourth pixel plug, and the fifth pixel metal layer M5. The second portions 712 and 722 are both formed by the peripheral plug 204 connected to the top peripheral metal layer M6 and the peripheral metal layer M7 adjacent to the top peripheral metal layer M6. The second portions 712 and 722 are connected to the top peripheral metal layer M6 via the peripheral plug 204. Furthermore, the orthographic projections of the first portion 711 and the second portion 712 on the substrate 201 overlap, and the orthographic projections of the first portion 721 and the second portion 722 on the substrate 201 overlap.

[0086] In the disclosed embodiment, the first portion and the first pixel metal layer M1, the first pixel plug, the second pixel metal layer M2, the second pixel plug, the third pixel metal layer M3, the third pixel plug, the fourth pixel metal layer M4, and the fourth pixel plug in the first interconnect layer 110 can be formed simultaneously, and the second portion and the peripheral plug 204 and the peripheral metal layer M7 adjacent to the top peripheral metal layer M6 can be formed simultaneously. This can enhance the adhesion between the top peripheral metal layer M6 and the other metal layers, preventing deformation or cracks caused by the stress mismatch between the TSV (main structure 610) and the stress of the second interconnect layer 203. In addition, the stress protection structure can also form a water vapor barrier to prevent the intrusion of water vapor from the external environment.

[0087] In some embodiments, the first portion extends from the first pixel metal layer M1 to the fifth pixel metal layer M5 .

[0088] In other embodiments, the second portion is formed by all peripheral metal layers and peripheral plugs included in the second interconnect layer 203. In other words, the second portion may extend from the top peripheral metal layer M6 to the device structure on the substrate 201. Thus, the second portion may also form a water vapor barrier to prevent water vapor from invading the external environment.

[0089] In some embodiments, the main structure is connected to the top peripheral metal layer. Figure 12 and Figure 13As shown, the main structure 610 in the through-structure penetrates the first semiconductor structure 100 from the back side of the first semiconductor structure 100 and extends to the top peripheral metal layer M6 in the second semiconductor structure 200. The main structure 610 is connected to the top peripheral metal layer M6. Here, the main structure 610 in the through-structure acts as a TSV.

[0090] It should be noted that the main structure 610 being connected to the top peripheral metal layer M6 means that the bottom of the main structure 610 is in contact with the top peripheral metal layer M6.

[0091] In a specific example, the stress protection structure, the pixel metal layer, the pixel plug, the peripheral metal layer, and the peripheral plug are made of copper.

[0092] In some embodiments, the main structure includes at least a conductive layer, a dielectric layer, and a filler layer. The conductive layer in the main structure is connected to the metal mesh structure. In a specific example, the conductive layer and the metal mesh structure are made of tungsten.

[0093] like Figures 8 to 11 As shown, the main structure 210 includes at least a conductive layer 211, a dielectric layer 212, and a filling layer 213. The conductive layer 211 in the main structure 210 is connected to the metal mesh structure 101, and the material of the conductive layer 211 is the same as that of the metal mesh structure 101.

[0094] like Figures 12 to 13 As shown, the main structure 610 includes at least a conductive layer 611, a dielectric layer 612, and a filling layer 613. The conductive layer 611 in the main structure 610 is connected to the metal mesh structure 101, and the material of the conductive layer 611 is the same as that of the metal mesh structure 101.

[0095] In some embodiments, the image sensor further includes: a bonding layer BF, located between the top pixel metal layer M5 and the top peripheral metal layer M6. Specifically, the first bonding layer in the first semiconductor structure 100 and the second bonding layer in the second semiconductor structure 200 are bonded to obtain the bonding layer BF. The first bonding layer includes a first bonding pad, and the second bonding layer includes a second bonding pad; the first bonding pad and the second bonding pad are bonded to each other. In the embodiment of the present disclosure, the materials of the first bonding pad and the second bonding pad can be copper, nickel, cobalt, gold, tin, aluminum and / or any alloy material based on such metal materials, and the first bonding pad and the second bonding pad are dielectric materials. The bonding method of the first bonding layer and the second bonding layer can be hybrid bonding. It should be noted that the "bonding" referred to in the present disclosure can be any appropriate bonding technology, such as the hybrid bonding, anodic bonding, melt bonding, transfer bonding, adhesive bonding and eutectic bonding mentioned above.

[0096] In some embodiments, the first semiconductor structure further includes a transistor T, the transistor T having a source S, a drain D and a gate G, the source S and the drain D being electrically connected to the first pixel metal layer M1; it should be noted that the metal layers of the same layer may not be completely connected due to reasons such as wiring density, signal isolation and thermal management, such as Figure 8 and Figure 13 As shown, the source S and the drain D are both electrically connected to the first pixel metal layer M1 , but since the first pixel metal layer M1 is not continuous, the source and the drain can transmit signals separately through the pixel metal layer.

[0097] The embodiments of the present disclosure provide an image sensor and an electronic device. The image sensor includes: a first semiconductor structure and a second semiconductor structure arranged in a stack; the first semiconductor structure includes a pixel array and a first interconnect layer, and the second semiconductor structure includes a peripheral circuit and a second interconnect layer; a through-structure, the through-structure at least partially penetrates the first semiconductor structure and is connected to the first interconnect layer or the second interconnect layer; the through-structure includes a main structure and a stress protection structure, the stress protection structure is arranged around the main structure, and the main structure is connected to the first interconnect layer or the second interconnect layer; the stress protection structure is arranged in the first interconnect layer and / or the second interconnect layer. The through-structure provided by the embodiments of the present disclosure includes a main structure and a stress protection structure, the stress protection structure is arranged around the main structure, thereby avoiding stress mismatch through the stress protection structure, and can also use the stress protection structure to block the intrusion of water vapor from the external environment.

[0098] The present disclosure also provides an electronic device including the above-mentioned image sensor. The electronic device may be a camera, a video camera, an artificial intelligence device, a wearable device, or other imaging device that captures digital image data.

[0099] It should be noted that the electronic device and other details are similar to the structure of the aforementioned image sensor. For the parts not mentioned, reference can be made to the embodiments of the aforementioned image sensor, and they will not be described in detail here.

[0100] It should be understood that “one embodiment” or “an embodiment” mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, “in one embodiment” or “in an embodiment” appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0101] The above description is only a preferred embodiment of the present disclosure and does not limit the patent scope of the present disclosure. All equivalent structural transformations made by using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or direct / indirect application in other related technical fields are included in the patent protection scope of the present disclosure.

Claims

1. An image sensor, characterized in that: include: A first semiconductor structure and a second semiconductor structure are stacked; The first semiconductor structure includes a pixel array and a first interconnect layer, and the second semiconductor structure includes a peripheral circuit and a second interconnect layer; a through structure, the through structure at least partially penetrating the first semiconductor structure and connected to the first interconnect layer or the second interconnect layer; The through structure includes a main structure and a stress protection structure, wherein the stress protection structure is arranged around the main structure, and the main structure is connected to the first interconnection layer or the second interconnection layer; The stress protection structure is provided in the first interconnect layer and / or the second interconnect layer.

2. The image sensor according to claim 1, wherein The stress protection structure includes at least one annular structure, each annular structure includes a plurality of protection columns arranged along the circumferential direction of the main structure, and each of the protection columns in the annular structure is equidistant from the main structure.

3. The image sensor according to claim 2, wherein: The stress protection structure includes a first annular structure and a second annular structure, the first annular structure surrounds the main structure, and the second annular structure surrounds the first annular structure; the protection columns in the first annular structure and the protection columns in the second annular structure are aligned or staggered along the radial direction of the main structure.

4. The image sensor according to claim 1, wherein The stress protection structure includes at least one annular structure, and the annular structure is a closed figure.

5. The image sensor according to claim 4, wherein: The stress protection structure includes a first annular structure and a second annular structure, wherein the first annular structure surrounds the main structure and the second annular structure surrounds the first annular structure; the distance between the first annular structure and the main structure is greater than the distance between the second annular structure and the first annular structure.

6. The image sensor according to any one of claims 1 to 5, characterized in that The first interconnect layer includes multiple pixel metal layers, and the pixel metal layer closest to the second semiconductor structure among the multiple pixel metal layers is a top pixel metal layer; The second interconnect layer includes a plurality of peripheral metal layers, wherein the peripheral metal layer closest to the first semiconductor structure among the plurality of peripheral metal layers is a top peripheral metal layer; The main structure is connected to the top pixel metal layer or the top peripheral metal layer.

7. The image sensor according to claim 6, wherein: The stress protection structure is formed by the first interconnection layer.

8. The image sensor according to claim 6, wherein: The first interconnect layer further includes a pixel plug for connecting adjacent pixel metal layers; The stress protection structure is formed by the pixel plug connected to the top pixel metal layer and the pixel metal layer adjacent to the top pixel metal layer.

9. The image sensor according to claim 7 or 8, characterized in that The first semiconductor structure further includes a metal mesh structure electrically connected to the through structure.

10. The image sensor according to claim 6, wherein: The stress protection structure is formed by the first interconnection layer and the second interconnection layer.

11. The image sensor according to claim 1, wherein The first semiconductor structure further includes: a first bonding layer; the second semiconductor structure further includes: a second bonding layer; the first bonding layer and the second bonding layer are bonded and connected, and are located between the top pixel metal layer and the top peripheral metal layer.

12. The image sensor according to claim 1, wherein The main structure at least includes a conductive layer, a dielectric layer and a filling layer.

13. An electronic device, characterized in that: The electronic device comprises: the image sensor according to any one of claims 1-12.

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