Preparation method of solar cell and solar cell

Abstract

The invention provides a preparation method of a solar cell and the solar cell, and relates to the technical field of solar cells, and the method comprises the steps: firstly obtaining a cell main body sheet, then forming a passivation protection layer on the surface of the cell main body sheet, and then printing on the passivation protection layer to form a grid line. After the grid lines are formed, a first preset reverse bias voltage can be applied to the edge grid lines, a second preset reverse bias voltage can be applied to the middle grid lines, and then laser scanning is carried out. Compared with the prior art, the embodiment of the invention has the advantages that different preset reverse bias voltages are applied to different probe rows, a row of probe rows is newly added at the edge and smaller bias voltage is applied, so that the actual potential at the pressing point can be reduced, and the pressing point is not influenced by the reverse bias voltage applied to the middle probe row. The voltage of the edge area is small, the high temperature problem caused by scanning after bias voltage is applied can be effectively relieved, the abnormal phenomenon of black edges is effectively reduced, and the product yield and quality are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and in particular to a method for preparing a solar cell and the solar cell. Background Art

[0002] During the production of solar cells, silicon wafers undergo a series of treatments before being coated, and silver electrodes are subsequently formed via screen printing. However, the coating process on current production lines has certain technical flaws. Specifically, the silicon wafers are carried by a graphite boat during coating. However, because the silicon wafers are not tightly fitted to the boat blades, wrap-around coating occurs at the edge of the silicon wafer during the coating process. This wrap-around coating significantly increases the film thickness at the edge of the silicon wafer, while the film layer in the middle area is relatively thin, resulting in an uneven film thickness distribution. This uneven film distribution can adversely affect subsequent processes.

[0003] LECO (Laser-enhanced contact optimization) technology provides an effective means to improve the efficiency of solar cells. Especially in the pursuit of high-performance photovoltaic devices, it can significantly improve the contact quality between the electrode and the semiconductor layer, reduce contact resistance, and improve carrier collection efficiency.

[0004] During the electrode preparation stage (the gate line formation stage), thermal sintering is usually required. During the sintering stage, the glass component in the slurry corrodes and opens the silicon nitride film layer. The silver particles in the slurry then form an ohmic contact with the silicon substrate, thus forming an electrode. However, due to the thicker edge film layer, the edge film layer may not be fully opened. During the LECO (Laser-enhanced contact optimization) process, a normal bias voltage is applied and laser scanning is performed. Since the edge part of the film layer is not fully opened, a higher temperature will be caused in the edge area, resulting in overburning of the surrounding area, which will cause the black edge abnormality and affect the yield and quality. Summary of the Invention

[0005] The object of the present invention is to provide a method for preparing a solar cell and a solar cell, which can effectively reduce the black edge abnormality through bias control and improve product yield and quality.

[0006] In one aspect, an embodiment of the present invention provides a method for preparing a solar cell, comprising: Obtain the battery main body sheet; forming a passivation protection layer on the battery main body sheet; forming a gate line on the passivation protection layer; Applying a first preset reverse bias voltage to the edge gate lines, and applying a second preset reverse bias voltage to the middle gate lines; Laser scanning is performed on the passivation protection layer to ensure that the grid lines are in sintered contact with the battery main body sheet; The first preset reverse bias voltage is smaller than the second preset reverse bias voltage.

[0007] In an optional embodiment, the first preset reverse bias voltage is 3V-10V, and the second preset reverse bias voltage is 10V-20V.

[0008] In an optional embodiment, before the step of applying a first preset reverse bias voltage to the edge gate lines and applying a second preset reverse bias voltage to the middle gate lines, the preparation method includes: Pressing a first probe row onto the gate line in the edge area of ​​the passivation protection layer; The second probe row is pressed onto the gate line in the middle area of ​​the passivation protection layer.

[0009] In an optional embodiment, the step of pressing the first probe row onto the gate line in the edge region of the passivation protection layer includes: Partitioning the passivation protection layer along the width direction of the gate line to divide the passivation protection layer into a first side edge region, a first side middle region, a second side middle region, and a second side edge region that are sequentially connected, wherein the first side edge region and the second side edge region are located at both side edge regions of the passivation protection layer, and the first side middle region and the second side middle region are located at a middle region of the passivation protection layer; The first probe row is pressed onto the corresponding gate line, wherein the corresponding gate line is located in the first side edge region or in the second side edge region.

[0010] In an optional embodiment, the step of pressing the first probe row onto the corresponding gate line includes: The first probe row is aligned with the gate lines in the first side edge region and then pressed downward until the first probe row contacts the corresponding gate lines and the pressing force reaches a preset value.

[0011] In an optional embodiment, the step of forming a gate line on the passivation protection layer includes: The gate lines are formed on the surface of the passivation protection layer by screen printing.

[0012] In an optional embodiment, after the step of forming gate lines by screen printing on the surface of the passivation protection layer, the preparation method further comprises: The grid lines are sintered in a hot furnace.

[0013] In an optional embodiment, after the step of forming gate lines by screen printing on the surface of the passivation protection layer, the preparation method further comprises: Light is injected into the main cell sheet.

[0014] In an optional embodiment, the step of forming a passivation protection layer on the battery main body sheet includes: Depositing an aluminum oxide layer and a silicon nitride layer in sequence on the front surface of the battery main body sheet; Depositing a silicon nitride layer on the back side of the battery main body sheet; The thickness of the middle region of the silicon nitride layer is smaller than the thickness of the edge region.

[0015] In an optional embodiment, the thickness of the middle region of the silicon nitride layer is between 75 nm and 85 nm.

[0016] In an optional embodiment, the step of obtaining a battery main sheet includes: Texturing is performed on the front and back sides of the N-type silicon wafer to form a velvet surface; Performing boron diffusion doping on the front surface of the N-type silicon wafer to form a P+ diffusion layer and a borosilicate glass layer distributed in sequence; forming a silicon oxide layer and a polysilicon layer on the back side of the N-type silicon wafer; Diffusion-doping the polysilicon layer on the back side of the N-type silicon wafer with phosphorus to form an N+ diffusion layer and a phosphorus silicon glass layer distributed in sequence; The borosilicate glass layer and the phosphosilicate glass layer are removed.

[0017] In another aspect, an embodiment of the present invention provides a solar cell manufactured using the aforementioned method for manufacturing a solar cell, the solar cell comprising: Battery main body; A passivation protection layer, the passivation protection layer is provided on the battery main body sheet; a gate line, the gate line being arranged on the passivation protection layer; The grid line passes through the passivation protection layer and is sintered into contact with the battery main body sheet.

[0018] In an optional embodiment, the battery main body includes an N-type silicon wafer, a P+ diffusion layer, a silicon oxide layer and an N+ diffusion layer, the front side of the N-type silicon wafer is formed with a velvet surface, the P+ diffusion layer is arranged on the front side of the N-type silicon wafer, and the silicon oxide layer and the N+ diffusion layer are arranged in sequence on the back side of the N-type silicon wafer.

[0019] The beneficial effects of the embodiments of the present invention include: The method for preparing a solar cell and the solar cell provided by an embodiment of the present invention include: first, obtaining a battery main body sheet, then forming a passivation protective layer on the surface of the battery main body sheet, the passivation protective layer being able to cover the front and back of the battery main body sheet, and then printing and sintering on the passivation protective layer to form grid lines. Since the passivation protective layer in the middle area is of normal thickness (thinner), the grid lines in the middle area can open the passivation protective layer and directly contact the surface of the battery main body sheet. However, the passivation protective layer in the edge area will significantly increase in thickness (thicker) due to the plating phenomenon, so the grid lines in the edge area do not completely open the passivation protective layer. After the grid lines are formed by printing and sintering, a first preset reverse bias can be applied to the edge grid lines, and a second preset reverse bias can be applied to the middle grid lines, and then laser scanning can be performed so that the grid lines in the edge area of ​​the passivation protective layer can open and penetrate the passivation protective layer to contact the battery main body sheet, and the grid lines are sintered to contact the battery main body sheet, wherein the first preset reverse bias is less than the second preset reverse bias. Compared with the existing technology, the embodiment of the present invention applies different preset reverse bias voltages through different probe rows, and the voltage in the edge area is relatively small, which can effectively alleviate the high temperature problem caused by scanning after applying the bias, effectively reduce the black edge abnormality, and improve product yield and quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0021] Figure 1 A schematic diagram of the temperature generated by applying bias voltage at different positions in the LECO process in the prior art; Figure 2 A diagram showing the steps of a method for preparing a solar cell according to an embodiment of the present invention; Figures 3 to 11 for Figure 2 Process flow chart of step S1; Figure 12 for Figure 2 The process diagram of step S2; Figure 13 for Figure 2 The process diagram of step S3; Figure 14 for Figure 2 The process diagram of step S4; Figure 15 for Figure 2 Process diagram of step S5 and step S6; Figure 16 for Figure 2 Process diagram of step S7 and step S8; Figure 17 A schematic structural diagram of a solar cell provided by an embodiment of the present invention.

[0022] Icons: 100-solar cell; 110-cell main body; 111-N-type silicon wafer; 112-P+ diffusion layer; 113-silicon oxide layer; 114-N+ diffusion layer; 115-aluminum oxide layer; 116-borosilicate glass layer; 117-polysilicon layer; 118-phosphosilicate glass layer; 130-passivation protection layer; 131-first side edge region; 133-first side middle region; 135-second side middle region; 137-second side edge region; 150-gate line; 200a-probe row; 200b-second probe row; 300-laser scanning equipment. DETAILED DESCRIPTION

[0023] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0024] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but rather merely represents selected embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort shall fall within the scope of protection of the present invention.

[0025] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not require further definition or explanation in subsequent drawings.

[0026] In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the accompanying drawings, or is the orientation or position relationship in which the product of the invention is usually placed when in use. It is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be understood as a limitation on the present invention.

[0027] In addition, the terms "first", "second", etc., if used, are merely used to distinguish and describe, and should not be understood as indicating or implying relative importance.

[0028] As disclosed in the background, in the existing LECO (Laser Enhanced Contact Optimization) process, laser scanning is typically performed under normal bias voltage. However, due to the thicker film layer in the edge region, the electrode is not fully opened during fabrication, resulting in increased resistance in this area and a significant local temperature rise under the laser. This temperature anomaly can cause overheating, which in turn affects the performance and quality of the cell. Therefore, optimizing the bias setting and controlling the temperature distribution in the edge region have become key challenges in improving LECO process stability and product quality.

[0029] As researchers have discovered, in the existing LECO (laser enhanced contact optimization) process, the probe row is currently pressed on the grid lines on one side of the cell (usually pressed on the 2nd to 4th grid lines from the edge), and the laser scans the other half. During scanning, the laser power and bias voltage remain constant, resulting in a relatively large bias voltage applied to the edge area. Therefore, the process intensity is relatively high, and the silicon nitride film area at the edge of the cell fails to fully open, generating ultra-high temperatures, which causes overburning and produces black edges.

[0030] like Figure 1 As shown, the left side shows the state of the membrane layer being normally opened, and the silver electrode completely penetrates the membrane layer and forms direct contact with the silicon wafer below. When a -20V bias is applied and laser scanning is performed, the temperature distribution diagram shows that the maximum temperature is about 600°C. This temperature range is suitable for the laser sintering process. The battery cell can be laser sintered normally to form a good ohmic contact, which can ensure a good ohmic contact between the silver electrode and the silicon wafer, thereby ensuring the stable performance of the battery cell. In contrast, the right side shows a state where the membrane layer is not fully opened, and the silver electrode fails to penetrate the membrane layer, resulting in poor contact between the electrode and the silicon wafer. Under the same -20V bias, the temperature distribution diagram shows that the local temperature rises sharply to about 8000°C, far exceeding the normal process range. This abnormally high temperature can cause the battery cell to overburn, forming defects such as black edges, seriously affecting the yield and performance of the product.

[0031] The prior art typically addresses this issue by increasing the sintering furnace temperature. This involves raising the temperature before the LECO process, allowing the glass in the slurry to further corrode and break open the film. However, this excessively high temperature can affect the cell's passivation, reducing its electrical performance. It can also cause the silver powder to partially alloy with the silicon substrate, impacting electrical performance. Alternatively, the prior art also employs an overall reduction in bias voltage to reduce overall process intensity. However, this approach results in insufficient temperatures in the central region, hindering the formation of a good ohmic contact.

[0032] To optimize the process, it's crucial to focus on bias voltage settings to ensure the silver electrode fully penetrates the film. The inventors discovered that by adding a probe row at the edge and applying a lower bias voltage, the actual potential at that point can be reduced, unaffected by the reverse bias applied by the middle probe row. This allows for processing of the edge region and effectively mitigates high temperatures at the edge during laser scanning.

[0033] See also Figures 2 to 17 In order to solve the above problems, the embodiments of the present invention provide a novel method for preparing a solar cell 100 and a solar cell 100. It should be noted that the features in the embodiments of the present invention can be combined with each other without conflict.

[0034] The present invention provides a method for fabricating a solar cell 100 that, through bias control, effectively mitigates high temperatures in edge regions, effectively reducing the black edge phenomenon caused by increased process intensity, and improving product yield and quality. Furthermore, the method is simple to operate, requires minimal changes to existing processes, and offers high compatibility and guaranteed process efficiency.

[0035] See also Figure 2 The method for preparing the solar cell 100 provided by the embodiment of the present invention includes the following steps: S1: Obtain the battery main body sheet 110.

[0036] See also Figures 3 to 11 Specifically, the cell main body 110 may be a tunnel oxide passivated contact cell (TOPCon) or a back contact cell (BC), or may be a solar cell 100 having other doped polysilicon layers 117 . In this embodiment, a tunnel oxide passivated contact cell (TOPCon) is used as an example for explanation. The tunnel oxide passivated contact cell (i.e., TOPCon cell) is a passivated contact type cell. It reduces minority carrier recombination (i.e., the process of recombination of minority carriers and majority carriers in a semiconductor) by isolating the metal from the silicon substrate through a thin film. A layer of ultra-thin silicon oxide is prepared on the back of the cell, and then a thin layer of doped polycrystalline silicon is deposited to form a passivated contact structure. The ultra-thin silicon oxide can allow majority electrons to tunnel into the polycrystalline silicon layer 117, and can also block the recombination of minority carriers and holes, so that electrons are transmitted laterally in the polycrystalline silicon layer 117 and collected by the metal, thereby greatly reducing the metal contact recombination current, improving the open circuit voltage and short circuit current of the cell, and thus improving the cell conversion efficiency, the open circuit voltage and the short circuit current of the cell.

[0037] In actual preparation, step S1 may specifically include the following steps (steps S101 to S106): S101: Texturing is performed on the front and back surfaces of the N-type silicon wafer 111 to form a textured surface.

[0038] See also Figure 3 Specifically, the N-type silicon wafer 111 may be cleaned first and then textured to form a nano-scale textured surface and a pyramid structure on the front and back surfaces of the N-type silicon wafer 111. The textured process here can refer to conventional textured processes and will not be described in detail here.

[0039] S102 : performing boron diffusion doping on the front surface of the N-type silicon wafer 111 to form a P+ diffusion layer 112 and a borosilicate glass layer 116 that are distributed in sequence.

[0040] See also Figure 4 Specifically, a boron diffusion step can be performed first. This involves introducing BCl3 gas to diffuse boron onto the front surface of the textured N-type silicon wafer 111. This forms a doped P+ diffusion layer 112 and a boron-doped silicon glass (BSG) layer 116 on the front surface of the N-type silicon wafer 111, while a boron-doped silicon glass layer 116 is formed on the back surface of the N-type silicon wafer 111. During the boron diffusion process, the edges of the main cell wafer 110 may be expanded around.

[0041] See also Figure 5 Then, hydrofluoric acid can be used to pickle and remove the borosilicate glass layer 116 on the back of the N-type silicon wafer 111. Hydrofluoric acid is used to remove the borosilicate glass layer 116 on the back and edge sides, exposing the P+ diffusion layer 112 on the edge sides and back, while retaining the borosilicate glass layer 116 on the front.

[0042] See also Figure 6 The back of the N-type silicon wafer 111 is then cleaned and polished with a sodium hydroxide solution to form a flat surface structure. A backside alkaline polishing process can be performed to remove the edge and backside wraparound while retaining the borosilicate glass layer 116 on the front side.

[0043] S103 : forming a silicon oxide layer 113 and a polysilicon layer 117 on the back surface of the N-type silicon wafer 111 , and forming a polysilicon layer 117 on the surface of the borosilicate glass layer 116 .

[0044] See also Figure 7Specifically, a silicon oxide layer 113 with a thickness of 1-2 nm can be formed on the entire back surface of the N-type silicon wafer 111. For example, the thickness of silicon oxide layer 113 can be any value among 1 nm, 1.5 nm, and 2 nm, or a value between any two values. Preferably, silicon oxide layer 113 has a thickness of 1.6 nm, forming a tunneling oxide layer. A polysilicon layer 117 with a thickness of 120-150 nm is then grown on silicon oxide layer 113. The thickness of polysilicon layer 117 can be any value among 120 nm, 135 nm, and 150 nm, or a value between any two values. Preferably, the thickness of polysilicon layer 117 is 150 nm. Polysilicon layer 117 serves as a passivation layer. Polysilicon layer 117 is also formed on borosilicate glass layer 116 on the front surface of N-type silicon wafer 111. That is, the LPCVD process (Low Pressure Chemical Vapor Deposition) is used to form a tunneling oxide layer and a poly silicon passivation layer.

[0045] S104 : performing phosphorus diffusion doping on the polysilicon layer 117 on the back side of the N-type silicon wafer 111 to form an N+ diffusion layer 114 and a phosphorus silicon glass layer 118 that are distributed in sequence.

[0046] See also Figure 8 Specifically, phosphorus is first diffused into the polysilicon layer 117 on the back side of the N-type silicon wafer 111 to form an N+ polysilicon layer 117 and a phosphorus-doped silicon glass (PSG) layer 118. The sheet resistance of the N+ polysilicon layer 117 is 40-50Ω, for example, any value among 40Ω, 45Ω, and 50Ω, or a value between any two values, preferably 45Ω. Simultaneously, an N+ polysilicon layer 117 and a phosphorus-doped silicon glass layer 118 are formed on the front side of the N-type silicon wafer 111. A phosphorus diffusion process is then performed to dope the polysilicon on the back side with phosphorus to form an N+ diffusion layer 114 and a phosphorus-doped silicon glass layer 118.

[0047] S105 : removing the borosilicate glass layer 116 and the phosphosilicate glass layer 118 .

[0048] See also Figure 9 Specifically, the phosphosilicate glass layer 118 on the front and edge of the N-type silicon wafer 111 is first removed by a roller-moving chain-type hydrofluoric acid pickling method.

[0049] See also Figure 10 Then, a sodium hydroxide solution bath alkaline cleaning method is used to remove the polysilicon layer 117 on the front and edge of the N-type silicon wafer 111. Finally, a hydrofluoric acid bath pickling method (RCA) is used to remove the borosilicate glass layer 116 on the front of the N-type silicon wafer 111 and the phosphosilicate glass layer 118 on the back of the N-type silicon wafer 111.

[0050] After completing step S105, the battery main body 110 is obtained, and the subsequent process of the battery main body 110 can be completed (continuing to execute steps S2 to S5). Of course, in other preferred embodiments of the present invention, other pre-processes can also be used to obtain the battery main body 110.

[0051] S2: forming a passivation protection layer 130 on the battery main sheet 110 .

[0052] Specifically, the front passivation protective layer 130 may include an aluminum oxide layer 115 and a silicon nitride layer. First, an aluminum oxide layer 115 may be deposited on the front of the battery main body 110, followed by a silicon nitride layer. Then, a silicon nitride layer may be deposited on the back of the battery main body 110. The thickness of the silicon nitride layer in the middle region is thinner than that in the edge regions. Preferably, the thickness of the silicon nitride layer in the middle region is between 75 nm and 85 nm, for example, any one of 75 nm, 80 nm, or 85 nm, or a value between any two of these values.

[0053] In actual preparation, in actual preparation, see Figure 11 First, aluminum oxide can be deposited on the P+ diffusion layer 112 on the front surface of the N-type silicon wafer 111 using ALD (Atomic Layer Deposition) under vacuum at 300°C. Water / TMA / N2 is introduced to form a 4-6 nm thick aluminum oxide layer 115. For example, the thickness can be any value among 4 nm, 5 nm, or 6 nm, or any value between two values. The aluminum oxide here serves as a passivation agent.

[0054] Then, see Figure 12 On the aluminum oxide layer 115 on the front of the N-type silicon wafer 111, NH3 and SiH4 were introduced under vacuum to form a silicon nitride layer with a thickness of approximately 78 nm using PECVD. It should be noted that the deposition thickness here refers to the thickness of the silicon nitride layer in the middle region.

[0055] Then, NH3 and SiH4 are introduced under vacuum to form a SiN layer with a thickness of about 80 nm on the N+ diffusion layer 114 on the back side of the N-type silicon wafer 111 using a PECVD (Plasma-Enhanced Chemical Vapor Deposition) deposition process.

[0056] It should be noted that the passivation protective layer 130 here covers the entire front and back sides of the N-type silicon wafer 111. Due to process reasons, wrap-around plating occurs at the edges, resulting in the passivation protective layer 130 being thicker at the edges than in the middle. Subsequent laser scanning only scans the passivation protective layer 130 on the front or back sides.

[0057] S3 : forming a gate line 150 on the passivation protection layer 130 .

[0058] See also Figure 13 Specifically, the gate line 150 can be formed by screen printing on the surface of the passivation protection layer 130, and then the gate line 150 is sintered in a hot furnace, and light is injected into the battery main body 110. During actual preparation, electrodes can be printed on the front and back of the N-type silicon wafer 111. The electrode printing process can refer to the existing printed electrode preparation process. After printing, sintering and light injection are performed to form the gate line 150. The gate line 150 can be a silver electrode. Among them, there are multiple gate lines 150, and the multiple gate lines 150 are evenly spaced along the width direction on the surface of the passivation protection layer 130. In addition, when performing hot furnace sintering, conventional heating sintering is performed in a sintering furnace, which mainly relies on the temperature generated by the heat of the infrared lamp. The sintering temperature can be adjusted through the parameters on the panel.

[0059] It should be noted that since the thickness of the passivation layer 130 in the middle region is within a preset range, partial contact between the gate lines 150 and the silicon substrate can be achieved after sintering. Specifically, the thickness of the passivation layer 130 in the first side middle region 133 and the second side middle region 135 is the preset thickness. Therefore, after the printed gate lines 150 are sintered, the passivation layer 130 can be opened, allowing the gate lines 150 to directly contact the battery main body 110, allowing for normal scanning during subsequent laser scanning. However, the thickness of the passivation layer 130 in the first side edge region 131 and the second side edge region 137 is slightly greater than the preset thickness. Therefore, during the electrode printing process, due to the integrated process, the passivation layer 130 in the edge regions is not fully opened, resulting in no direct contact between the gate lines 150 and the battery main body 110. Therefore, a low reverse bias voltage must be applied to the edge regions and laser scanning is performed to mitigate overheating caused by localized high temperatures. Therefore, applying a low reverse bias voltage to the edge regions and laser scanning mitigates overheating caused by localized high temperatures.

[0060] S4 : Pressing the first probe row 200 a onto the gate line 150 in the edge region of the passivation protection layer 130 .

[0061] See also Figure 14Specifically, after the gate line 150 is prepared, the first probe row 200a can be positioned and pressed onto the gate line 150 in the edge area. First, the passivation protection layer 130 can be partitioned along the width direction of the gate line 150 to divide the passivation protection layer 130 into a first side edge area 131, a first side middle area 133, a second side middle area 135, and a second side edge area 137, which are connected in sequence. The first side edge area 131 and the second side edge area 137 are located at the side edge areas of the passivation protection layer 130, and the first side middle area 133 and the second side middle area 135 are located in the middle area of ​​the passivation protection layer 130. Then, the first probe row 200a is pressed onto the corresponding gate line 150, wherein the corresponding gate line 150 is located in the first side edge area 131 or the second side edge area 137.

[0062] It should be noted that the first side edge area 131, the first side middle area 133, the second side middle area 135 and the second side edge area 137 are spliced ​​in sequence along the width direction of the gate line 150. Specifically, the gate line 150 here refers to the gate line, and the width direction of the gate line 150 refers to the direction perpendicular to the extension direction of the gate line. In addition, the first side edge area 131, the first side middle area 133, the second side middle area 135 and the second side edge area 137 can be divided by a virtual line distributed on the passivation protection layer 130, and the virtual line is parallel to the extension direction of the gate line 150. There is a gate line 150 in the first side edge area 131 and the second side edge area 137. There are multiple gate lines 150 in the first side middle area 133 and the second side middle area 135. During actual pressing, the first probe row 200a can be pressed on the gate line 150 at the edge.

[0063] In actual operation, the battery cell can be fixed with a positioning clamp and placed on the processing table, and an additional image recognition device can be designed above the passivation protection layer 130. Specifically, the image recognition device can obtain image information of the entire passivation protection layer 130 and divide the passivation protection layer 130 into a first side edge area 131, a first side middle area 133, a second side middle area 135, and a second side edge area 137. The partitioning rules can be pre-set in the image recognition device. The image recognition device is connected to the robot arm of the first probe row 200a and the laser scanning device 300 in communication, and can accurately place the first probe row 200a into the corresponding partition (i.e., the first side edge area 131 or the second side edge area 137).

[0064] It should be noted that the first probe row 200a can be in the form of an elongated strip, with a width greater than the width of the gate line 150 and less than the width of the gap between two adjacent gate lines 150. Furthermore, the length of the first probe row 200a can be adapted to the length of the gate line 150, so that the first probe row 200a can be fully pressed onto the corresponding gate line 150 to ensure electrical connection. The structure, materials, and operating principle of the first probe row 200a can refer to existing probe structures and will not be described in detail here.

[0065] In certain embodiments, the first probe row 200a is pressed onto the step on the corresponding grid line 150. During actual operation, the battery main body sheet 110 can be placed on the processing table after the mechanical arm adsorption rotation is first utilized, and then the first probe row 200a is pressed down after being aligned with the corresponding grid line 150, until the first probe row 200a contacts the corresponding grid line 150 and the pressing force reaches a preset value. Wherein, a tiny pressure sensor can be set on the first probe row 200a. During the pressing process, the pressure sensor can monitor the pressure value in real time. After contacting and applying a certain pressure, the pressing action of the first probe row 200a can be stopped. Alternatively, a pressure sensor can be set between the first probe row 200a and the mechanical arm, and the reverse pressure that the first probe row 200a is subjected to is monitored at all times, and then it is judged that the first probe row 200a is pressed into place. If the pressing amount of the first probe row 200a is too large, there will be a hidden crack in the battery cell. If the pressing amount is too small, there will be a situation in which the battery cell cannot be processed. Conventional techniques typically rely on the experience of equipment personnel to adjust the pressing depth after replacing the first probe row 200a, resulting in poor reliability and difficulty in achieving automated operation. However, in the embodiments of the present invention, a tiny pressure sensor is installed on the first probe row 200a. This pressure sensor is able to communicate with the driving structure that pushes the first probe row 200a downward. Once the first probe row 200a contacts the gate line 150 and applies a certain pressure (e.g., 0.1N), the pressing action of the first probe row 200a is stopped, ensuring reliable contact while preventing hidden cracking.

[0066] It should be noted that, when aligning the grid line 150 here, it is determined by the screen drawing of the battery. As long as the screen drawing of the battery does not change and the positioning clip is positioned without abnormality, the first probe row 200a can ensure that it is pressed on the grid line 150. Further, in order to be more precise and avoid the error caused by positioning abnormality, the grid line 150 can be positioned by a visual scheme. Specifically, in some embodiments, the mechanical arm where the first probe row 200a is located is communicated with the image recognition device above the passivation protective layer 130, and the image information of the entire passivation protective layer 130 is obtained by the image recognition device, and the image information can include all the grid lines 150. Then, the corresponding grid line 150 is accurately identified according to the preset positioning point, and the first probe row 200a is placed above the grid line 150 to perform a downward pressing action.

[0067] S5 : Pressing the second probe row 200 b onto the gate line 150 in the middle area of ​​the passivation protection layer 130 .

[0068] See also Figure 15 Specifically, the second probe row 200b has the same structure and shape as the first probe row 200a, and its pressing process is also similar to that of the first probe row 200a. By applying the second probe row 200b to the grid lines 150 in the middle area, two probe rows can be applied simultaneously.

[0069] S6 : applying a first preset reverse bias voltage to the edge gate lines 150 , and applying a second preset reverse bias voltage to the middle gate lines 150 .

[0070] Specifically, after the first probe row 200a and the second probe row 200b are accurately aligned and pressed together, the first probe row 200a can be used to apply a first preset reverse bias, and the second probe row 200b can be used to apply a second preset reverse bias. The value of the first preset reverse bias is 5V-10V, for example, the value of the first preset reverse bias can be any point value among 5V, 8V or 10V or a value between any two points, preferably 5V. The value of the second preset reverse bias is 10V-20V, for example, the value of the second preset reverse bias can be any point value among 10V, 15V or 20V or a value between any two points, preferably 20V can be used. In addition, it is necessary to ensure that the second preset reverse bias is greater than the first preset reverse bias, and preferably the second preset reverse bias can be 20V. Of course, the reverse bias size here can also be adaptively adjusted according to the size and type of the battery cell, and this is not specifically limited.

[0071] It should be noted that after the first preset bias voltage is applied here, the bias voltage value is small. Even if the passivation protection layer 130 in the edge area is not fully opened, the temperature generated is not high, and the overburned black edge phenomenon will not occur. Moreover, the temperature is not low enough to further open the passivation protection layer 130.

[0072] S7: Laser scanning the passivation protective layer.

[0073] See also Figure 16 Specifically, through laser scanning, the grid line 150 can be sintered into contact with the battery main body sheet 110. Laser scanning can perform laser scanning on the edge area and the middle area in turn. And because the first preset reverse bias is relatively small, even if the second preset reverse bias is relatively large, it will not generate excessively high temperatures in the edge area. When laser scanning is performed, the temperature difference between the edge area and the middle area is not much. This temperature is suitable for the laser sintering process, and laser sintering can be performed normally to form a good ohmic contact between the grid line 150 and the battery main body sheet 110, thereby ensuring the stable performance of the battery cell. Of course, in order to further ensure the laser sintering effect, the speed is relatively slower when laser scanning the edge.

[0074] It should be noted that steps S5 and S6 can be performed simultaneously, i.e., the first probe row 200a, the second probe row 200b, and the laser scanning device 300 can be powered on simultaneously. After laser scanning, in order to further optimize the contact characteristics, in some embodiments, it is preferred to perform an annealing treatment again. Annealing can promote atomic diffusion, eliminate stress, and enhance the bond strength between the electrode and the semiconductor layer. At the same time, the LECO process is completed after laser scanning. After the laser treatment is completed, the solar cell 100 can be subjected to a comprehensive electrical performance test, including measurement of contact resistance, open circuit voltage (Uoc), short circuit current (Isc), and fill factor (FF), to verify whether the expected effect has been achieved.

[0075] In addition, for black edges, black edge detection can be performed after the electrical performance test. The detection can be done manually or automatically using a visual recognition solution. Preferably, automatic detection can be achieved through a visual recognition solution, and defective battery cells can be marked after detection, so that the entire production line can be automated.

[0076] It should be noted that the laser scanning device 300 can use infrared laser (IR), green laser (Green), and ultraviolet laser (UV). Lasers of different wavelengths are suitable for different materials and processing requirements. Infrared laser: Suitable for deeper penetration processing, often used for localized heating during the sintering process. Green laser: Suitable for processing at intermediate depths, capable of achieving effective energy transfer without damaging the underlying material. Ultraviolet laser: Features high precision and shallow penetration, suitable for fine processing and surface treatment. In addition, the laser scanning device 300 can control the laser power through a controller.

[0077] Referring to the experimental comparison data in the table below, after multiple tests, using the conventional LECO process as a comparative example, it can be seen that by controlling the bias voltage, that is, applying different bias voltages through the first probe row 200a and the second probe row 200b, respectively, the two bias voltages are 3-10V and 10-20V, respectively. This bias control method can effectively reduce the black edge ratio from 2.8% to 1.2%, significantly improving the product yield. Furthermore, it can be seen that the method used in the embodiment of the present invention has no substantial impact on the performance parameters of the solar cell 100, and can also ensure the quality of the solar cell 100.

[0078]

[0079] Uoc is the open circuit voltage, which is the voltage across the solar cell 100 when it is in an open circuit state (i.e., without an external load connected). The open circuit voltage reflects the maximum output voltage capability of the solar cell 100 under no-load conditions. It is a measure of the internal electric field strength of the cell.

[0080] Isc is the short-circuit current, or Isc, which is the current flowing through the short-circuit path when the output terminals of solar cell 100 are directly short-circuited (load resistance is zero). It represents the maximum current that solar cell 100 can produce under ideal lighting conditions and is proportional to the light intensity.

[0081] Fill Factor (FF) is a key parameter for measuring the conversion efficiency of a solar cell 100. It is defined as the ratio of the solar cell's maximum power point (Pmax) to the product of its theoretical open-circuit voltage (Voc) and short-circuit current (Isc). In other words, the fill factor reflects the rectangularity of the solar cell's IV curve and is a key indicator of cell conversion efficiency. The closer the fill factor is to 1, the closer the cell's IV curve is to its ideal state, and the higher the energy conversion efficiency.

[0082] RS is the series resistance, which is the sum of all resistive losses within the solar cell 100, including the resistance of the semiconductor material itself and metal contact resistance. Higher series resistance increases voltage drop, which reduces output power and affects the overall performance of the cell.

[0083] RSH stands for shunt resistance, which describes the total resistance of the leakage paths within the solar cell 100 due to defects or other reasons. A lower shunt resistance means more current is lost through the leakage paths, reducing the current actually available for operation and lowering the cell efficiency.

[0084] Irev2 is the reverse leakage current, which is the current flowing through the solar cell 100 when a reverse bias voltage is applied to the solar cell 100. Generally, significant reverse current is undesirable during normal operation of the solar cell 100. However, under certain extreme conditions (such as overvoltage or damage), a non-zero reverse leakage current may occur, indicating the presence of internal defects or damage.

[0085] Of course, the above table only tests some parameters of the solar cell 100 and is not limited thereto. Other parameters of the solar cell 100 may also be tested simultaneously.

[0086] See also Figure 17 The embodiment of the present invention further provides a solar cell 100, which is manufactured using the aforementioned manufacturing method.

[0087] The solar cell 100 includes a main cell wafer 110, a passivation layer 130, and a gate line 150. The passivation layer 130 is disposed on the main cell wafer 110; the gate line 150 is disposed on the passivation layer 130; the gate line 150 passes through the passivation layer 130 and is sintered into contact with the main cell wafer 110. It should be noted that the sintered contact mentioned in the embodiments of the present invention refers to the gate line 150 undergoing a laser scanning process under an applied bias voltage, which opens the passivation layer 130 and establishes good ohmic contact between the gate line 150 and the main cell wafer 110.

[0088] Furthermore, the battery main body 110 includes an N-type silicon wafer 111, a P+ diffusion layer 112, a silicon oxide layer 113, an N+ diffusion layer 114 and an aluminum oxide layer 115. The front side of the N-type silicon wafer 111 is formed with a velvet surface, the P+ diffusion layer 112 is arranged on the front side of the N-type silicon wafer 111, the silicon oxide layer 113 and the N+ diffusion layer 114 are arranged in sequence on the back side of the N-type silicon wafer 111, and aluminum oxide is arranged on the P+ diffusion layer 112.

[0089] The beneficial effects of the embodiments of the present invention are: The method for preparing a solar cell 100 and the solar cell 100 provided in an embodiment of the present invention first obtain a main cell wafer 110, then form a passivation protective layer 130 on the surface of the main cell wafer 110. The passivation protective layer 130 can cover the front and back surfaces of the main cell wafer 110, and then print and sinter the passivation protective layer 130 to form a grid line 150. Since the passivation protective layer 130 in the middle region is of normal thickness (relatively thin), the grid lines 150 in the middle region can open the passivation protective layer 130 and directly contact the surface of the main cell wafer 110. However, the passivation protective layer 130 in the edge region has a significantly increased thickness (relatively thicker) due to the wrap-around plating phenomenon, so the grid lines 150 in the edge region do not completely open the passivation protective layer 130. After forming the grid lines 150, a laser scanning process with different bias voltages can be performed to apply a first preset reverse bias voltage to the edge grid lines 150, while applying a second preset reverse bias voltage to the middle grid lines 150. The passivation protective layer 130 is then laser scanned to ensure that the grid lines 150 are in sintered contact with the battery main sheet 110, wherein the first preset reverse bias voltage is less than the second preset reverse bias voltage. Compared to the prior art, the embodiments of the present invention, through the application of bias control and laser scanning processes, add a row of probes at the edge to apply a smaller bias voltage, thereby reducing the actual potential at the pressure point, and is not affected by the reverse bias voltage applied to the pressure point by the middle probe row. Therefore, the black edge anomaly phenomenon is effectively reduced, thereby improving product yield and quality.

[0090] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A method for preparing a solar cell, characterized in that: include: Obtaining a battery main body sheet (110); forming a passivation protection layer (130) on the battery main body sheet (110); forming a gate line (150) on the passivation protection layer (130); Applying a first preset reverse bias voltage to the edge gate lines (150), and applying a second preset reverse bias voltage to the middle gate lines (150); Laser scanning is performed on the passivation protection layer (130) to sinter the gate line (150) into contact with the battery main body sheet (110); The first preset reverse bias voltage has a value smaller than the second preset reverse bias voltage.

2. The method for preparing a solar cell according to claim 1, wherein: The first preset reverse bias voltage is 3V-10V, and the second preset reverse bias voltage is 10V-20V.

3. The method for preparing a solar cell according to claim 1 or 2, wherein: Before the steps of applying a first preset reverse bias voltage to the edge gate lines (150) and applying a second preset reverse bias voltage to the middle gate lines (150), the preparation method comprises: Pressing a first probe row (200a) onto the gate line (150) in the edge region of the passivation protection layer (130); The second probe row (200b) is pressed onto the gate line (150) in the middle area of ​​the passivation protection layer (130).

4. The method for preparing a solar cell according to claim 3, wherein: The step of pressing a first probe row (200a) onto the gate line (150) in the edge region of the passivation protection layer (130) comprises: The passivation protection layer (130) is partitioned along the width direction of the gate line (150) to divide the passivation protection layer (130) into a first side edge region (131), a first side middle region (133), a second side middle region (135) and a second side edge region (137) connected in sequence, wherein the first side edge region (131) and the second side edge region (137) are located at both side edge regions of the passivation protection layer (130), and the first side middle region (133) and the second side middle region (135) are located at the middle region of the passivation protection layer (130); The first probe row (200a) is pressed onto the corresponding gate line (150), wherein the corresponding gate line (150) is located in the first side edge region (131) or in the second side edge region (137).

5. The method for preparing a solar cell according to claim 4, wherein: The step of pressing the first probe row (200a) onto the corresponding grid line (150) comprises: The first probe row (200a) is aligned with the grid line (150) in the first side edge area (131) and then pressed downward until the first probe row (200a) contacts the corresponding grid line (150) and the pressing force reaches a preset value.

6. The method for preparing a solar cell according to claim 1, wherein: The step of forming a gate line (150) on the passivation protection layer (130) comprises: A gate line (150) is formed on the surface of the passivation protection layer (130) by screen printing.

7. The method for preparing a solar cell according to claim 6, wherein: After the step of forming the gate lines (150) by screen printing on the surface of the passivation protection layer (130), the preparation method further comprises: The grid lines (150) are sintered in a hot furnace.

8. The method for preparing a solar cell according to claim 6, wherein: After the step of forming the gate lines (150) by screen printing on the surface of the passivation protection layer (130), the preparation method further comprises: Light is injected into the battery main body sheet (110).

9. The method for preparing a solar cell according to claim 1, wherein: The step of forming a passivation protection layer (130) on the battery main body sheet (110) comprises: Depositing an aluminum oxide layer and a silicon nitride layer in sequence on the front surface of the battery main body sheet (110); Depositing a silicon nitride layer on the back side of the battery main body sheet (110); The thickness of the middle region of the silicon nitride layer is smaller than the thickness of the edge region.

10. The method for preparing a solar cell according to claim 9, wherein: The thickness of the middle region of the silicon nitride layer is between 75 nm and 85 nm.

11. The method for preparing a solar cell according to claim 1, wherein: The step of obtaining a battery main body sheet (110) comprises: Texturing the front and back sides of an N-type silicon wafer (111) to form a velvet surface; Performing boron diffusion doping on the front surface of the N-type silicon wafer (111) to form a P+ diffusion layer (112) and a borosilicate glass layer (116) that are distributed in sequence; forming a silicon oxide layer (113) and a polysilicon layer (117) on the back side of the N-type silicon wafer (111); Phosphorus diffusion doping is performed on the polysilicon layer (117) on the back side of the N-type silicon wafer (111) to form an N+ diffusion layer (114) and a phosphorus silicon glass layer (118) that are distributed in sequence; The borosilicate glass layer (116) and the phosphosilicate glass layer (118) are removed.

12. A solar cell manufactured by the method for manufacturing a solar cell according to claim 1, characterized in that: The solar cell comprises: Battery main body sheet (110); a passivation protection layer (130), the passivation protection layer (130) being provided on the battery main body sheet (110); a gate line (150), the gate line (150) being arranged on the passivation protection layer (130); The grid line (150) passes through the passivation protection layer (130) and is sintered into contact with the battery main body sheet (110).

13. The solar cell according to claim 12, wherein: The battery main body (110) comprises an N-type silicon wafer (111), a P+ diffusion layer (112), a silicon oxide layer (113) and an N+ diffusion layer (114); a velvet surface is formed on the front surface of the N-type silicon wafer (111); the P+ diffusion layer (112) is arranged on the front surface of the N-type silicon wafer (111); and the silicon oxide layer (113) and the N+ diffusion layer (114) are sequentially arranged on the back surface of the N-type silicon wafer (111).

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