Silicon wafer, battery piece and photovoltaic device

Abstract

The invention provides a silicon wafer, a battery piece and a photovoltaic device, and relates to the technical field of photovoltaics. The silicon wafer comprises two opposite surfaces along the thickness direction of the silicon wafer; at least one of the two surfaces is provided with one or more concave structures; and one or more convex structures are arranged in the concave structure. According to the silicon wafer and the manufacturing method thereof, the concave structures can play a good light trapping role on light rays incident at a large angle, the convex structures can play a good role in scattering light rays incident at a small angle to a peripheral area, and the silicon wafer provided by the invention has good light trapping capability on the light rays incident at the large angle and the light rays incident at the small angle; the silicon wafer has good light trapping capability for incident light almost in a full-angle range, so that the light trapping capability of the silicon wafer is improved, particularly, the silicon wafer has better light trapping capability for a photovoltaic product which cannot be installed at an optimal angle and contains the silicon wafer, and the comprehensive power generation capability of the photovoltaic product containing the silicon wafer is improved.

Description

Technical Field

[0001] The present application relates to the field of photovoltaic technology, and in particular to a silicon wafer, a battery cell and a photovoltaic device. Background Art

[0002] Solar cells based on silicon wafers have higher photoelectric conversion efficiency, higher stability and reliability, and scalable production costs. Therefore, silicon wafers have received a lot of attention in the photovoltaic field.

[0003] Most current silicon wafers have relatively flat surfaces. However, these relatively flat surfaces have the problem of poor light trapping performance. Summary of the Invention

[0004] The present application provides a silicon wafer, a solar cell and a photovoltaic device, aiming to solve the problem of poor light trapping effect of existing silicon wafers.

[0005] In a first aspect of the present application, a silicon wafer is provided, comprising:

[0006] Two surfaces facing each other along the thickness direction of the silicon wafer; at least one of the two surfaces has one or more recessed structures;

[0007] One or more convex structures are arranged in the concave structure.

[0008] In the present application, the concave structure can play a good light-trapping role for light incident at a larger angle, and the convex structure can play a good light-scattering role for light incident at a smaller angle to the surrounding area, or in other words, the convex structure has a good light-trapping effect for light incident at a small angle. Therefore, the silicon wafer provided in the present application has a good light-trapping ability for both light incident at a large angle and light incident at a small angle, that is, it has a good light-trapping ability for light incident at almost the entire angle range, thereby improving the light-trapping ability of the silicon wafer, especially for photovoltaic products containing the silicon wafer that cannot be installed at the optimal angle (such as vertical installation, rooftop installation, etc.), which has better light-trapping ability and improves the comprehensive power generation capacity of photovoltaic products containing the silicon wafer.

[0009] In some possible embodiments, the surface having the recessed structure further includes a connection area connected to the recessed area, and a top height of the protruding structure within the recessed structure does not exceed a height of the connection area.

[0010] During the transportation and storage of silicon wafers, the connecting region connecting adjacent recessed structures can provide some protection for the raised structures, preventing the tops of the raised structures from collapsing. For example, when stacking silicon wafers, because the tops of the raised structures do not exceed the height of the connecting region, adjacent silicon wafers may only contact the connecting region and are unlikely to contact the raised structures, thereby preventing collisions with the raised structures.

[0011] In some possible embodiments, both surfaces have a plurality of recessed structures; wherein the number of recessed structures on one surface is greater than or equal to the number of recessed structures on the other surface.

[0012] The more recessed structures there are, the better the light trapping effect is. However, there is a certain difference in the light trapping effect between the light-facing side and the backlight side of the silicon wafer. This silicon wafer can be used in scenarios where there is a difference in the light trapping effect between the light-facing side and the backlight side of the silicon wafer.

[0013] In some possible embodiments, the surface having the recessed structure includes: an edge area where the recessed structure is not set, a middle area at the center of the surface having the recessed structure, and a transition area in which the distribution density of the recessed structures is greater than the distribution density of the recessed structures in the middle area, and the transition area is located between the middle area and the edge area.

[0014] On the one hand, in the surface of the battery cell with a recessed structure, the edge area is prone to some appearance problems. The transition area is closer to the edge area, and the recessed structure in the transition area is denser, which can appropriately reduce or eliminate the appearance problems. On the other hand, from the perspective of carrier generation, by setting a denser recessed structure in the transition area, the carrier generation rate in the transition area can be appropriately enhanced, which can reduce or even eliminate the limitation of the low carrier generation rate in the transition area on the performance of the battery cell.

[0015] In some possible embodiments, in the surface having the recessed structures, some adjacent recessed structures have intervals between them, and / or some adjacent recessed structures are continuously arranged.

[0016] In some possible embodiments, one or more pit structures are provided in the recessed structure, and in the same recessed structure, the pit structures and the protruding structures are staggered in distribution.

[0017] The concave structure contains both a pit structure and a convex structure, which further enhances the light trapping effect.

[0018] In some possible embodiments, the edge area of ​​the surface having the recessed structure is not provided with the recessed structure, which significantly reduces the risk of cracking or breaking of the silicon wafer, especially reduces the risk of cracking or breaking of the edge area of ​​the surface of the silicon wafer having the aforementioned recessed structure, improves the mechanical strength, and facilitates mass production.

[0019] In some possible embodiments, the cross-section of the recessed structure along the thickness direction of the silicon wafer includes at least one of a rectangle, a trapezoid, a semi-ellipse, and an irregular shape; and / or,

[0020] The cross-sectional shape of the protrusion structure along the thickness direction of the silicon wafer includes at least one of a triangle, a trapezoid, a rectangle, a stacked structure or an irregular shape; and / or,

[0021] The shape of the concave structure on the surface having the concave structure includes: a ring shape or a strip shape; and / or,

[0022] The shape of the protruding structure on the surface having the concave structure includes: a circle or a strip.

[0023] In some possible embodiments, the strip shape includes: a straight line shape and / or a wavy shape.

[0024] In some possible embodiments, the shape of the concave structure on the surface having the concave structure includes: annular, multiple annular concave structures are nested with each other, and the convex structure is arranged in the inner annular structure; and / or,

[0025] The shape of the concave structure on the surface having the concave structure includes: a strip shape, a plurality of strip-shaped concave structures are nested with each other, and the convex structure is arranged in the inner strip structure.

[0026] In some possible embodiments, at the bottom of the concave structure, the width of the convex structure is B3, 0.08≤B2 / B3≤1.3; and / or,

[0027] At the bottom of the concave structure, the width of the concave structure is B4, and 0.08≤B3 / B4<1.

[0028] In some possible embodiments, at the bottom of the recessed structure, the width of the protruding structure is B3, the width of the recessed structure is B4, and B3 and B4 satisfy the relationship: 0.5≤B3 / B4<0.8; and / or,

[0029] In the thickness direction of the silicon wafer, at the position where the center line of the protruding structure is located, the width of the protruding structure is B2, and at the bottom of the recessed structure, the width of the protruding structure is B3, and B2 and B3 satisfy the relationship: 0.3≤B2 / B3≤1.2.

[0030] In some possible embodiments, the width B1 of the recessed structure on the surface having the recessed structure is 3 μm to 480 μm; and / or,

[0031] In the thickness direction of the silicon wafer, at the position where the center line of the protruding structure is located, the width B2 of the protruding structure is 0.7 μm to 470 μm; and / or,

[0032] At the bottom of the recessed structure, the width B3 of the protruding structure is 0.53 μm to 350 μm; and / or,

[0033] At the bottom of the recessed structure, the width B4 of the recessed structure is 3 μm to 400 μm; and / or,

[0034] The depth of the recessed structure is greater than or equal to 3 percent of the thickness of the silicon wafer and less than or equal to 90 percent of the thickness of the silicon wafer.

[0035] In some possible embodiments, the width B1 of the recessed structure on the surface having the recessed structure is 30 μm to 300 μm; and / or,

[0036] In the thickness direction of the silicon wafer, at the position where the center line of the protruding structure is located, the width B2 of the protruding structure is 5 μm to 180 μm; and / or,

[0037] At the bottom of the recessed structure, the width B3 of the protruding structure is 7.5 μm to 150 μm; and / or,

[0038] At the bottom of the recessed structure, the width B4 of the recessed structure is 10 μm to 200 μm; and / or

[0039] The depth of the recessed structure is 10 μm to 125 μm.

[0040] In a second aspect of the present application, a battery cell is provided, comprising: an electrode structure, and any of the aforementioned silicon wafers; the electrode structure is arranged on the silicon wafer.

[0041] In some possible embodiments, the electrode structure is staggered with the recessed structure. After the electrode structure is disconnected by the recessed structure, its conductivity is severely damaged. Therefore, staggering the electrode structure with the recessed structure can not only ensure the conductivity of the electrode structure, but also avoid the problem of reduced light trapping effect caused by the electrode structure blocking the recessed structure.

[0042] In some possible embodiments, one of the two surfaces is a light-facing surface of the silicon wafer, and the other surface is a backlight-facing surface of the silicon wafer, and the electrode structure includes: a plurality of front gate line electrodes located on the light-facing surface of the silicon wafer, and a plurality of back gate line electrodes located on the backlight-facing surface of the silicon wafer;

[0043] There is a first spacing region between adjacent front gate line electrodes, and the recessed structure is located in at least a portion of the first spacing region; and / or there is a second spacing region between adjacent back gate line electrodes, and the recessed structure is located in at least a portion of the second spacing region.

[0044] In some possible embodiments, one of the two surfaces is the light-facing surface of the silicon wafer, and the other surface is the backlight surface of the silicon wafer, and the electrode structure includes: a plurality of first gate line electrodes and a plurality of second gate line electrodes, all of which are located on the backlight surface of the silicon wafer; a third spacing area is provided between adjacent first gate line electrodes and second gate line electrodes; the recessed structure is located in at least a portion of the third spacing area corresponding to the backlight surface; and / or the recessed structure is located in at least a portion of the light-facing surface.

[0045] In some possible embodiments, the battery cell further includes: a functional film layer located between the electrode structure and the surface having the recessed structure along the thickness direction of the battery cell;

[0046] The functional film layer is conformally arranged on the silicon wafer, and the concave-convex morphology on the functional film layer can further enhance the light trapping effect.

[0047] In some possible embodiments, at least a portion of the inner surface of the recessed structure is provided with a suede structure; and / or,

[0048] At least a portion of the outer surface of the raised structure is provided with a velvet structure.

[0049] In some possible embodiments, at least a portion of the inner surface of the pit structure within the recessed structure is provided with a suede structure.

[0050] In some possible embodiments, the width B5 of the recessed structure on the surface having the recessed structure is 5 μm to 500 μm; and / or,

[0051] In the thickness direction of the battery cell, at the position where the center line of the protruding structure is located, the width B6 of the protruding structure is 0.5 μm to 450 μm; and / or

[0052] At the bottom of the recessed structure, the width B7 of the protruding structure is 0.35 μm to 300 μm; and / or

[0053] At the bottom of the recessed structure, a width B8 of the recessed structure is 4 μm to 450 μm.

[0054] In some possible embodiments, a width B5 of the recessed structure on the surface having the recessed structure is 50 μm to 300 μm; and / or,

[0055] In the thickness direction of the battery cell, at the position where the center line of the protruding structure is located, the width B6 of the protruding structure is 2 μm to 20 μm; and / or

[0056] At the bottom of the concave structure, the width B7 of the convex structure is 10 μm to 50 μm; and / or

[0057] At the bottom of the recessed structure, a width B8 of the recessed structure is 12 μm to 250 μm.

[0058] In some possible embodiments, at the bottom of the concave structure, the width of the convex structure is B7, 0.05≤B6 / B7≤1.2; and / or,

[0059] At the bottom of the concave structure, the width of the concave structure is B8, and 0.05≤B7 / B8<1.

[0060] In some possible embodiments, in the thickness direction of the battery cell, at the position where the midline of the convex structure is located, the width of the convex structure is B6, and at the bottom of the concave structure, the width of the convex structure is B7, and B6 and B7 satisfy the relationship: 0.2≤B6 / B7≤1.1; and / or,

[0061] At the bottom of the concave structure, the width of the concave structure is B8, the width of the convex structure is B7, and B8 and B7 satisfy the relationship: 0.4≤B7 / B8<0.75.

[0062] According to a third aspect of the present application, a photovoltaic device is provided, comprising: a plurality of battery strings connected in series and / or in parallel, wherein the battery strings comprise: an electrical connector and any of the aforementioned battery cells, wherein the electrical connector electrically connects the electrode structures of at least two of the battery cells.

[0063] The above-mentioned silicon wafers, solar cells and photovoltaic devices have the same or similar beneficial effects, and will not be described again here to avoid repetition. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0065] Figures 1 to 3 Schematic diagrams of partial cross-sectional structures of three silicon wafers in the embodiments of the present application are shown;

[0066] Figures 4 to 7 Shows a schematic diagram of the partial cross-sectional structure of various battery cells in the embodiments of the present application;

[0067] Figures 8 to 10 Schematic diagrams of partial top or bottom views of several silicon wafers in the embodiments of the present application are shown;

[0068] Figures 11 to 13 Shows partial top or bottom views of several battery cells in the embodiments of the present application;

[0069] Figure 14 A partial top-view SEM image or a partial photograph of a silicon wafer in an embodiment of the present application is shown.

[0070] Description of the accompanying figures:

[0071] 1-silicon wafer, 11-recessed structure, 12-convex structure, 13-connection area, 14-pit structure, 2-functional film layer, 3-first doped contact layer, 4-second doped contact layer, 5-front gate line electrode, 6-back gate line electrode. DETAILED DESCRIPTION

[0072] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0073] It should be noted that the partial views of the drawings in this application only show one or two recessed structures for exemplary purposes.

[0074] This application provides a silicon wafer, referring to Figures 1 to 7 、 Figure 14 The silicon wafer 1 includes two surfaces opposite to each other along the thickness direction E of the silicon wafer 1. Figure 14 It is a local SEM image or a local photograph of a surface of a silicon wafer. SEM refers to a scanning electron microscope image. Figures 1 to 7 、 Figure 14 In the above description, the two surfaces refer to the upper and lower surfaces of the silicon wafer. At least one of the two surfaces has one or more recessed structures 11; one or more protruding structures 12 are arranged in the recessed structures 11, for example, Figures 1 to 4 and Figure 6 、 Figure 14 In the embodiment, a convex structure 12 is provided in a concave structure 11. Figure 5 and Figure 7 In the embodiment, a plurality of convex structures 12 are arranged in a concave structure 11. For example, any one of the two surfaces has one or more concave structures 11, and one or more convex structures 12 are arranged in the concave structure 11. For another example, both surfaces have one or more concave structures 11, and one or more convex structures 12 are arranged in the concave structure 11. In one surface, the number of concave structures 11 can be one or more, and a plurality refers to two or more. There is no specific limitation on the number of concave structures 11 in one surface. The number of convex structures 12 in one concave structure can be one or more, and a plurality refers to two or more. There is no specific limitation on the number of convex structures 12 in one concave structure.

[0075] For example, Figure 1 、 Figure 14 In the embodiment, one of the two surfaces has a plurality of concave structures 11 , and a convex structure 12 is arranged in the concave structure 11 .

[0076] It should be noted that, in the case of multiple recessed structures, the protruding structures in different recessed structures may be the same or different, and this application does not limit this.

[0077] In the related art, the reason why the relatively flat surface of the silicon wafer has a poor light trapping effect is that the relatively flat surface has a more serious reflection, so the light trapping effect is poor. Alternatively, a light trapping structure of similar size and shape is set in the silicon wafer, and this light trapping structure also has the problem of poor light trapping effect. The size and shape of the light trapping structure determine the incident angle of the incident light or the incident light within a smaller incident angle range for which it has a good light trapping effect, while the light trapping effect for incident light at other incident angles is poor, or even no light trapping effect. Since the size and shape of the light trapping structure are relatively similar, the light trapping structure only has a good light trapping effect for incident light at a certain incident angle, but has a poor light trapping effect for incident light at other incident angles, or even no light trapping effect. Especially when the incident angle of the incident light varies, or when the silicon wafer cannot be installed at the optimal angle in application scenarios such as distributed photovoltaic systems and photovoltaic building integration, light trapping structures of similar size and shape have the problem of poor light trapping effect.

[0078] Figure 2 and Figure 3 Schematic diagram of light in the concave structure 11 (the line with the arrow is the light). Figure 2 In the present application, the light-trapping structures on the surface of the silicon wafer have various shapes, and have good light-trapping effects for light of various incident angles. Specifically, in the present application, the recessed structure 11 can play a good light-trapping role for light incident at a larger angle, and the raised structure 12 can play a good light-trapping role for light incident at a smaller angle to the surrounding area, or in other words, the raised structure 12 has a good light-trapping effect for light incident at a small angle. Therefore, the silicon wafer 1 provided in the present application has good light-trapping capabilities for both large-angle incident light and small-angle incident light, that is, it has good light-trapping capabilities for incident light of almost the entire angle range, thereby improving the light-trapping capability of the silicon wafer 1, especially for photovoltaic products containing the silicon wafer 1 that have variable incident angles or cannot be installed at the optimal angle, thereby improving the comprehensive power generation capacity of photovoltaic products containing the silicon wafer 1.

[0079] It should be noted that the high-angle incident light mentioned in this application refers to incident light with a large angle relative to the normal of the base plane, while the low-angle incident light refers to incident light with a small angle relative to the normal of the base plane. The base plane here refers to the plane perpendicular to the thickness direction of the silicon wafer.

[0080] In some possible embodiments, reference Figure 2 and Figure 3 , the surface with the recessed structure 11 also includes a connection area 13 connected to the recessed structure, and the top height of the protruding structure 12 in the recessed structure does not exceed the height of the connection area 13. The top of the protruding structure 12 refers to the end of the protruding structure 12 away from the center of the silicon wafer along the thickness direction of the silicon wafer 1. Specifically, the top of the protruding structure 12 may easily collapse during a collision, and the height of the top of the protruding structure 12 in the recessed structure 11 does not exceed the height of the connection area 13. During the transportation and storage of the silicon wafer, the connection area 13 can play a certain protective role for the protruding structure 12, preventing the top of the protruding structure 12 from collapsing. For example, when stacking silicon wafers, since the protruding structure 12 does not exceed the connection area 13, adjacent silicon wafers may only contact the connection area 13, and adjacent silicon wafers may most likely not contact the protruding structure 12, thereby avoiding collisions with the protruding structure 12.

[0081] It is understood that the connection area connecting adjacent recessed structures may be a non-recessed area with a relatively uniform height (for example, along the thickness direction of the silicon wafer, the non-recessed area has the same height as the surface of the silicon wafer without the recessed structure). Alternatively, a portion of the connection area may be lower than the non-recessed area (for example, when two recessed structures are relatively close to each other, the corresponding connection area may be lower than the non-recessed area of ​​the silicon wafer due to the presence of the recessed structure or the influence of subsequent wet processing).

[0082] It should be noted that the connection region 13 is flatter than the region where the recessed structure 11 is located, or the connection region 13 has less undulation than the region where the recessed structure 11 is located. Along the thickness direction of the silicon wafer 1, the connection region 13 may be farther away from the geometric center of the silicon wafer than the region where the recessed structure 11 is located.

[0083] In some possible embodiments, both surfaces have a plurality of recessed structures 11; the number of recessed structures 11 on one surface is greater than or equal to the number of recessed structures 11 on the other surface. Specifically, in a cell, one of the two surfaces is the light-facing side of the silicon wafer 1, and the other is the backlight side of the silicon wafer 1. During normal operation of the cell or photovoltaic device, the light-facing side of the silicon wafer 1 primarily receives light, with the light-facing side and the backlight side facing each other. The number of recessed structures 11 on one surface of the silicon wafer 1 is greater than or equal to the number of recessed structures 11 on the other surface. A greater number of recessed structures 11 results in a better light-trapping effect. There is a certain difference in light-trapping effect between the light-facing side and the backlight side of the silicon wafer 1. This silicon wafer can be used in scenarios where there is a difference in light-trapping effect between the light-facing side and the backlight side of the silicon wafer 1. For example, in a cell or photovoltaic device, the light-facing side of the silicon wafer has more recessed structures, and since the light-facing side is the surface that primarily receives light, the light-trapping effect can be further improved. It should be noted that the difference in the number of recessed structures is not limited.

[0084] In some possible embodiments, the surface having the aforementioned recessed structure 11 includes: an edge region, a middle region, and a transition region located between the middle region and the edge region; the edge region may refer to a connecting region 13 where no recessed structure is provided, the middle region includes the center of the surface having the aforementioned recessed structure 11, and a recessed structure is provided on the middle region, and a recessed structure is provided in the transition region, and the distribution density of the recessed structures 11 in the transition region is greater than the distribution density of the recessed structures 11 in the middle region, or in other words, the distribution of the recessed structures 11 in the transition region is denser than the distribution of the recessed structures 11 in the middle region. Specifically, on the one hand, in the battery cell, the edge area is prone to some appearance problems, for example, the edge area is prone to bluing, etc. The transition area is closer to the edge area, and the recessed structure 11 in the transition area is denser, which can appropriately reduce or eliminate the appearance problems; on the other hand, from the perspective of carrier generation, there are silicon wafers around the recessed structure 11 in the middle area, and carriers can be generated. However, the transition area has relatively less silicon wafer coverage on the side close to the edge area, and the carrier generation density is relatively small. The position with a lower carrier generation density in the battery cell usually limits the performance of the battery cell. Therefore, in this application, by setting a denser recessed structure 11 in the transition area, the light trapping effect can be appropriately enhanced, thereby enhancing the carrier generation rate in the transition area, reducing or even eliminating the limitation of the low carrier generation rate in the transition area on the performance of the battery cell.

[0085] The edge area here refers to the area adjacent to the edge line (for example, the boundary line between the side and the front) of the surface with the recessed structure 11, the middle area refers to the area closer to the inside of the surface, and the middle area may include the center of the surface. The transition area refers to the area between the middle area and the edge area. The sizes of the areas of the edge area, the transition area and the middle area are not limited. For example, the areas of the middle area, the transition area and the edge area decrease in sequence. The same size area can be arbitrarily selected in the transition area and the middle area of ​​the surface with the recessed structure 11, and the number of recessed structures 11 in the same size area can be counted to characterize the distribution density of the recessed structures 11 in the transition area and the middle area. For example, an area of ​​the same area is arbitrarily selected in the transition area and the middle area of ​​the surface with the recessed structure 11, for a total of two areas, where the number of recessed structures 11 in the area of ​​the same area in the transition area is greater than the number of recessed structures 11 in the area of ​​the same area in the middle area, then the distribution of the recessed structures 11 in the transition area is more dense.

[0086] In some possible embodiments, reference Figure 1 、 Figure 2, the edge region of the surface having the recessed structure 11 is not provided with the aforementioned recessed structure 11. Specifically, if the recessed structure 11 is provided in the edge region, the risk of cracking or breaking of the silicon wafer is higher. In the present application, the recessed structure 11 is not provided in the edge region, which significantly reduces the risk of cracking or breaking of the silicon wafer, especially reduces the risk of cracking or breaking of the edge region of the surface of the silicon wafer having the aforementioned recessed structure 11, improves the mechanical strength, and facilitates mass production.

[0087] In some possible embodiments, reference Figure 1 In the surface having recessed structures 11, some adjacent recessed structures 11 have spaces between them. Such spaces can enhance the mechanical strength of the silicon wafer. In one embodiment, the surface having recessed structures 11 may have spaces between some adjacent recessed structures 11. In another embodiment, the surface having recessed structures 11 may have connecting regions 13 between some adjacent recessed structures 11.

[0088] In some possible embodiments, some adjacent recessed structures 11 are continuously arranged, which can reduce the processing difficulty and appropriately expand the process window.

[0089] In some possible embodiments, reference Figure 3 The concave structure is further provided with one or more pit structures 14. By providing the pit structure in the concave structure, the space occupied on the surface of the silicon wafer can be reduced, and the absorption of incident light by the silicon wafer can be increased.

[0090] It is understood that the cross-section of the pit structure parallel to the thickness direction of the silicon wafer can be an inverted triangle, an inverted semicircle, an inverted trapezoid, or other shapes, and this application is not limited thereto. For example, the pit structure and the depression structure have the same shape and only differ in size.

[0091] In some possible implementations, the concave structures 14 and the convex structures are staggered. The concave structures contain both concave structures 14 and convex structures, further enhancing the light trapping effect.

[0092] In some other possible implementations, the protrusion structure may be disposed within the concave structure 14 , which is not limited in this application.

[0093] In some possible embodiments, the cross-sectional shape of the recessed structure 11 along the thickness direction E of the silicon wafer 1 includes at least one of a rectangle, a trapezoid, a semi-ellipse, and an irregular shape. Specifically, in a cross-sectional shape parallel to the thickness E of the silicon wafer 1, the shape of the recessed structure 11 includes at least one of a rectangle, a trapezoid, a semi-ellipse, and an irregular shape. Recessed structures of the above shapes are easy to prepare and mass-produce, and have good light trapping effects for light with larger incident angles. It should be noted that the term "rectangular" in this application includes shapes similar to a rectangle, "trapezoidal" includes shapes similar to a trapezoid, and "semi-elliptical" includes shapes similar to a semi-ellipse.

[0094] For example, Figures 1 to 3 This is a schematic diagram of a cross section parallel to the thickness E of the silicon wafer 1. Figure 1 The cross-sectional shape of the middle concave structure 11 is trapezoidal. Figures 2 to 7 The cross-sectional shape of the middle recessed structure 11 is trapezoidal.

[0095] It should be noted that, in the embodiment of the present application, the transition area between the recessed structure 11 and the connecting area may be a radian transition (e.g. Figure 1 ), or a broken line transition (e.g. Figure 2 This application does not limit this.

[0096] In some possible embodiments, the shape of the cross section of the protruding structure 12 along the thickness direction E of the silicon wafer 1 includes at least one of a triangle, a rectangle, a trapezoid, a stacked structure, and an irregular figure. Specifically, on a cross section parallel to the thickness E of the silicon wafer 1, the shape of the protruding structure 12 includes at least one of a triangle, a rectangle, a trapezoid, and an irregular figure. The protruding structure of the above shape is easy to prepare, easy to achieve mass production, and has a good light trapping effect for light with a smaller incident angle. It should be noted that the rectangle here includes a shape similar to a rectangle, the trapezoid includes a shape similar to a trapezoid, and the semi-ellipse includes a shape similar to a semi-ellipse. The stacked structure here may include: stacked trapezoids, stacked triangles, stacked irregular figures, etc., and is not specifically limited to this. For example, a stacked trapezoid can be understood as a stacked cake shape.

[0097] For example, Figures 1 to 3 This is a schematic diagram of a cross section parallel to the thickness E of the silicon wafer 1. Figures 1 to 5 In the figure, the cross-sectional shape of the protruding structure 12 is a triangle. Figures 6 and 7 The cross-section of the middle protrusion structure 12 is trapezoidal.

[0098] In some possible embodiments, the shape of the recessed structure 11 on the surface having the recessed structure 11 includes at least one of a ring shape and a strip shape. The recessed structure of the above shape is easy to prepare and mass-produce, and has a good light trapping effect for light with a large incident angle. The strip shape has a clear extension direction.

[0099] Figure 8 、 Figure 9 and Figure 10 Each of them is a partial schematic diagram of a surface of a silicon wafer 1 having a recessed structure 11. For example, Figure 8 The shape of the middle concave structure 11 on the surface having the concave structure 11 is annular. Figures 9 to 13 The shape of the middle concave structure 11 on the surface having the concave structure 11 is strip-shaped. It should be noted that, Figures 8 to 10 In the figure, except for the raised structure 12, the rest of the parts are only the outermost frame lines. Figures 11 to 13 In the figure, except for the back gate line electrode 6, the rest of the parts are only the outermost frame lines.

[0100] It should be noted that the ring or strip can be a closed structure or an unclosed structure. For example, the ring can be a semi-ring structure or a discontinuous ring structure, and the strip can be a strip structure with some areas not closed or formed discontinuously.

[0101] In some possible embodiments, the shape of the protrusions 12 on the surface of the recessed structures 11 includes at least one of a circle and a strip. These protrusions are easy to prepare and mass-produce, and have a good light-trapping effect for light with a small incident angle. The strip has a distinct extension direction.

[0102] For example, Figure 8 and Figure 10 The cross-sectional shape of the middle convex structure 12 on the surface with the concave structure 11 is circular. Figure 9 、 Figure 11 Figure 13 The shape of the middle convex structure 12 on the surface with the concave structure 11 is stripe-shaped.

[0103] It should be noted that the structure formed by the combination of the concave structure and the convex structure may include: a circular convex structure disposed within an annular concave structure, a strip-shaped convex structure disposed within an annular concave structure, a circular convex structure disposed within a strip-shaped concave structure, and a strip-shaped convex structure disposed within a strip-shaped concave structure, and this is not specifically limited. Where a strip-shaped convex structure is disposed within a strip-shaped concave structure, the concave structure may extend in a direction parallel to that of the convex structure, or the concave structure may extend in a direction perpendicular to that of the convex structure (for example, a plurality of strip-shaped convex structures extending in a direction perpendicular to the concave structure may be disposed within an extended strip-shaped concave structure), and this application does not limit this.

[0104] It is understandable that when there are multiple protruding structures in the recessed structure, the shapes of the multiple protruding structures may be the same or different, and this application does not limit this.

[0105] It can also be understood that the circular shape of the protruding structure 12 on the surface with the concave structure can also be understood as a circle with a certain radius, or it can be just a dot (for example, the cross section of the protruding structure along the thickness direction is a triangle).

[0106] In some possible embodiments, the aforementioned strips may include: straight lines, broken lines, and / or wavy shapes. The undulation degree of the straight line is less than that of the wavy shape. The undulation degree of the straight line is less than that of the broken line shape. For example, Figures 9 to 13 In the text, strip refers to a straight line.

[0107] In some possible embodiments, the shape of the recessed structure 11 on the surface having the recessed structure 11 includes: annular, multiple recessed structures 11 of annular structure are nested with each other, and a convex structure 12 is provided in the recessed structure 11 of the inner annular structure. In this case, the number of recessed structures 11 on the surface may be relatively large, and it has a good light trapping effect for light with a larger incident angle. The multiple here refers to 2 or more. In the case where the recessed structures 11 of multiple annular structures are nested with each other, the heights of the recessed structures 11 of multiple annular structures can be flat, or have a tendency to rise from the outside to the inside, or have a tendency to fall from the outside to the inside, or have no obvious trend, that is, the height levels are uneven and randomly distributed.

[0108] In some possible embodiments, the shape of the recessed structure 11 on the surface having the recessed structure 11 includes: strip-shaped, multiple strip-shaped recessed structures 11 are nested with each other, and a convex structure 12 is provided in the inner strip-shaped recessed structure 11. In this case, the number of recessed structures 11 on the surface may be relatively large, which has a good light trapping effect for light with a larger incident angle. The multiple here refers to 2 or more. In the case where the recessed structures 11 of multiple strip-shaped structures are nested with each other, the heights of the recessed structures 11 of multiple strip-shaped structures can be flat, or have a tendency to rise from the outside to the inside, or have a tendency to fall from the outside to the inside, or have no obvious trend, that is, the height levels are uneven and randomly distributed.

[0109] In some possible embodiments, reference Figure 1 、 Figure 8 The width B1 of the recessed structure 11 on the surface having the recessed structure 11 is 3 μm to 480 μm. Furthermore, the B1 can be 30 μm to 300 μm. If the width B1 is too small, the light trapping effect for light with a larger incident angle is poor. If the width B1 is too large, it will have a greater impact on the mechanical strength of the silicon wafer and introduce the risk of breakage. When B1 is within this range, it not only has a good light trapping effect for light with a larger incident angle, but also has a lower risk of silicon wafer breakage.

[0110] For example, B1 can be 3μm, 5μm, 8μm, 10μm, 12μm, 15μm, 17μm, 20μm, 25μm, 30μm, 50μm, 70μm, 90μm, 100μm, 130μm, 150μm, 180μm, 200μm, 220μm, 250μm, 290μm, 300μm, 310μm, 350μm, 370μm, 400μm, 410μm, 420μm, 450μm, 480μm.

[0111] It should be noted that, on a surface having the recessed structure 11, if the recessed structure 11 is significantly larger in a certain direction, the larger dimension in that direction is the length of the recessed structure 11, and the distance between the two boundaries of the recessed structure 11 that are farther apart in a direction perpendicular to the length is the width of the recessed structure 11. On a surface having the recessed structure 11, if the recessed structure 11 is substantially equal in size in all directions, the distance between the two boundaries of the recessed structure 11 that are farther apart in any direction is the width of the recessed structure 11.

[0112] In some possible embodiments, reference Figure 1 , in the thickness direction E of the silicon wafer 1, at the position where the midline of the raised structure 12 is located, the width B2 of the raised structure 12 is 0.7μm to 470μm. Furthermore, the B2 can be 5μm to 180μm. That is to say, the raised structure in the present application is different from the pyramid velvet structure. B2 is the width at the position where half the height of the raised structure 12 is located in the thickness direction E of the silicon wafer 1. If B2 is too small, the light trapping effect for light with a larger incident angle will be poor. If the width B2 is too large, the light cannot enter the area between the side walls of the raised structure and the recessed structure, and the light trapping effect will also be worse. Therefore, within this range, B2 can have a good light trapping effect on light.

[0113] For example, B2 can be 0.7μm, 0.9μm, 1μm, 2μm, 5μm, 8μm, 10μm, 12μm, 15μm, 17μm, 20μm, 25μm, 30μm, 50μm, 70μm, 90μm, 100μm, 13 0μm, 150μm, 180μm, 200μm, 220μm, 250μm, 290μm, 300μm, 310μm, 350μm, 370μm, 400μm, 410μm, 420μm, 450μm, 470μm.

[0114] In some possible embodiments, reference Figure 1At the bottom of the recessed structure 11, the width of the raised structure 12 is B3, and B3 is 0.53μm to 350μm. Further, B3 is 2μm to 350μm. Further, B3 can be 7.5μm to 150μm. B3 is the width of the raised structure 12 at the bottom of the recessed structure 11. If B3 is too small, the light trapping effect for light with a large incident angle is poor. If the width B3 is too large, the light cannot enter the area between the raised structure and the sidewall of the recessed structure, and the light trapping effect will also be poor. Therefore, within this range, B3 can have a good light trapping effect on light.

[0115] For example, B3 can be 0.53μm, 0.8μm, 1μm, 2μm, 3μm, 4μm, 5μm, 8μm, 10μm, 12μm, 15μm, 17μm, 20μm, 25μm, 30μm, 50μm, 8 0μm, 90μm, 100μm, 120μm, 150μm, 170μm, 200μm, 210μm, 250μm, 270μm, 300μm, 320μm, 350μm, 380μm, 400μm.

[0116] In some possible embodiments, at the bottom of the recessed structure 11, the width B4 of the recessed structure is 3 μm to 400 μm. Further, B4 is 10 μm to 200 μm. For example, B3 can be 10 μm, 12 μm, 15 μm, 17 μm, 20 μm, 25 μm, 30 μm, 50 μm, 80 μm, 90 μm, 100 μm, 120 μm, 150 μm, 170 μm, or 200 μm.

[0117] In some possible embodiments, reference Figure 1 At the bottom of the recessed structure 11, the width of the raised structure 12 is B3, where 0.08 ≤ B2 / B3 ≤ 1.3; further, 0.3 ≤ B2 / B3 ≤ 1.2. B2 / B3 represents the slope or rate of change in the width of the raised structure 12 in the thickness direction E of the silicon wafer 1. A value too small relative to 1 indicates a too small slope or rate of change in the width of the raised structure 12. A value too large relative to 1 indicates a too large slope or rate of change in the width of the raised structure 12. Within this range, B2 / B3 provides a wide processing window and a high process yield.

[0118] For example, B2 / B3 can be 0.08, 0.09, 0.1, 0.12, 0.15, 0.18, 0.2, 0.22, 0.25, 0.29, 0.3, 0.32, 0.35, 0.4, 0.44, 0.5, 0.55, 0.6, 0.65, 0.7, 0.75, 0.8, 0.88, 0.9, 0.95, 1, 1.1, 1.2, or 1.3.

[0119] It should be noted that when B2 / B3 is less than 1, the width of the protruding structure 12 decreases from the bottom of the recessed structure to the top of the recessed structure in the thickness direction E of the silicon wafer 1. When B2 / B3 is greater than 1, the width of the protruding structure 12 increases from the bottom of the recessed structure to the top of the recessed structure in the thickness direction E of the silicon wafer 1. This creates a brim-like structure on the upper surface of the protruding structure, allowing light entering between the protruding structure and the sidewalls of the recessed structure to be reflected back and forth, resulting in better absorption and further enhancing the light trapping effect.

[0120] In some possible embodiments, reference Figure 1 At the bottom of the recessed structure 11, the width of the recessed structure 11 is B4, 0.08≤B3 / B4<1, further, 0.5≤B3 / B4<0.8; B3 / B4 can represent the size ratio of the protruding structure 12 to the recessed structure 11 in the width direction of the recessed structure. If this value is too small, it means that the width ratio of the protruding structure 12 to the recessed structure 11 is too small, and the light trapping effect for light with a smaller incident angle is poor. When B3 / B4 is within the above range, the light trapping effect for light with a smaller incident angle is better.

[0121] For example, B3 / B4 can be 0.08, 0.09, 0.1, 0.12, 0.15, 0.18, 0.2, 0.22, 0.25, 0.29, 0.3, 0.32, 0.35, 0.4, 0.44, 0.5, 0.55, 0.6, 0.65, 0.7, 0.75, 0.8, 0.88, 0.9, 0.95, 1.

[0122] In some possible implementations, B3 / B4 may also be equal to 1, indicating that the bottom width of the convex structure 12 is equal to the bottom width of the concave structure 11. For example, when B3 / B4=1 and the top height of the convex structure 12 is lower than the height of the connection area, the concave structure 11 and the convex structure 12 can still be combined to achieve light trapping from multiple angles. Alternatively, when B3 / B4=1, the cross-sectional shape of the concave structure is different from the cross-sectional shape of the convex structure in the direction parallel to the thickness of the silicon wafer, the concave structure 11 and the convex structure 12 can still be combined to achieve light trapping from multiple angles. When B3 / B4=1, the junction of the concave structure 11 and the convex structure can be roughly connected at an acute angle. In some possible embodiments, the depth H1 of the concave structure 11 is greater than or equal to three percent of the thickness of the silicon wafer and less than or equal to ninety percent of the thickness of the silicon wafer. This configuration, when H1 is within the above range, prevents the reflection of incident light within the recessed structure, which could be caused by an excessively small H1. This improves the transmission path of incident light within the recessed structure and increases the light absorption rate of the silicon wafer. Furthermore, it prevents the effective thickness of the portion of the silicon wafer where the recessed structure is located from being reduced, which could affect its strength, due to an excessively large H1. This reduces the risk of silicon wafer fracture and improves the wafer's ability to withstand mechanical loads.

[0123] For example, the depth H1 of the recessed structure 11 is 3%, 5%, 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, or 90% of the thickness of the silicon wafer.

[0124] In some possible embodiments, reference Figure 1 The depth H1 of the recessed structure 11 is greater than or equal to 10 μm and less than or equal to 125 μm. If the depth of the recessed structure 11 is too small, the light trapping effect for light with a larger incident angle will be poor. Therefore, in this application, the depth H1 of the recessed structure 11 is greater than or equal to 10 μm, which has a better light trapping effect for light with a larger incident angle.

[0125] For example, H1 can be 10μm, 13μm, 15μm, 20μm, 30μm, 35μm, 40μm, 45μm, 50μm, 60μm, 70μm, 80μm, 100μm, 120μm, or 125μm.

[0126] The present application also provides a method for preparing a silicon wafer, comprising the following steps: providing a silicon substrate; the silicon substrate comprising: two surfaces opposing each other along the thickness direction of the silicon substrate; forming one or more recessed structures in at least one of the two surfaces of the silicon wafer; and disposing one or more raised structures within the recessed structures. For example, the recessed structures can be formed using a laser, and the silicon wafer can be obtained directly by laser etching, which is a simple process. The specific laser process parameters are not limited.

[0127] The present application also provides a solar cell, comprising: an electrode structure and any of the aforementioned silicon wafers, wherein the electrode structure is disposed on the silicon wafer and is used to collect and conduct current.

[0128] In some possible embodiments, reference Figure 7 、 Figures 11 to 12 The electrode structure is staggered with the recessed structure 11. Specifically, the conductivity of the electrode structure is severely damaged after being disconnected by the recessed structure 11. Therefore, staggering the electrode structure with the recessed structure 11 can not only ensure the conductivity of the electrode structure, but also avoid the problem of reduced light trapping effect caused by the electrode structure blocking the recessed structure 11.

[0129] It can be understood that the arrangement of the electrode structures staggered with the recessed structures 11 may mean that all the electrode structures in the battery cell are staggered with the recessed structures 11 .

[0130] In some possible embodiments, reference Figure 13 , the electrode structure can be arranged across the recessed structure 11 .

[0131] In some possible embodiments, reference Figure 7 One of the two aforementioned surfaces is the light-facing side of the silicon wafer 1, and the other is the backlight side of the silicon wafer 1. The electrode structure includes: a plurality of front gateline electrodes 5 located on the light-facing side of the silicon wafer 1, and a plurality of back gateline electrodes 6 located on the backlight side of the silicon wafer 1. A first spacing region is defined between adjacent front gateline electrodes 5, with a recessed structure located in at least a portion of the first spacing region. When light is irradiated along the thickness direction of the cell, the projections of the recessed structure and the first spacing region overlap, and the size relationship between the projections is not specifically defined. For example, on the light-facing side, the projection of the first spacing region may be greater than or equal to the projection of the recessed structure. And / or, a second spacing region is defined between adjacent back gateline electrodes 6, with a recessed structure 11 located in at least a portion of the second spacing region corresponding to the backlight side. When light is irradiated along the thickness direction of the cell, the projections of the recessed structure and the second spacing region overlap, and the size relationship between the projections is not specifically defined. For example, on the backlight side, the projection of the second spacing region can be greater than or equal to the projection of the recessed structure. The first spacing region is not provided with the front gateline electrode 5, and the second spacing region is not provided with the back gateline electrode 6. Therefore, the front gateline electrode 5 and the back gateline electrode 6 are both staggered from the recessed structure 11, ensuring the conductivity of the electrode structure and avoiding the problem of reduced light trapping effect caused by the electrode structure blocking the recessed structure 11.

[0132] Here, the recessed structure 11 may be located only in at least part of the first spacing area on the light-facing surface, or the recessed structure 11 may be located only in at least part of the second spacing area on the backlight surface, or the recessed structure 11 may be located in at least part of the first spacing area on the light-facing surface and also in at least part of the second spacing area corresponding to the backlight surface. In some possible embodiments, one of the two surfaces mentioned above is the light-facing surface of the silicon wafer 1, and the other surface is the backlight surface of the silicon wafer 1. The electrode structure includes: a plurality of first gate line electrodes and a plurality of second gate line electrodes, all of which are located on the backlight surface of the silicon wafer. There is a third spacing area between adjacent first gate line electrodes and second gate line electrodes, and the third spacing area can also play a role in avoiding short circuits within the battery cell. The recessed structure 11 is located in at least part of the third spacing area corresponding to the backlight surface; and / or the recessed structure 11 is located on at least part of the light-facing surface of the silicon wafer 1. Specifically, refer to Figures 4 to 6 This cell is a back contact cell, and there is no electrode structure on the light-facing side of the silicon wafer. Since there is no electrode blocking the light-facing side, it is more beautiful and has better performance. Figure 4 and Figure 5 The two doped contact layers overlap, but they can be electrically isolated by providing an insulating layer. The insulating layer here can be a film layer that can play a passivation and anti-reflection role, etc., and this is not specifically limited. Alternatively, the two doped layers overlap here and can be designed to have local contact, thereby achieving an anti-hot spot effect. In the back-contact cell, the third spacing area is not provided with an electrode structure. Therefore, the first gate line electrode and the second gate line electrode are staggered with the recessed structure 11, ensuring the conductivity of the electrode structure and avoiding the problem of reduced light trapping effect caused by the electrode structure blocking the recessed structure 11.

[0133] Here, the recessed structure 11 may be located only in at least a portion of the light-facing surface, or the recessed structure 11 may be located only in at least a portion of the third spacing area of ​​the backlight surface, or the recessed structure 11 may be located in at least a portion of the light-facing surface and also in at least a portion of the third spacing area corresponding to the backlight surface.

[0134] It should be noted that the back contact cell may further include a first doped contact layer 3 and a second doped contact layer 4 , one of which is an N-type doped contact layer and the other is a P-type doped contact layer.

[0135] In a cell, cell, or photovoltaic device, during normal operation, the light-facing side of the silicon wafer 1 primarily receives light, with the light-facing side being opposite to the backlight side. In some possible embodiments, the number of recessed structures 11 on the light-facing side of the silicon wafer 1 is greater than or equal to the number of recessed structures 11 on the backlight side of the silicon wafer. The greater the number of recessed structures 11, the better the light-trapping effect. In a cell or photovoltaic device, the light-facing side of the silicon wafer has more recessed structures, and the light-facing side of the silicon wafer is the surface that primarily receives light, so the light-trapping effect can be further enhanced. It should be noted that the difference in the number of recessed structures is not limited.

[0136] In some possible embodiments, reference Figures 4 to 7 The cell also includes: a functional film layer 2 located between the electrode structure and the surface having the aforementioned recessed structure 11 along the thickness direction E of the cell; the functional film layer 2 may be a passivation anti-reflection layer, or the functional film layer 2 may include a doped silicon layer, etc. The functional film layer 2 is conformally disposed on the silicon wafer 1. Conformal here means that when the area covered by the functional film layer 2 includes the recessed structure 11, the position corresponding to the recessed structure 11 in the functional film layer 2 and its vicinity have a tendency to be recessed toward the silicon wafer side, and / or, when the area covered by the functional film layer 2 includes the protruding structure 12, the position corresponding to the protruding structure 12 in the functional film layer 2 and its vicinity have a tendency to be convex toward the silicon wafer side, indicating that the recessed degree of the recessed structure 11 on the silicon wafer 1 is relatively large, and the protruding degree of the protruding structure 12 is relatively large. The concave-convex morphology on the functional film layer 2 can further enhance the light trapping effect.

[0137] It should be noted that when the recessed structure is located in at least part of the first spacing area, and on the light-facing side, the projection of the first spacing area can be greater than or equal to the projection of the recessed structure: this means that the first spacing area covers part of the connection area, and the functional film layer can still be retained in the area where the recessed structure is located, and only the connection areas on both sides of the recessed structure in the first spacing area are disconnected. The functional film layer located there can play a certain passivation and protection role in the area where the recessed structure is located; or, the functional film layer is not retained in the area where the recessed structure is located, and there is no specific limitation on this. The case where the recessed structure is located in at least part of the second spacing area and the third spacing area is similar. To avoid repetition, it will not be described here. In some possible embodiments, at least part of the inner surface of the recessed structure 11 is provided with a velvet structure. The velvet structure has different dimensions from the aforementioned recessed structure 11 and convex structure 12, so that the cell has a better light trapping effect for incident light at more angles. The velvet structure here can be a positive pyramid structure, an inverted pyramid structure, etc.

[0138] In some possible embodiments, at least part of the outer surface of the protruding structure 12 is provided with a velvet structure, which can also provide a better light trapping effect for incident light at more angles. The velvet structure here can be a positive pyramid structure, an inverted pyramid structure, etc. For example, Figure 14 As shown, the raised structure is in the shape of a stacked cake, and a pyramid-like structure is provided on the surface of the top cake.

[0139] In some possible embodiments, when a pit structure is further provided in the recessed structure 11 , a velvet structure may also be provided on at least a portion of the inner surface of the pit structure, thereby achieving a better light trapping effect for incident light at more angles.

[0140] In some possible embodiments, reference Figure 4 In the battery cell, the width B5 of the recessed structure 11 in the silicon wafer 1 on the surface having the recessed structure 11 is 5 μm to 500 μm, and further B5 is 50 μm to 300 μm. If the width B5 is too small, the light trapping effect for light with a larger incident angle will be poor. If the width B5 is too large, it will have a greater impact on the mechanical strength of the silicon wafer or battery cell, and introduce the risk of breakage. When B5 is within this range, it not only has a good light trapping effect for light with a larger incident angle, but also reduces the risk of silicon wafer or battery cell breakage.

[0141] For example, B5 can be 5 μm, 8 μm, 10 μm, 12 μm, 15 μm, 17 μm, 20 μm, 25 μm, 30 μm, 50 μm, 70 μm, 90 μm, 100 μm, 130 μm, 150 μm, 180 μm, 200μm, 220μm, 250μm, 290μm, 300μm, 310μm, 350μm, 370μm, 400μm, 410μm, 420μm, 450μm, 480μm, 500μm.

[0142] In some possible embodiments, in a battery cell, at the bottom of the recessed structure, the width B8 of the recessed structure is 4 μm to 450 μm. Further, B8 is 12 μm to 250 μm. For example, B8 can be 4 μm, 5 μm, 8 μm, 10 μm, 12 μm, 15 μm, 17 μm, 20 μm, 25 μm, 30 μm, 50 μm, 70 μm, 90 μm, 100 μm, 130 μm, 150 μm, 180 μm, 200 μm, 220 μm, 250 μm, 290 μm, 300 μm, 310 μm, 350 μm, 370 μm, 400 μm, 410 μm, 420 μm, or 450 μm.

[0143] In some possible embodiments, reference Figure 4In the cell, at the centerline of the raised structure 12 on the silicon wafer in the thickness direction E of the cell, the width B6 of the raised structure 12 is between 0.5μm and 450μm. Furthermore, B6 is between 2μm and 20μm. B6 is the width of the raised structure 12 at half its height in the thickness direction E of the silicon wafer 1. A smaller B6 will result in poor light trapping at higher angles of incidence. A larger B6 will significantly impact the mechanical strength of the silicon wafer and cell, increasing the risk of breakage. Within this range, B6 not only provides good light trapping at higher angles of incidence, but also reduces the risk of breakage of the silicon wafer and cell.

[0144] For example, B6 can be 0.5μm, 0.7μm, 0.9μm, 1μm, 2μm, 5μm, 8μm, 10μm, 12μm, 15μm, 17μm, 20μm, 25μm, 30μm, 50μm, 70μm, 90μm, 10 0μm, 130μm, 150μm, 180μm, 200μm, 220μm, 250μm, 290μm, 300μm, 310μm, 350μm, 370μm, 400μm, 410μm, 420μm, 450μm.

[0145] In some possible embodiments, reference Figure 4 In the cell, the width of the raised structure 12 at the bottom of the recessed structure 11 of the silicon wafer is B7. The width B7 of the raised structure is 0.35μm to 300μm. Furthermore, B7 is 10μm to 50μm. B7 is the width of the raised structure 12 at the bottom of the recessed structure 11 in the cell. If B7 is too small, the light trapping effect for light with a larger incident angle is poor. If the width B7 is too large, the light cannot enter the area between the sidewalls of the raised structure and the recessed structure, and the light trapping effect will also be poor. Therefore, within this range, B7 can have a good light trapping effect on light.

[0146] For example, B7 can be 0.35μm, 0.5μm, 1μm, 3μm, 5μm, 7μm, 10μm, 12μm, 15μm, 18μm, 20μm, 22μm, 25μm, 30μm, 32μm, 35μm, 39μm m, 40μm, 41μm, 45μm, 48μm, 50μm, 80μm, 90μm, 100μm, 120μm, 150μm, 170μm, 200μm, 210μm, 250μm, 270μm, 300μm.

[0147] In some possible embodiments, the depth of the recessed structure in the battery cell may be 10μm-100μm. For example, the depth of the recessed structure in the battery cell may be 10μm, 11μm, 15μm, 18μm, 20μm, 23μm, 25μm, 30μm, 31μm, 35μm, 38μm, 40μm, 41μm, 45μm, 46μm, 50μm, 60μm, 70μm, 80μm, 90μm, or 100μm.

[0148] In some possible embodiments, reference Figure 4 In the cell, at the bottom of the recessed structure 11 of the silicon wafer, the width of the raised structure 12 is B7, 0.05≤B6 / B7≤1.2, and further, 0.2≤B6 / B7≤1.1. B6 / B7 can represent the slope or rate of change of the width of the raised structure 12 in the thickness direction E of the cell 1. If the difference between this value and 1 is too small, it means that the slope or rate of change of the width of the raised structure 12 is too small. If the difference between this value and 1 is too large, it means that the slope or rate of change of the width of the raised structure 12 is too large. When B6 / B7 is within the above range, the processing window is large and the process yield is high.

[0149] For example, B6 / B7 can be 0.05, 0.06, 0.08, 0.09, 0.1, 0.12, 0.15, 0.18, 0.2, 0.22, 0.25, 0.29, 0.3, 0.32, 0.35, 0.4, 0.44, 0.5, 0.55, 0.6, 0.65, 0.7, 0.75, 0.8, 0.88, 0.9, 0.95, 1, 1.1, 1.2.

[0150] In some possible embodiments, reference Figure 4 In the cell, at the bottom of the recessed structure 11, the width of the recessed structure is B8, with 0.05 ≤ B7 / B8 < 1, and further, 0.4 ≤ B7 / B8 < 0.75. B7 / B8 represents the ratio of the size of the raised structure 12 to the width of the recessed structure. A smaller value indicates that the ratio of the raised structure 12 to the width of the recessed structure is too small, resulting in poor light trapping for light at smaller incident angles. Within the above range, B7 / B8 provides better light trapping for light at smaller incident angles.

[0151] For example, B7 / B8 can be 0.05, 0.06, 0.08, 0.09, 0.1, 0.12, 0.15, 0.18, 0.2, 0.22, 0.25, 0.29, 0.3, 0.32, 0.35, 0.4, 0.44, 0.5, 0.55, 0.6, 0.65, 0.7, 0.75, 0.8, 0.88, 0.9, 0.95, 0.99.

[0152] It should be noted that, in a cell, B5 of the recessed structure 11 is generally larger than B1 of the recessed structure 11 in the silicon wafer, and B8 of the recessed structure 11 is generally larger than B4 of the recessed structure 11 in the silicon wafer. In a cell, B6 of the raised structure 12 is generally smaller than B2 of the raised structure 12 in the silicon wafer, and B7 of the raised structure 12 is generally smaller than B3 of the raised structure 12 in the silicon wafer.

[0153] The present application also provides a photovoltaic device comprising: a plurality of battery strings connected in series and / or in parallel, the battery string comprising: an electrical connector and any of the aforementioned battery cells, the electrical connector electrically connecting the electrode structures of at least two battery cells. The electrical connector extends along the battery string, electrically connecting the positive electrode of the preceding battery cell to the negative electrode of the succeeding battery cell. The electrical connector may be a conductive backsheet, a soldering ribbon, or the like.

[0154] The photovoltaic device only needs to include any of the aforementioned cells, and there is no limitation on the specific form of the photovoltaic device. For example, there is no limitation on whether the photovoltaic device includes a frame. For another example, the photovoltaic device may include a photovoltaic module, a photovoltaic system, etc. The photovoltaic system here may be a distributed photovoltaic system, or a photovoltaic and building integrated system (BIPV), etc. The photovoltaic device may be a variety of photovoltaic products including the aforementioned cells. Encapsulation materials may also be provided on opposite sides of the cell in the photovoltaic module, and there is no limitation on the specific structure.

[0155] It should be noted that the relevant parts of the silicon wafer, battery cell and photovoltaic device mentioned in this application can be referenced to each other. In order to avoid repetition, the relevant parts are briefly described or not elaborated.

[0156] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0157] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of this application, ordinary technicians in this field can also make many forms without departing from the purpose of this application and the scope of protection of the claims, all of which are protected by this application.

Claims

1. A silicon wafer, characterized in that: The silicon wafer comprises: Two surfaces facing each other along the thickness direction of the silicon wafer; at least one of the two surfaces has one or more recessed structures; One or more convex structures are arranged in the concave structure.

2. The silicon wafer according to claim 1, wherein The surface having the concave structure further includes a connection area connected to the concave structure, and the top height of the convex structure in the concave structure does not exceed the height of the connection area.

3. The silicon wafer according to claim 1 or 2, characterized in that: There are a plurality of concave structures in both surfaces; wherein the number of the concave structures on one surface is greater than or equal to the number of the concave structures on the other surface.

4. The silicon wafer according to any one of claims 1 to 3, characterized in that The surface having the recessed structure includes: an edge area where the recessed structure is not set, a middle area at the center of the surface having the recessed structure, and a transition area in which the distribution density of the recessed structures is greater than the distribution density of the recessed structures in the middle area, and the transition area is located between the middle area and the edge area.

5. The silicon wafer according to any one of claims 1 to 4, characterized in that One or more pit structures are further arranged in the recessed structure.

6. The silicon wafer according to any one of claims 1 to 5, characterized in that: The edge area of ​​the surface having the recessed structure is not provided with the recessed structure; and / or, The cross-sectional shape of the recessed structure along the thickness direction of the silicon wafer includes at least one of a rectangle, a trapezoid, a semi-ellipse or an irregular shape; and / or, The cross-sectional shape of the protrusion structure along the thickness direction of the silicon wafer includes at least one of a triangle, a trapezoid, a rectangle, a stacked structure or an irregular shape; and / or, The shape of the concave structure on the surface having the concave structure includes: a ring shape or a strip shape; and / or, The shape of the protruding structure on the surface having the concave structure includes: a circle or a strip.

7. The silicon wafer according to claim 6, wherein: The shape of the concave structure on the surface having the concave structure includes: annular, multiple annular concave structures are nested with each other, and the convex structure is arranged in the inner annular structure; and / or, The shape of the concave structure on the surface having the concave structure includes: a strip shape, a plurality of strip-shaped concave structures are nested with each other, and the convex structure is arranged in the inner strip structure.

8. The silicon wafer according to any one of claims 1 to 7, characterized in that: At the bottom of the concave structure, the width of the convex structure is B3, the width of the concave structure is B4, and B3 and B4 satisfy the relationship: 0.08≤B3 / B4<1; and / or, In the thickness direction of the silicon wafer, at the position where the center line of the protruding structure is located, the width of the protruding structure is B2, and at the bottom of the recessed structure, the width of the protruding structure is B3, and B2 and B3 satisfy the relationship: 0.08≤B2 / B3≤1.

3.

9. The silicon wafer according to any one of claims 1 to 7, characterized in that: At the bottom of the concave structure, the width of the convex structure is B3, the width of the concave structure is B4, and B3 and B4 satisfy the relationship: 0.5≤B3 / B4<0.8; and / or, In the thickness direction of the silicon wafer, at the position where the center line of the protruding structure is located, the width of the protruding structure is B2, and at the bottom of the recessed structure, the width of the protruding structure is B3, and B2 and B3 satisfy the relationship: 0.3≤B2 / B3≤1.

2.

10. The silicon wafer according to any one of claims 1 to 9, wherein a width B1 of the recessed structure on the surface having the recessed structure is 3 μm to 480 μm; and / or, In the thickness direction of the silicon wafer, at the position where the center line of the protruding structure is located, the width B2 of the protruding structure is 0.7 μm to 470 μm; and / or, At the bottom of the concave structure, the width B3 of the convex structure is 0.53 μm to 350 μm; and / or, At the bottom of the recessed structure, the width B4 of the recessed structure is 3 μm to 400 μm; and / or, The depth of the recessed structure is greater than or equal to 3 percent of the thickness of the silicon wafer and less than or equal to 90 percent of the thickness of the silicon wafer.

11. The silicon wafer according to any one of claims 1 to 9, wherein a width B1 of the recessed structure on the surface having the recessed structure is 30 μm to 300 μm; and / or In the thickness direction of the silicon wafer, at the position where the center line of the protruding structure is located, the width B2 of the protruding structure is 5 μm to 180 μm; and / or, At the bottom of the concave structure, the width B3 of the convex structure is 7.5 μm to 150 μm; and / or, At the bottom of the recessed structure, the width B4 of the recessed structure is 10 μm to 200 μm; and / or The depth of the recessed structure is 10 μm to 125 μm.

12. A battery cell, characterized in that: include: An electrode structure, and a silicon wafer as claimed in any one of claims 1 to 11; The electrode structure is arranged on the silicon wafer.

13. The battery cell according to claim 12, characterized in that: The electrode structures are staggered with respect to the recessed structures.

14. The battery cell according to claim 13, characterized in that: One of the two surfaces is a light-facing surface of the silicon wafer, and the other surface is a backlight surface of the silicon wafer. The electrode structure includes: a plurality of front gate line electrodes located on the light-facing surface of the silicon wafer, and a plurality of back gate line electrodes located on the backlight surface of the silicon wafer. There is a first spacing region between adjacent front gate line electrodes, and the recessed structure is located in at least a portion of the first spacing region; and / or, A second spacing region is provided between adjacent back gate line electrodes; the recessed structure is located in at least a portion of the second spacing region.

15. The battery cell according to claim 13, characterized in that: One of the two surfaces is the light-facing surface of the silicon wafer, and the other surface is the backlight surface of the silicon wafer; the electrode structure includes: a plurality of first gate line electrodes and a plurality of second gate line electrodes, all of which are located on the backlight surface of the silicon wafer, with a third spacing area between adjacent first gate line electrodes and second gate line electrodes, the recessed structure is located in at least a portion of the third spacing area corresponding to the backlight surface, and / or the recessed structure is located in at least a portion of the light-facing surface.

16. The battery cell according to any one of claims 12 to 15, characterized in that: Also includes: A functional film layer located between the electrode structure and the surface having the recessed structure along the thickness direction of the battery cell; The functional film layer is conformally arranged on the silicon wafer.

17. The battery cell according to any one of claims 12 to 16, characterized in that: At least part of the inner surface of the recessed structure is provided with a suede structure; and / or, At least a portion of the outer surface of the raised structure is provided with a velvet structure.

18. The battery cell according to any one of claims 12 to 17, characterized in that: At least a portion of the inner surface of the pit structure within the recessed structure is provided with a suede structure.

19. The battery cell according to any one of claims 12 to 18, characterized in that: The width B5 of the recessed structure on the surface having the recessed structure is 5 μm to 500 μm; and / or, In the thickness direction of the battery cell, at the position where the center line of the protruding structure is located, the width B6 of the protruding structure is 0.5 μm to 450 μm; and / or At the bottom of the concave structure, the width B7 of the convex structure is 0.35 μm to 300 μm; and / or At the bottom of the recessed structure, a width B8 of the recessed structure is 4 μm to 450 μm.

20. The battery cell according to any one of claims 12 to 18, characterized in that: The width B5 of the recessed structure on the surface having the recessed structure is 50 μm to 300 μm; and / or, In the thickness direction of the battery cell, at the position where the center line of the protruding structure is located, the width B6 of the protruding structure is 2 μm to 20 μm; and / or At the bottom of the concave structure, the width B7 of the convex structure is 10 μm to 50 μm; and / or At the bottom of the recessed structure, a width B8 of the recessed structure is 12 μm to 250 μm.

21. The battery cell according to any one of claims 12 to 20, characterized in that: In the thickness direction of the battery cell, at the position where the midline of the convex structure is located, the width of the convex structure is B6, and at the bottom of the concave structure, the width of the convex structure is B7, and B6 and B7 satisfy the relationship: 0.05≤B6 / B7≤1.2; and / or, At the bottom of the concave structure, the width of the concave structure is B8, the width of the convex structure is B7, and B8 and B7 satisfy the relationship: 0.05≤B7 / B8<1.

22. The battery cell according to any one of claims 12 to 21, characterized in that: In the thickness direction of the battery cell, at the position where the midline of the convex structure is located, the width of the convex structure is B6, and at the bottom of the concave structure, the width of the convex structure is B7, and B6 and B7 satisfy the relationship: 0.2≤B6 / B7≤1.1; and / or, At the bottom of the concave structure, the width of the concave structure is B8, the width of the convex structure is B7, and B8 and B7 satisfy the relationship: 0.4≤B7 / B8<0.

75.

23. A photovoltaic device, characterized in that: include: A plurality of battery strings connected in series and / or in parallel, the battery string comprising: an electrical connector and a battery cell according to any one of claims 12 to 22, the electrical connector electrically connecting the electrode structures of at least two of the battery cells.

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