Display device

Abstract

A display device includes a display panel that emits light for image display. The display panel includes a substrate, a circuit layer disposed on the substrate, and an element layer disposed on the circuit layer. The main area of the substrate includes a display area and a non-display area disposed around the display area. The display area includes a front display area and a peripheral display area disposed around the front display area and having a curved shape. The display panel further includes a strain adjusting portion overlapping a corner region of the peripheral display region adjacent to a corner of an edge of the substrate, and spaced apart from the edge of the substrate. The substrate has a first thickness in a portion that does not overlap the strain adjustment portion. A portion of the substrate overlapping the strain adjusting portion has a second thickness less than the first thickness.

Description

Technical Field

[0001] The present disclosure relates to a display device. Background Art

[0002] With the advancement of information society, there is an increasing demand for display devices that display images in various ways. For example, display devices are applied to various electronic devices such as smart phones, digital cameras, laptop computers, navigation devices, and smart TVs.

[0003] The display device may be a flat panel display device such as a liquid crystal display device, a field emission display device, and a light-emitting display device. Examples of the light-emitting display device may include an organic light-emitting display device including an organic light-emitting element, an inorganic light-emitting display device including an inorganic light-emitting element such as an inorganic semiconductor, and a micro light-emitting display device including a micro light-emitting element.

[0004] Organic light-emitting display devices use light-emitting elements to display images. Each light-emitting element includes a light-emitting layer made of an organic light-emitting material. As described above, organic light-emitting display devices use self-luminous elements to display images. Therefore, compared with other display devices, they can have relatively superior performance in terms of power consumption, response speed, luminous efficiency, brightness, and wide viewing angle.

[0005] In a display device, a display surface from which light is emitted may include a display area displaying an image and a non-display area around the display area. An emission area emitting light having corresponding brightness and color may be arranged in the display area. Summary of the Invention

[0006] When the display area is set wider in the display surface of the display device, the area from which the display device emits light becomes wider, and thus, the aesthetics can be improved and the compatibility with various electronic devices can be improved. Therefore, measures for reducing the width of the non-display area in the display surface have been studied and developed.

[0007] However, due to the presence of wirings and elements disposed in the non-display area, there is a limit to reducing the width of the non-display area.

[0008] In view of the above, aspects of the present disclosure provide a display device in which the width of a non-display area visually recognized in a front direction facing a display surface can be reduced by deforming the edge of the display area into a curved shape.

[0009] However, the aspects of the present disclosure are not limited to the aspects described herein. By referring to the detailed description of the present disclosure given below, the above and other aspects of the present disclosure will become more apparent to those skilled in the art in the art to which the present disclosure belongs.

[0010] According to an aspect of the present disclosure, a display device is provided, which includes a display panel that emits light for image display. The display panel includes a substrate, a circuit layer provided on the substrate, and an element layer provided on the circuit layer. The main area of ​​the substrate includes a display area in which an emission area is arranged and a non-display area provided around the display area. The display area includes a front display area and a peripheral display area provided around the front display area and having a curved shape. The display panel further includes a strain adjustment portion that overlaps with a corner area of ​​the peripheral display area and adjacent to a corner of an edge of the substrate, and is spaced apart from the edge of the substrate. The substrate has a first thickness in a portion that does not overlap with the strain adjustment portion. Due to the strain adjustment portion, the portion of the substrate that overlaps with the strain adjustment portion has a second thickness that is less than the first thickness.

[0011] The substrate includes a first supporting layer; a barrier layer disposed on the first supporting layer; and a second supporting layer disposed on the barrier layer at a third thickness in a portion not overlapping with the strain adjustment portion. The strain adjustment portion includes a first groove penetrating at least a portion of the first supporting layer; and a second groove overlapping the first groove and penetrating a portion of the second supporting layer.

[0012] An inclination angle of a side surface of the second groove relative to a plane of the substrate is greater than or equal to 5° and less than or equal to 15°.

[0013] A thickness of a portion of the second supporting layer overlapping the bottom surface of the second groove is greater than or equal to 50% of the third thickness and less than or equal to 85% of the third thickness.

[0014] The thickness of a portion of the second supporting layer overlapping with the bottom surface of the second groove is 3 μm or more.

[0015] The first supporting layer has a fourth thickness greater than the third thickness in a portion not overlapping the strain adjustment portion. The thickness of the portion of the first supporting layer overlapping the first groove is less than 10% of the fourth thickness.

[0016] A minimum value of a separation distance between the strain adjustment portion and the edge of the substrate is 150 μm to 180 μm.

[0017] The peripheral display area further includes side regions parallel to edge sides of the substrate. The strain adjustment portion further overlaps portions of the side regions and adjacent to the corner regions.

[0018] The strain adjustment portion further overlaps portions of the non-display area and adjacent to the corner area.

[0019] The peripheral display region further includes a side region parallel to an edge side of the substrate, and the strain adjustment portion further overlaps the side region.

[0020] The strain adjustment portion further overlaps with portions of the front display area adjacent to the corner area.

[0021] The strain adjustment portion further overlaps a portion of the non-display area and adjacent to the peripheral display area.

[0022] The strain adjustment portion further overlaps with portions of the front display area and adjacent to the corner areas.

[0023] The front display area includes a first side and a second side extending in a first direction and opposite to each other, and a third side and a fourth side extending in a second direction intersecting the first direction and opposite to each other. The peripheral display area further includes: a first side area, a second side area, a third side area, and a fourth side area, which are in contact with the first side, the second side, the third side, and the fourth side of the front display area, respectively. The corner area includes: a first corner area, which is in contact with the vertex at which the first side and the third side intersect and is arranged between the first side area and the third side area; a second corner area, which is in contact with the vertex at which the second side and the third side intersect and is arranged between the second side area and the third side area; a third corner area, which is in contact with the vertex at which the second side and the fourth side intersect and is arranged between the second side area and the fourth side area; and a fourth corner area, which is in contact with the vertex at which the first side and the fourth side intersect and is arranged between the first side area and the fourth side area. The strain adjustment portion overlaps with the first corner area, the second corner area, the third corner area, and the fourth corner area.

[0024] The display device further includes a bracket supporting the display panel and a cover window disposed on the display panel and coupled to the bracket. The peripheral display area is bent toward the bracket.

[0025] According to aspects of the present disclosure, a display device is provided, comprising: a display panel that emits light for image display; a bracket that supports the display panel; and a cover window disposed on the display panel and coupled to the bracket. The display panel includes a substrate, a circuit layer disposed on the substrate, and a component layer disposed on the circuit layer. The main area of ​​the substrate includes a display area in which an emission area is arranged, and a non-display area disposed around the display area. The display area includes a front display area and a peripheral display area disposed around the front display area and having a shape curved toward the bracket. The display panel further includes a strain adjustment portion that overlaps with a corner area of ​​the peripheral display area adjacent to a corner of an edge of the substrate and is spaced apart from the edge of the substrate. The substrate has a first thickness in a portion not overlapping with the strain adjustment portion. Due to the strain adjustment portion, the portion of the substrate overlapping with the strain adjustment portion has a second thickness that is less than the first thickness. The substrate includes: a first supporting layer; a barrier layer disposed on the first supporting layer; and a second supporting layer disposed on the barrier layer. The strain adjustment portion includes: a first groove that penetrates at least a portion of the first supporting layer; and a second groove that overlaps with the first groove and penetrates a portion of the second supporting layer.

[0026] The second supporting layer is provided with a third thickness in a portion not overlapping with the strain adjustment portion. The first supporting layer is provided with a fourth thickness greater than the third thickness in a portion not overlapping with the strain adjustment portion. The thickness of the portion of the second supporting layer overlapping with the bottom surface of the second groove is greater than or equal to 50% and less than or equal to 85% of the third thickness. The thickness of the portion of the first supporting layer overlapping with the first groove is less than or equal to 10% of the fourth thickness.

[0027] A minimum value of a separation distance between the strain adjustment portion and the edge of the substrate is 150 μm to 180 μm.

[0028] The peripheral display area further includes a side region parallel to an edge side of the substrate. The strain adjustment portion further overlaps at least some portions of the side region and adjacent to the corner region.

[0029] The strain adjustment portion further overlaps at least some portions of the non-display area and adjacent to the corner area.

[0030] The display device according to the embodiment may include a display panel that emits light for image display, and the main area of ​​the substrate of the display panel may include a display area in which the emission area is arranged and a non-display area provided around the display area. The display area may include a front display area and a peripheral display area provided around the front display area and having a curved shape.

[0031] Therefore, because the display area includes a curved peripheral display area, the non-display area connected to the peripheral display area can have a curved shape along with the peripheral display area. In other words, the width of the curved non-display area, as seen from the front facing the display surface, can be smaller than the width of the non-display area in the unfolded state. Therefore, the width of the display area, as seen from the front facing the display surface, can be increased, thereby improving the aesthetics and compatibility of the display device.

[0032] Each corner region of the curved peripheral display area may have a double curvature region, where the curvature on one side differs from the other. Because such a double curvature region bends at two curvatures, it may experience higher bending stress than a region that bends at a single curvature. As a result, defects such as substrate delamination and fracture may occur more easily in the double curvature region.

[0033] To prevent this, according to an embodiment, the display panel further includes a strain adjustment portion that overlaps a corner region of the peripheral display region adjacent to a corner of an edge of the substrate and is spaced apart from the edge of the substrate.

[0034] The substrate is provided with a first thickness, but due to the strain adjustment portion, a portion of the substrate overlapping the strain adjustment portion has a second thickness that is less than the first thickness.

[0035] That is, the strain adjustment portion can provide a higher strain to the corner region of the substrate as a double curvature region by being provided with a relatively thin second thickness, thereby reducing defects caused by high bending stress in the double curvature region.

[0036] Therefore, the lifespan and quality reliability of the display device can be improved.

[0037] However, the effects according to the embodiments of the present disclosure are not limited to those exemplified above, and various other effects are also included herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The above and other aspects and features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings.

[0039] Figure 1 is a perspective view illustrating a display device according to an embodiment.

[0040] Figure 2 It is along Figure 1 A cross-sectional view taken along line AA'.

[0041] Figure 3 is shown along Figure 1BB' cross-sectional view of the display panel.

[0042] Figure 4 It shows Figure 3 A plan view of the substrate.

[0043] Figure 5 The diagram shows Figure 4 Layout diagram of part C.

[0044] Figure 6 is a diagram showing a method according to an embodiment of the present invention. Figure 5 Equivalent circuit diagram of the light-emitting pixel driver.

[0045] Figure 7 The diagram shows the Figure 6 A cross-sectional view of a light-emitting element and a first transistor and a sixth transistor of a light-emitting pixel driver according to an embodiment of the present invention.

[0046] Figure 8 is a diagram showing a method according to an embodiment of the present invention. Figure 5 Equivalent circuit diagram of the light-emitting pixel driver.

[0047] Figure 9 It shows that according to Figure 8 A cross-sectional view of a light-emitting element and a first transistor, a second transistor, a fourth transistor, and a sixth transistor of a light-emitting pixel driver according to an embodiment of the present invention.

[0048] Figure 10 is a plan view illustrating a display panel according to an embodiment.

[0049] Figure 11 According to the embodiment Figure 10 A cross-sectional view taken along line D-D'.

[0050] Figure 12 According to the embodiment Figure 10 A cross-sectional view taken along line EE'.

[0051] Figure 13 、 Figure 14 、 Figure 15 、 Figure 16 and Figure 17 is a process diagram illustrating steps of a process of providing a strain adjustment portion according to an embodiment.

[0052] Figure 18 According to the embodiment Figure 10 A cross-sectional view taken along line D-D'.

[0053] Figure 19 is a plan view illustrating a display panel according to an embodiment.

[0054] Figure 20 It is along Figure 19 A cross-sectional view taken along line FF'.

[0055] Figure 21 、 Figure 22 、 Figure 23 and Figure 24 is a plan view showing a display panel according to an embodiment. DETAILED DESCRIPTION

[0056] Each embodiment will now be described more fully below with reference to the accompanying drawings. However, each embodiment may be provided in different forms and should not be construed as limiting. Throughout this disclosure, the same reference numerals indicate the same components. In the accompanying drawings, the thickness of each layer and region may be exaggerated for clarity.

[0057] For the purpose of describing the embodiments of the present disclosure, some parts that are not related to the description may not be provided.

[0058] It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. In contrast, when an element is referred to as being “directly on” another element, there may not be intervening elements present.

[0059] In addition, the term "in a plan view" means when the object portion is observed from above, and the term "in a schematic cross-sectional view" means when a schematic cross-section obtained by vertically cutting the object portion is observed from the side. The term "overlapping" or "overlapping" means that the first object can be above, below, or to the side of the second object, and vice versa. In addition, the term "overlapping" can include stacking, stacking, facing or facing, extending thereon, covering or partially covering, or any other appropriate terms that a person of ordinary skill in the art will appreciate and understand. The expression "non-overlapping" can include meanings such as "separated from..." or "separated from..." or "offset from..." and any other appropriate equivalent expressions that a person of ordinary skill in the art will appreciate and understand. The terms "facing" and "facing" can mean that the first object can be directly or indirectly opposite to the second object. In the case where a third object is between the first object and the second object, the first object and the second object can be understood to be indirectly opposite to each other, although still facing each other.

[0060] For ease of description, spatially relative terms such as "below," "beneath," "under," "above," or "upper" may be used herein to describe the relationship between one element or component and another element or component as illustrated in the figures. It will be understood that, in addition to the orientations depicted in the accompanying drawings, spatially relative terms are intended to cover different orientations of the device in use or operation. For example, where the device illustrated in the figures is flipped, a device positioned "below" or "below" another device may be placed "above" the other device. Accordingly, the illustrative term "below" may include both a lower position and an upper position. The device may also be oriented in other directions, and therefore, the spatially relative terms may be interpreted differently depending on the orientation.

[0061] When an element is referred to as being “connected” or “coupled” to another element, the element may be “directly connected” or “directly coupled” to the other element, or “electrically connected” or “electrically coupled” to the other element with one or more intervening elements interposed therebetween. It will be further understood that when the terms “comprising,” “having,” and / or “including,” and variations thereof, are used, they may specify the presence of recited features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of other features, integers, steps, operations, elements, components, and / or any combination thereof.

[0062] It will be understood that although the terms "first," "second," or "third," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another or to facilitate description and explanation. For example, when discussing a "first element" in the description, it could be referred to as a "second element" or a "third element," and similar references could be made to the "second element" and "third element" without departing from the teachings herein.

[0063] As used herein, the terms "about" or "approximately" include the recited value and mean within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the measurements in question and the errors associated with the measurement of a particular quantity (e.g., limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the recited value, or within ±30%, ±20%, ±10%, ±5% of the recited value.

[0064] In this specification and claims, as far as its meaning and interpretation are concerned, the term "and / or" is intended to include any combination of the term "and" and the term "or". For example, "A and / or B" may be understood to mean "A, B, or A and B". The term "and" and the term "or" may be used in a conjunction or a disjunction sense and may be understood to be equivalent to "and / or". In this specification and claims, as far as its meaning and interpretation are concerned, the term "at least one of..." is intended to include the meaning of "at least one selected from the group of..." For example, "at least one of A and B" may be understood to mean "A, B, or A and B".

[0065] Unless otherwise defined or implied, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will be further understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless explicitly defined in this specification.

[0066] Hereinafter, various embodiments will be described with reference to the accompanying drawings.

[0067] Figure 1 is a perspective view illustrating a display device 10 according to an embodiment. Figure 2 It is along Figure 1 A cross-sectional view taken along line AA'.

[0068] refer to Figure 1 The display device 10 according to the embodiment, which is a device for displaying moving images or still images, can be used as a display screen of various devices (such as televisions, laptop computers, monitors, billboards, and Internet of Things (IOT) devices) and portable electronic devices (such as mobile phones, smart phones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and ultra mobile PCs (UMPCs)).

[0069] In an embodiment, the display device 10 according to the embodiment can be applied to a dashboard of a vehicle, a central instrument panel of a vehicle, a central information display (CID) set on the dashboard of a vehicle, an interior mirror display instead of a side-view mirror of a vehicle, or a display set on the rear surface of a front seat of a vehicle for rear-seat entertainment.

[0070] refer to Figure 2 , the display device 10 according to the embodiment may include a display panel 100 that emits light for image display.

[0071] The display device 10 according to the embodiment may further include a bracket 200 supporting the display panel 100 and a cover window 300 disposed on the display panel 100 and coupled to the bracket 200 .

[0072] The display panel 100 may be a light-emitting display panel including a light-emitting element. For example, the display panel 100 may be an organic light-emitting display panel using an organic light-emitting diode including an organic light-emitting layer, a micro light-emitting diode display panel using micro-LEDs, a quantum dot light-emitting display panel using a quantum dot light-emitting diode including a quantum dot light-emitting layer, or an inorganic light-emitting display panel using an inorganic light-emitting element including an inorganic semiconductor. The following description is for the case where the display panel 100 is an organic light-emitting display panel.

[0073] The bracket 200 may include a rigid insulating material to prevent deformation of the display panel 100 and to relieve external physical and electrical shocks to the display panel 100. However, this is merely an example, and the material of the bracket 200 may be variously changed.

[0074] The cover window 300 may include a light-transmitting material. The cover window 300 may be made of an inorganic material such as glass or an organic material such as plastic or polymer material.

[0075] The cover window 300 may be fastened to the bracket 200 by an adhesive material 400 disposed on the edge.

[0076] The cover window 300 may be attached to the display panel 100 by a transparent adhesive member such as an optically clear adhesive (OCA) film or an optically clear resin (OCR).

[0077] Through such a cover window 300 , the display panel 100 can be protected from electrical shock and physical shock to the display surface.

[0078] like Figure 1 As shown in FIG, according to an embodiment, the display panel 100 may include a display area DA from which light is emitted and a non-display area NDA disposed around the display area DA.

[0079] The display area DA may include a front display area FSA having a flat shape and a peripheral display area PSA disposed around the front display area FSA and having a curved shape.

[0080] The front display area FSA may include first and second sides SD1 and SD2 extending in the first direction DR1 and opposite to each other, and third and fourth sides SD3 and SD4 extending in the second direction DR2, connecting between the first and second sides SD1 and SD2, and opposite to each other.

[0081] For example, the first side SD1 and the second side SD2 may have shorter lengths than the third side SD3 and the fourth side SD4. That is, the front display area FSA may have a quadrangular shape in a plan view.

[0082] In another example, a corner at which each of the first and second sides SD1 and SD2 intersects each of the third and fourth sides SD3 and SD4 may have an arc shape or a right-angled vertex shape.

[0083] However, the shape of the front display area FSA according to the embodiment is not limited to Figure 1 , and may be a circle, an ellipse, or a polygon other than a quadrilateral.

[0084] The peripheral display area PSA may include a first side area SS1 in contact with the first side SD1 of the front display area FSA, a second side area SS2 in contact with the second side SD2 of the front display area FSA, a third side area SS3 in contact with the third side SD3 of the front display area FSA, and a fourth side area SS4 in contact with the fourth side SD4 of the front display area FSA.

[0085] In addition, the peripheral display area PSA may further include a first corner area CS1 that contacts the vertex at which the first side SD1 and the third side SD3 intersect and is arranged between the first side area SS1 and the third side area SS3, a second corner area CS2 that contacts the vertex at which the second side SD2 and the third side SD3 intersect and is arranged between the second side area SS2 and the third side area SS3, a third corner area CS3 that contacts the vertex at which the second side SD2 and the fourth side SD4 intersect and is arranged between the second side area SS2 and the fourth side area SS4, and a fourth corner area CS4 that contacts the vertex at which the first side SD1 and the fourth side SD4 intersect and is arranged between the first side area SS1 and the fourth side area SS4.

[0086] The first side region SS1 may extend from the first side SD1 and bend toward the bracket 200 with a predetermined first curvature.

[0087] The second side region SS2 may extend from the second side SD2 and be bent with a predetermined second curvature toward the bracket 200. The second curvature may be within the same range as that of the first curvature.

[0088] The third side region SS3 may extend from the third side SD3 and be bent with a predetermined third curvature toward the bracket 200. The third curvature may be in the same or similar range as that of the first or second curvature, but is not limited thereto.

[0089] The fourth side region SS4 may extend from the fourth side SD4 and be bent with a fourth curvature toward the bracket 200. The fourth curvature may be within the same range as that of the third curvature.

[0090] The first corner region CS1 may be disposed between one side of the first side region SS1 and one side of the third side region SS3 .

[0091] The first corner region CS1 may be a double curvature region bent with a first curvature of a first side region SS1 contacting one side thereof and a third curvature of a third side region SS3 contacting the other side thereof.

[0092] The second corner region CS2 may be disposed between one side of the second side region SS2 and the other side of the third side region SS3 .

[0093] The second corner region CS2 may be a double curvature region bent with a second curvature of the second side region SS2 contacting one side thereof and a third curvature of the third side region SS3 contacting the other side thereof.

[0094] The third corner region CS3 may be disposed between the other side of the second side region SS2 and one side of the fourth side region SS4 .

[0095] The third corner region CS3 may be a double curvature region bent with a second curvature of the second side region SS2 contacting one side thereof and a fourth curvature of the fourth side region SS4 contacting the other side thereof.

[0096] The fourth corner region CS4 may be disposed between the other side of the first side region SS1 and the other side of the fourth side region SS4 .

[0097] The fourth corner region CS4 may be a double curvature region bent with a first curvature of the first side region SS1 contacting one side thereof and a fourth curvature of the fourth side region SS4 contacting the other side thereof.

[0098] That is, since the first corner area CS1, the second corner area CS2, the third corner area CS3 and the fourth corner area CS4 are each a double curvature area affected by two different curvatures, they can withstand higher bending stress compared to the first side area SS1, the second side area SS2, the third side area SS3 and the fourth side area SS4.

[0099] As described above, according to the embodiment, the display area DA includes not only the front display area FSA in a flat shape but also the peripheral display area PSA in a shape bent toward the bracket 200 .

[0100] Since the non-display area NDA is disposed around the display area DA, it may be connected to the outer edge of the peripheral display area PSA.

[0101] The bent shape of the peripheral display area PSA may extend to the non-display area NDA. That is, the non-display area NDA may have a bent shape together with the curved peripheral display area PSA.

[0102] In an embodiment, the bent shape of the peripheral display area PSA may not extend to the non-display area NDA, and the non-display area NDA may be provided in a flat shape in a direction perpendicular to the front display area FSA.

[0103] In addition, a portion of the non-display area NDA adjacent to the peripheral display area PSA may have a curved shape together with the peripheral display area PSA, while being adjacent to the substrate 110 (see FIG. Figure 3 ) may have a flat shape in a direction perpendicular to the front display area FSA.

[0104] like Figure 2 As shown in , the display device 10 may include a display area DA of the display panel 100 from which light is emitted, and a non-display area NDA that is disposed around the display area DA and from which no light is emitted.

[0105] The peripheral display area PSA (see FIG. 1 ) at the edge of the display area DA of the display panel 100 Figure 1 ) may be bent toward the bracket 200. Accordingly, due to the curved shape of the peripheral display area PSA, the non-display area NDA of the display device 10 may be disposed on the side surface of the display device 10.

[0106] In addition, similar to the display panel 100 , each of the bracket 200 and the cover window 300 may also have a curved edge.

[0107] Accordingly, in the display device 10, in the front display area FSA (see Figure 1 ) in a front direction of light (eg, a direction opposite to the third direction DR3) in the bent shape may be smaller than a width L of the non-display area NDA in the unfolded state.

[0108] Therefore, since the width W of the non-display area NDA visually recognized in the front direction in the display surface of the display device 10 is reduced, the proportion of the display area DA of the display surface can be increased, thereby improving the aesthetics and compatibility of the display device 10.

[0109] Figure 3 is shown along Figure 1 1 is a cross-sectional view of the display panel 100 taken along line BB′.

[0110] refer to Figure 3 The display panel 100 of the display device 10 according to the embodiment may include a substrate 110 , a circuit layer 120 disposed on the substrate 110 , and an element layer 130 disposed on the circuit layer 120 .

[0111] The substrate 110 may include a main area MA and a sub-area SBA.

[0112] The main area MA may include a display area DA and a non-display area NDA disposed around the display area DA.

[0113] The display area DA may include a front display area FSA and a peripheral display area PSA disposed around the front display area FSA and having a curved shape.

[0114] The edge of the front display area FSA may include a first side SD1 and a second side SD2 opposite to each other in the second direction DR2.

[0115] The peripheral display area PSA may include a first side area SS1 disposed between the first side SD1 of the front display area FSA and the non-display area NDA, and a second side area SS2 disposed between the second side SD2 of the front display area FSA and the non-display area NDA.

[0116] In addition, if Figure 1 As shown in FIG, the edge of the front display area FSA may further include a third side SD3 and a fourth side SD4 opposite to each other in the first direction DR1.

[0117] The peripheral display area PSA may further include a third side area SS3 disposed between the third side SD3 of the front display area FSA and the non-display area NDA, and a fourth side area SS4 disposed between the fourth side SD4 of the front display area FSA and the non-display area NDA.

[0118] In addition, the peripheral display area PSA may further include a first corner area CS1 that contacts the vertex at which the first side SD1 and the third side SD3 intersect and is arranged between the first side area SS1 and the third side area SS3, a second corner area CS2 that contacts the vertex at which the second side SD2 and the third side SD3 intersect and is arranged between the second side area SS2 and the third side area SS3, a third corner area CS3 that contacts the vertex at which the second side SD2 and the fourth side SD4 intersect and is arranged between the second side area SS2 and the fourth side area SS4, and a fourth corner area CS4 that contacts the vertex at which the first side SD1 and the fourth side SD4 intersect and is arranged between the first side area SS1 and the fourth side area SS4.

[0119] like Figure 3 As shown in , according to an embodiment, the display device 10 may further include a display driving circuit 500 provided as an integrated circuit (IC) chip and mounted on the pad area PDA of the sub area SBA of the substrate 110 .

[0120] The display driving circuit 500 can transmit the data signal Vdata (see Figure 6 and Figure 8 ) is supplied to the data line DL of the circuit layer 120 (see Figure 6 and Figure 8 ).

[0121] According to an embodiment, the display device 10 may further include a circuit board bonded to the pad area PDA of the sub-area SBA of the substrate 110. The circuit board may be bonded to the pads provided in the sub-area SBA of the substrate 110 by using a low-resistance, high-reliability material such as an anisotropic conductive film or SAP.

[0122] Emission area EA (see Figure 5 ) may be arranged in the display area DA.

[0123] The circuit layer 120 may include light emitting pixel drivers EPD arranged side by side in the first direction DR1 and the second direction DR2 (see FIG. Figure 5 ).

[0124] The element layer 130 may include light emitting elements LE respectively disposed in the emission areas EA (see Figure 6 、 Figure 7 、 Figure 8 and Figure 9 ). Light emitting element LE (see Figure 6 、 Figure 7 、 Figure 8 and Figure 9 ) can be electrically connected to the light emitting pixel driver EPD (see Figure 5 ).

[0125] The display panel 100 according to the embodiment may further include an encapsulation layer 140 disposed on the element layer 130 and a touch sensor layer 150 disposed on the encapsulation layer 140 .

[0126] The encapsulation layer 140 is disposed on the element layer 130 and may have a structure in which two or more inorganic films and at least one organic film are alternately stacked.

[0127] The touch sensor layer 150 may include a touch electrode for detecting a signal that varies depending on the touch of a person or an object and sensing a point in the main area MA where the touch of the person or the object has occurred.

[0128] According to an embodiment, the display panel 100 may further include a polarization layer 160 (eg, see FIG. 1 ) on the touch sensor layer 150. Figure 7 、 Figure 9 ).

[0129] The polarizing layer 160 blocks external light reflected from the touch sensor layer 150 , the encapsulation layer 140 , the element layer 130 , and the circuit layer 120 and their interfaces, and this is to prevent degradation of image visibility due to external light reflection.

[0130] Figure 4 It shows Figure 3 A plan view of the substrate 110 is shown. Figure 5 The diagram shows Figure 4 Layout diagram of part C.

[0131] refer to Figure 4 , the display panel 100 of the display device 10 according to the embodiment may include a substrate 110 .

[0132] The substrate 110 may include a main area MA corresponding to a display surface and a sub-area SBA protruding from one side of the main area MA.

[0133] The main area MA may include a display area DA from which light is emitted and a non-display area NDA disposed around the display area DA and from which no light is emitted.

[0134] refer to Figure 5 , an emission area EA that emits light having corresponding color and brightness for image display may be arranged in the display area DA.

[0135] The display area DA may further include a non-emission area disposed in a gap between the emission areas EA.

[0136] The emission area EA may have a rhombus shape or a rectangular shape in a plan view. However, this is only an example, and the planar shape of the emission area EA according to the embodiment is not limited to Figure 5 That is, in a plan view, the emission area EA may have a polygonal shape such as a square, a pentagon, a hexagon, etc., or may have a circular shape or an elliptical shape including curved edges.

[0137] The emission area EA may include a first emission area EA1 emitting a first color light in a predetermined band, a second emission area EA2 emitting a second color light in a band lower than the first color band, and a third emission area EA3 emitting a third color light in a band lower than the second color band.

[0138] For example, the first color may be red having a wavelength of approximately 600 nm to 750 nm, the second color may be green having a wavelength of approximately 480 nm to 560 nm, and the third color may be blue having a wavelength of approximately 370 nm to 460 nm.

[0139] The first emission regions EA1 and the third emission regions EA3 may be alternately arranged in at least one of the first direction DR1 and the second direction DR2.

[0140] The second emission regions EA2 may be arranged side by side in at least one of the first direction DR1 and the second direction DR2.

[0141] In addition, the second emission region EA2 may be adjacent to the first emission region EA1 and the third emission region EA3 in oblique directions DR4 and DR5 crossing the first direction DR1 and the second direction DR2 .

[0142] The pixel PX displaying its own brightness and color may be provided by the first emission area EA1 , the second emission area EA2 , and the third emission area EA3 adjacent to each other among the emission areas EA.

[0143] In other words, the pixel PX may be a basic unit for displaying various colors including white at a predetermined brightness.

[0144] Each of the pixels PX may include at least one first emission area EA1, at least one second emission area EA2, and at least one third emission area EA3 adjacent to each other. Accordingly, by mixing the light emitted from the first emission area EA1, the second emission area EA2, and the third emission area EA3 adjacent to each other, each of the pixels PX may display various colors.

[0145] like Figure 4As shown in FIG, the display area DA of the substrate 110 of the display panel 100 according to the embodiment may include a front display area FSA located at the center and a peripheral display area PSA provided around the front display area FSA.

[0146] The front display area FSA may maintain a flat shape on a plane defined by the first direction DR1 and the second direction DR2 .

[0147] The front display area FSA may include first and second sides SD1 and SD2 extending in the first direction DR1 and opposite to each other, and third and fourth sides SD3 and SD4 extending in the second direction DR2, connecting between the first and second sides SD1 and SD2, and opposite to each other.

[0148] The peripheral display area PSA may be disposed between the front display area FSA and the non-display area NDA. The peripheral display area PSA may have a ring shape surrounding the periphery of the front display area FSA.

[0149] like Figure 1 and Figure 2 As shown in , the peripheral display area PSA can be deformed into a curved shape.

[0150] like Figure 4 As shown in , the peripheral display area PSA may include: a first side region SS1, a second side region SS2, a third side region SS3, and a fourth side region SS4 that are in contact with the first side SD1, the second side SD2, the third side SD3, and the fourth side SD4 of the front display area FSA, respectively. Furthermore, the peripheral display area PSA may further include: a first corner region CS1 that is in contact with the vertex at which the first side SD1 and the third side SD3 intersect and is disposed between the first side region SS1 and the third side region SS3; a second corner region CS2 that is in contact with the vertex at which the second side SD2 and the third side SD3 intersect and is disposed between the second side region SS2 and the third side region SS3; a third corner region CS3 that is in contact with the vertex at which the second side SD2 and the fourth side SD4 intersect and is disposed between the second side region SS2 and the fourth side region SS4; and a fourth corner region CS4 that is in contact with the vertex at which the first side SD1 and the fourth side SD4 intersect and is disposed between the first side region SS1 and the fourth side region SS4.

[0151] Hereinafter, for simplicity of description, the first side region SS1, the second side region SS2, the third side region SS3, and the fourth side region SS4 may be collectively referred to as side regions, and these side regions are parallel to the sides of the edge of the substrate 110 (sometimes referred to as the edge sides of the substrate 110). In addition, the first corner region CS1, the second corner region CS2, the third corner region CS3, and the fourth corner region CS4 may be collectively referred to as corner regions.

[0152] The non-display area NDA may be disposed at an edge of the main area MA, and may be in a ring shape surrounding the display area DA.

[0153] The non-display area NDA may include a gate driving circuit area GDRA where a gate driving circuit is disposed.

[0154] The gate driving circuit may supply signals to the gate lines of the circuit layer 120. Each of the gate lines may be electrically connected to a gate electrode of at least one of the transistors of the light emitting pixel driver EPD.

[0155] according to Figure 6 In an embodiment, the gate lines may include a scan write line GWL for transmitting a scan write signal GW, a scan initialization line GIL for transmitting a scan initialization signal GI, an emission control line ECL for transmitting an emission control signal EC, and a gate control line GCL for transmitting a gate control signal GC.

[0156] In addition, according to Figure 8 In an embodiment of the present invention, the gate line may further include a bias control line GBL for transmitting a bias control signal GB.

[0157] The gate driving circuit area GDRA may face one side of the edge of the display area DA extending in the second direction DR2 .

[0158] In one example, the non-display area NDA may include two gate driving circuit areas GDRA respectively facing a pair of sides extending in the second direction DR2 of the edge of the display area DA.

[0159] The sub area SBA may face the first side SD1 of the front display area FSA.

[0160] The sub area SBA may include a bending region BA deformed into a bent shape and a pad area PDA connected to the bending region BA.

[0161] When the main area MA has a shape similar to that of the front display area FSA, the edge of the main area MA may include four sides and four corners at which two sides extending in different directions are connected.

[0162] That is, the edge of the main area MA may have two sides extending in the first direction DR1 and opposite to each other and two sides extending in the second direction DR2 and opposite to each other.

[0163] The corners of the main area MA may have an arc shape or a right-angled vertex shape.

[0164] However, the shape of the main area MA according to the embodiment is not limited to Figure 4 , and may be a circle, an ellipse, or a polygon other than a quadrilateral.

[0165] Figure 6 is a diagram showing a method according to an embodiment of the present invention. Figure 5 Equivalent circuit diagram of the light-emitting pixel driver.

[0166] refer to Figure 6 The light-emitting pixel driver EPD of the circuit layer 120 may be electrically connected between the first power line VDL for transmitting the first power ELVDD and the light-emitting elements LE of the element layer 130. One of the light-emitting elements LE of the element layer 130 may be electrically connected between one of the light-emitting pixel drivers EPD of the circuit layer 120 and the second power line VSL for transmitting the second power ELVSS.

[0167] That is, the anode electrode of the light emitting element LE is electrically connected to the light emitting pixel driver EPD, and the cathode electrode of the light emitting element LE may be applied with the second power ELVSS lower than the first power ELVDD from the second power line VSL.

[0168] The capacitor Cel connected in parallel with the light emitting element LE is a parasitic capacitance between the anode electrode and the cathode electrode.

[0169] The circuit layer 120 may include a first power line VDL for transmitting the first power ELVDD, a gate initialization voltage line VGIL for transmitting the gate initialization voltage VGINT, and an anode initialization voltage line VAIL for transmitting the anode initialization voltage VAINT.

[0170] The circuit layer 120 may further include a scan write line GWL for transmitting a scan write signal GW, a scan initialization line GIL for transmitting a scan initialization signal GI, an emission control line ECL for transmitting an emission control signal EC, and a gate control line GCL for transmitting a gate control signal GC.

[0171] The scan write line GWL, the scan initialization line GIL, the emission control line ECL, and the gate control line GCL are electrically connected to the gate electrodes of the second to seventh transistors T2 to T7 , and thus, may be collectively referred to as gate lines hereinafter.

[0172] The circuit layer 120 may further include a gate driving circuit area GDRA (see FIG. 1 ) disposed in the non-display area NDA. Figure 4 ) and supplies signals to the gate driving circuit of the gate lines GWL, GIL, ECL and GCL.

[0173] One light emitting pixel driver EPD of the circuit layer 120 may include a first transistor T1 configured to generate a driving current for driving the light emitting element LE, two or more of transistors T2 to T7 electrically connected to the first transistor T1 , and at least one capacitor PC1 .

[0174] The first transistor T1 may be electrically connected between a first node N1 and a second node N2. The first node N1 is electrically connected to a first electrode (eg, source electrode) of the first transistor T1. The second node N2 is electrically connected to a second electrode (eg, drain electrode) of the first transistor T1.

[0175] The first node N1 may be electrically connected to the first power line VDL through the fifth transistor T5 .

[0176] The second node N2 may be electrically connected to the anode electrode of the light emitting element LE through the sixth transistor T6 .

[0177] The first capacitor PC1 may be electrically connected between the first power line VDL and a third node N3. The third node N3 is electrically connected to the gate electrode of the first transistor T1.

[0178] That is, the gate electrode of the first transistor T1 may be electrically connected to the first power line VDL through the first capacitor PC1 .

[0179] Accordingly, the potential of the gate electrode of the first transistor T1 may be maintained at the voltage charged in the first capacitor PC1 .

[0180] The second transistor T2 may be electrically connected between the data line DL and the first node N1 .

[0181] The second transistor T2 may be electrically connected between the first electrode of the first transistor T1 and the data line DL.

[0182] That is, the first electrode of the first transistor T1 may be electrically connected to the data line DL through the second transistor T2 .

[0183] The second transistor T2 may be turned on by the scan write signal GW of the scan write line GWL.

[0184] The fifth transistor T5 may be electrically connected between the first node N1 and the first power line VDL.

[0185] The sixth transistor T6 may be electrically connected between the second node N2 and a fourth node N4. The fourth node N4 is electrically connected to the anode electrode of the light emitting element LE.

[0186] That is, the fifth transistor T5 may be electrically connected between the first electrode of the first transistor T1 and the first power line VDL.

[0187] The sixth transistor T6 may be electrically connected between the second electrode of the first transistor T1 and the anode electrode of the light emitting element LE.

[0188] The fifth transistor T5 and the sixth transistor T6 may be turned on by the emission control signal EC of the emission control line ECL.

[0189] When the data signal Vdata of the data line DL is transmitted to the first electrode of the first transistor T1 through the turned-on second transistor T2 , a voltage difference between the gate electrode of the first transistor T1 and the first electrode of the first transistor T1 may be a voltage difference between the first power ELVDD and the data signal Vdata.

[0190] In this case, when the voltage difference between the gate electrode of the first transistor T1 and the first electrode of the first transistor T1 (i.e., the gate-source voltage difference) becomes greater than or equal to the threshold voltage, the first transistor T1 may be turned on, thereby generating a drain-source current of the first transistor T1 corresponding to the data signal Vdata.

[0191] Subsequently, when the fifth transistor T5 and the sixth transistor T6 are turned on, the first power line VDL, the first transistor T1, the light emitting element LE, and the second power line VSL can be connected in series. Accordingly, the drain-source current of the first transistor T1 corresponding to the data signal Vdata can be supplied as the driving current of the light emitting element LE.

[0192] Accordingly, the light emitting element LE may emit light having brightness corresponding to the data signal Vdata.

[0193] The third transistor T3 may be electrically connected between the second node N2 and the third node N3. That is, the third transistor T3 may be electrically connected between the gate electrode of the first transistor T1 and the second electrode of the first transistor T1.

[0194] The third transistor T3 may include a plurality of sub-transistors connected in series. For example, the third transistor T3 may include a first sub-transistor T31 and a second sub-transistor T32.

[0195] A first electrode of the first sub-transistor T31 may be connected to the gate electrode of the first transistor T1, a second electrode of the first sub-transistor T31 may be connected to the first electrode of the second sub-transistor T32, and a second electrode of the second sub-transistor T32 may be connected to the second electrode of the first transistor T1.

[0196] In this manner, it is possible to prevent the potential of the gate electrode of the first transistor T1 from changing due to leakage current caused by the third transistor T3 that is not turned on.

[0197] The first sub-transistor T31 and the second sub-transistor T32 may be turned on by the scan write signal GW of the scan write line GWL.

[0198] When the first sub-transistor T31 and the second sub-transistor T32 are turned on, a voltage difference between the second node N2 and the third node N3 may be initialized.

[0199] The fourth transistor T4 may be electrically connected between the gate initialization voltage line VGIL and the third node N3. That is, the fourth transistor T4 may be connected between the gate electrode of the first transistor T1 and the gate initialization voltage line VGIL.

[0200] The fourth transistor T4 may include a plurality of sub-transistors connected in series. For example, the fourth transistor T4 may include a third sub-transistor T41 and a fourth sub-transistor T42.

[0201] A first electrode of the third sub-transistor T41 may be connected to the gate electrode of the first transistor T1 , a second electrode of the third sub-transistor T41 may be connected to a first electrode of the fourth sub-transistor T42 , and a second electrode of the fourth sub-transistor T42 may be connected to the gate initialization voltage line VGIL.

[0202] In this manner, it is possible to prevent the potential of the gate electrode of the first transistor T1 from changing due to leakage current caused by the fourth transistor T4 that is not turned on.

[0203] The third sub-transistor T41 and the fourth sub-transistor T42 may be turned on by the scan initialization signal GI of the scan initialization line GIL.

[0204] When the third sub-transistor T41 and the fourth sub-transistor T42 are turned on, the potential of the third node N3 may be initialized to the gate initialization voltage VGINT.

[0205] The seventh transistor T7 may be electrically connected between the fourth node N4 and the anode initialization voltage line VAIL. In other words, the seventh transistor T7 may be electrically connected between the anode electrode of the light emitting element LE and the anode initialization voltage line VAIL.

[0206] The seventh transistor T7 may be turned on by the gate control signal GC of the gate control line GCL.

[0207] The potential of the fourth node N4 may be initialized to the anode initialization voltage VAINT through the turned-on seventh transistor T7 .

[0208] like Figure 6 As shown in , according to an embodiment, the first to seventh transistors T1 to T7 may be provided as P-type MOSFETs.

[0209] Figure 7 The diagram shows the Figure 6 sectional view of a light emitting element LE and a first transistor T1 and a sixth transistor T6 of a light emitting pixel driver EPD according to an embodiment of the present invention.

[0210] refer to Figure 7 The display panel 100 of the display device 10 according to the embodiment may include a substrate 110 , a circuit layer 120 on the substrate 110 , and an element layer 130 on the circuit layer 120 .

[0211] The display panel 100 of the display device 10 according to the embodiment may further include an encapsulation layer 140 on the element layer 130 , a touch sensor layer 150 on the encapsulation layer 140 , and a polarization layer 160 on the touch sensor layer 150 .

[0212] According to an embodiment, the substrate 110 may include a first supporting layer 111 , a barrier layer 112 disposed on the first supporting layer 111 , and a second supporting layer 113 disposed on the barrier layer 112 .

[0213] Each of the first and second supporting layers 111 and 113 may include an organic insulating material that can be easily provided with a thickness sufficient to buffer external foreign matter. In one example, each of the first and second supporting layers 111 and 113 may include polyimide (PI).

[0214] The barrier layer 112 may include an inorganic insulating material different from the materials of the first and second supporting layers 111 and 113 to prevent oxygen or moisture from penetrating through the substrate 110 .

[0215] The circuit layer 120 may include a first semiconductor layer arranged on the substrate 110, a first gate insulating layer 122 covering the first semiconductor layer, a first gate conductive layer arranged on the first gate insulating layer 122, a second gate insulating layer 123 covering the first gate conductive layer, a second gate conductive layer arranged on the second gate insulating layer 123, an interlayer insulating layer 124 arranged on the second gate conductive layer, a first source-drain conductive layer arranged on the interlayer insulating layer 124, a first planarizing layer 125 covering the first source-drain conductive layer, a second source-drain conductive layer arranged on the first planarizing layer 125, and a second planarizing layer 126 covering the second source-drain conductive layer.

[0216] According to an embodiment, an interlayer insulating layer 124 may be disposed on the second gate insulating layer 123 and cover the second gate conductive layer.

[0217] The circuit layer 120 may further include a buffer layer 121 covering the substrate 110 .

[0218] In this case, the first semiconductor layer may be disposed on the buffer layer 121 .

[0219] The circuit layer 120 may include light emitting pixel drivers EPD corresponding to the emission areas EA, respectively.

[0220] Each of the light emitting pixel drivers EPD may include a first transistor T1, a second transistor T2 to a seventh transistor T7 electrically connected to the first transistor T1 (see Figure 6 ) and at least one capacitor PC1 (see Figure 6 ).

[0221] The first semiconductor layer on the buffer layer 121 may include channel portions (e.g., channel portions CH1 and CH6) of the first to seventh transistors T1 to T7, first electrode portions (e.g., first electrode portions E11 and E16), and second electrode portions (e.g., second electrode portions E21 and E26).

[0222] That is, the channel portions CH1 and CH6 of the first and sixth transistors T1 and T6 , the first electrode portions E11 and E16 , and the second electrode portions E21 and E26 may be provided as a first semiconductor layer on the buffer layer 121 .

[0223] In the first and sixth transistors T1 and T6 , the first electrode portions E11 and E16 may be connected to one ends of the channel portions CH1 and CH6 , and the second electrode portions E21 and E26 may be connected to the other ends of the channel portions CH1 and CH6 .

[0224] The second electrode portion E21 of the first transistor T1 may be connected to the first electrode portion E16 of the sixth transistor T6 .

[0225] The first gate conductive layer on the first gate insulating layer 122 may include gate electrodes G1 and G6 of the first and sixth transistors T1 and T6 .

[0226] That is, the gate electrodes G1 and G6 of the first and sixth transistors T1 and T6 may be provided as a first gate conductive layer on the first gate insulating layer 122 .

[0227] In the first transistor T1 and the sixth transistor T6 , the gate electrodes G1 and G6 may overlap with the channel portions CH1 and CH6 , respectively.

[0228] exist Figure 6 In the light-emitting pixel driver EPD, the second transistor T2, the first sub-transistor T31, the second sub-transistor T32, the third sub-transistor T41, the fourth sub-transistor T42, the fifth transistor T5 and the seventh transistor T7 are provided as the same P-type MOSFET as the first transistor T1 and the sixth transistor T6, and therefore, a redundant description thereof will be omitted below.

[0229] The second gate conductive layer on the second gate insulating layer 123 may include a capacitor electrode CAE.

[0230] The capacitor electrode CAE may overlap with the gate electrode G1 of the first transistor T1 .

[0231] Accordingly, the first capacitor PC1 (see Figure 6 ) may be provided by an overlapping region between the capacitor electrode CAE and the gate electrode G1 of the first transistor T1.

[0232] The first source-drain conductive layer on the interlayer insulating layer 124 may include a first anode connection electrode ANCE1 .

[0233] The first anode connection electrode ANCE1 may be electrically connected to the second electrode portion E26 of the sixth transistor T6 through the first anode connection hole ANCH1 .

[0234] The second source-drain conductive layer on the first planarization layer 125 may include a second anode connection electrode ANCE2 .

[0235] The second anode connection electrode ANCE2 may be electrically connected to the first anode connection electrode ANCE1 through the second anode connection hole ANCH2 .

[0236] The anode electrode 131 of the element layer 130 may be disposed on the second planarization layer 126 and may be electrically connected to the second anode connection electrode ANCE2 through the third anode connection hole ANCH3 .

[0237] Accordingly, the anode electrode 131 may be electrically connected to the second electrode portion E26 of the sixth transistor T6 through the first and second anode connection electrodes ANCE1 and ANCE2 .

[0238] The element layer 130 on the circuit layer 120 may include light emitting elements LE respectively disposed in the emission areas EA1 , EA2 , and EA3 .

[0239] Each of the light emitting elements LE may include a structure in which a light emitting layer 133 is provided between an anode electrode 131 and a cathode electrode 134 facing each other.

[0240] In an embodiment, each of the light emitting elements LE may further include a first common layer 135 disposed between the anode electrode 131 and the light emitting layer 133 , and a second common layer 136 disposed between the light emitting layer 133 and the cathode electrode 134 .

[0241] That is, according to an embodiment, the element layer 130 may include an anode electrode 131 respectively arranged in the emission area EA, a pixel defining layer 132 arranged in the non-emission area NEA and covering the edge of the anode electrode 131, a spacer layer 132' arranged on a portion of the pixel defining layer 132, a first common layer 135 respectively arranged on the anode electrode 131, a light emitting layer 133 respectively arranged on the first common layer 135, a second common layer 136 arranged on the light emitting layer 133, the pixel defining layer 132 and the spacer layer 132', and a cathode electrode 134 arranged on the second common layer 136.

[0242] The encapsulation layer 140 may be disposed on the circuit layer 120 and cover the element layer 130 .

[0243] The encapsulation layer 140 is used to prevent oxygen or moisture from penetrating into the element layer 130 , and is used to reduce electrical impact or physical impact on the circuit layer 120 and the element layer 130 .

[0244] The encapsulation layer 140 may include a first encapsulation layer 141 that is arranged on the circuit layer 120, covers the component layer 130 and includes an inorganic insulating material, a second encapsulation layer 142 that is arranged on the first encapsulation layer 141, overlaps with the component layer 130 and includes an organic insulating material, and a third encapsulation layer 143 that is arranged on the first encapsulation layer 141, covers the second encapsulation layer 142 and includes an inorganic insulating material.

[0245] The touch sensor layer 150 may be disposed on the encapsulation layer 140 .

[0246] The touch sensor layer 150 may include driving electrodes TE and sensing electrodes RE spaced apart from each other, and bridge electrodes BE electrically connecting adjacent driving electrodes TE to each other.

[0247] The touch sensor layer 150 may include a touch buffer layer 151 arranged on the encapsulation layer 140, a first touch conductive layer arranged on the touch buffer layer 151, a touch interlayer insulating layer 152 covering the first touch conductive layer, a second touch conductive layer arranged on the touch interlayer insulating layer 152, and a touch planarization layer 153 covering the second touch conductive layer.

[0248] The bridging electrode BE may be provided in a different touch conductive layer from the driving electrode TE and the sensing electrode RE.

[0249] As an example, the bridge electrode BE may be provided as a first touch conductive layer on the touch buffer layer 151 .

[0250] The driving electrodes TE and the sensing electrodes RE may be provided as a second touch conductive layer on the touch interlayer insulating layer 152 .

[0251] The driving electrode TE may be electrically connected to the bridge electrode BE through the touch electrode connection hole TCNT penetrating the touch interlayer insulating layer 152 .

[0252] The touch buffer layer 151 may include an inorganic insulating material.

[0253] According to an embodiment, each of the touch interlayer insulating layer 152 and the touch planarizing layer 153 may include an organic insulating material.

[0254] In an embodiment, the touch interlayer insulating layer 152 may include an inorganic insulating material.

[0255] The polarizing layer 160 may be disposed on the touch sensor layer 150 .

[0256] Figure 6 The light-emitting pixel driver EPD includes first to seventh transistors T1 to T7 provided as P-type MOSFETs. However, this is merely an example, and some of the first to seventh transistors T1 to T7 may be provided as N-type MOSFETs. For example, the third transistor T3 and the fourth transistor T4 may be provided as N-type MOSFETs.

[0257] Figure 8 is a diagram showing a method according to an embodiment of the present invention. Figure 5 Equivalent circuit diagram of the light-emitting pixel driver.

[0258] Except that the third transistor T3 and the fourth transistor T4 among the first to seventh transistors T1 to T7 of the light emitting pixel driver EPD are provided as N-type MOSFETs, Figure 8 The circuit layer 120 of the display panel 100 of the embodiment Figure 6The circuit layer 120 of the embodiment shown in FIG. 1 is substantially the same, and therefore, a redundant description thereof will be omitted below.

[0259] according to Figure 8 In the embodiment of the present invention, the third transistor T3 may be electrically connected between the second node N2 and the third node N3. That is, the third transistor T3 may be electrically connected between the gate electrode of the first transistor T1 and the second electrode of the first transistor T1.

[0260] Since the third transistor T3 is provided as an N-type MOSFET, it can be turned on by the gate control signal GC from the gate control line GCL.

[0261] By the turned-on third transistor T3 , a voltage difference between the second node N2 and the third node N3 may be initialized.

[0262] The fourth transistor T4 may be electrically connected between the gate initialization voltage line VGIL and the third node N3. That is, the fourth transistor T4 may be connected between the gate electrode of the first transistor T1 and the gate initialization voltage line VGIL.

[0263] The fourth transistor T4 may be turned on by the scan initialization signal GI of the scan initialization line GIL.

[0264] The potential of the third node N3 may be initialized by the turned-on fourth transistor T4.

[0265] Since the fourth transistor T4 is provided as an N-type MOSFET, the seventh transistor T7 may be turned on by the bias control signal GB of the bias control line GBL instead of the scan initialization signal GI of the scan initialization line GIL.

[0266] Since the bias control line GBL is electrically connected to the gate electrode of the seventh transistor T7 , it may be collectively referred to as a gate line GL hereinafter along with the scan write line GWL, the scan initialization line GIL, the emission control line ECL, and the gate control line GCL.

[0267] Figure 9 It shows that according to Figure 8 sectional view of a light emitting element LE and a first transistor T1, a second transistor T2, a fourth transistor T4 and a sixth transistor T6 of a light emitting pixel driver EPD according to an embodiment of the present invention.

[0268] In addition to further comprising an auxiliary interlayer insulating layer 127, a third gate insulating layer 128, and a second semiconductor layer and a third gate conductive layer for providing an N-type MOSFET, according to Figure 9 The circuit layer 120 of the display panel 100 of the embodiment shown in FIG. Figure 7The circuit layer 120 of the embodiment shown in FIG. 1 is substantially the same, and therefore, a redundant description thereof will be omitted below.

[0269] according to Figure 9 In an embodiment, the circuit layer 120 may further include an auxiliary interlayer insulating layer 127 covering the second gate conductive layer, a second semiconductor layer arranged on the auxiliary interlayer insulating layer 127, a third gate insulating layer 128 covering the second semiconductor layer, and a third gate conductive layer arranged on the third gate insulating layer 128 and covered by the interlayer insulating layer 124.

[0270] In addition, according to Figure 9 In the embodiment, the circuit layer 120 may further include a barrier layer 129 disposed on the substrate 110 and a first light blocking layer LB1 disposed on the barrier layer 129 and covered by the buffer layer 121 .

[0271] In other words, according to Figure 9 In an embodiment of the present invention, the circuit layer 120 may include a barrier layer 129 disposed on the substrate 110, a first light blocking layer LB1 disposed on the barrier layer 129, a buffer layer 121 covering the first light blocking layer LB1, a first semiconductor layer disposed on the buffer layer 121, a first gate insulating layer 122 covering the first semiconductor layer, a first gate conductive layer disposed on the first gate insulating layer 122, a second gate insulating layer 123 covering the first gate conductive layer, a second gate conductive layer disposed on the second gate insulating layer 123, and an auxiliary interlayer insulating layer covering the second gate conductive layer. an insulating layer 127, a second semiconductor layer arranged on the auxiliary interlayer insulating layer 127, a third gate insulating layer 128 covering the second semiconductor layer, a third gate conductive layer arranged on the third gate insulating layer 128 and covered by the interlayer insulating layer 124, an interlayer insulating layer 124 covering the third gate conductive layer, a first source-drain conductive layer arranged on the interlayer insulating layer 124, a first planarizing layer 125 covering the first source-drain conductive layer, a second source-drain conductive layer arranged on the first planarizing layer 125, and a second planarizing layer 126 covering the second source-drain conductive layer.

[0272] The first semiconductor layer on the buffer layer 121 may include a first transistor T1, a second transistor T2, a fifth transistor T5 (see FIG. Figure 8 ), the sixth transistor T6 and the seventh transistor T7 (see Figure 8 )'s channel portions (e.g., channel portions CH1, CH2, and CH6), first electrode portions (e.g., first electrode portions E11, E12, and E16), and second electrode portions (e.g., second electrode portions E21, E22, and E26).

[0273] The first gate conductive layer on the first gate insulating layer 122 may include a first transistor T1, a second transistor T2, a fifth transistor T5 (see FIG. 1 ) provided as a P-type MOSFET. Figure 8 ), the sixth transistor T6 and the seventh transistor T7 (see Figure 8 ) of the gate electrodes (e.g., gate electrodes G1, G2, and G6).

[0274] Since the fifth transistor T5 and the seventh transistor T7 have the same structure as those of the first transistor T1 , the second transistor T2 , and the sixth transistor T6 , redundant description will be omitted below.

[0275] In the first transistor T1 , the second transistor T2 , and the sixth transistor T6 , the channel portions CH1 , CH2 , and CH6 may overlap with the gate electrodes G1 , G2 , and G6 .

[0276] A channel portion CH1 of the first transistor T1 may overlap the first light blocking layer LB1 under the buffer layer 121 .

[0277] In the first, second and sixth transistors T1, T2 and T6, first electrode portions E11, E12 and E16 may be connected to one ends of the channel portions CH1, CH2 and CH6, and second electrode portions E21, E22 and E26 may be connected to the other ends of the channel portions CH1, CH2 and CH6.

[0278] The first electrode portion E11 of the first transistor T1 may be connected to the second electrode portion E22 of the second transistor T2 .

[0279] The second electrode portion E21 of the first transistor T1 may be connected to the first electrode portion E16 of the sixth transistor T6 .

[0280] The second gate conductive layer on the second gate insulating layer 123 may include a capacitor electrode CAE and a second light blocking layer LB2 .

[0281] The second semiconductor layer on the auxiliary interlayer insulating layer 127 may include a third transistor T3 provided as an N-type MOSFET (see Figure 8 ) and a channel portion (e.g., channel portion CH4), a first electrode portion (e.g., first electrode portion E14), and a second electrode portion (e.g., second electrode portion E24) of each of the first and fourth transistors T4.

[0282] The third gate conductive layer on the third gate insulating layer 128 may include a third transistor T3 provided as an N-type MOSFET (see Figure 8 ) and a gate electrode (eg, gate electrode G4) of each of the fourth transistors T4.

[0283] In the third transistor T3 (see Figure 8 ) and each of the fourth transistor T4, a channel portion (eg, channel portion CH4) may overlap the second light blocking layer LB2 under the auxiliary interlayer insulating layer 127.

[0284] A channel portion CH4 of the fourth transistor T4 may overlap with the gate electrode G4 of the fourth transistor T4 .

[0285] The first electrode portion E14 of the fourth transistor T4 may be connected to one end of the channel portion CH4 of the fourth transistor T4 , and the second electrode portion E24 of the fourth transistor T4 may be connected to the other end of the channel portion CH4 of the fourth transistor T4 .

[0286] Since the third transistor T3 and the fourth transistor T4 are provided as the same N-type MOSFET, redundant description thereof will be omitted below.

[0287] The first source-drain conductive layer on the interlayer insulating layer 124 may include a first anode connection electrode ANCE1 , a data link electrode DCE, a gate initialization voltage line VGIL, and a node auxiliary connection electrode NACE.

[0288] The second source-drain conductive layer on the first planarization layer 125 may include a second anode connection electrode ANCE2 and a data line DL.

[0289] The data link electrode DCE may be electrically connected to the first electrode portion E12 of the second transistor T2 through the first data link hole DCH1.

[0290] The data line DL may be electrically connected to the data link electrode DCE through the second data connection hole DCH2 .

[0291] Accordingly, the data line DL may be electrically connected to the first electrode portion E12 of the second transistor T2 through the data connection electrode DCE.

[0292] The gate initialization voltage line VGIL may be electrically connected to the first electrode portion E14 of the fourth transistor T4 through the gate initialization voltage connection hole VGCH.

[0293] The node auxiliary connection electrode NACE may be electrically connected to the second electrode portion E24 of the fourth transistor T4 through the node auxiliary connection hole NACH.

[0294] according to Figure 9 The element layer 130, the encapsulation layer 140, the touch sensor layer 150 and the polarization layer 160 of the display panel 100 of the embodiment shown in FIG. Figure 7 Those layers of the embodiment shown in are substantially the same, and therefore, redundant descriptions thereof will be omitted below.

[0295] The display panel 100 according to the embodiment is deformed so that the peripheral display area PSA at the edge of the display area DA is bent. As a result, bending stress is applied to the peripheral display area PSA. In particular, relatively excessive bending stress may be applied to the corner areas CS1, CS2, CS3, and CS4, which are double curvature regions of the peripheral display area PSA, thereby easily causing defects.

[0296] To prevent this, according to an embodiment, the display panel 100 may further include a strain adjusting portion STR (see Figure 10 ), the strain adjustment portion STR overlaps at least with the corner regions CS1, CS2, CS3, and CS4 of the peripheral display area PSA.

[0297] Figure 10 is a plan view illustrating a display panel 100 according to an embodiment. Figure 11 According to the embodiment Figure 10 A cross-sectional view taken along line D-D'. Figure 12 According to the embodiment Figure 10 A cross-sectional view taken along line EE'.

[0298] refer to Figure 10 The display panel 100 of the display device 10 according to the embodiment further includes a strain adjustment portion STR, which overlaps with corner areas CS1, CS2, CS3 and CS4 adjacent to the corners of the edge of the substrate 110 in the peripheral display area PSA and is spaced apart from the edge of the substrate 110.

[0299] The strain adjustment portion STR may further overlap some portions of the side regions SS1 , SS2 , SS3 , and SS4 of the peripheral display area PSA, which are adjacent to the corner regions CS1 , CS2 , CS3 , and CS4 .

[0300] according to Figure 10 In an embodiment, the strain adjustment portion STR may include a first strain adjustment portion STR1, a second strain adjustment portion STR2, a third strain adjustment portion STR3, and a fourth strain adjustment portion STR4 that overlap with the first corner region CS1, the second corner region CS2, the third corner region CS3, and the fourth corner region CS4, respectively.

[0301] refer to Figure 11 and Figure 12 , the substrate 110 may have a first thickness TH1 in a portion not overlapping the strain adjustment portion STR. In addition, due to the strain adjustment portion STR, a portion of the substrate 110 overlapping the strain adjustment portion STR may have a second thickness TH2 smaller than the first thickness TH1.

[0302] In one example, the second thickness TH2 may be greater than or equal to 50% and less than or equal to 85% of the first thickness TH1 .

[0303] The substrate 110 may include a first supporting layer 111 , a barrier layer 112 disposed on the first supporting layer 111 , and a second supporting layer 113 disposed on the barrier layer 112 .

[0304] The strain adjustment portion STR may include a first groove GR1 penetrating at least a portion of the first supporting layer 111 and a second groove GR2 overlapping the first groove GR1 and penetrating a portion of the second supporting layer 113 .

[0305] Since the circuit layer 120 is disposed on the second supporting layer 113, the side surface of the second groove GR2 may have a relatively gentle inclination angle θ relative to the plane of the substrate 110 (i.e., relative to the plane defined by the first direction DR1 and the second direction DR2). In one example, the inclination angle θ of the side surface of the second groove GR2 may be greater than or equal to 5° and less than or equal to 15°.

[0306] In this manner, defects such as peeling and disconnection in the circuit layer 120 due to the level difference of the second groove GR2 may be prevented.

[0307] The second supporting layer 113 may be provided with a third thickness TH3 in a portion not overlapping the strain adjustment portion STR.

[0308] A portion of the second supporting layer 113 overlapping the bottom surface of the second groove GR2 has a variation thickness MTH3 that is smaller than the third thickness TH3 .

[0309] A portion of the second supporting layer 113 overlapping the side surface of the second groove GR2 may have a thickness gradually varying between a third thickness TH3 and a variation thickness MTH3 .

[0310] The varied thickness MTH3 may be greater than or equal to 50% and less than or equal to 85% of the third thickness TH3.

[0311] If the variation thickness MTH3 is less than 50% of the third thickness TH3, the circuit layer 120 and the element layer 130 on the substrate 110 may be difficult to be stably supported by the strain adjustment portion STR, resulting in degradation of image quality of the corner regions CS1, CS2, CS3, and CS4.

[0312] In one example, the variation thickness MTH3 may be 3 μm or more.

[0313] Furthermore, if the variation thickness MTH3 is greater than 85% of the third thickness TH3 , the strain improvement of the substrate 110 by the strain adjustment portion STR may be insignificant, and thus it may be difficult to achieve the effect of reducing defects caused by excessive bending stress in the double curvature region.

[0314] The first supporting layer 111 may have a fourth thickness TH4 greater than the third thickness TH3 in a portion not overlapping the strain adjustment portion STR.

[0315] According to an embodiment, the first groove GR1 may completely penetrate the first supporting layer 111 and expose the barrier layer 112 .

[0316] like Figure 10 and Figure 11 As shown in FIG, according to an embodiment, the strain adjustment portion STR may limitedly overlap only a portion including the corner regions CS1, CS2, CS3, and CS4 as double curvature regions in the peripheral display area PSA.

[0317] Accordingly, in an embodiment, the strain adjustment portion STR may be spaced apart from the gate driving circuit area GDRA of the non-display area NDA.

[0318] As described above, according to the embodiment, the display panel 100 includes the strain adjustment portion STR overlapping a portion including the corner regions CS1 , CS2 , CS3 , and CS4 as double curvature regions in the peripheral display area PSA.

[0319] Because the strain adjustment portion STR includes a first groove GR1 that penetrates at least a portion of the first supporting layer 111 and a second groove GR2 that penetrates a portion of the second supporting layer 113, the portion of the substrate 110 that overlaps with the strain adjustment portion STR can have a second thickness TH2 that is smaller than the first thickness TH1 of the portion of the substrate 110 that does not overlap with the strain adjustment portion STR, thereby having a higher strain. Accordingly, the incidence of defects caused by bending stress in the double curvature region can be reduced.

[0320] like Figure 10 and Figure 12 As shown in FIG, according to an embodiment, the strain adjustment portion STR is spaced apart from the edge of the substrate 110.

[0321] A minimum value of a separation distance GAP between the strain adjustment portion STR and the edge of the substrate 110 may be 150 μm to 180 μm.

[0322] That is, the strain adjustment portion STR may be spaced apart from the edge of the substrate 110 by more than 150 μm.

[0323] In other words, since the strain adjustment portion STR does not extend to the edge of the substrate 110, the edge of the substrate 110 can be maintained at the first thickness TH1 in the same manner as the front display area FSA. Accordingly, even if the display panel 100 further includes the strain adjustment portion STR, the tensile stress at the edge of the substrate 110 can be maintained, thereby preventing a wrap-around defect at the edge of the substrate 110.

[0324] Figure 13 、 Figure 14 、 Figure 15 、 Figure 16 and Figure 17 is a process diagram illustrating steps of a process of providing a strain adjustment portion according to an embodiment.

[0325] refer to Figure 13 、 Figure 14 、 Figure 15 、 Figure 16 and Figure 17 The process of providing the strain adjustment portion STR may include: providing a first mask layer MSL1 (see Figure 13 ); through the first opening portion OPP1 of the first mask layer MSL1 (see Figure 13 ) partially etches the second supporting layer 113 to form a preliminary groove PGR; ashes the first mask layer MSL1 to prepare a second mask layer MSL2; partially etches the second supporting layer 113 through the first opening portion OPP1 and the second opening portion OPP2 of the second mask layer MSL2 to form a second groove GR2; and removes the second mask layer MSL2 and partially etches the first supporting layer 111 to form a first groove GR1.

[0326] refer to Figure 13 In the step of setting the first mask layer MSL1, the first mask layer MSL1 may be prepared by setting a mask material layer on the second support layer 113 of the substrate 110 and developing the mask material layer differently exposed through the halftone exposure mask EXMS.

[0327] The half-tone exposure mask EXMS may include a light-blocking portion LBL1 that blocks most of the light, a semi-transmitting portion LBL2 that blocks a portion of the light, and a transmitting portion TR that transmits the light.

[0328] The transmission portion TR may overlap a portion of the peripheral display area PSA, and the semi-transmission portion LBL2 may be disposed around the transmission portion TR. The light blocking portion LBL1 may be disposed in a remaining portion except for the transmission portion TR and the semi-transmission portion LBL2.

[0329] The first mask layer MSL1 may include a first blocking portion BLP1 facing the light blocking portion LBL1 and maintained at the first mask thickness MSTH1, a second blocking portion BLP2 facing the semi-transmitting portion LBL2 and set with a second mask thickness MSTH2 less than the first mask thickness MSTH1, and a first opening portion OPP1 facing the transmitting portion TR and exposing the second supporting layer 113.

[0330] refer to Figure 14 In the step of forming the preliminary groove PGR, the preliminary groove PGR may be formed by partially etching a portion of the second supporting layer 113 exposed through the first opening portion OPP1 of the first mask layer MSL1.

[0331] refer to Figure 15 In the step of preparing the second mask layer MSL2, an ashing process may be performed until the first mask layer MSL1 is removed (see Figure 14 ) up to the second blocking portion BLP2 to prepare the second mask layer MSL2.

[0332] The second mask layer MSL2 may include a first opening portion OPP1, a third blocking portion BLP3 formed by thinning the first blocking portion BLP1 of the first mask layer MSL1 through an ashing process, and a second opening portion OPP2 formed by removing the second blocking portion BLP2 of the first mask layer MSL1 through an ashing process.

[0333] refer to Figure 16 In the step of forming the second groove GR2 , the second groove GR2 may be formed by partially etching portions of the second supporting layer 113 exposed through the first and second opening portions OPP1 and OPP2 of the second mask layer MSL2 .

[0334] In the second opening portion OPP2, the second supporting layer 113 may be easily exposed to the etching material at a position closer to the preliminary groove PGR formed by the first opening portion OPP1, but may be difficult to be exposed to the etching material at a position closer to the third blocking portion BLP3, so that the side surface of the second groove GR2 can have a gentle inclination angle.

[0335] The bottom surface of the second groove GR2 may be the preliminary groove PGR (see Figure 14 ) variant.

[0336] refer to Figure 17 In the step of forming the first groove GR1 , the first groove GR1 may be formed by partially irradiating a laser LASER to a portion of the first supporting layer 111 overlapping a portion of the peripheral display area PSA to remove a portion of the first supporting layer 111 .

[0337] Therefore, a strain adjustment portion STR including the first groove GR1 and the second groove GR2 may be provided.

[0338] In the step of forming the first groove GR1, the amount of the first supporting layer 111 removed may vary depending on the irradiation amount of the laser. That is, the first groove GR1 may not completely penetrate a portion of the first supporting layer 111, and a residual portion of the first supporting layer 111 may remain in the first groove GR1.

[0339] Figure 18 According to the embodiment Figure 10 A cross-sectional view taken along line D-D'.

[0340] like Figure 18 As shown in FIG, except that the first groove GR1 of the strain adjustment portion STR does not completely penetrate the first supporting layer 111, the display panel 100 of the display device 10 according to the embodiment is Figure 10 、 Figure 11 and Figure 12 The display panel 100 of the embodiment shown in FIG. 1 is substantially the same, and thus, a redundant description thereof will be omitted below.

[0341] The first supporting layer 111 may be provided with a fourth thickness TH4 in a portion not overlapping the strain adjustment portion STR, the fourth thickness TH4 being greater than a third thickness TH3 of the second supporting layer 113 in a portion not overlapping the strain adjustment portion STR.

[0342] When the first supporting layer 111 remains in the first groove GR1 , a thickness MTH4 of a portion of the first supporting layer 111 overlapping the first groove GR1 may be 10% or less of the fourth thickness TH4 .

[0343] When the thickness MTH4 of the portion of the first supporting layer 111 overlapping the first groove GR1 is greater than 10% of the fourth thickness TH4, the strain improvement of the strain adjustment portion STR on the substrate 110 may be negligible, making it difficult to achieve the effect of reducing defects caused by excessive bending stress in the double curvature region.

[0344] according to Figure 18 In the embodiment, since the first supporting layer 111 remains in the first groove GR1, the barrier layer 112 can be protected from laser irradiation.

[0345] Figure 19 is a plan view illustrating a display panel 100 according to an embodiment. Figure 20 It is along Figure 19 A cross-sectional view taken along line FF'.

[0346] Except that the strain adjustment portion STR further overlaps with some portions of the non-display area NDA and adjacent to the corner regions CS1, CS2, CS3, and CS4, according to Figure 19 and Figure 20 The display panel 100 of the display device 10 of the embodiment shown in FIG. Figure 10 、 Figure 11 、 Figure 12 and Figure 18 The display panel 100 of the embodiment shown in FIG. 1 is substantially the same, and thus, a redundant description thereof will be omitted below.

[0347] The gate driving circuit area GDRA of the non-display area NDA is disposed adjacent to the display area DA. Therefore, when the strain adjustment portion STR extends into a portion of the non-display area NDA, the strain adjustment portion STR may overlap a portion of the gate driving circuit area GDRA.

[0348] Furthermore, even when the strain adjustment portion STR extends into a portion of the non-display area NDA, the strain adjustment portion STR is spaced apart from the edge of the substrate 110. That is, a minimum value of a separation distance GAP between the strain adjustment portion STR and the edge of the substrate 110 may be 150 μm to 180 μm.

[0349] As described above, according to Figure 19 and Figure 20 In the embodiment shown in FIG, the strain adjustment portion STR overlaps not only with the corner regions CS1, CS2, CS3, and CS4, but also with portions of the non-display area NDA adjacent to the corner regions CS1, CS2, CS3, and CS4. Accordingly, even when the influence of the bending stress in the double curvature region extends to portions of the non-display area NDA adjacent to the corner regions CS1, CS2, CS3, and CS4, which are the double curvature regions, the bending stress can be reduced by the strain adjustment portion STR, and the incidence of defects caused by the bending stress can be reduced.

[0350] Figure 21 、 Figure 22 、 Figure 23 and Figure 24 is a plan view showing a display panel 100 according to an embodiment.

[0351] In addition to the strain adjustment portion STR further overlapping with the side regions SS1, SS2, SS3 and SS4, according to Figure 21 The display panel 100 of the display device 10 of the embodiment shown in FIG. Figure 10 、 Figure 11 、 Figure 12 and Figure 18The display panel 100 of the embodiment shown in FIG. 1 is substantially the same, and thus, a redundant description thereof will be omitted below.

[0352] Since the peripheral display area PSA is deformed toward the bracket 200 (see Figure 2 ) is a curved shape, so bending stress may be applied.

[0353] The strain adjustment portion STR may be provided in a single closed curve shape overlapping the peripheral display area PSA.

[0354] Accordingly, when the strain adjustment portion STR completely overlaps the peripheral display area PSA including the corner regions CS1 , CS2 , CS3 , and CS4 and the side regions SS1 , SS2 , SS3 , and SS4 , the occurrence rate of defects due to bending stress may be further reduced.

[0355] Except that the strain adjustment portion STR further overlaps with some portions of the front display area FSA and adjacent to the corner regions CS1, CS2, CS3, and CS4, according to Figure 22 The display panel 100 of the display device 10 of the embodiment shown in FIG. Figure 21 The display panel 100 of the embodiment shown in FIG. 1 is substantially the same, and thus, a redundant description thereof will be omitted below.

[0356] The bending stress in the double curvature region may also be applied to portions of the front display area FSA adjacent to the corner regions CS1, CS2, CS3, and CS4.

[0357] according to Figure 22 In the embodiment shown in FIG, the strain adjustment portion STR overlaps not only the peripheral display area PSA deformed into a bent shape, but also overlaps portions of the front display area FSA adjacent to the corner regions CS1, CS2, CS3, and CS4. Accordingly, even when the influence of the bending stress in the double curvature region extends to a portion of the front display area FSA, the bending stress can be reduced by the strain adjustment portion STR, and the incidence of defects caused by the bending stress can be reduced.

[0358] Except that the strain adjustment portion STR further overlaps with a portion of the non-display area NDA adjacent to the peripheral display area PSA, according to Figure 23 The display panel 100 of the display device 10 of the embodiment shown in FIG. Figure 21 The display panel 100 of the embodiment shown in FIG. 1 is substantially the same, and thus, a redundant description thereof will be omitted below.

[0359] according to Figure 23In the embodiment shown in FIG, the strain adjustment portion STR not only overlaps the peripheral display area PSA deformed into the bent shape, but also overlaps a portion of the non-display area NDA adjacent to the peripheral display area PSA.

[0360] In this case, the gate driving circuit area GDRA of the non-display area NDA may completely overlap the strain adjustment portion STR.

[0361] In this manner, even when the bending stress in the peripheral display area PSA extends to the non-display area NDA, the occurrence rate of defects due to the bending stress can be further reduced.

[0362] Except that the strain adjustment portion STR further overlaps with some portions of the front display area FSA adjacent to the corner regions CS1, CS2, CS3, and CS4, Figure 24 The display panel 100 of the display device 10 shown in FIG. Figure 23 The display panel 100 of the embodiment shown in FIG. 1 is substantially the same, and thus, a redundant description thereof will be omitted below.

[0363] In this way, even when the influence of the bending stress in the double curvature region extends to a portion of the front display area FSA, the bending stress can be reduced by the strain adjustment portion STR, and the occurrence rate of defects due to the bending stress can be reduced.

[0364] However, the effects of the present disclosure are not limited to the effects described herein. The above and other effects of the present disclosure will become more apparent to those skilled in the art by referring to the claims.

Claims

1. A display device, comprising: A display panel emits light for image display. The display panel includes a substrate, a circuit layer provided on the substrate, and a component layer provided on the circuit layer. The main area of ​​the substrate includes a display area in which an emission area is arranged and a non-display area provided around the display area, The display area includes a front display area and a peripheral display area provided around the front display area and having a curved shape, The display panel further includes a strain adjustment portion that overlaps a corner region of the peripheral display area adjacent to a corner of an edge of the substrate and is spaced apart from the edge of the substrate, the substrate having a first thickness in a portion not overlapping the strain adjustment portion, and Due to the strain adjustment portion, a portion of the substrate overlapping the strain adjustment portion has a second thickness that is smaller than the first thickness.

2. The display device according to claim 1, wherein The substrate comprises: a first supporting layer; a barrier layer disposed on the first supporting layer; and a second supporting layer provided with a third thickness on the barrier layer in a portion not overlapping with the strain adjustment portion, Wherein, the strain adjustment part includes: a first groove penetrating at least a portion of the first supporting layer; and The second groove overlaps with the first groove and penetrates a portion of the second supporting layer.

3. The display device according to claim 2, wherein: An inclination angle of a side surface of the second groove relative to a plane of the substrate is greater than or equal to 5° and less than or equal to 15°.

4. The display device according to claim 2, wherein A thickness of a portion of the second supporting layer overlapping the bottom surface of the second groove is greater than or equal to 50% and less than or equal to 85% of the third thickness.

5. The display device according to claim 4, wherein The thickness of the portion of the second supporting layer overlapping the bottom surface of the second groove is 3 μm or greater. The display device according to claim 2 , wherein: The first supporting layer has a fourth thickness greater than the third thickness in a portion not overlapping the strain adjustment portion, and A thickness of a portion of the first supporting layer overlapping the first groove is less than 10% of the fourth thickness.

7. The display device according to claim 2, wherein: A minimum value of a separation distance between the strain adjustment portion and the edge of the substrate is 150 μm to 180 μm.

8. The display device according to claim 7, wherein: The peripheral display area further includes a side area parallel to an edge side of the substrate, and The strain adjustment portion further overlaps portions of the side region and adjacent to the corner region.

9. The display device according to claim 8, wherein The strain adjustment portion further overlaps portions of the non-display area adjacent to the corner area.

10. The display device according to claim 7, wherein: The peripheral display area further includes a side area parallel to an edge side of the substrate, and The strain modulation portion further overlaps the side region.

11. The display device according to claim 10, wherein: The strain adjustment portion further overlaps portions of the front display area adjacent to the corner area.

12. The display device according to claim 10, wherein: The strain adjustment portion further overlaps a portion of the non-display area adjacent to the peripheral display area.

13. The display device according to claim 12, wherein: The strain adjustment portion further overlaps portions of the front display area adjacent to the corner area.

14. The display device according to claim 2, wherein: The front display area includes a first side and a second side extending in a first direction and facing each other, and a third side and a fourth side extending in a second direction intersecting the first direction and facing each other. The peripheral display area further includes: The first side region, the second side region, the third side region and the fourth side region are in contact with the first side, the second side, the third side and the fourth side of the front display region, respectively, and The corner area includes: a first corner region contacting a vertex at which the first side and the third side intersect and disposed between the first side region and the third side region; a second corner region in contact with a vertex at which the second side and the third side intersect and disposed between the second side region and the third side region; a third corner region contacting the vertex at which the second side and the fourth side meet and disposed between the second side region and the fourth side region; and a fourth corner region contacting a vertex at which the first side and the fourth side intersect and disposed between the first side region and the fourth side region, Wherein, the strain adjustment portion overlaps with the first corner area, the second corner area, the third corner area and the fourth corner area.

15. The display device according to any one of claims 2 to 14, further comprising: a bracket, supporting the display panel; as well as a cover window disposed on the display panel and coupled to the bracket, Wherein, the peripheral display area is bent toward the bracket.

16. A display device comprising: a display panel emitting light for image display; a bracket, supporting the display panel; as well as a cover window disposed on the display panel and coupled to the bracket, The display panel includes a substrate, a circuit layer provided on the substrate, and a component layer provided on the circuit layer. The main area of ​​the substrate includes a display area in which an emission area is arranged and a non-display area provided around the display area, The display area includes a front display area and a peripheral display area provided around the front display area and having a shape bent toward the bracket, The display panel further includes a strain adjustment portion that overlaps a corner region of the peripheral display area adjacent to a corner of an edge of the substrate and is spaced apart from the edge of the substrate, the substrate having a first thickness in a portion not overlapping the strain adjustment portion, and Due to the strain adjustment portion, a portion of the substrate overlapping the strain adjustment portion has a second thickness that is smaller than the first thickness, Wherein, the substrate comprises: a first supporting layer; a barrier layer disposed on the first supporting layer; and a second supporting layer, disposed on the barrier layer, Wherein, the strain adjustment part includes: a first groove penetrating at least a portion of the first supporting layer; and The second groove overlaps with the first groove and penetrates a portion of the second supporting layer.

17. The display device according to claim 16, wherein: the second supporting layer is provided with a third thickness in a portion not overlapping with the strain adjustment portion, The first supporting layer is provided with a fourth thickness greater than the third thickness in a portion not overlapping with the strain adjustment portion, The thickness of a portion of the second supporting layer overlapping the bottom surface of the second groove is greater than or equal to 50% of the third thickness and less than or equal to 85% of the third thickness, and A thickness of a portion of the first supporting layer overlapping the first groove is less than 10% of the fourth thickness.

18. The display device according to claim 17, wherein: A minimum value of a separation distance between the strain adjustment portion and the edge of the substrate is 150 μm to 180 μm.

19. The display device according to claim 18, wherein: The peripheral display area further includes a side area parallel to an edge side of the substrate, and The strain adjustment portion further overlaps at least some portions of the side regions adjacent to the corner regions.

20. The display device according to claim 19, wherein The strain adjustment portion further overlaps at least some portions of the non-display area adjacent to the corner area.

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