Display device, method of manufacturing display device, and electronic device

Abstract

A display device, a method of manufacturing the same, and an electronic device are provided. The display device includes: a substrate including an emission area and a non-emission area; a first light emitting element on the emission region of the substrate; a pixel defining layer on the non-emission region of the substrate and defining a first opening; a bank structure on the pixel defining layer, defining a second opening, and including a groove; and a first encapsulation layer on the first light emitting element and the bank structure. The bank structure includes: a first bank layer including a first side surface facing the emission region and a second side surface opposite the first side surface; and a second bank layer on the first bank layer and including a first tip protruding toward the emission area and a second tip protruding toward the groove. The first encapsulation layer entirely covers the first tip and the second tip.

Description

[0001] This application claims priority to and all benefits derived from Korean Patent Application No. 10-2024-0036028, filed on March 14, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to a display device and a method of manufacturing the display device. Background Art

[0003] With the development of the information society, the demand for display devices for displaying images has increased and diversified. For example, display devices have been applied to various electronic devices such as smartphones, digital cameras, laptop computers, navigation devices, and smart TVs. The display device can be a flat panel display device such as a liquid crystal display device, a field emission display device, or an organic light-emitting display device. Among such flat panel display devices, a light-emitting display device can display images without a backlight unit that provides light to the display panel because each pixel of the display panel includes a light-emitting element that can emit light by itself.

[0004] With the development of various electronic devices, the demand for high aperture ratio and high resolution display devices has increased. Since some high aperture ratio and high resolution display devices may require highly integrated pixels, a display device corresponding to highly integrated pixels and a method of manufacturing the display device are desired. Summary of the Invention

[0005] Aspects of the present disclosure provide a display device and a method of manufacturing the display device that solve reliability defects caused by moisture penetration.

[0006] However, aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0007] In a disclosed embodiment, a display device includes: a substrate including an emission area and a non-emission area; a first light-emitting element located on the emission area of ​​the substrate; a pixel-defining layer located on the non-emission area of ​​the substrate and defining a first opening; a dam structure located on the pixel-defining layer, defining a second opening, and including a groove; and a first encapsulation layer located on the first light-emitting element and the dam structure, wherein the dam structure includes: a first dam layer including a first side surface facing the emission area and a second side surface opposite to the first side surface; and a second dam layer located on the first dam layer and including a first tip protruding much more toward the emission area than the first side surface and a second tip protruding much more toward the groove than the second side surface, and the first encapsulation layer entirely covers the first tip and the second tip.

[0008] In an embodiment, the display device may further include a second light-emitting element separated from the first light-emitting element, and the pixel defining layer and the embankment structure are placed between the second light-emitting element and the first light-emitting element separated from each other, wherein the first light-emitting element and the second light-emitting element are in contact with the first embankment layer.

[0009] In an embodiment, the first light emitting element and the second light emitting element may be electrically connected to each other through the first bank layer.

[0010] In an embodiment, the first bank layer may include aluminum, and the second bank layer may include titanium.

[0011] In an embodiment, the second opening may entirely surround the first opening in a plan view.

[0012] In an embodiment, the first light emitting element may include an anode electrode, a light emitting layer, and a cathode electrode, and the light emitting layer and the cathode electrode may be in contact with the first side surface.

[0013] In an embodiment, the display device may further include: an organic pattern located on the second bank layer, including the same material as the light-emitting layer and separated from the light-emitting layer; and an electrode pattern located on the organic pattern, including the same material as the cathode electrode and separated from the cathode electrode, wherein the organic pattern and the electrode pattern overlap with the first tip and the second tip.

[0014] In an embodiment, the organic pattern and the electrode pattern may be positioned such that the organic pattern and the electrode pattern surround the first opening, and the first encapsulation layer entirely covers the organic pattern and the electrode pattern.

[0015] In an embodiment, the display device may further include a residual pattern located between the anode electrode and the pixel defining layer in a direction perpendicular to the substrate, wherein the residual pattern overlaps the first tip.

[0016] In embodiments, the residual pattern may be in contact with the light emitting layer.

[0017] In an embodiment, the first embankment layer may include: a first portion in contact with the first light-emitting element; a second portion in contact with the second light-emitting element; and a third portion overlapping with the groove, the first portion, the second portion and the third portion being formed integrally, and the third portion being located between the first portion and the second portion.

[0018] In an embodiment, the third portion may be spaced apart from the first encapsulation layer, with a space interposed between the third portion and the first encapsulation layer in a direction perpendicular to the substrate.

[0019] In an embodiment, the display device may further include a second encapsulation layer on the first encapsulation layer, wherein the third portion may be in contact with the second encapsulation layer.

[0020] In an embodiment, the second bank layer may include a first subportion on the first portion of the first bank layer and a second subportion on the second portion of the first bank layer, and the first subportion and the second subportion are spaced apart from each other in a direction parallel to the substrate.

[0021] In an embodiment, the first encapsulation layer may include a first inorganic layer entirely covering the first subportion and a second inorganic layer entirely covering the second subportion, and the first and second inorganic layers are spaced apart from each other in a direction parallel to the substrate.

[0022] In an embodiment, the first embankment layer may include: a first portion, which is in contact with the first light-emitting element; a second portion, which is spaced apart from the first portion and does not contact the first light-emitting element; and a third portion, which is overlapped with the groove, the first portion, the second portion and the third portion are formed integrally, and the third portion is located between the first portion and the second portion.

[0023] In an embodiment, the second bank layer may include a first sub-portion on the first portion and a second sub-portion on the second portion, and the first sub-portion and the second sub-portion are spaced apart from each other in a direction parallel to the substrate.

[0024] In an embodiment, the display device may further include: an organic pattern and an electrode pattern located on a first sub-portion of the second bank layer; and an organic residual pattern and an electrode residual pattern located on a third portion of the first bank layer, wherein the organic pattern and the organic residual pattern are spaced apart from each other, and the electrode pattern and the electrode residual pattern are spaced apart from each other.

[0025] In embodiments, the first encapsulation layer may entirely cover the electrode pattern and the electrode residual pattern.

[0026] In a disclosed embodiment, a method for manufacturing a display device includes the following steps: forming a substrate including an emission area and a non-emission area, forming an anode electrode and a sacrificial layer on the emission area of ​​the substrate, and then forming a pixel defining layer and a dam structure on the sacrificial layer, the dam structure including a first dam layer and a second dam layer; exposing the anode electrode by removing the pixel defining layer and the dam structure in a portion overlapping with the emission area, and forming a groove by removing a portion of the dam structure in a portion overlapping with the non-emission area; forming a second dam layer including a first tip and a second tip by removing a portion of the dam structure, the first tip protruding much more toward the emission area than the first side surface of the first dam layer, and the second tip protruding much more toward the groove than the second side surface of the first dam layer; and forming a light-emitting element by forming a light-emitting layer and a cathode electrode on the anode electrode and the dam structure, and forming an encapsulation layer that entirely covers the first tip and the second tip.

[0027] In a disclosed embodiment, the electronic device includes a display device, the display device including: a substrate including an emission area and a non-emission area; a first light-emitting element located on the emission area of ​​the substrate; a pixel-defining layer located on the non-emission area of ​​the substrate and defining a first opening; a dam structure located on the pixel-defining layer, defining a second opening, and including a groove; and a first encapsulation layer located on the first light-emitting element and the dam structure, wherein the dam structure includes: a first dam layer including a first side surface facing the emission area and a second side surface opposite to the first side surface; and a second dam layer located on the first dam layer and including a first tip protruding much more toward the emission area than the first side surface and a second tip protruding much more toward the groove than the second side surface, and the first encapsulation layer entirely covers the first tip and the second tip.

[0028] Details of other embodiments are described in the detailed description and shown in the accompanying drawings.

[0029] According to one or more embodiments of the present disclosure, a display device and a method of manufacturing the display device are provided, which solve reliability defects occurring due to the penetration of moisture and oxygen caused in a manufacturing process of the display device.

[0030] The effects of the present disclosure are not limited to the aforementioned effects, and various other effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other aspects and features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which: Figure 1 is a perspective view showing a display device according to an embodiment; Figure 2 yes Figure 1 A schematic cross-sectional view of a display device; Figure 3 It shows Figure 2 a plan view of an arrangement of emission regions in a display area; Figure 4 It is along Figure 3 A cross-sectional view of the display layer taken along line X1-X1'; Figure 5 is with Figure 4 An enlarged cross-sectional view of a display element layer and a thin film encapsulation layer stacked on a first emission region; Figure 6 is located in Figure 4 An enlarged cross-sectional view of a display element layer and a thin film encapsulation layer stacked in a non-emitting area between the first emission area and the second emission area; Figures 7 to 18 It shows the manufacturing Figure 4A schematic cross-sectional view of a method for forming a display element layer and a thin film encapsulation layer in FIG. Figure 19 According to another embodiment, Figure 3 a schematic cross-sectional view of the display area taken along line X1-X1'; and Figure 20 is located in Figure 19 An enlarged cross-sectional view of a display element layer and a thin film encapsulation layer overlapping a non-emitting area between a first emission area and a second emission area. DETAILED DESCRIPTION

[0032] The invention will now be described more fully hereinafter with reference to the accompanying drawings, in which various embodiments are shown. However, the aspects supported by the present disclosure may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, the example embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the example aspects of the disclosure to those skilled in the art. Like reference numerals refer to like elements throughout.

[0033] It will be understood that when an element is referred to as being “on” another element, it can be directly on the other element or intervening elements may be present therebetween. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.

[0034] It will be understood that although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings herein, the "first element," "first component," "first region," "first layer," or "first part" discussed below may be referred to as a second element, second component, second region, second layer, or second part.

[0035] The terminology used herein is for the purpose of describing specific embodiments and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms "a," "an," and "the" are intended to include the plural forms "at least one..." and "at least one...". Thus, a reference to "an" element followed by "the" element in a claim includes both one and multiple elements. For example, unless the context clearly indicates otherwise, "element" has the same meaning as "at least one element." "At least one..." should not be construed as limiting "a" or "an." "Or" means "and / or." As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It will also be understood that when the terms "comprises" or "comprising" and / or their variations are used in this specification, they specify the presence of the recited features, regions, wholes, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, components, and / or groups thereof.

[0036] Furthermore, relative terms, such as "lower" or "bottom" and "upper" or "top," may be used herein to describe the relationship of one element to another element as shown in the accompanying drawings. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the accompanying drawings. For example, if the device in one of the drawings is turned over, an element described as being "on the "lower" side of another element would subsequently be oriented as being "on the "upper" side of the other element. Thus, the term "lower" can encompass both "lower" and "upper" orientations, depending on the particular orientation of the drawing. Similarly, if the device in one of the drawings is turned over, an element described as being "below" or "beneath" another element would subsequently be oriented as being "above" the other element. Thus, the terms "lower" or "beneath" can encompass both "upper" and "lower" orientations.

[0037] As used herein, "about" or "approximately" is inclusive of the stated value and means within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system). For example, the term "about" or "approximately" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0038] As used herein, the term "substantially" means approximately or practically. The term "substantially equal" means approximately or practically equal. The term "substantially the same" means approximately or practically the same. The term "substantially perpendicular" means approximately or practically perpendicular. The term "substantially parallel" means approximately or practically parallel.

[0039] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and in the disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly defined as such herein.

[0040] The embodiments are described herein with reference to schematically illustrated cross-sectional illustrations as example embodiments. As such, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown here, but rather include deviations in shapes due to, for example, manufacturing. For example, a region shown or described as flat may typically have rough and / or nonlinear features. Furthermore, sharp angles shown may be rounded. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions and are not intended to limit the scope of the present claims.

[0041] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0042] Figure 1 is a perspective view showing a display device according to an embodiment.

[0043] Reference Figure 1 The display device 10 displays moving images or still images. The display device 10 may refer to any electronic device that provides a display screen. For example, a television, laptop computer, monitor, billboard, Internet of Things (IoT) device, mobile phone, smartphone, tablet personal computer (PC), electronic watch, smartwatch, watch phone, head-mounted display, mobile communication terminal, electronic notebook, electronic book, portable multimedia player (PMP), navigation device, game console, digital camera, camcorder, etc. that provide a display screen may be included in the display device 10.

[0044] exist Figure 1, a first direction (X-axis direction), a second direction (Y-axis direction) and a third direction (Z-axis direction) are defined. The first direction (X-axis direction) and the second direction (Y-axis direction) may be perpendicular to each other, the first direction (X-axis direction) and the third direction (Z-axis direction) may be perpendicular to each other, and the second direction (Y-axis direction) and the third direction (Z-axis direction) may be perpendicular to each other. It will be understood that the first direction (X-axis direction) refers to the lateral direction in the drawings, the second direction (Y-axis direction) refers to the longitudinal direction in the drawings, and the third direction (Z-axis direction) refers to the up and down direction (i.e., thickness direction) in the drawings. In the following description, unless otherwise specified, the term "direction" may refer to two directions toward both sides extending along the direction. In some aspects, when two "directions" extending to both sides are to be distinguished from each other, one side will be referred to as "one side in the direction" and the other side will be referred to as "the other side in the direction." In Figure 1 , a direction pointed by an arrow indicating a direction will be referred to as one side, and a direction opposite to such a direction will be referred to as the other side.

[0045] Hereinafter, for ease of explanation, when referring to the surfaces of the respective components constituting the display device 10, one surface facing one side in the direction in which an image is displayed (i.e., the third direction (Z-axis direction)) will be referred to as an upper surface, and the surface opposite to the one surface will be referred to as the other surface. However, the embodiments of the present disclosure are not limited thereto, and the one surface and the other surface of the component may be referred to as a front surface and a rear surface, respectively, or as a first surface and a second surface, respectively. In some aspects, when describing the relative positions of the respective components of the display device 10, one side in the third direction (Z-axis direction) may be referred to as an upper portion, and the other side in the third direction (Z-axis direction) may be referred to as a lower portion.

[0046] The shape of the display device 10 can be variously changed. For example, the display device 10 can have a shape such as a rectangular shape with a width greater than a length, a rectangular shape with a length greater than a width, a square shape, a rectangular shape with rounded corners (vertices), other polygonal shapes, or a circular shape.

[0047] The display device 10 may include a display panel 100 , a display driver 200 , a circuit board 300 , and a touch driver 400 .

[0048] The display panel 100 may include a main area MA and sub-areas SBA. The main area MA may include a display area DA, which includes pixels displaying an image, and a non-display area NDA, which is disposed around the display area DA. The main area MA and sub-areas SBA may be made of flexible materials that can be bent, folded, and rolled. Each component of the display panel 100 (e.g., the substrate 110) may include regions corresponding to regions of the display panel 100 (e.g., the emission area EA and the non-emission area NLA).

[0049] The display area DA is an area where images can be displayed, while the non-display area NDA is an area where images are not displayed. The display area DA may also be referred to as an active area, and the non-display area NDA may also be referred to as an inactive area. The display area DA may substantially occupy the center of the display device 10. The non-display area NDA may be an area outside the display area DA. The non-display area NDA may be defined as an edge area of ​​the main area MA of the display panel 100. The non-display area NDA may include lines that supply signals to the display area DA and lines that connect the display driver 200 to the display area DA.

[0050] The sub-area SBA may be an area extending from one side of the main area MA. In an example where the sub-area SBA is curved, the sub-area SBA may overlap the main area MA in the thickness direction (e.g., the third direction (Z-axis direction)). The sub-area SBA may include the display driver 200 and a display pad (also known as a "pad" or "solder pad") connected to the circuit board 300. In another embodiment, the sub-area SBA may be omitted, and the display driver 200 and the display pad may be located in the non-display area NDA.

[0051] The display driver 200 can output signals and voltages for driving the display panel 100. The display driver 200 can be formed as an integrated circuit (IC) and mounted on the display panel 100 using a chip-on-glass (COG) method, a chip-on-plastic (COP) method, or an ultrasonic bonding method. As an example, the display driver 200 can be disposed in the sub-area SBA and can overlap the main area MA in the thickness direction due to the bending of the sub-area SBA. As another example, the display driver 200 can be mounted on the circuit board 300.

[0052] The circuit board 300 may be attached to the display pad of the display panel 100 using an anisotropic conductive film (ACF). The circuit board 300 may be electrically connected to the display pad. The circuit board 300 may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

[0053] The touch driver 400 may be mounted on the circuit board 300. The touch driver 400 may be connected to the touch sensor layer 180 (see FIG. Figure 2 ).

[0054] Figure 2 yes Figure 1 Schematic cross-sectional view of a display device.

[0055] Reference Figure 2 The display panel 100 may include a display layer DPL, a touch sensor layer 180 and a color filter layer 190. The display layer DPL may include a substrate 110, a thin film transistor layer 130, a display element layer 150 and a thin film encapsulation layer 170.

[0056] The substrate 110 may be a base substrate or a base member. The substrate 110 may be a flexible substrate that can be bent, folded, and rolled. For example, the substrate 110 may include a polymer resin such as polyimide (PI), but is not limited thereto. In another embodiment, the substrate 110 may include a glass material or a metal material.

[0057] The thin film transistor layer 130 may be provided on the substrate 110. The thin film transistor layer 130 may be located in a portion overlapping the display area DA, the non-display area NDA, and the sub-area SBA. The thin film transistor layer 130 may include a plurality of layers constituting the pixel PX (see FIG. Figure 3 ) of multiple thin film transistors TFT (see Figure 4 ).

[0058] The display element layer 150 may be disposed on the thin film transistor layer 130. The display element layer 150 may be located in a portion overlapping the display area DA. The display element layer 150 may include at least one of an organic light emitting diode (LED) including an organic light emitting layer, a quantum dot LED including a quantum dot light emitting layer, an inorganic LED including an inorganic semiconductor, and a micro LED, but is not limited thereto.

[0059] The thin film encapsulation layer 170 may be located on the display element layer 150. The thin film encapsulation layer 170 may be located in a portion overlapping the display area DA and the non-display area NDA. The thin film encapsulation layer 170 may cover the upper and side surfaces of the display element layer 150 and may protect the display element layer 150 from external oxygen and moisture. The thin film encapsulation layer 170 may include at least one inorganic film and at least one organic film for encapsulating the display element layer 150.

[0060] The touch sensor layer 180 may be disposed on the thin film encapsulation layer 170. The touch sensor layer 180 may be located in a portion overlapping the display area DA and the non-display area NDA. The touch sensor layer 180 may sense a user's touch in a mutual capacitance manner or a self-capacitance manner.

[0061] A color filter layer 190 may be provided on the touch sensor layer 180. The color filter layer 190 may be located in a portion overlapping the display area DA and the non-display area NDA. The color filter layer 190 may absorb some of the light introduced from outside the display device 10 to reduce reflected light caused by the external light. Thus, for example, the color filter layer 190 may prevent color distortion caused by external light reflection.

[0062] Since the color filter layer 190 is directly provided on the touch sensor layer 180, the display device 10 can be implemented without a separate substrate for the color filter layer 190. Therefore, for example, the thickness of the display device 10 can be relatively small. The color filter layer 190 may also be omitted according to embodiments.

[0063] like Figure 2 As shown in , a portion of the display layer DPL overlapping the sub-area SBA may be bent. In the example where a portion of the display layer DPL is bent, the display driver 200, the circuit board 300, and the touch driver 400 may overlap the main area MA in the third direction (Z-axis direction).

[0064] Figure 3 It shows Figure 2 A plan view of the arrangement of emission areas in a display area.

[0065] Reference Figure 3 , the display area DA according to the embodiment may include an emission area EA and a non-emission area NLA.

[0066] The emission area EA may include a first emission area EA1, a second emission area EA2, and a third emission area EA3 that emit light of different colors. The first emission area EA1, the second emission area EA2, and the third emission area EA3 may emit red light, green light, or blue light, respectively, and the color of the light emitted from the first emission area EA1, the second emission area EA2, and the third emission area EA3 may be selected according to the light emitting element ED (see FIG. 1 ) to be described later. Figure 4 As an example, the first emission area EA1 may emit red light, the second emission area EA2 may emit green light, and the third emission area EA3 may emit blue light, but the embodiments of the present disclosure are not limited thereto. Figure 3 Although the sizes or shapes of the first, second, and third emission areas EA1, EA2, and EA3 are shown to be identical, the embodiments of the present disclosure are not limited thereto. That is, the sizes and shapes of the first, second, and third emission areas EA1, EA2, and EA3 can be freely adjusted according to target (e.g., desired) characteristics.

[0067] The emission area EA may be defined by the first opening OP1 and the second opening OP2. In a plan view, the second opening OP2 may completely surround the first opening OP1 and may be completely surrounded by the non-emission area NLA.

[0068] In some embodiments, at least one first emission area EA1, at least one second emission area EA2, and at least one third emission area EA3 disposed adjacent to each other may constitute a pixel group PXG. The pixel group PXG may be the smallest unit emitting white light. Figure 3 In the embodiment, one first emission area EA1, two second emission areas EA2, and one third emission area EA3 are shown to constitute the pixel group PXG, but the embodiments of the present disclosure are not limited thereto. The type and / or number of the first emission area EA1, the second emission area EA2, and the third emission area EA3 constituting the pixel group PXG may be varied according to the embodiment.

[0069] The non-emission area NLA may be positioned so that the non-emission area NLA surrounds the emission area EA. The non-emission area NLA may block each light emitted from the plurality of first emission areas EA1, second emission areas EA2, and third emission areas EA3. The non-emission area NLA may help prevent each light emitted from the plurality of first emission areas EA1, second emission areas EA2, and third emission areas EA3 from mixing with each other.

[0070] Figure 4 It is along Figure 3 A cross-sectional view of the display layer taken along line X1-X1'.

[0071] Figure 4 is a partial cross-sectional view of the display device 10 overlapping the display area DA, and shows cross sections of the substrate 110, the thin film transistor layer 130, the display element layer 150, and the thin film encapsulation layer 170. The substrate 110 has been described, and thus description of the substrate 110 is omitted.

[0072] Reference Figure 4 The thin film transistor layer 130 may be located on the substrate 110. The thin film transistor layer 130 may include a first buffer layer 111, a thin film transistor TFT, a gate insulating layer 113, a first interlayer insulating layer 121, a capacitor electrode CPE, a second interlayer insulating layer 123, a first connection electrode CNE1, a first via layer 125, a second connection electrode CNE2, and a second via layer 127.

[0073] The first buffer layer 111 may be provided on the substrate 110. The first buffer layer 111 may include an inorganic film capable of preventing air or moisture from penetrating. For example, the first buffer layer 111 may include a plurality of inorganic films alternately stacked.

[0074] A thin film transistor (TFT) may be disposed on the first buffer layer 111 and may constitute a pixel circuit connected to each of the plurality of pixels PX. For example, the thin film transistor (TFT) may be a driving transistor or a switching transistor of the pixel circuit. The thin film transistor (TFT) may include an active layer (ACT), a source electrode (SE), a drain electrode (DE), and a gate electrode (GE).

[0075] The active layer ACT may be disposed on the first buffer layer 111. The active layer ACT may overlap the gate electrode GE in the third direction (Z-axis direction) and may be insulated from the gate electrode GE by the gate insulating layer 113. The source electrode SE and the drain electrode DE may be formed by changing the conductivity of the material of the active layer ACT in a portion of the active layer ACT.

[0076] The gate electrode GE may be disposed on the gate insulating layer 113. The gate electrode GE may overlap the active layer ACT with the gate insulating layer 113 interposed therebetween.

[0077] The gate insulating layer 113 may be disposed on the active layer ACT. For example, the gate insulating layer 113 may cover the active layer ACT and the first buffer layer 111 and may insulate the active layer ACT and the gate electrode GE from each other. The gate insulating layer 113 may include a contact hole through which the first connection electrode CNE1 penetrates.

[0078] The first interlayer insulating layer 121 may cover the gate electrode GE and the gate insulating layer 113. The first interlayer insulating layer 121 may include a contact hole through which the first connection electrode CNE1 penetrates. The contact hole of the first interlayer insulating layer 121 may be connected to the contact hole of the gate insulating layer 113 and the contact hole of the second interlayer insulating layer 123.

[0079] The capacitor electrode CPE may be disposed on the first interlayer insulating layer 121. The capacitor electrode CPE may overlap the gate electrode GE in the third direction (Z-axis direction). The capacitor electrode CPE and the gate electrode GE may form a capacitor.

[0080] The second interlayer insulating layer 123 may cover the capacitor electrode CPE and the first interlayer insulating layer 121. The second interlayer insulating layer 123 may include a contact hole through which the first connection electrode CNE1 penetrates. The contact hole of the second interlayer insulating layer 123 may be connected to the contact hole of the first interlayer insulating layer 121 and the contact hole of the gate insulating layer 113.

[0081] The first connection electrode CNE1 may be disposed on the second interlayer insulating layer 123. The first connection electrode CNE1 may electrically connect the drain electrode DE of the thin film transistor TFT and the second connection electrode CNE2 to each other. The first connection electrode CNE1 may be inserted into a contact hole formed in the first interlayer insulating layer 121, the second interlayer insulating layer 123, and the gate insulating layer 113 to contact the drain electrode DE of the thin film transistor TFT.

[0082] The first via layer 125 may cover the first connection electrode CNE1 and the second interlayer insulating layer 123. The first via layer 125 may planarize the underlying structure. The first via layer 125 may include a contact hole through which the second connection electrode CNE2 penetrates.

[0083] The second connection electrode CNE2 may be disposed on the first via layer 125. The second connection electrode CNE2 may be inserted into a contact hole formed in the first via layer 125 to contact the first connection electrode CNE1. The second connection electrode CNE2 may electrically connect the first connection electrode CNE1 and the anode electrode AE ​​to each other.

[0084] The second via layer 127 may cover the second connection electrode CNE2 and the first via layer 125. The second via layer 127 may include a contact hole through which the anode electrode AE ​​penetrates.

[0085] The display element layer 150 according to the embodiment may be provided on the thin film transistor layer 130. The display element layer 150 may include a light emitting element ED, a pixel defining layer 151, a residual pattern 153, and a bank structure 160.

[0086] The light emitting element ED according to the embodiment may include a first light emitting element ED1 disposed in the first emission area EA1 , a second light emitting element ED2 disposed in the second emission area EA2 , and a third light emitting element ED3 disposed in the third emission area EA3 .

[0087] The first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 can emit light of different colors according to the material of the light emitting layer EL. For example, the first light emitting element ED1 can emit red light, the second light emitting element ED2 can emit green light, and the third light emitting element ED3 can emit blue light.

[0088] The light-emitting element ED may include an anode electrode AE, a light-emitting layer EL, and a cathode electrode CE. As an example, the first light-emitting element ED1 may include a first anode electrode AE1, a first light-emitting layer EL1, and a first cathode electrode CE1; the second light-emitting element ED2 may include a second anode electrode AE2, a second light-emitting layer EL2, and a second cathode electrode CE2; and the third light-emitting element ED3 may include a third anode electrode AE3, a third light-emitting layer EL3, and a third cathode electrode CE3.

[0089] The anode electrode AE ​​according to the embodiment may be disposed on the second via layer 127. The anode electrode AE ​​may be electrically connected to the drain electrode DE of the thin film transistor TFT through the first and second connection electrodes CNE1 and CNE2.

[0090] The anode electrodes AE may include a first anode electrode AE1 located in the first emission area EA1, a second anode electrode AE2 located in the second emission area EA2, and a third anode electrode AE3 located in the third emission area EA3. The first, second, and third anode electrodes AE1, AE2, and AE3 may be disposed on the second via layer 127 to be spaced apart from each other.

[0091] The pixel defining layer 151 according to an embodiment may be located on the second via layer 127 and the anode electrode AE. The pixel defining layer 151 may define a first opening OP1. The pixel defining layer 151 may expose the anode electrode AE ​​at a portion of the anode electrode AE ​​overlapping the first opening OP1, and the light emitting layer EL may be directly disposed on the anode electrode AE ​​at a portion of the anode electrode AE ​​overlapping the first opening OP1.

[0092] The pixel defining layer 151 may include an inorganic insulating material. As an example, the pixel defining layer 151 may include any one of aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride.

[0093] The bank structure 160 according to an embodiment may be located on the pixel defining layer 151. The bank structure 160 may define the second opening OP2. The bank structure 160 may include a first bank layer 161 and a second bank layer 163 including different metal materials and structures and having different functions.

[0094] The embankment structure 160 may include a first tip TIP1 located in a portion overlapping the emission area EA. Typically, in a high-resolution display device, the intervals between a plurality of light-emitting elements ED adjacent to each other may be narrow. Therefore, for example, due to the narrow intervals, it may be difficult to form the plurality of light-emitting elements ED included in the high-resolution display device using a mask in a manufacturing process. According to one or more embodiments of the present disclosure, the embankment structure 160 of the display device 10 includes a first tip TIP1, which supports the formation of a plurality of light-emitting elements ED overlapping the first emission area EA1, the second emission area EA2, and the third emission area EA3 without using a mask in a manufacturing process.

[0095] The embankment structure 160 according to an embodiment may include a groove GRV in a portion overlapping the non-emission area NLA. The groove GRV may be formed by etching a portion of the embankment structure 160 in a manufacturing process of the display device 10. The manufacturing process will be described later.

[0096] The embankment structure 160 according to the embodiment may include a second tip TIP2 located in a portion overlapping the groove GRV. The second tip TIP2 may be formed in the same process as the process of forming the groove GRV. Details thereof will be described later.

[0097] The light-emitting layer EL according to an embodiment may be disposed on the anode electrode AE. The light-emitting layer EL may be an organic light-emitting layer formed of an organic material and may be formed on the anode electrode AE ​​through a deposition process. In an example in which the thin film transistor TFT applies a predetermined voltage to the anode electrode AE ​​and the cathode electrode CE receives a common voltage or a cathode voltage, holes and electrons may move to the light-emitting layer EL through the hole transport layer and the electron transport layer, respectively, and may recombine with each other in the light-emitting layer EL to emit light.

[0098] The light-emitting layer EL may include a first light-emitting layer EL1, a second light-emitting layer EL2, and a third light-emitting layer EL3, respectively disposed in a first emission region EA1, a second emission region EA2, and a third emission region EA3. As an example, the first light-emitting layer EL1 may be a light-emitting layer emitting red light, the second light-emitting layer EL2 may be a light-emitting layer emitting green light, and the third light-emitting layer EL3 may be a light-emitting layer emitting blue light, but the embodiments of the present disclosure are not limited thereto.

[0099] The residual pattern 153 according to an embodiment may be located between the anode electrode AE ​​and the pixel defining layer 151 in the third direction (Z-axis direction). Details thereof will be described later.

[0100] According to an embodiment, a cathode electrode CE may be provided on the light-emitting layer EL. The cathode electrode CE may include a transparent conductive material to emit light generated by the light-emitting layer EL. The cathode electrode CE may receive a common voltage or a low-potential voltage. In an example where the anode electrode AE ​​receives a voltage corresponding to a data voltage and the cathode electrode CE receives a low-potential voltage, a potential difference is formed between the anode electrode AE ​​and the cathode electrode CE, allowing the light-emitting layer EL to emit light.

[0101] The cathode electrode CE may include a first cathode electrode CE1, a second cathode electrode CE2, and a third cathode electrode CE3. The first cathode electrode CE1 may be disposed on the first light-emitting layer EL1 in the first emission area EA1, the second cathode electrode CE2 may be disposed on the second light-emitting layer EL2 in the second emission area EA2, and the third cathode electrode CE3 may be disposed on the third light-emitting layer EL3 in the third emission area EA3.

[0102] The first cathode electrode CE1, the second cathode electrode CE2, and the third cathode electrode CE3 may be spaced apart from each other, and the embankment structure 160 is interposed between the first cathode electrode CE1 and the second cathode electrode CE2, between the second cathode electrode CE2 and the third cathode electrode CE3, and between the third cathode electrode CE3 and the first cathode electrode CE1. The first cathode electrode CE1, the second cathode electrode CE2, and the third cathode electrode CE3 may be electrically connected to each other via the first bank layer 161 of the embankment structure 160.

[0103] The organic pattern ELP according to an embodiment may be located on the bank structure 160. The organic pattern ELP may be disposed on the second bank layer 163 such that the organic pattern ELP surrounds the first opening OP1. The organic pattern ELP may include the same material as the light emitting layer EL.

[0104] The organic pattern ELP may include a first organic pattern ELP1, a second organic pattern ELP2, and a third organic pattern ELP3. As an example, the first organic pattern ELP1 may include the same material as the first light-emitting layer EL1, the second organic pattern ELP2 may include the same material as the second light-emitting layer EL2, and the third organic pattern ELP3 may include the same material as the third light-emitting layer EL3. The organic pattern ELP may be a trace formed by, during the manufacturing process of the display device 10, the material forming the light-emitting layer EL is disconnected from the light-emitting layer EL and is not connected to the light-emitting layer EL because the embankment structure 160 includes the first tip TIP1.

[0105] The electrode pattern CEP according to an embodiment may be located on the organic pattern ELP. The electrode pattern CEP may be disposed on the organic pattern ELP such that the electrode pattern CEP surrounds the first opening OP1. The electrode pattern CEP may include the same material as the cathode electrode CE.

[0106] The electrode pattern CEP may include a first electrode pattern CEP1, a second electrode pattern CEP2, and a third electrode pattern CEP3. As an example, the first electrode pattern CEP1 may include the same material as the first cathode electrode CE1, the second electrode pattern CEP2 may include the same material as the second cathode electrode CE2, and the third electrode pattern CEP3 may include the same material as the third cathode electrode CE3. The electrode pattern CEP may be a trace formed by: during the manufacturing process of the display device 10, because the embankment structure 160 includes the first tip TIP1, the material forming the cathode electrode CE is disconnected from the cathode electrode CE and is not connected to the cathode electrode CE.

[0107] The thin film encapsulation layer 170 according to an embodiment may be located on the display element layer 150. The thin film encapsulation layer 170 may prevent oxygen or moisture from penetrating into the display element layer 150 and may protect the display element layer 150 from foreign matter, such as dust, for example. The thin film encapsulation layer 170 may include a first encapsulation layer 171, a second encapsulation layer 172, a third encapsulation layer 173, and a fourth encapsulation layer 175 stacked in sequence. The first encapsulation layer 171, the second encapsulation layer 172, and the fourth encapsulation layer 175 may include one or more inorganic insulating materials, and the third encapsulation layer 173 may include a polymer-based organic material.

[0108] The first encapsulation layer 171 according to the embodiment may entirely cover the first and second tip ends TIP1 and TIP2 of the embankment structure 160. In the display device 10 according to the embodiment, the first encapsulation layer 171 may entirely cover the first and second tip ends TIP1 and TIP2, thereby preventing moisture and oxygen from penetrating during the manufacturing process. Therefore, for example, the display device 10 according to the embodiment may resolve reliability defects caused by moisture and oxygen penetration.

[0109] According to the embodiment, the first encapsulation layer 171 may include a first inorganic layer 171-1, a second inorganic layer 171-2, and a third inorganic layer 171-3. The first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3 may be located in portions overlapping with the respective emission regions EA1, EA2, and EA3 and the non-emission region NLA. As an example, the first inorganic layer 171-1 may cover the first cathode electrode CE1 and the first electrode pattern CEP1 in the portion overlapping with the first emission region EA1 and the non-emission region NLA, the second inorganic layer 171-2 may cover the second cathode electrode CE2 and the second electrode pattern CEP2 in the portion overlapping with the second emission region EA2 and the non-emission region NLA, and the third inorganic layer 171-3 may cover the third cathode electrode CE3 and the third electrode pattern CEP3 in the portion overlapping with the third emission region EA3 and the non-emission region NLA. The first inorganic layer 171 - 1 , the second inorganic layer 171 - 2 , and the third inorganic layer 171 - 3 may be spaced apart from each other in a portion overlapping the non-emission area NLA.

[0110] Already in Figure 4, the first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3 are shown as being formed on the same layer. However, the first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3 may be formed in different processes. As an example, the first inorganic layer 171-1 may be formed after forming the first cathode electrode CE1, the second inorganic layer 171-2 may be formed after forming the second cathode electrode CE2, and the third inorganic layer 171-3 may be formed after forming the third cathode electrode CE3. The manufacturing process will be described later.

[0111] Figure 5 is with Figure 4 An enlarged cross-sectional view of the display element layer and the thin film encapsulation layer stacked on the first emission area in FIG.

[0112] Reference Figure 5 The pixel-defining layer 151 may be located on the second via layer 127 and the first anode electrode AE1. The pixel-defining layer 151 may be spaced apart from the first anode electrode AE1 in the third direction (Z-axis direction) in the portion overlapping the second opening OP2, and the residual pattern 153 may be located in the portion where the pixel-defining layer 151 and the first anode electrode AE1 are spaced apart from each other. The residual pattern 153 may contact the first light-emitting layer EL1 and may be positioned to overlap the first tip TIP1 in the third direction (Z-axis direction).

[0113] The display device 10 may include a sacrificial layer SFL (see FIG. 1 ) disposed between the pixel defining layer 151 and the anode electrode AE ​​during a manufacturing process. Figure 7 ). The sacrificial layer SFL may be disposed between the pixel defining layer 151 and the anode electrode AE ​​and then partially removed by a subsequent etching process. In this case, the unremoved portion of the sacrificial layer SFL may remain between the pixel defining layer 151 and the anode electrode AE ​​as a residual pattern 153. The manufacturing process will be described later.

[0114] The first bank layer 161 according to an embodiment may be located on the pixel defining layer 151. The first bank layer 161 may include a metal having high electrical conductivity. As an example, the first bank layer 161 may include aluminum (Al).

[0115] In some embodiments, the first bank layer 161 may include a first side surface 1c and a second side surface 1d. The first side surface 1c may be a surface facing the first opening OP1 and may be positioned more recessed than the pixel defining layer 151 in the first direction (X-axis direction). The second side surface 1d may be located in a portion overlapping the non-emission area NLA and may be a surface opposite to the first side surface 1c.

[0116] The first light emitting layer EL1 and the first cathode electrode CE1 according to the embodiment may be in contact with the first side surface 1c. In the display device 10 according to the embodiment, the larger the contact area Wce between the first cathode electrode CE1 and the first side surface 1c, the lower the resistance. Therefore, for example, the contact area Wce between the cathode electrode CE and the first side surface 1c of the first bank layer 161 can be adjusted according to the target (e.g., desired) characteristics of the display device 10.

[0117] The second bank layer 163 according to an embodiment may be located on the first bank layer 161. The second bank layer 163 may include a material having a lower etch rate than the first bank layer 161. As an example, the second bank layer 163 may include titanium (Ti).

[0118] The second bank layer 163 may include a first tip TIP1 that protrudes further toward the first opening OP1 than the first side surface 1c of the first bank layer 161. Thus, for example, the first tip TIP1 of the second bank layer 163 and the first side surface 1c of the first bank layer 161 may form an undercut in a portion overlapping the first emission area EA1. In some aspects, the second bank layer 163 may include a second tip TIP2 that protrudes further on one side in the first direction (X-axis direction) than the second side surface 1d of the first bank layer 161. Thus, for example, the second tip TIP2 of the second bank layer 163 and the second side surface 1d of the first bank layer 161 may form an undercut in a portion overlapping the non-emission area NLA.

[0119] The first organic pattern ELP1 according to an embodiment may be positioned to overlap the first and second tip ends TIP1 and TIP2 of the second bank 163. In some aspects, the first electrode pattern CEP1 according to an embodiment may be positioned to overlap the first and second tip ends TIP1 and TIP2 of the second bank 163.

[0120] The first inorganic layer 171-1 according to the embodiment may entirely cover the first light emitting element ED1 in a portion overlapping the first opening OP1, and may entirely cover the first side surface 1c of the first bank 161 and the first tip TIP1 of the second bank 163 in a portion overlapping the second opening OP2. In some aspects, the first inorganic layer 171-1 according to the embodiment may entirely cover the second tip TIP2 of the second bank 163, and may cover a portion of the second side surface 1d of the first bank 161 in a portion overlapping the non-emission area NLA. In some aspects, the first inorganic layer 171-1 according to the embodiment may entirely cover the first organic pattern ELP1 and the first electrode pattern CEP1.

[0121] In the display device 10 according to the embodiment, the first inorganic layer 171-1 can prevent the penetration of moisture and oxygen caused during the manufacturing process by entirely covering the first and second tip tips TIP1 and TIP2 of the second bank layer 163, the first organic pattern ELP1, and the first electrode pattern CEP1. Therefore, for example, the display device 10 according to the embodiment can solve reliability defects caused by the penetration of moisture and oxygen. Repeated descriptions are omitted.

[0122] For ease of explanation, the display element layer 150 and the thin film encapsulation layer 170 located in the portion overlapping with the first emission area EA1 have been shown and described, and the structure and characteristics of the display element layer 150 and the thin film encapsulation layer 170 located in the portion overlapping with the second emission area EA2 and the third emission area EA3 may be the same as the structure and characteristics described herein.

[0123] Figure 6 is located in Figure 4 An enlarged cross-sectional view of a display element layer and a thin film encapsulation layer overlapping a non-emitting area between a first emission area and a second emission area.

[0124] Reference Figure 6 According to an embodiment, the first anode electrode AE1 and the second anode electrode AE2 may be spaced apart from each other, with the pixel defining layer 151 interposed therebetween. In some aspects, the first light-emitting element ED1 and the second light-emitting element ED2 may be spaced apart from each other, with the pixel defining layer 151 and the embankment structure 160 interposed therebetween.

[0125] The embankment structure 160 according to an embodiment may include a groove GRV located in a portion overlapping the non-emission area NLA. The groove GRV may refer to a portion where portions of the first and second embankment layers 161 and 163 are removed in the portion overlapping the non-emission area NLA. In other words, the groove GRV may refer to a portion where the first and second embankment layers 161 and 163 are partially retracted in a direction toward the pixel defining layer 151. The groove GRV may be formed by performing an etching process in the manufacturing process of the display device 10. The manufacturing method will be described later.

[0126] The groove GRV according to the embodiment may have a curved shape according to different etching rates of the first and second bank layers 161 and 163. That is, the width of the groove GRV in the first direction (X-axis direction) may be greater between portions of the first bank layer 161 than between portions of the second bank layers 163.

[0127] In some embodiments, the first bank 161 may include a first portion 161A, a second portion 161B, and a third portion 161C. The first portion 161A may be a portion in contact with the first light emitting element ED1, the second portion 161B may be a portion in contact with the second light emitting element ED2, and the third portion 161C may be a portion overlapping the groove GRV.

[0128] The third portion 161C may be located between the first portion 161A and the second portion 161B in the first direction (X-axis direction). In other words, the first portion 161A and the second portion 161B may be spaced apart from each other, with the third portion 161C positioned between the first portion 161A and the second portion 161B. The third portion 161C may not contact the light-emitting element ED. The first portion 161A, the second portion 161B, and the third portion 161C may be integrally formed. That is, the first portion 161A and the second portion 161B may extend from the third portion 161C.

[0129] In some embodiments, the second bank layer 163 may include a first sub-portion 163A and a second sub-portion 163B. The first sub-portion 163A may be located on and in contact with the first portion 161A of the first bank layer 161. The second sub-portion 163B may be located on and in contact with the second portion 161B of the first bank layer 161. The first sub-portion 163A and the second sub-portion 163B may be spaced apart from each other in the first direction (X-axis direction), with a groove GRV interposed between the first sub-portion 163A and the second sub-portion 163B. The first sub-portion 163A and the second sub-portion 163B may be electrically connected to each other through the first bank layer 161.

[0130] In an embodiment, the first organic pattern ELP1 and the first electrode pattern CEP1 may be located on the first subportion 163A of the second bank layer 163, and the second organic pattern ELP2 and the second electrode pattern CEP2 may be located on the second subportion 163B of the second bank layer 163. The first organic pattern ELP1 and the second organic pattern ELP2 may be spaced apart from each other, and the groove GRV of the bank structure 160 may be positioned between the first organic pattern ELP1 and the second organic pattern ELP2, and the first electrode pattern CEP1 and the second electrode pattern CEP2 may be spaced apart from each other, and the groove GRV of the bank structure 160 may be positioned between the first electrode pattern CEP1 and the second electrode pattern CEP2.

[0131] According to an embodiment, the first encapsulation layer 171 may be spaced apart from the first bank layer 161 in the third direction (Z-axis direction), and a space SA may be interposed between the first encapsulation layer 171 and the first bank layer 161 in a portion overlapping the groove GRV of the bank structure 160. The space SA may be formed by forming the organic pattern ELP and the electrode pattern CEP in a manufacturing process of the display device 10 and then removing the organic pattern ELP and the electrode pattern CEP in the groove GRV in a subsequent process. The manufacturing method will be described later.

[0132] The first and second inorganic layers 171-1 and 171-2 may entirely surround the first and second tip ends TIP1 and TIP2 of the second bank layer 163. The first and second inorganic layers 171-1 and 171-2 may be spaced apart from each other with the groove GRV of the bank structure 160 interposed therebetween. Repeated descriptions are omitted.

[0133] According to an embodiment, the second encapsulation layer 172 may be located on the first encapsulation layer 171. The second encapsulation layer 172 may cover the first encapsulation layer 171 along the outline formed by the first inorganic layer 171-1 and the second inorganic layer 171-2 in a portion overlapping the non-emission area NLA. The second encapsulation layer 172 may fill the space SA formed between the first encapsulation layer 171 and the first bank layer 161.

[0134] The third encapsulation layer 173 according to an embodiment may planarize a profile formed by the second encapsulation layer 172. Repeated descriptions are omitted.

[0135] For ease of explanation, the display element layer 150 and the thin film encapsulation layer 170 located in the portion overlapping the non-emission area NLA between the first emission area EA1 and the second emission area EA2 have been shown and described, and the structures and characteristics of the display element layer 150 and the thin film encapsulation layer 170 located in the portion overlapping the non-emission area NLA between the second emission area EA2 and the third emission area EA3 may be the same as the structures and characteristics described herein.

[0136] Figures 7 to 18 It shows the manufacturing Figure 4 Schematic cross-sectional view of a method for forming a display element layer and a thin film encapsulation layer in FIG. Hereinafter, the manufacturing process of the display device 10 will be described in conjunction with the formation order of each layer.

[0137] In the description of the method herein, operations may be performed in a different order than that shown and / or described, or may be performed in a different order or at different times. Certain operations may also be omitted from the method, one or more operations may be repeated, or other operations may be added. Descriptions of "can be provided with" elements, "can be formed with" elements, etc. include methods, processes, and techniques for providing, forming, locating, and modifying elements, etc., according to the exemplary aspects described herein.

[0138] Reference Figure 7 , the method may include: forming an anode electrode AE ​​on the thin film transistor layer 130; and forming a sacrificial layer SFL on the anode electrode AE. Figure 7 , but the structure of the thin film transistor layer 130 is the same as that of the thin film transistor layer 130 shown here. Figure 4 The structures described are the same. A repeated detailed description thereof is omitted. The plurality of anode electrodes AE and the sacrificial layer SFL may be located in a portion overlapping the emission area EA, and the plurality of anode electrodes AE and the sacrificial layer SFL may be disposed to be spaced apart from each other.

[0139] According to embodiments, the sacrificial layer SFL can help prevent the anode electrode AE ​​and the pixel defining layer 151 from contacting each other. In some aspects, the sacrificial layer SFL can protect the anode electrode AE ​​during subsequent etching processes. The sacrificial layer SFL can include an oxide semiconductor. As an example, the sacrificial layer SFL can include at least one of indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), and indium tin oxide (IZO).

[0140] Subsequently, the method may include forming a pixel-defining material layer 151L and a bank material layer 160L on the plurality of anode electrodes AE and the sacrificial layer SFL. The pixel-defining material layer 151L may entirely cover the sacrificial layer SFL and the thin film transistor layer 130, and the bank material layer 160L may entirely cover the pixel-defining material layer 151L. The bank material layer 160L may include a first bank material layer 161L and a second bank material layer 163L.

[0141] Next, refer to Figure 8 and Figure 9 The method may include: forming a photoresist PR on the second bank material layer 163L; and performing a first etching process (first etching) using the photoresist PR as a mask. As an example, the method may include performing a dry etching process as the first etching process (first etching).

[0142] In this process, the method may include forming a photoresist PR in the form of a half-tone mask. A plurality of photoresists PR may be spaced apart from each other on the second bank material layer 163L, while exposing portions overlapping the corresponding anode electrodes AE. In this process, the method may include isotropically etching the first bank material layer 161L and the second bank material layer 163L, which include different metal materials.

[0143] Subsequently, the method may include performing a photoresist ashing process (PR ashing). In this process, the method may include removing a portion of the photoresist PR formed at a relatively low height.

[0144] Next, refer to Figure 10 and Figure 11 The method may include performing a second etching process (second etching) using the photoresist PR remaining in the photoresist ashing process (PR ashing) as a mask. As an example, the method may include performing a dry etching process as the second etching process (second etching).

[0145] In this process, the method may include removing a portion of the embankment material layer 160L and a portion of the pixel-defining material layer 151L. The step of removing the portion of the embankment material layer 160L and the portion of the pixel-defining material layer 151L may expose the sacrificial layer SFL located in a portion overlapping the emission area EA. The step of removing the portion of the embankment material layer 160L and the portion of the pixel-defining material layer 151L may form a groove GRV in a portion of the embankment material layer 160L located in a portion overlapping the non-emission area NLA.

[0146] Next, refer to Figure 12 and Figure 13 , the method may include performing a third etching process (third etching) using the photoresist PR as a mask. As an example, the method may include performing a wet etching process as the third etching process (third etching). In this process, the method may include forming Figure 4 The first bank layer 161, the second bank layer 163, the pixel defining layer 151, and the residual pattern 153 shown in FIG, and the method may include exposing the anode electrode AE.

[0147] In this process, the method may include anisotropically etching the first bank material layer 161L and the second bank material layer 163L including different materials. Specifically, the first bank material layer 161L may have a higher etching rate than the second bank material layer 163L. Therefore, for example, the second bank layer 163 may include a first tip TIP1 that protrudes further toward the emission area EA than the first side surface 1c of the first bank layer 161, and a second tip TIP2 that protrudes further toward the groove GRV than the second side surface 1d of the first bank layer 161.

[0148] In this process, the sacrificial layer SFL may not be completely removed and may remain as a partial residual pattern 153 in the space between the pixel defining layer 151 and the anode electrode AE. The residual pattern 153 may be located in a portion overlapping the first tip TIP1 of the second bank layer 163 .

[0149] Next, refer to Figure 14 The method may include forming a first light emitting layer EL1 and a first cathode electrode CE1 on the first anode electrode AE1. In this process, a first light emitting element ED1 may be formed.

[0150] The light-emitting layer EL according to an embodiment can be formed by a thermal evaporation process. This method may include performing a thermal evaporation process to form the light-emitting layer EL at an angle of 45° to 50° relative to the upper surface of the anode electrode AE. Thus, for example, the light-emitting layer EL can be formed so that the light-emitting layer EL fills the space between the anode electrode AE ​​and the pixel defining layer 151, which are spaced apart from each other, and is formed on the side surface of the first bank layer 161 that is hidden by the first tip TIP1 of the second bank layer 163.

[0151] The method may include forming the cathode electrode CE according to an embodiment through a thermal evaporation process. The method may include performing the thermal evaporation process to form the cathode electrode CE at an angle of 30° to 40° relative to the upper surface of each anode electrode AE. In other words, the method may include performing the thermal evaporation process to form the cathode electrode CE at an angle closer to the upper surface of the anode electrode AE ​​than the thermal evaporation process used to form the light-emitting layer EL. Thus, for example, the cathode electrode CE according to an embodiment may be formed on a side surface of the first bank layer 161 that is hidden by the first tip TIP1 of the second bank layer 163, and may entirely cover the light-emitting layer EL.

[0152] In this process, the material forming the first light emitting layer EL1 and the first cathode electrode CE1 can be formed not only on the first anode electrode AE1, but also on the second anode electrode AE2, the first bank layer 161, and the second bank layer 163. In this process, the material forming the first light emitting layer EL1 and the material forming the first cathode electrode CE1 located on the second bank layer 163 can be formed on the first anode electrode AE1. Figure 4 The organic pattern ELP and the electrode pattern CEP shown in .

[0153] Since the second bank layer 163 according to the embodiment includes the first tip TIP1 protruding toward the emission area EA, the first light emitting layer EL1 and the first cathode electrode CE1 may be spaced apart from the organic pattern ELP and the electrode pattern CEP.

[0154] In this process, the method may include forming an organic pattern ELP and an electrode pattern CEP on the first bank layer 161 in a portion overlapping the non-emission area NLA. However, the method may include removing the organic pattern ELP and the electrode pattern CEP formed on the first bank layer 161 through a subsequent etching process.

[0155] Next, the method may include forming a first encapsulation material layer 171L on the first cathode electrode CE1 and the electrode pattern CEP. The method may include forming the first encapsulation material layer 171L using a chemical vapor deposition (CVD) process. The method may include forming the first encapsulation material layer 171L into a uniform film regardless of steps in the underlying structure. As an example, the first encapsulation material layer 171L may cover the first and second tip tips TIP1 and TIP2, an undercut formed by the first tip tip TIP1 and the first bank layer 161, and an undercut formed by the second tip tip TIP2 and the first bank layer 161.

[0156] Then, refer to Figures 15 to 18 The method may include forming a photoresist PR on the first anode electrode AE1 and the second bank layer 163 located around the first anode electrode AE1, and the method may include performing a fourth etching process (fourth etching) using the photoresist PR as a mask. As an example, as the fourth etching process (fourth etching), the method may include alternately performing a wet etching process and a dry etching process.

[0157] In this process, the method may include removing the first light emitting layer EL1, the first cathode electrode CE1, the organic pattern ELP, the electrode pattern CEP, and the first encapsulation material layer 171L in the portion where the photoresist PR is not formed. Figure 4 1 , and the first organic pattern ELP1 , the first electrode pattern CEP1 , and the first inorganic layer 171 - 1 are shown in FIG.

[0158] In this process, the method may include removing the organic pattern ELP and the electrode pattern CEP located on the first bank layer 161, and the removal step may form a space SA in the third direction (Z-axis direction) between the first inorganic layer 171-1 and the first bank layer 161 in the portion overlapping the groove GRV. In other words, in the portion overlapping the second tip TIP2, the first bank layer 161 and the first inorganic layer 171-1 may be spaced apart from each other in the third direction (Z-axis direction), with the space SA interposed between the first bank layer 161 and the first inorganic layer 171-1.

[0159] In the present process, the first inorganic layer 171 - 1 may entirely surround the first and second tip ends TIP1 and TIP2 , and may entirely surround the first organic pattern ELP1 and the first electrode pattern CEP1 .

[0160] Next, the method may include forming a second light-emitting layer EL2, a second cathode electrode CE2, a second organic pattern ELP2, a second electrode pattern CEP2, and a second inorganic layer 171-2 on the second anode electrode AE2 by performing the process described herein. In this process, the light-emitting element ED, the pixel defining layer 151, the residual pattern 153, and the embankment structure 160 included in the display element layer 150 may be formed. The first inorganic layer 171-1 and the second inorganic layer 171-2 may be spaced apart from each other in the first direction (X-axis direction), with a groove GRV disposed between the first inorganic layer 171-1 and the second inorganic layer 171-2. Repeated descriptions are omitted.

[0161] Next, the method may include forming a thin film encapsulation layer 170 by forming a second encapsulation layer 172 , a third encapsulation layer 173 , and a fourth encapsulation layer 175 on the first encapsulation layer 171 .

[0162] In this process, the method may include forming second encapsulation layer 172 by a chemical vapor deposition process, and may form second encapsulation layer 172 with the same thickness along a contour formed by first encapsulation layer 171 located below second encapsulation layer 172. The method may include filling space SA formed between first encapsulation layer 171 and first bank layer 161 with second encapsulation layer 172. The method may include forming third encapsulation layer 173 by an inkjet method, and the method may include flattening the contour formed by second encapsulation layer 172.

[0163] Figure 19 According to another embodiment, Figure 3 Schematic cross-sectional view of the display area taken along line X1-X1'. Figure 20 is located in Figure 19 An enlarged cross-sectional view of a display element layer and a thin film encapsulation layer overlapping a non-emitting area between a first emission area and a second emission area.

[0164] Reference Figure 19 and Figure 20 , the embankment structure 160 included in the display device 30 may have a structure different from the embankment structure 160 of the display device 10. Hereinafter, description of the common structure between the display device 10 and the display device 30 is omitted, and the difference between the display device 10 and the display device 30 will be described later.

[0165] The bank structure 160 included in the display device 30 may include a plurality of grooves GRV formed in a portion overlapping the non-emission area NLA. Embodiments of the present disclosure may include forming the grooves GRV by etching a portion of the bank structure 160 during a manufacturing process of the display device 30.

[0166] The groove GRV included in the display device 30 may have a curved shape according to different etching rates of the first and second bank layers 161 and 163. That is, the width of the groove GRV in the first direction (X-axis direction) may be greater between portions of the first bank layer 161 than between portions of the second bank layers 163.

[0167] In some embodiments, the first bank layer 161 included in the display device 30 may include a first portion 161A, a second portion 161B, and a third portion 161C in a portion overlapping the non-emission area NLA. The first portion 161A, the second portion 161B, and the third portion 161C may be integrally formed.

[0168] In some embodiments, each of the first portions 161A may be located in a direction toward the emission area EA and in contact with the light-emitting element ED. The second portion 161B may be located between the plurality of first portions 161A and not in contact with the light-emitting element ED. The third portion 161C may be located between the first portion 161A and the second portion 161B and overlapped with the groove GRV of the embankment structure 160. The first portion 161A and the second portion 161B of the first embankment layer 161 included in the display device 30 may be spaced apart from each other in the first direction (X-axis direction), with the groove GRV interposed between the first portion 161A and the second portion 161B.

[0169] In some embodiments, the organic residual pattern EP may be located on the third portion 161C of the first bank layer 161. The organic residual pattern EP may include the same material as the light-emitting layer EL, the first organic pattern ELP1, and the second organic pattern ELP2. The second bank layer 163 includes a second tip TIP2 and a third tip TIP3. Thus, for example, the material forming the light-emitting layer EL is spaced apart from the first organic pattern ELP1, the second organic pattern ELP2, and the third organic pattern ELP3, so that the organic residual pattern EP may be formed.

[0170] The electrode residue pattern CP may be located on the organic residue pattern EP included in the display device 30. The electrode residue pattern CP may be located in a portion overlapping the third portion 161C of the first bank layer 161. The first electrode pattern CEP1, the second electrode pattern CEP2, the third electrode pattern CEP3, and the electrode residue pattern CP may all include the same material. The second bank layer 163 includes a second tip TIP2 and a third tip TIP3, so that, for example, the material forming the cathode electrode CE is spaced apart from the first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3, so that the electrode residue pattern CP may be formed.

[0171] In some embodiments, the second bank layer 163 included in the display device 30 may include a first subportion 163A and a second subportion 163B. The first subportion 163A may be located on and in contact with the first portion 161A of the first bank layer 161. In some aspects, the second subportion 163B may be located on and in contact with the second portion 161B of the first bank layer 161. The first subportion 163A and the second subportion 163B may be integrally formed during the manufacturing process of the display device 30. The first subportion 163A and the second subportion 163B may be spaced apart from each other in the first direction (X-axis direction) due to the formation of the groove GRV, with the groove GRV interposed between the first subportion 163A and the second subportion 163B. The first subportion 163A and the second subportion 163B of the second bank layer 163 may be electrically connected to each other via the first bank layer 161.

[0172] In some embodiments, the second sub-portion 163B of the second bank layer 163 may have a third tip TIP3 that protrudes more than the side surface 1h included in the second portion 161B of the first bank layer 161 in the first direction (X-axis direction). The second tip TIP2 and the third tip TIP3 may be located in a portion overlapping the groove GRV of the bank structure 160. As described herein, the organic residue pattern EP and the electrode residue pattern CP located on the third portion 161C of the first bank layer 161 may be separated from the first organic pattern ELP1, the second organic pattern ELP2, the first electrode pattern CEP1, and the second electrode pattern CEP2 by the second tip TIP2 and the third tip TIP3 included in the second bank layer 163.

[0173] In some embodiments, the organic pattern ELP and the electrode pattern CEP included in the display device 30 may not be located on the second sub-portion 163B. In the manufacturing process of the display device 30, the manufacturing steps may include forming the organic pattern ELP and the electrode pattern CEP on the second sub-portion 163B, and then removing the organic pattern ELP and the electrode pattern CEP (or portions of the organic pattern ELP and the electrode pattern CEP) on the second sub-portion 163B through a subsequent etching process. Thus, for example, the upper surface of the second sub-portion 163B may be exposed and may be in contact with the second encapsulation layer 172.

[0174] The first encapsulation layer 171 included in the display device 30 may be located on the cathode electrode CE and the electrode pattern CEP and may be in contact with the cathode electrode CE and the electrode pattern CEP. The first encapsulation layer 171 included in the display device 30 may entirely cover the first tip TIP1 and the second tip TIP2, and may partially cover the third tip TIP3. The first encapsulation layer 171 included in the display device 30 may entirely fill a portion overlapping the groove GRV of the embankment structure 160.

[0175] In other words, in the display device 30 , the dam structure 160 may include a plurality of grooves GRV in a portion overlapping the non-emission area NLA, and may include a first tip TIP1 , a second tip TIP2 , and a third tip TIP3 .

[0176] In the display device 30, the embankment structure 160 includes the first tip TIP1, so that, for example, the light emitting element ED located in the portion overlapping each emission area EA can be formed without using a separate fine metal mask. Therefore, for example, the embodiment of the present disclosure provides a high-resolution display device with highly integrated pixels.

[0177] In some aspects, the first encapsulation layer 171 included in the display device 30 may cover the tip TIP of the bank structure 160 and may entirely cover the organic pattern ELP and the electrode pattern CEP. Thus, for example, the display device 30 may resolve reliability defects caused by the penetration of oxygen and moisture during the manufacturing process.

[0178] The invention should not be construed as limited to the embodiments set forth herein. Rather, example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art.

[0179] While the invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit or scope of the invention as defined by the claims.

Claims

1. A display device, comprising: a substrate, including an emissive region and a non-emissive region; a first light-emitting element, located on the emission area of ​​the substrate; a pixel defining layer, located on the non-emitting area of ​​the substrate and defining a first opening; a bank structure, located on the pixel defining layer, defining a second opening and including a groove; and a first encapsulation layer, located on the first light-emitting element and the embankment structure; The embankment structure includes: a first embankment layer including a first side surface facing the emission region and a second side surface opposite to the first side surface; and a second embankment layer located on the first embankment layer and including a first tip protruding more toward the emission region than the first side surface and a second tip protruding more toward the groove than the second side surface, and The first encapsulation layer entirely covers the first tip and the second tip.

2. The display device according to claim 1 , further comprising a second light-emitting element spaced apart from the first light-emitting element, wherein the pixel defining layer and the embankment structure are disposed between the second light-emitting element and the first light-emitting element spaced apart from each other. in, The first light emitting element and the second light emitting element are in contact with the first bank layer.

3. The display device according to claim 2, wherein: The first light emitting element and the second light emitting element are electrically connected to each other through the first bank layer.

4. The display device according to claim 3, wherein: The first bank layer includes aluminum, and The second bank layer includes titanium.

5. The display device according to claim 4, wherein: In a plan view, the second opening entirely surrounds the first opening.

6. The display device according to claim 2, wherein: The first bank layer includes: a first portion in contact with the first light emitting element; a second portion in contact with the second light emitting element; and a third portion overlapping the groove. The first portion, the second portion and the third portion are integrally formed, and The third portion is located between the first portion and the second portion.

7. The display device according to claim 6, wherein: The third portion is spaced apart from the first encapsulation layer, and a space is interposed between the third portion and the first encapsulation layer in a direction perpendicular to the substrate.

8. The display device according to claim 7, further comprising a second encapsulation layer located on the first encapsulation layer. in, The third portion contacts the second encapsulation layer.

9. The display device according to claim 6, wherein: The second bank layer includes a first sub-portion located on the first portion of the first bank layer and a second sub-portion located on the second portion of the first bank layer, and The first subsection and the second subsection are spaced apart from each other in a direction parallel to the substrate.

10. The display device according to claim 9, wherein: The first encapsulation layer includes a first inorganic layer entirely covering the first sub-portion and a second inorganic layer entirely covering the second sub-portion, and The first inorganic layer and the second inorganic layer are spaced apart from each other in the direction parallel to the substrate.

11. The display device according to claim 1, wherein: The first light emitting element includes an anode electrode, a light emitting layer and a cathode electrode, and The light emitting layer and the cathode electrode are in contact with the first side surface.

12. The display device according to claim 11, further comprising: an organic pattern located on the second bank layer, comprising the same material as the light emitting layer, and spaced apart from the light emitting layer; as well as an electrode pattern, located on the organic pattern, comprising the same material as the cathode electrode and spaced apart from the cathode electrode, The organic pattern and the electrode pattern overlap with the first tip and the second tip.

13. The display device according to claim 12, wherein: The organic pattern and the electrode pattern are positioned such that the organic pattern and the electrode pattern surround the first opening, and The first encapsulation layer entirely covers the organic pattern and the electrode pattern.

14. The display device according to claim 11, further comprising a residual pattern, wherein the residual pattern is located between the anode electrode and the pixel defining layer in a direction perpendicular to the substrate. in, The residual pattern overlaps the first tip.

15. The display device according to claim 14, wherein The residual pattern contacts the light emitting layer.

16. The display device according to claim 1, wherein: The first bank layer includes: a first portion in contact with the first light emitting element; a second portion spaced apart from the first portion and not in contact with the first light emitting element; and a third portion overlapping the groove. The first portion, the second portion and the third portion are integrally formed, and The third portion is located between the first portion and the second portion.

17. The display device according to claim 16, wherein: The second bank layer includes a first sub-portion located on the first portion and a second sub-portion located on the second portion, and The first subsection and the second subsection are spaced apart from each other in a direction parallel to the substrate.

18. The display device according to claim 17, further comprising: an organic pattern and an electrode pattern located on the first sub-portion of the second bank layer; as well as an organic residual pattern and an electrode residual pattern located on the third portion of the first bank layer, wherein the organic pattern and the organic residual pattern are spaced apart from each other, and The electrode pattern and the electrode residual pattern are spaced apart from each other.

19. The display device according to claim 18, wherein: The first encapsulation layer entirely covers the electrode pattern and the electrode residual pattern.

20. A method for manufacturing a display device, the method comprising the following steps: forming a substrate including an emission region and a non-emission region, forming an anode electrode and a sacrificial layer on the emission region of the substrate, and forming a pixel defining layer and a dam structure on the sacrificial layer, wherein the dam structure includes a first dam layer and a second dam layer; exposing the anode electrode by removing the pixel defining layer and the embankment structure in a portion overlapping the emission region, and forming a groove by removing a portion of the embankment structure in a portion overlapping the non-emission region; forming a second bank layer including a first tip and a second tip by removing a portion of the bank structure, the first tip protruding more toward the emission region than a first side surface of the first bank layer, and the second tip protruding more toward the groove than a second side surface of the first bank layer; as well as A light emitting element is formed by forming a light emitting layer and a cathode electrode on the anode electrode and the bank structure, and an encapsulation layer entirely covering the first tip and the second tip is formed.

21. An electronic device, comprising a display device, the display device comprising: a substrate, including an emissive region and a non-emissive region; a first light-emitting element, located on the emission area of ​​the substrate; a pixel defining layer, located on the non-emitting area of ​​the substrate and defining a first opening; a bank structure, located on the pixel defining layer, defining a second opening and including a groove; and a first encapsulation layer, located on the first light-emitting element and the embankment structure; The embankment structure includes: a first embankment layer including a first side surface facing the emission region and a second side surface opposite to the first side surface; and a second embankment layer located on the first embankment layer and including a first tip protruding more toward the emission region than the first side surface and a second tip protruding more toward the groove than the second side surface, and The first encapsulation layer entirely covers the first tip and the second tip.

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