Multi-period modulation driving assembly, method, system and product

Abstract

The invention provides a multi-cycle modulation driving assembly, method, system and product. A control plane and hardware are decoupled by utilizing an SDN technology, a remote controller can realize storage unit data configuration and circuit logic device programming of different devices according to codes of controlled devices, and various periodic / non-periodic time sequence driving signals required by various device chips are provided; and the time sequence requirements of array driving and data reading of different equipment chips are met. The multi-cycle modulation driving assembly comprises a state division assembly, a synchronous multi-cycle configuration assembly and a single-cycle modulation assembly. The state division component is used for performing functional decoding according to the function mode of the equipment and generating a trigger signal matched with a time sequence according to the specific function mode; the synchronous multi-cycle configuration component is used for generating multiple types of cycle / non-cycle enable signals under different dominant frequencies according to the configuration information so as to realize multi-cycle time sequence driving; the single-cycle modulation assembly can be used as a universal modulation unit, and each unit can generate periodic in-compact time sequence driving signals according to configuration information and multi-cycle driving signals, so that the driving requirements of digital and analog reading units of different equipment chips are met. According to the invention, the overall time sequence structure of the driving chip can be greatly simplified, and the remote controller can realize the output of multi-period modulation driving signals in batches by using the programmable interconnection connection sub-module array generated by software; and the requirements of different devices on flexible configuration and real-time switching of periodic and non-periodic driving signals in multiple modes can be met without additional independent customized design. The design complexity is reduced, each module subunit can be configured with an independent time sequence outside a chip, the error-tolerant rate and flexibility of chip time sequence design are improved, and meanwhile the design period is shortened through reusability of multiple modules.

Description

Technical Field

[0001] The present invention provides a multi-cycle modulated driving component, a driving method, a driving system and a product, belonging to the field of digital integrated circuits. Background Art

[0002] Modern device chips with complex functions inevitably require drivers with complex multi-cycle timing. This places high demands on the timing alignment between front- and back-end modules in the hardware circuit. Timing becomes even more complex in pipeline operation. Consequently, complex multi-cycle timing driver circuits are often required to drive sequential digital and analog readouts, thus meeting the driving and readout requirements of complex device chips.

[0003] The current mainstream design approach for the drive and readout circuits of device chips is a top-down design method, which means first planning the top-level timing requirements, and then designing the previous and next stage circuits based on the timing. This approach requires first determining the hardware structure of the array drive circuit and readout circuit of the entire chip, then designing the timing, and finally designing the control logic that generates the timing. The circuit usually uses a complex counter module, which outputs a drive signal that meets the chip drive requirements through off-chip triggering of working signals and timing configuration information. This approach has complex on-chip circuit design, a large area, a long design cycle, and is often customized for special drive requirements. Timing adjustments are all fine-tuning of the state duration, and it is impossible to change the overall drive timing. The waveform controllable flexibility is low, and the subsequent verification manpower and docking costs are very high. Summary of the Invention

[0004] The present invention proposes a multi-cycle modulation drive component, drive method, drive system, and product. By utilizing technologies such as Software-Defined Networking (SDN) to decouple the control plane from the hardware, a remote controller can implement storage unit data configuration and circuit logic device programming for different controlled devices based on device coding, providing multiple periodic / non-periodic timing drive signals required by multiple controlled device chips, and compatibility with the timing requirements of driving and data reading of different device chip arrays. Using a software-generated programmable interconnection connecting submodule arrays, the remote controller can batch-produce multi-cycle modulation drive signal outputs. This eliminates the need for additional, individually customized designs and meets the flexible configuration and real-time switching of periodic and non-periodic drive signals required by different devices in multiple modes, reducing design complexity and design and verification costs, and enabling flexible configuration of drive signals across multiple devices and multiple modes. This drive component, drive method, drive system, and product not only meet the drive requirements of different device chips but also provide a drive solution for current satellite device programming and cloud device control. By converting digital drive signals into control signals, microprocessors and microcontrollers in different devices can drive various functions of electronic devices, such as controlling mechanical motion, processing data, and managing communications.

[0005] The technical solution adopted by the circuit of the present invention is as follows:

[0006] A multi-cycle modulation drive component and its driving method are characterized by utilizing, for example, SDN technology to separate the control plane from the hardware, utilizing a logically centralized remote controller, and configuring parameters of a multi-cycle modulation driven digital control circuit based on device coding information via a communication data interface between the control and hardware layers implemented through protocols such as OpenFlow. The drive component also transmits real-time data feedback back to the controller via a data feedback link, enabling flexible and efficient configuration of the hardware circuit. A software-generated programmable interconnected submodule array circuit includes a state partitioning component, a synchronous multi-cycle configuration component, and a single-cycle modulation component connected in sequence. The state partitioning component is configured to perform functional decoding based on a functional mode and generate a trigger signal that meets timing requirements based on the specific functional mode. The synchronous multi-cycle configuration component is configured to generate multiple types of periodic / non-periodic enable signals at different clock frequencies based on configuration information, thereby achieving multi-cycle sequential drive. The single-cycle modulation component, as a universal modulation unit, can generate a periodic, compound, on-chip sequential drive signal based on configuration information and a multi-cycle drive signal, thereby meeting the drive requirements of different device chips.

[0007] Furthermore, the remote controller can be a host computer or a cloud device. The multi-cycle modulation driver component based on SDN technology abstracts the underlying hardware devices into a virtualized resource pool, and the control is no longer tightly coupled with the hardware. Hardware technicians use remote controllers through OpenFlow, Serial Peripheral Interface (SPI), Inter-Integrated Circuit (IC) and other interfaces. 2 C) and other protocols to achieve the matching of the control layer and the communication data interface at the hardware layer, reorganize the data flow and data packet so that the feedback link can adjust the data packet and transmit it after receiving the information, and realize the storage unit data configuration and circuit logic device programming for different controlled devices.

[0008] Furthermore, the state division component is adapted to at least one digital input signal and one digital output signal, and is used to perform functional decoding according to the functional mode of the device chip and generate a timing matching trigger signal according to the specific functional mode; wherein the one digital input signal is data configuration information Config_Data1, which includes the chip's operating mode information and configuration parameters under different functional modes, the chip's operating mode information includes request information TriggerBegin requiring the controlled device to start; the configuration parameters under different functional modes may include, for example, at least one of the state durations of a reset state, an exposure state, a readout state, and a programming state; and the one digital output signal is a timing matching trigger signal MatchTriggerBegin transmitted to the synchronous multi-cycle configuration component;

[0009] Furthermore, the state division component includes a mode judgment logic module and a trigger delay module. The mode judgment logic module ModeJudge_Logic performs combinational logic judgment and configures, for example, the delay storage unit MatchNum based on the data configuration information Config_Data1; the trigger delay module TriggerDelay modulates the delay time of the external trigger signal and the cycle enable drive signal under different functional modes based on the configuration information of the delay storage unit and the request information TriggerBegin for the controlled device to start, and outputs the timing-matched trigger signal MatchTriggerBegin to the synchronous multi-cycle configuration component;

[0010] Furthermore, the synchronous multi-cycle configuration component is adapted to two digital input signals and two digital output signals, and is used to generate various types of periodic / non-periodic enable signals at different clock frequencies based on off-chip configuration information, and simultaneously realize multi-cycle timing drive on the chip; wherein the two digital input signals are the trigger signal MatchTriggerBegin and the data configuration information Config_Data2 from the state division component, respectively, and the two digital output signals are a set of one-dimensional array drive enable signals PeriodValid and one-dimensional array end signals ModeEnd that can characterize multiple period types of the chip. The drive enable signal PeriodValid and the end signal ModeEnd are preferably one-dimensional array signals, but this does not constitute a limitation. In fact, the drive enable signal PeriodValid and the end signal ModeEnd can also be two-dimensional arrays, for example, to input, output and process multiple related data combinations.

[0011] Furthermore, the synchronous multi-cycle configuration component includes a decoding module, k clock reset generation submodules, and k configuration submodules to implement multi-cycle enable modulation under the same clock frequency group, where k is the number of enable signals generated and is a positive integer. The remote controller can instantiate multiple synchronous multi-cycle configuration components through data communication, and each component can operate independently. The multiple synchronous multi-cycle configuration components can generate drive signals under different frequency groups, such as a Hz frequency group and a kHz frequency group. In a synchronous multi-cycle configuration component, the decoding module decodes and outputs data to the internal submodule based on its data configuration information Config_Data2, configures and selects the submodule, and the submodule that is not selected is in a standby state. The internal k submodules realize the generation of drive signals at different main frequencies in the same frequency group; the clock reset generation submodule provides stable and reliable clock signals and synchronous reset signals of different frequencies for the configuration submodule and the single-cycle modulation component in the same clock frequency group, ensuring that each module operates at a specific main frequency; the configuration submodule performs combinational logic judgment and configures the corresponding storage units PeriodNum, EnableNum and RepeatNum based on its data configuration information Config_Data2, realizes the timing configuration of periodic and non-periodic drive signals through counters PeriodCounter and RepeatCounter, realizes the timing configuration of periodic and non-periodic drive signals at a specific clock main frequency, and outputs the multi-periodic drive enable signal PeriodValid and end signal ModeEnd of the single-period modulation component.

[0012] Furthermore, the single-cycle modulation component is adapted to at least four digital input signals and at least one digital output signal as a modulation unit. Each modulation unit generates a periodic composite on-chip timing drive signal based on the off-chip signal type code and configuration information as well as the multi-cycle drive enable signal and end signal, thereby driving all subsequent digital and analog readout units; the four digital input signals are the signal type code Config_Type, the timing data configuration information Config_Data3 of the corresponding signal, the drive enable signal PeriodValid, and the end signal ModeEnd; the one digital output signal is the complex on-chip timing drive signal DriverSignal required by the chip's digital and analog readout units;

[0013] Furthermore, the single-cycle modulation component includes n driver submodules, responsible for generating multiple complex on-chip timing drive signals, where n is the number of drive signals generated and is a positive integer. The driver submodules, based on the input signal type code Config_Type, use combinational logic to determine the drive signal type and the number of high- and low-level toggle times. Upon receiving the input drive enable signal PeriodValid, they begin operation and modulate the generated drive signal DriverSignal via the state machine submodule. Based on the device code DeviceType in the data configuration information, a selector is used to output the modulated drive signal DriverSignal or directly output the enable signal PeriodValid.

[0014] The present invention employs a variety of storage units, such as a delay storage unit, an enable signal period storage unit, a high-level duration storage unit within a single cycle, and a single-cycle repetition count storage unit. These storage units can be general-purpose memory units, but registers are preferred. This has been demonstrated through research and simulation of the present invention's products.

[0015] The term "composite" in the composite chip timing drive signal, composite timing, composite multi-cycle drive signal, etc. involved in the scheme of the present invention refers to multiple parallel timing signals and multiple required compound drive signals, as well as the complicated timing form and signal waveform of a single timing signal.

[0016] The present invention further provides a driving method for a driving component using the multi-cycle modulation, the driving method comprising the following steps:

[0017] S1, data configuration is written. Hardware technicians can send instructions to network devices through programming languages. After receiving the instructions, the remote controller selects storage unit configuration information based on the device coding information. The controller realizes data communication with the hardware circuit through protocols such as OpenFlow, adjusts data transmission according to the information received in the feedback link, and realizes storage unit data configuration and circuit logic device programming of the CNC circuit driven by multi-cycle modulation for different devices.

[0018] S2, perform functional state division: the state division component receives the target device working mode code, corresponding functional mode timing and data configuration information Config_Data1, and the mode judgment logic module is set to configure the delay storage unit MatchNum; the trigger delay module is set to start working under the trigger of the external request information TriggerBegin signal based on the request for the controlled device to start. When its built-in counter counts to MatchNum, it outputs the trigger signal MatchTriggerBegin signal with timing matching, and the signal high level lasts for at least one clock cycle.

[0019] S3, configure the multi-cycle enable signal. The remote controller can instantiate multiple synchronous multi-cycle configuration components through data communication. After receiving the data configuration information Config_Data2 containing the submodule selection signal, main frequency selection signal, working status encoding information, timing configuration information and drive switching enable, the synchronous multi-cycle configuration component selects the submodule and performs data configuration via the combinational logic decoder. The submodules that are not selected are in standby state. The clock reset generation submodule selects the working main frequency based on the data configuration information, and provides stable and reliable clock signals of different frequencies and synchronous reset signals to the configuration submodule and the single-cycle modulation component, ensuring that each module operates at a specific main frequency. The configuration submodule judges and configures the enable signal period storage unit PeriodNum, the high level duration storage unit EnableNum within a single cycle and the single cycle repetition number storage unit RepeatNum through combinational logic based on the data configuration information; the k submodules instantiated by the synchronous multi-cycle configuration component start working after receiving the timing matching trigger signal MatchTriggerBegin, the counter PeriodCounter starts counting, and outputs the enable signal PeriodValid with a single cycle duration of PeriodNum and a high level duration of EnableNum within the cycle; after the counter RepeatCounter counts the single cycle repetition number of the enable signal to EnableNum, it outputs the mode end signal ModeEnd, and simultaneously realizes the multi-cycle drive enable of the subsequent k single-cycle modulation submodules on the chip.

[0020] S4 generates a modulation signal within a single cycle; the single-cycle modulation component receives the off-chip configuration information Config_Type and Config_Data3, determines the type and timing information of the drive signal through combinational logic, and configures the corresponding storage unit. The n sub-modules instantiated by the single-cycle modulation component operate under the same drive enable signal PeriodValid. When the drive enable signal PeriodValid is at a high level, the built-in counter and sub-state machine modulate PeriodValid into n periodic, complex on-chip timing drive signals DriverSignal. Based on the device code DeviceType in the data configuration information, the module uses a selector to output the modulated drive signal DriverSignal or directly output the enable signal PeriodValid, ultimately achieving timing drive of the digital and analog readout units of the entire chip.

[0021] The present invention proposes a multi-cycle modulated drive component and its driving method. Specifically, for example, the control plane is decoupled from the hardware using SDN technology, and the storage unit data configuration and circuit logic device programming of different controlled devices are realized by a remote controller according to the device coding. The sub-module array is connected by a programmable interconnect generated by software, and the remote controller can realize the output of multi-cycle modulated drive signals in batches. The digital control circuit decouples the original complex drive signal generation module on the chip and divides it into three hardware components, namely the status division component (StatusDivision), the synchronous multi-cycle configuration component (ConfigureBlock) and the single-cycle modulation component (ModuateBlock). By dividing the hardware functions and software programming, each module is flexible and adjustable, and can be combined to realize the flexible configuration and switching of the periodic / non-periodic drive signals of different device chips, meeting the complex driving requirements of digital and analog readout units in multiple devices and multiple modes. Since the three hardware components can realize functional configuration and hardware circuit programming according to the data configuration of the remote controller, the drive module can be designed in advance without determining the timing in advance, and is compatible with the timing requirements of driving and data reading of different device chip arrays. The synchronous multi-cycle configuration component and single-cycle modulation component have low hardware complexity, and sub-modules can be repeatedly instantiated in batches internally, significantly reducing the complexity of the driver module. Subsequent circuit design, circuit verification, and back-end design can all be performed in batches, significantly reducing design and verification costs. Accordingly, the driving method of the present invention includes data configuration writing, functional state division, synchronous multi-cycle enable configuration, and single-cycle drive configuration. This driving method can flexibly and efficiently configure complex drive signal timing.

[0022] In summary, the present invention, based on SDN technology, can provide flexible and reliable digital drives for different device chips through data configuration from a remote controller, improving the fault tolerance and flexibility of chip timing design. Compared with traditional solutions, the present invention shortens the design cycle while meeting complex drive requirements through flexible off-chip adjustability and multi-module reusability. It also reduces the difficulty of chip design and verification. By converting digital drive signals into control signals, the microprocessors and microcontrollers of different devices can drive various functions of electronic devices, such as controlling mechanical movement, processing data, and managing communications. At the same time, based on the programmable characteristics and flexible data configuration of this digital control circuit, it also provides a drive solution for current satellite equipment programming and cloud device control.

[0023] According to another aspect of the present invention, the present invention also discloses a system for multiple multi-cycle, multi-timing working processes, including various types of multi-cycle modulated driving components described in the present invention, which are used to generate composite multi-cycle driving signals for multiple controlled devices that control the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a block diagram of a digital control circuit of a multi-cycle modulated drive component in an embodiment of the present invention;

[0025] Figure 2 This is a functional configuration and hardware circuit programming block diagram of a multi-cycle modulation drive component in an embodiment of the present invention;

[0026] Figure 3 is a flow chart of a driving method of a driving component with multi-cycle modulation in an embodiment of the present invention;

[0027] Figure 4 is a timing diagram of a synchronous multi-cycle enable configuration in an embodiment of the present invention;

[0028] Figure 5 : is the modulation truth table of the driving signal in a single cycle in an embodiment of the present invention (taking 4 bits as an example);

[0029] Figure 6 This is a state sequence diagram of a sub-state machine of a single-cycle modulation component in an embodiment of the present invention;

[0030] Figure 7 1 is a timing diagram of timing modulation and periodic / non-periodic drive signal switching within a single cycle in an embodiment of the present invention;

[0031] Figure 8 The invention discloses a multi-cycle modulation driving system.

[0032] Figure 9 It is a multi-cycle modulation driver disclosed in the present invention. DETAILED DESCRIPTION

[0033] This embodiment provides a multi-cycle modulated drive component and its driving method. This circuit can utilize SDN technology to implement storage unit data configuration and circuit logic device programming for different devices based on device coding through a remote controller. By utilizing a software-generated programmable interconnection to connect the submodule array, the remote controller can batch-control the output of multi-cycle modulated drive signals at different clock frequencies. This drive component decouples the originally complex on-chip drive signal generation module and divides it into three components: a state division component, a synchronous multi-cycle configuration component, and a single-cycle modulation component. The state division component is used to perform functional decoding based on the functional mode and generate a timing-matched trigger signal based on the specific functional mode; the synchronous multi-cycle configuration component is used to generate multiple types of periodic / non-periodic enable signals at different main frequencies based on the configuration information, thereby achieving multi-cycle sequential drive; and the single-cycle modulation component, as a universal modulation unit, can generate a periodic composite on-chip sequential drive signal based on the configuration information and the multi-cycle drive signal, thereby meeting the drive requirements of different device chips.

[0034] This embodiment provides a multi-cycle modulation driving method, the steps of the flow chart are as follows: Figure 1 As shown ( Figure 1 MatchTriggerBegin is the trigger signal for timing matching; PeriodValid is the drive enable signal of the single-cycle modulation component, which is usually an array; ModeEnd is the end signal of the single-cycle modulation component, which is usually an array; DriverSignal is the final output drive signal, which is usually an array).

[0035] Figure 2 The functional configuration of the drive component and the hardware circuit programming block diagram are shown. Hardware technicians use TopControl (e.g., remote controller, host computer, etc.) to implement control-level and hardware-level communication data interfaces through protocols such as OpenFlow. Based on information received from the feedback link, they adjust transmission data to implement storage unit data configuration and circuit logic device programming for different controlled devices. The software-generated programmable interconnected submodule array circuit includes a state partitioning component 120, a synchronous multi-cycle configuration component 121, and a single-cycle modulation component 122 connected in sequence. This can meet the needs of different devices for flexible configuration and real-time switching of periodic and non-periodic drive signals in multiple modes.

[0036] Reference Figure 2Functional configuration of the drive component and hardware circuit programming block diagram: First, the remote controller 110 configures the parameters of the multi-cycle modulated drive component 111 (including: state division component 120, synchronous multi-cycle configuration component 121 and single-cycle modulation component 122) according to the coded information Device_fN (N=0, 1, ..., K-1, K is a positive integer) of the controlled device 123 through the control layer and hardware layer communication data interface implemented by protocols such as OpenFlow. The digital control circuit of the drive component 111 also sends real-time data feedback to the remote controller 110 through the data feedback link to achieve flexible and effective configuration of the hardware circuit. Then the functional state decoding is performed. Figure 3 The input to the state division component 120 is the data configuration signal Config_Data1. The mode judgment logic module 130 (ModeJudge_Logic) performs functional decoding based on the Config_Data1 signal, then performs combinational logic judgment and configures a delay storage unit. The delay value in the configured delay storage unit is represented by MatchNum to meet the requirements of synchronous triggering between modules in different modes. The trigger delay module 131 (TriggerDelay) begins operation after receiving the TriggerBegin signal, a request for the controlled device to start, in the external configuration information Config_Data1. After its built-in counter counts to MatchNum, it outputs a timing-matching trigger signal, MatchTriggerBegin, whose high-level duration is typically at least greater than a predetermined value (e.g., one clock cycle), to ensure the normal operation of the synchronous triggering process. It should be noted that the high-level duration of the timing-matching trigger signal MatchTriggerBegin does not necessarily have to be greater than one clock cycle; it can be longer or relatively shorter, as long as the synchronous triggering process can proceed normally.

[0037] Next, the multi-cycle enable signal is configured. Synchronous multi-cycle configuration component 121 generates various types of periodic and aperiodic drive enable signals at different clock frequencies based on off-chip configuration information, enabling multi-cycle sequential drive on-chip. The inputs to synchronous multi-cycle configuration component 121 are the MatchTriggerBegin signal and the external data configuration signal Config_Data2. In the synchronous multi-cycle configuration component 121, the decoding module 132 (Decoder) decodes according to its data configuration information Config_Data2 and outputs the decoded data to the internal sub-modules (such as the clock reset generation sub-module 133 (CRG) and the configuration sub-module 134 (ConfigureBlock)) to configure and select the sub-modules, while the sub-modules that are not selected are in standby state, and the internal k sub-modules realize the generation of driving signals at different main frequencies in the same frequency group; each sub-module performs combinational logic judgment and configures the enable signal period storage unit (the configured value of which is represented by PeriodNum), the high level duration storage unit in a single cycle (the configured value of which is represented by EnableNum) and the single cycle repetition number storage unit (the configured value of which is represented by RepeatNum) based on the off-chip configuration information (such as the above-mentioned data configuration information Config_Data2). The submodule begins operating after receiving the trigger signal MatchTriggerBegin. The counter PeriodCounter begins counting and outputs the enable signal PeriodValid, which has a single-cycle duration of PeriodNum and a high-level duration of EnableNum within the cycle. After the counter RepeatCounter counts the number of single-cycle repetitions of the enable signal to EnableNum, it outputs the mode end signal ModeEnd. Based on the switching enable of periodic drive and non-periodic drive, the switching between periodic drive and non-periodic drive can be flexibly controlled. The output PeriodValid signal serves as the enable signal for the subsequent single-cycle modulation component. Only the selected ConfigureBlock will work, and the unselected ConfigureBlock will be in standby mode. The output ModeEnd signal is the end signal of the controlled device's operating mode, which is fed back to the state division component and output to the single-cycle modulation component to perform a Clear operation on the storage unit within the component and shut down the output drive signal.

[0038] Finally, the single-cycle drive signal modulation is generated. The single-cycle modulation component 122 can, for example, instantiate n driver submodules 135, all of which operate under the same driver enable signal PeriodValid. The single-cycle modulation component 122 receives the off-chip configuration information Config_Type and Config_Data3, determines the type and timing information of the drive signal through combinational logic, and configures the corresponding storage unit. The n submodules operate when the enable signal PeriodValid is at a high level. The built-in counter and sub-state machine modulate PeriodValid into n periodic composite on-chip timing drive signals DriverSignal. The built-in selector of the submodule can select modulated output or non-modulated output according to the device model DeviceType, ultimately realizing the timing drive of the digital and analog readout units of the controlled device chip.

[0039] The specific module block diagram of the digital control circuit of the driving component provided in this embodiment is as follows Figure 3 As shown, in Figure 3 Config_Data1, Config_Data2, Config_Data3 and Config_Type are off-chip configuration parameters; ModeJudge_Logic is the mode judgment logic module; TriggerDelay is the trigger delay module; MatchNum is the delay value configured by the delay storage unit; MatchTriggerBegin is the trigger signal for timing matching; Decorder is the decoding module; CRG is the clock reset generation submodule; ConfigureBlock is the configuration submodule; PeriodValid is the single-cycle modulation component enable signal; ModeEnd is the mode end signal; ClockSwitch is the clock switching module; Synchronous is the synchronizer; Period dCounter is a period duration counter module; RepeatCounter is a repetition counter module; PeriodNum is the value configured for the enable signal period storage unit; EnableNum is the value configured for the high level duration storage unit within a single cycle; RepeatNum is the value configured for the single cycle repetition storage unit, which can be used to indicate the number of repetitions of the enable signal period; DriverBlock is a single cycle driver submodule; Judge_Logic is a combinational logic judgment module; Modulate_Counter is a high and low level delay time counter; State_Counter is a signal flip count counter; FSM is a sub-state machine; DeviceType is the device chip number; DriverSignal is the drive signal.

[0040] The state division component includes one digital input signal and one digital output signal. The digital input signal is data configuration information Config_Data1, and the digital output signal is a timing matching trigger signal MatchTriggerBegin. The data configuration information Config_Data1 includes the operating mode information of the controlled device chip and configuration parameters for different functional modes. The device chip's operating mode information includes the request message TriggerBegin for the controlled device chip to start up, as well as chip operating mode information, such as at least one of gradient mode, grayscale mode, programming mode, and color image mode. The configuration parameters for different functional modes include the state duration of at least one of the reset state, exposure state, readout state, and programming state. The state division component 120 includes a mode judgment logic module 130 and a trigger delay module 131. The mode determination logic module 130 uses combinational logic to determine the current operating mode of the device chip based on the off-chip data configuration information Config_Data1 and configures the delay storage unit (such as the value MatchNum) according to the configuration parameters for different functional modes. The trigger delay module 131 begins operation after receiving the TriggerBegin signal requesting the controlled device to start. It generates trigger signals for timing matching in different functional modes through counter counting. When the counter reaches MatchNum, it outputs the trigger signal MatchTriggerBegin for the timing matching of the synchronous multi-cycle configuration component.

[0041] The synchronous multi-cycle configuration component includes two digital input signals and two digital output signals. The two digital input signals are a trigger signal (MatchTriggerBegin) and data configuration information (Config_Data2), respectively. The two digital output signals are a set of drive enable signals (PeriodValid) and end signals (ModeEnd) that can represent various cycle types of the controlled device chip. The drive enable signal (PeriodValid) and end signal (ModeEnd) are preferably one-dimensional array signals, but this is not a limitation. The MatchTriggerBegin signal is a trigger signal that meets timing requirements. The Config_Data2 signal includes configuration parameters for the corresponding mode, such as at least one of full sampling, downsampling, windowing, and windowing position; single-cycle time and high-level delay time; switching between periodic and non-periodic drive; submodule selection information; and a clock frequency selection signal. The synchronous multi-cycle configuration component 121 includes a decoding module 132, k clock reset generation submodules 133, and k configuration submodules 134, where k is a positive integer. For example, the remote controller can communicate data by adopting multiple synchronous multi-cycle configuration groups, and each component can work independently to realize the generation of driving signals under different clock frequency groups, such as Hz frequency group, KHz frequency group, etc. In a synchronous multi-cycle configuration component, the decoding module 132 performs data configuration and gating on k submodules (such as the clock reset generation submodule 133 (CRG) and the configuration submodule 134 (ConfigureBlock)) based on the data configuration information Config_Data2, and the submodules that are not gated are in standby state. The k clock reset generation submodules can flexibly select the working clock frequency of the configuration submodule and the single-cycle modulation component based on the clock frequency selection information, thereby realizing the generation of driving signals under different clock frequencies in the same frequency group. The ClockSwitch module selects the working frequency based on the clock frequency selection information, and the reset and trigger signals are synchronized by the Synchronous module and input into the subsequent configuration submodule and the single-cycle modulation component. The k configuration submodules can independently configure different period / non-periodic modulation enable signals by off-chip configuration parameters. The ConfigureBlock submodule includes a combinational logic judgment module and two key counters, PeriodCounter and RepeatCounter. The combinational logic judgment module is responsible for configuring the storage unit, while the PeriodCounter and RepeatCounter counters are responsible for driving the period count and the number of cycles count, respectively.The specific drive process of the configuration submodule is as follows: The off-chip adjustable Config_Data2 signal input combination logic judgment module configures the key storage unit for the two counters PeriodCounter and RepeatCounter to store the enable signal period length (PeriodNum), the high level duration within the period (EnableNum), and the number of period repetitions (RepeatNum) based on the configuration parameters of the device's current mode, such as full sampling, downsampling, windowing, and windowing position. RepeatCounter is a row counter. For example, for full resolution, this counter needs to count to n, while for downsampling 2x, it needs to count to n / 2. PeriodCounter is a signal period counter. This module calculates the corresponding drive signal period based on the enable signal period. When the counter reaches a predetermined value, it will be cleared and RepeatCounter will be incremented by one. After the ConfigureBlock module receives the trigger signal MatchTriggerBegin, the PeriodCounter counter begins operating and the PeriodValid signal goes high. When the counter reaches the preset value EnableNum, the PeriodValid signal goes low and continues counting. When the counter reaches the preset value PeriodNum, the counter is cleared and RepeatCounter increments by one. The PeriodValid signal persists throughout the entire mode operation phase until RepeatCounter reaches RepeatNum. The off-chip periodic / non-periodic switching enable input controls the selection of submodule drive signals, enabling flexible switching between periodic drive enable and non-periodic drive enable. The Synchronous Multi-Period Configuration component can instantiate multiple submodules to implement, for example, Figure 4 The driving signal PeriodValid is a multi-period type shown.

[0042] Reference Figure 4 Based on the configuration data of the controlled device, the synchronous multi-cycle configuration component selects the operating clock frequencies CLK_0, CLK_1, and so on for the corresponding configuration submodules through multiple CRG modules. The configuration submodules use the period counter PeriodCounter to count the periods of the periodic drive enable signals, such as Period1, Period2, Period3, and so on. The high-level duration (EnableNum) within a period controls the high level of the drive enable signal, and the low-level duration is obtained by subtracting the enable signal period duration (PeriodNum) from the high-level duration (EnableNum) within the period. The period repetition counter RepeatCounter counts the periods of the drive enable signal and outputs the end signal ModeEnd when the count reaches RepeatNum.

[0043] The single-cycle modulation component includes four digital input signals and one digital output signal. The four digital input signals are the signal type code Config_Type, the corresponding signal's timing data configuration information Config_Data3, the drive enable signal PeriodValid, and the end signal ModeEnd. The one digital output signal is the DriverSignal signal, which is required for the composite on-chip timing drive required by the digital and analog readout units of the controlled device chip. The single-cycle modulation component 122 includes n driver modulation submodules 135. Individual submodules can be instantiated in batches, and each submodule can be independently configured using off-chip configuration parameters to achieve composite on-chip timing drive within a single cycle, where n is the number of drive signals generated and is a positive integer. The DriverBlock submodule includes a combinational logic judgment module, a sub-state machine FSM, a high- and low-level delay time counter Modulate_Counter, and a signal flip count counter State_Counter. Based on the input signal type code Config_Type, the submodule uses combinational logic to determine the type of drive signal generated and the number of high- and low-level flips, and configures the corresponding storage unit. The highest bit of the input signal type code (Config_Type) passes through the first-level selector in the combination judgment logic (Judge_Logic) to determine the initial level of the drive signal. If it is 1, the initial level is high; if it is 0, the initial level is low. The other bits pass through the second-level selector in the combination judgment logic (Judge_Logic) to determine the number of high-low level toggle times. The submodule's built-in selector selects modulated or non-modulated output based on the device model (DeviceType), ultimately meeting the complex driving requirements of the digital and analog readout units of different device chips at different clock frequencies.

[0044] Figure 5 The modulation truth table of the driving signal in a single cycle is shown, taking 4 bits as an example. The highest bit of Config_Type determines the initial level, and the remaining bits determine the flipping change of the driving signal. Config_Type is not limited to 4 bits and can be any other multi-bit data. The sub-state machine modulates and generates the driving signal DriverSignal based on the input enable signal PeriodValid and the configured storage unit. After the sub-state machine receives PeriodValid, Modulate_Counter starts counting. After the counter counts to a predetermined value, it is cleared to zero. The state machine output state flips and State_Counter is increased by 1. After State_Counter counts to a predetermined value, it enters the next cycle. The driving signal DriverSignal output by the state machine will continue throughout the entire mode working phase.

[0045] The sub-state machine module is as follows Figure 6As shown in the figure, there are four states: S0 (standby state), S1 (high level state), S2 (low level state), and S3 (end state). It is necessary to jump to the corresponding state according to the type of signal and the number of high and low level flips. If you want to achieve a periodic drive signal output with a low starting level and 4 flips within a cycle, you need to implement a state cycle from S0 to S2 to S1 to S2 to S1 to S3. The generation of the drive signal is as follows Figure 7 DriverSignal2 in Figure 7; To switch from a periodic signal to a non-periodic drive signal, with the non-periodic drive signal starting at a high level and flipping between high and low levels three times, an off-chip input switch enable signal SwitchEnable is required to implement a state cycle from S0 to S1 to S2 to S1 to S3. The drive signal is generated as in the non-periodic stage of DriverSignal2 in Figure 7. The timing data configuration information Config_Data3 of the corresponding signal is input, and the built-in counter of the single-cycle modulation component is used to generate the state machine transition trigger signals CounterDone and EndStateValid, thereby achieving periodic composite on-chip timing drive signal output.

[0046] Figure 7 The timing diagram of timing modulation and periodic / non-periodic drive signal switching within a single cycle is shown. Figure 7 , using the enable signal PeriodValid_0 output by the synchronous multi-cycle configuration component as the drive enable of the single-cycle modulation component, the configuration implements the timing diagram for the generation of periodic composite on-chip timing drive signals. The single-cycle modulation component can start working when the enable signal is high based on the off-chip configuration information Config_Data3 and Config_Type, and modulate the drive timing signal to achieve a constant high level, a constant low level, and a complex timing drive signal DriverSignal within a single cycle. For example, when Config_Type is 3'b101, the single-cycle modulation component uses the sub-state machine to modulate PeriodValid_0 into the DriverSignal_0 drive signal output based on the high and low level duration in Config_Data3. When Config_Type is 3'b111, PeriodValid_0 is modulated into the DriverSignal_1 drive signal output. Refer to Figure 7 The single-cycle modulation component, based on the off-chip input signal SwitchEnable, enables flexible modulation of both periodic and aperiodic drive. The enable time for aperiodic drive can be independently configured. If modulation is not enabled, the output is the timing of the DriverSignal_0 drive signal during the aperiodic phase. If modulation is enabled, the output is the timing of DriverSignal_1, DriverSignal_2, and so on during the aperiodic phase.

[0047] Figure 8 A multi-cycle modulation drive system is shown. The drive system includes a remote controller (for example, a host computer, etc.), a cloud, a software-defined network, and a controlled device. The multi-cycle modulation drive component based on SDN technology abstracts the underlying hardware devices into a virtualized resource pool. Hardware technicians can use the remote controller to match the control layer and the hardware layer communication data interface through the cloud or peripheral interface to achieve storage unit data configuration and circuit logic device programming for different controlled devices. The drive component based on SDN technology includes a state division component, k multi-cycle configuration components, and n single-cycle modulation components. Figure 8 , a state division component can trigger k multi-cycle configuration components according to the configuration information, and realize the modulation of the delay time of the external trigger signal and the cycle enable drive signal under different clock main frequencies and different functional modes. Figure 8 In the example, a multi-cycle configuration component _k-1 can drive n single-cycle modulation components and generate n modulated driving signals, thereby realizing the driving of multiple device chips.

[0048] Figure 9 A driver program (i.e., a computer program product) for multi-cycle modulation is presented. Hardware technicians can utilize a remote controller to communicate between the control layer and the hardware layer, either through the cloud or an external interface using protocols such as OpenFlow, based on the driving requirements of different device chips. This allows them to adjust transmission data based on feedback received through a feedback link, enabling configuration of storage unit data (Config_Data1, Config_Data2, Config_Data3, and Config_Type) and programming of circuit logic components for different controlled devices. The software-generated hardware circuit comprises a state partitioning component, a synchronous multi-cycle configuration component, and a single-cycle modulation component, all connected in sequence. Upon receiving the TriggerBegin signal contained in Config_Data1, requesting the controlled device to start, the state partitioning component initiates its built-in counter and outputs a MatchTriggerBegin signal that meets timing requirements to the synchronous multi-cycle configuration component. The synchronous multi-cycle configuration component configures the timing of periodic and aperiodic drive signals at a specific clock frequency, outputting the multi-cycle drive enable signal PeriodValid and the end signal ModeEnd for the single-cycle modulation component. Finally, the single-cycle modulation component modulates the PeriodValid signal using the configuration information to output a complex drive signal for multiple device chips. The computer program product includes a computer program that can be executed by a processor to implement the multi-cycle modulation driving method as described above.

Claims

1. A multi-cycle modulated driving component for generating multi-cycle driving signals for a plurality of controlled devices at the back end, characterized in that: The driving component includes a state division component, a synchronous multi-cycle configuration component and a single-cycle modulation component connected in sequence; and 1) The state division component is configured to: modulate the request information for the controlled device to start up to meet the requirements of synchronous triggering or asynchronous triggering of the timing; the state division component includes a mode judgment logic module ModeJudge_Logic and a trigger delay module TriggerDelay, and is adapted to at least one digital input signal and one digital output signal for performing functional decoding according to the functional mode of the controlled device and generating a timing matching trigger signal according to the functional mode of the controlled device; the at least one digital input signal is data configuration information Config_Data1, which includes operating mode information of the driving component and configuration parameters under different functional modes, wherein the operating mode information of the driving component includes request information TriggerBegin for requesting the controlled device to start up, and the configuration parameters under different functional modes include at least one of the duration of a reset state, an exposure state, a readout state, and a programming state; the at least one digital output signal is a timing matching trigger signal MatchTriggerBegin transmitted to the synchronous multi-cycle configuration component; and, The mode judgment logic module ModeJudge_Logic is configured to perform combinational logic judgment and configure the delay storage unit (MatchNum) according to the data configuration information Config_Data1; The trigger delay module TriggerDelay is configured to modulate the delay time of the external trigger signal and the cycle enable drive signal in different functional modes according to the configuration information of the delay storage unit (MatchNum) and the request information TriggerBegin, and output the trigger signal MatchTriggerBegin that meets the timing requirements to the synchronous multi-cycle configuration component; 2) The synchronous multi-cycle configuration component is configured to generate a multi-cycle / non-cycle drive enable signal based on the configuration information and the trigger signal at the operating clock frequency of different controlled devices; The synchronous multi-cycle configuration component is configured to adapt to at least two digital input signals and at least two digital output signals, so as to generate multiple types of periodic / non-periodic enable signals based on off-chip configuration information, and simultaneously implement multi-cycle timing drive on the chip; wherein the at least two digital input signals are respectively a trigger signal MatchTriggerBegin from the state division component and data configuration information Config_Data2 from off-chip, and the at least two digital output signals are a set of drive enable signals PeriodValid and end signals ModeEnd that can represent multiple cycle types of the chip; Among them, the synchronous multi-cycle configuration component includes a decoding module, k clock reset generation submodules and k configuration submodules, wherein the decoding module decodes according to the data configuration information Config_Data2 and outputs the decoded data to the k clock reset generation submodules and k configuration submodules to perform data configuration and selection on at least one submodule of the k clock reset generation submodules and k configuration submodules; each submodule of the k clock reset generation submodules and k configuration submodules generates different periodic / non-periodic drive enable signals PeriodValid according to the off-chip configuration information configuration to realize multi-cycle enable modulation under the same clock frequency group , where k is the number of drive enable signals generated, and k is a positive integer; the synchronous multi-cycle configuration component performs combinational logic judgment and configures the corresponding enable signal period storage unit (PeriodNum), the high level duration storage unit (EnableNum) within a single cycle, and the single cycle repetition count storage unit (RepeatNum) according to the data configuration information Config_Data2, and implements the timing configuration of the periodic and / or non-periodic drive signals through the counters PeriodCounter and RepeatCounter, outputs a multi-cycle drive enable signal PeriodValid and an end signal ModeEnd for a single-cycle modulation component, and 3) The single-cycle modulation component is configured to modulate and output a composite drive signal required by the controlled device chip based on configuration information and a drive enable signal; the single-cycle modulation component is adapted to at least four digital input signals and at least one digital output signal; the single-cycle modulation component generates a periodic composite on-chip timing drive signal based on an off-chip signal type code and configuration information as well as a multi-cycle drive enable signal PeriodValid and an end signal ModeEnd, thereby driving the digital and analog readout units in the controlled device chip; the four digital input signals are respectively a signal type code Config_Type, a corresponding signal timing data configuration information Config_Data3, a drive enable signal PeriodValid, and an end signal ModeEnd; the one digital output signal is a complex on-chip timing drive signal DriverSignal required by the digital and analog readout units in the controlled device chip; and, The single-cycle modulation component includes n driving submodules, which are responsible for generating multiple complex on-chip timing driving signals, where n is the number of driving signal generation and is a positive integer; and Each of the n driver sub-modules includes a state machine sub-module and a selector. According to the input signal type code Config_Type, the type of the drive signal and the number of high and low level flips are determined through combinational logic. According to the input drive enable signal PeriodValid, the state machine sub-module modulates and generates an on-chip timing drive signal DriverSignal; according to the device code DeviceType in the input timing data configuration information, the selector realizes the output of the on-chip timing drive signal DriverSignal or the output of the drive enable signal PeriodValid.

2. The multi-cycle modulated driving component according to claim 1, characterized in that: The digital input signal of the state division component also includes the request information TriggerBegin of the controlled device starting and the end signal ModeEnd; The TriggerBegin information is the request information for starting the controlled device. After receiving the TriggerBegin information, the state division component performs modulation according to the data configuration information Config_Data1 to meet the synchronous triggering or asynchronous triggering requirements of the working timing of the controlled device chip; the end signal ModeEnd is the end signal of the controlled device working mode, which is fed back to the state division component and output to the single-cycle modulation component to clear the storage units in the state division component and the single-cycle modulation component and turn off the output drive signal.

3. The multi-cycle modulated driving component according to claim 1 or 2, characterized in that: The storage unit is a register.

4. A multi-cycle modulated drive system, which includes multiple composite cycle processes during operation, characterized in that: The driving system comprises the multi-cycle modulated driving component according to claim 1 or 2, so as to generate multi-cycle driving signals for a plurality of controlled devices controlling the driving system.

5. A multi-cycle modulation driving method, characterized in that: A state division component, a synchronous multi-cycle configuration component, and a single-cycle modulation component are connected in sequence. The state division component includes a mode judgment logic module and a trigger delay module, and the driving method includes the following steps: S1, perform functional state division: after the state division component receives the data configuration information Config_Data1 containing the working mode code of the controlled device, the corresponding functional mode timing and data configuration, the mode judgment logic module is configured to configure the delay storage unit based on the data configuration information Config_Data1, and the delay value in the delay storage unit is represented as MatchNum; the trigger delay module is configured to start working under the trigger of the trigger signal of the request information TriggerBegin based on the request information requiring the controlled device to start in the external configuration information Config_Data1, and when its built-in counter counts to MatchNum, it outputs the trigger signal MatchTriggerBegin with matching timing, and the duration of the high level of MatchTriggerBegin is greater than the predetermined value, so that the synchronous trigger process can proceed normally. S2, configure the multi-cycle enable signal. After receiving the data configuration information Config_Data2 of the controlled device, the synchronous multi-cycle configuration component performs combinational logic judgment and configures the enable signal period storage unit, the high-level duration storage unit in a single cycle, and the single-cycle repetition number storage unit, wherein the value configured in the enable signal period storage unit is represented as PeriodNum, the value configured in the high-level duration storage unit in a single cycle is represented as EnableNum, and the value configured in the single-cycle repetition number storage unit is represented as RepeatNum; the k sub-modules instantiated by the synchronous multi-cycle configuration component start working after receiving the timing matching trigger signal MatchTriggerBegin, the counter PeriodCounter starts counting and outputs the enable signal PeriodValid with a single-cycle duration of PeriodNum and a high-level duration of EnableNum in a single cycle; after the counter RepeatCounter counts the single-cycle repetition number of the enable signal to EnableNum, it outputs the end signal ModeEnd, so as to simultaneously realize the multi-cycle drive enable of the subsequent k single-cycle modulation sub-modules on the chip. S3, generates a modulation signal within a single cycle; after receiving the off-chip configuration information Config_Type and Config_Data3, the single-cycle modulation component determines the type and timing information of the drive signal through combinational logic, and configures the corresponding storage unit; the n sub-modules instantiated by the single-cycle modulation component operate under the same drive enable signal PeriodValid, and operate when the drive enable signal PeriodValid is at a high level. The built-in counter and sub-state machine modulate PeriodValid into n periodic composite on-chip timing drive signals DriverSignal to realize the timing drive of the digital and analog readout units of the controlled device chip.

6. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the driving method as claimed in claim 5 is implemented.

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