Semiconductor device

Abstract

A small semiconductor device is provided. The semiconductor device includes a CPU, a switching circuit, and a plurality of memory cell arrays. The CPU includes a register circuit. The register circuit includes a volatile flip-flop circuit and a non-volatile backup circuit. A flip-flop circuit and a circuit other than a backup circuit included in another CPU are provided in a first layer, and include a transistor including silicon in a channel formation region. The switching circuit and the backup circuit are disposed in a second layer on the first layer, and include a transistor including a metal oxide in a channel formation region. The memory cell array in which data is written or the memory cell array in which data is read can be selected through the switching circuit. In addition, a selection result of the memory cell array to which data is written or the memory cell array to which data is read may be held in the switching circuit.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device. Another embodiment of the present invention relates to a memory device. Another embodiment of the present invention relates to a method for driving a semiconductor device. Another embodiment of the present invention relates to a method for driving a memory device.

[0002] Note that in this specification and other documents, a semiconductor device refers to any device that can operate by utilizing semiconductor properties. In addition to semiconductor elements such as transistors, semiconductor circuits, computing devices, and storage devices are examples of semiconductor devices. Display devices (such as liquid crystal display devices and light-emitting display devices), projection devices, lighting devices, electro-optical devices, power storage devices, storage devices, semiconductor circuits, imaging devices, and electronic devices are sometimes said to include semiconductor devices.

[0003] One embodiment of the present invention is not limited to the above-mentioned technical field. One embodiment of the invention disclosed in this specification and the like relates to an object, method, or manufacturing method. In addition, one embodiment of the present invention relates to a process, machine, product, or composition of matter. Background Art

[0004] Semiconductor circuits (IC chips) such as CPUs (Central Processing Units) and memories are mounted on printed circuit boards and used as components in various electronic devices. Furthermore, technology that uses semiconductor thin films to form transistors has attracted attention. These transistors are already used in electronic devices such as image display devices (sometimes simply referred to as display devices), and their application in these semiconductor circuits is expected.

[0005] Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors, while metal oxides are attracting attention as other materials. It is known that transistors using metal oxides have extremely low current flowing when they are in a non-conducting state (off state).

[0006] For example, Patent Document 1 discloses a memory device that utilizes the low leakage current characteristic of a transistor made of a metal oxide to achieve long-term retention of stored data.

[0007] In recent years, with the miniaturization and weight reduction of electronic devices, there has been an increasing demand for higher density integrated circuits. For example, Patent Document 2 and Non-Patent Document 1 disclose a technology that achieves higher density integrated circuits by stacking a first transistor using a metal oxide film and a second transistor using a metal oxide film to provide a plurality of overlapping memory cells.

[0008] Furthermore, if vertical transistors can be realized, integrated circuits can be made more dense. For example, Patent Document 3 discloses a vertical transistor in which the side surfaces of a metal oxide are covered with a gate electrode via a gate insulating layer. [Prior technical literature] [Patent Document]

[0009] [Patent Document 1] Japanese Patent Application Publication No. 2011-151383 [Patent Document 2] International Patent Application Publication No. 2021 / 053473 [Patent Document 3] Japanese Patent Application Publication No. 2013-211537 [Non-patent literature]

[0010] [Non-Patent Literature 1] M. Oota et al., “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm,” IEDM Tech. Dig., 2019, pp. 50-53 Summary of the Invention Technical problem to be solved by the invention

[0011] The on-state current of a transistor containing silicon, specifically, a transistor containing silicon in a channel formation region (also referred to as a Si transistor) is sometimes greater than that of a transistor containing a metal oxide, specifically, a transistor containing a metal oxide in a channel formation region (also referred to as an OS transistor). For example, the on-state current of a Si transistor containing silicon with high crystallinity such as single crystal silicon or polycrystalline silicon in a channel formation region is greater than that of an OS transistor. Therefore, for example, the transistor included in the CPU is preferably a Si transistor. For example, Si transistors are preferably used as a control circuit having a function of controlling the drive of the CPU and a register circuit having a function of holding data used for the calculation of the CPU.

[0012] The register circuit includes a flip-flop circuit, which can hold data. However, when the power supply voltage to the flip-flop circuit stops, the held data disappears. Therefore, by providing a nonvolatile backup circuit in the register circuit and backing up the data in the flip-flop circuit, data can be restored even if the flip-flop circuit loses data. This allows power gating of the CPU, reducing the power consumption of the semiconductor device including the CPU. For example, an OS transistor, whose off-state current is lower than that of a Si transistor, is preferably used as the backup circuit.

[0013] As described above, it is preferable to use Si transistors for the control circuits and trigger circuits included in the CPU, and OS transistors for the backup circuits. In this case, for example, the control circuits and trigger circuits are provided in the first layer, and the backup circuits are provided in the second layer above the first layer. Here, for example, if the backup circuit included in the CPU is provided in the second layer and the circuits other than the backup circuit are provided in the first layer, the number of transistors and other components provided in the second layer is less than the number of transistors and other components provided in the first layer. Therefore, the dead space (area where no components are provided) in the second layer is larger than that in the first layer.

[0014] One of the objects of one embodiment of the present invention is to provide a semiconductor device with a small dead space. Another object of one embodiment of the present invention is to provide a small semiconductor device. Another object of one embodiment of the present invention is to provide a low-power semiconductor device. Another object of one embodiment of the present invention is to provide a high-speed driven semiconductor device. Another object of one embodiment of the present invention is to provide a highly integrated semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device with good electrical characteristics. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device. Another object of one embodiment of the present invention is to provide a novel semiconductor device. Another object of one embodiment of the present invention is to provide a novel storage device. Another object of one embodiment of the present invention is to provide a novel method for driving a semiconductor device. Another object of one embodiment of the present invention is to provide a novel method for driving a storage device.

[0015] The description of multiple purposes does not prevent the existence of each other's purposes. One embodiment of the present invention does not necessarily achieve all of the purposes illustrated. In addition, purposes other than the purposes listed above are naturally known from the description of this specification, etc., and such purposes may become the purpose of one embodiment of the present invention. Means of solving technical problems

[0016] One embodiment of the present invention is a semiconductor device comprising a CPU, a switching circuit, a first memory cell array, and a second memory cell array, wherein the CPU comprises a control circuit and a register circuit, the register circuit comprises a trigger circuit and a backup circuit, in the first memory cell array, the first memory cells are arranged in a matrix, in the second memory cell array, the second memory cells are arranged in a matrix, the control circuit and the trigger circuit are arranged in a first layer, the switch circuit and the backup circuit are arranged in a second layer above the first layer, the first memory cell array and the second memory cell array are arranged in a third layer above the second layer, the switch circuit has a function of supplying a signal to one of the first memory cell and the second memory cell, the control circuit and the trigger circuit comprise a transistor containing silicon in a channel formation region, and the switch circuit and the backup circuit comprise a transistor containing metal oxide in a channel formation region.

[0017] One embodiment of the present invention is a semiconductor device including a CPU, a switching circuit, a first memory cell array, and a second memory cell array, wherein the CPU includes a control circuit and a register circuit, the register circuit includes a trigger circuit and a backup circuit, in the first memory cell array, the first memory cells are arranged in a matrix, in the second memory cell array, the second memory cells are arranged in a matrix, the first memory cell includes a first transistor and a second transistor, the second memory cell includes a third transistor and a fourth transistor, the control circuit and the trigger circuit are arranged in a first layer, the switch circuit and the backup circuit are arranged in a second layer above the first layer, the first transistor and the third transistor are arranged in a third layer above the second layer, and the second transistor and the fourth transistor are arranged in a fourth layer above the third layer, the switch circuit has a function of supplying a signal to one of the first memory cell and the second memory cell, the control circuit and the trigger circuit include a transistor including silicon in a channel formation region, the switch circuit and the backup circuit include a transistor including metal oxide in a channel formation region, and the first to fourth transistors include metal oxide in the channel formation region.

[0018] Alternatively, in the above embodiment, the switching circuit may include a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; a signal may be supplied to one of the source and drain of the fifth transistor and one of the source and drain of the sixth transistor; the gate of the fifth transistor may be electrically connected to one of the source and drain of the seventh transistor; the gate of the sixth transistor may be electrically connected to one of the source and drain of the eighth transistor; the other of the source and drain of the seventh transistor may be supplied with a first selection signal; the other of the source and drain of the eighth transistor may be supplied with a second selection signal; a signal may be output from the other of the source and drain of the fifth transistor or the other of the source and drain of the sixth transistor according to the first selection signal and the second selection signal; when the signal is output from the other of the source and drain of the fifth transistor, the signal may be supplied to the first storage unit; and when the signal is output from the other of the source and drain of the sixth transistor, the signal may be supplied to the second storage unit.

[0019] Alternatively, in the above method, the switching circuit may also include a first capacitor and a second capacitor, one electrode of the first capacitor may also be electrically connected to the gate of the fifth transistor, the other electrode of the first capacitor may also be electrically connected to the other of the source and the drain of the fifth transistor, one electrode of the second capacitor may also be electrically connected to the gate of the seventh transistor, and the other electrode of the second capacitor may also be electrically connected to the other of the source and the drain of the seventh transistor.

[0020] Alternatively, in the above method, the third layer may also include a first insulating layer, the fourth layer may also include a second insulating layer, the first insulating layer may also include a first opening portion and a second opening portion, the second insulating layer may also include a third opening portion and a fourth opening portion, the channel formation region of the first transistor may also have a region along the side surface of the first opening portion, the channel formation region of the second transistor may also have a region along the side surface of the second opening portion, the channel formation region of the third transistor may also have a region along the side surface of the third opening portion, and the channel formation region of the fourth transistor may also have a region along the side surface of the fourth opening portion.

[0021] Alternatively, in the above embodiment, the first storage unit may have the function of storing the first data, the second storage unit may have the function of storing the second data, and the types of the first data and the second data may be different.

[0022] Alternatively, in the above manner, the first data or the second data may also be program data. Effects of the Invention

[0023] According to one embodiment of the present invention, a semiconductor device with a small dead space can be provided. In addition, according to one embodiment of the present invention, a small semiconductor device can be provided. In addition, according to one embodiment of the present invention, a low-power semiconductor device can be provided. In addition, according to one embodiment of the present invention, a high-speed drive semiconductor device can be provided. In addition, according to one embodiment of the present invention, a highly integrated semiconductor device can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with good electrical characteristics can be provided. In addition, according to one embodiment of the present invention, a highly reliable semiconductor device can be provided. In addition, according to one embodiment of the present invention, a novel semiconductor device can be provided. In addition, according to one embodiment of the present invention, a novel storage device can be provided. In addition, according to one embodiment of the present invention, a novel method for driving a semiconductor device can be provided. In addition, according to one embodiment of the present invention, a novel method for driving a storage device can be provided.

[0024] The description of multiple effects does not preclude the existence of each other's effects. In addition, one embodiment of the present invention does not necessarily have all the effects illustrated. In one embodiment of the present invention, purposes, effects, and novel features other than those described above can be naturally understood from the description and drawings in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a perspective view showing a structural example of a semiconductor device. Figure 2 is a block diagram showing a structural example of a semiconductor device. Figures 3A to 3D is a circuit diagram showing a configuration example of a switching circuit. Figure 4A and Figure 4B This is a timing chart showing an example of a method for driving a switching circuit. Figure 5 is a block diagram showing a structural example of a semiconductor device. Figure 6 is a circuit diagram showing a structural example of a semiconductor device. Figure 7 is a circuit diagram showing a structural example of a semiconductor device. Figure 8A and Figure 8B is a circuit diagram showing a configuration example of a register circuit. Figure 9 is a circuit diagram showing a configuration example of a register circuit. Figure 10 This is a timing chart showing an example of a driving method of a register circuit. 11A to 11Dis a circuit diagram showing a structural example of a memory cell. Figure 12 2 is a timing chart showing an example of a method for driving a memory cell. Figure 13A and Figure 13B It is a perspective view showing a structural example of a storage unit. Figure 14A and Figure 14B is a plan view showing a structural example of a transistor. Figures 14C to 14E is a cross-sectional view showing a structural example of a memory cell. Figure 15A It is a perspective view showing a structural example of a storage unit. Figure 15B and Figure 15C is a cross-sectional view showing a structural example of a memory cell. Figure 16A is a cross-sectional view showing a structural example of a transistor. Figure 16B is a plan view showing a structural example of a transistor. Figure 17A is a plan view showing a structural example of a transistor. 17B to 17D is a cross-sectional view showing a structural example of a transistor. Figure 18 is a cross-sectional view showing a structural example of a semiconductor device. Figure 19 is a cross-sectional view showing a structural example of a semiconductor device. Figure 20 is a cross-sectional view showing a structural example of a semiconductor device. Figure 21 is a cross-sectional view showing a structural example of a semiconductor device. Figure 22 is a cross-sectional view showing a structural example of a semiconductor device. Figure 23 is a cross-sectional view showing a structural example of a semiconductor device. Figure 24A and Figure 24B It is a perspective view showing a structural example of a semiconductor device. Figure 25 It is a perspective view showing a structural example of a semiconductor device. Figure 26A and Figure 26B This is a diagram showing an example of an electronic component. Figure 27A and Figure 27B is a diagram illustrating an example of an electronic device. Figures 27C to 27E This is a diagram showing an example of a mainframe computer. Figure 28 This is a diagram showing an example of space equipment. Figure 29 FIG. 1 is a diagram illustrating an example of a storage system that can be used in a data center. Figure 30A and Figure 30B This diagram shows various storage devices in a hierarchical manner. Figure 31 is a block diagram illustrating a TEG according to an embodiment. Figure 32 is a timing diagram illustrating the operation of the TEG according to the embodiment. Figure 33 is a graph showing a normal bit rate per data retention time of a memory device according to an embodiment. Figures 34A to 34E is an image showing a planar layout of a chip according to an embodiment. Figure 35A and Figure 35B is a STEM image according to an embodiment. Modes for Carrying Out the Invention

[0026] The following describes the embodiments with reference to the accompanying drawings. However, those skilled in the art will readily appreciate that the embodiments may be implemented in a variety of different forms, and their methods and details may be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited solely to the embodiments described below.

[0027] In the drawings, sizes, layer thicknesses, or regions may be exaggerated for clarity. Therefore, the present invention is not limited to the dimensions shown in the drawings. Furthermore, the drawings schematically illustrate idealized examples, and therefore, the present invention is not limited to the shapes or numerical values ​​shown in the drawings.

[0028] In this specification, unless otherwise specified, the off-state current refers to the drain current when the transistor is in the off state (also called the non-conducting state or the blocking state). In an n-channel transistor, the off-state refers to the voltage V between the gate and the source. gs Below the threshold voltage V th (In a p-channel transistor, V gs Higher than V th ) status.

[0029] In this specification, metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (also referred to as OS). For example, when a metal oxide is used in the active layer of a transistor, the metal oxide is sometimes referred to as an oxide semiconductor. In other words, an OS transistor can be referred to as a transistor containing a metal oxide or an oxide semiconductor.

[0030] (Implementation 1) In this embodiment, a configuration example of a semiconductor device is described with reference to the drawings. Specifically, a configuration example of a memory device, which is one embodiment of a semiconductor device, is described with reference to the drawings.

[0031] One embodiment of the present invention relates to a semiconductor device including a CPU, a driver circuit, and a plurality of memory cell arrays. The memory cell arrays are provided on a layer where the CPU and the driver circuits are provided.

[0032] In a memory cell array, memory cells are arranged in a matrix. A driver circuit drives the memory cells. For example, the driver circuit writes data to the memory cells and reads data from the memory cells by supplying signals to the memory cells.

[0033] The CPU includes control circuits and register circuits. The control circuit controls the CPU's operation and is also called the CPU control circuit. The register circuit includes a flip-flop circuit and a backup circuit. The flip-flop circuit holds data used for CPU calculations. The backup circuit backs up the data in the flip-flop circuit.

[0034] Flip-flop circuits are volatile, and the data they hold disappears when the CPU power supply is stopped. Backup circuits, on the other hand, are nonvolatile and can retain data for a long time even if the CPU power supply is stopped. Therefore, by providing a backup circuit in the register circuit and backing up the data in the flip-flop circuit, even if the data in the flip-flop circuit disappears, the data can be restored from the backup circuit. This allows power gating of the CPU, reducing the power consumption of the semiconductor device.

[0035] Here, it is preferable to use transistors with low off-state current in the backup circuit because they can retain data for a long time. For example, OS transistors are preferably used in the backup circuit. On the other hand, it is preferable to use transistors with high on-state current in circuits other than the backup circuit, such as control circuits and trigger circuits, because they can drive the CPU at high speed. For example, it is preferable to use Si transistors in circuits other than the backup circuit.

[0036] As described above, when the structure of transistors included in the backup circuit differs from the structure of transistors included in circuits other than the backup circuit, the backup circuit is placed in a layer different from the circuits other than the backup circuit. For example, the circuits other than the backup circuit are placed in the first layer, and the backup circuit is placed in a second layer above the first layer. In this case, the number of transistors and other components placed in the second layer is smaller than the number of transistors and other components placed in the first layer. Therefore, the dead space in the second layer is larger than that in the first layer.

[0037] In a semiconductor device according to one embodiment of the present invention, a switch circuit is provided in the second layer in which the backup circuit is provided. The switch circuit has the function of supplying a signal supplied from the driver circuit to any one of a plurality of memory cell arrays. For example, the switch circuit has the function of selecting a memory cell array to which data is written or a memory cell array to which data is read. For example, the switch circuit can select a memory cell array to which data is written or a memory cell array to which data is read based on a selection signal.

[0038] In this specification and other documents, supplying a signal to at least one of the memory cells in a memory cell array is sometimes referred to as "supplying a signal to the memory cell array." Furthermore, writing data to at least one of the memory cells in the memory cell array is sometimes referred to as "writing data to the memory cell." Furthermore, reading data from at least one of the memory cells in the memory cell array is sometimes referred to as "reading data from the memory cell."

[0039] By dividing the memory cell array into multiple cells and providing a switching circuit, the load applied to the driver circuit can be reduced while suppressing an increase in the area occupied by the driver circuit. Therefore, a compact and high-speed semiconductor device can be provided.

[0040] By arranging the switching circuit in the second layer in which the backup circuit is provided, the ineffective space of the second layer can be reduced. Therefore, a smaller semiconductor device can be provided compared to, for example, the case where the switching circuit is provided in the first layer. In addition, an OS transistor can be used for the transistor included in the switching circuit. Therefore, for example, the selection result of the memory cell array for writing data or the memory cell array for reading data can be maintained in the switching circuit for a long time. Therefore, for example, during the period when data is written to the memory cells provided in the same memory cell array or when data is read from the memory cells provided in the same memory cell array, it is not necessary to supply a selection signal to the switching circuit. Therefore, a low-power semiconductor device can be provided. In particular, the longer the period during which data is written to the memory cells provided in the same memory cell array or the period during which data is read from the memory cells provided in the same memory cell array, the more smoothly the power consumption of the semiconductor device can be reduced.

[0041] <Semiconductor Device Structure Example_1> Figure 1 1 is a perspective view showing a structural example of a semiconductor device 10 according to one embodiment of the present invention. This perspective view is also called a block diagram. The semiconductor device 10 includes a layer 20, a layer 30 on the layer 20, and a layer 40 on the layer 30. Figure 1 In order to easily identify the structural examples of each layer, layer 20, layer 30, and layer 40 are shown separately from each other, but in reality, layer 30 may be in contact with the top surface of layer 20 and layer 40 may be in contact with the top surface of layer 30.

[0042] The semiconductor device 10 includes a CPU 21, a driver circuit 22, a switch circuit group 51, and a memory cell array 41. In the memory cell array 41, memory cells 42 are arranged in a matrix. The semiconductor device 10 includes a plurality of memory cell arrays 41. Figure 1 The semiconductor device 10 is shown as an example including a memory cell array 41 including a memory cell array 41_1 and a memory cell array 41_2. Here, the memory cells 42 arranged in the memory cell array 41_1 are referred to as memory cells 42_1, and the memory cells 42 arranged in the memory cell array 41_2 are referred to as memory cells 42_2. Since the semiconductor device 10 includes the memory cell array 41, it can be considered a memory device.

[0043] In this specification and the drawings, when the same reference numeral is used for a plurality of components and it is necessary to distinguish them, the reference numeral may be appended with "_1", "[1]", "[1,1]" or " <1> ” and other identification symbols. In addition, when describing the common content between multiple components with identification symbols or when there is no need to distinguish them, they may be described without adding identification symbols.

[0044] The memory cell array 41 is provided so as to have a region overlapping with the CPU 21 and the driver circuit 22. This allows for a smaller semiconductor device to be realized compared to, for example, providing the memory cell array 41, the CPU 21, the driver circuit 22, and the like in the same layer.

[0045] In the drawings of this specification, components are classified according to their functions and shown as independent blocks in block diagrams. However, in practice, components are difficult to be completely divided according to their functions, and one component may involve multiple functions.

[0046] CPU 21 is provided across layer 20 and layer 30. CPU 21 includes control circuit 23, register circuit 50, arithmetic circuit 25, cache 26, memory controller 27, and the like. Register circuit 50 includes flip-flop circuit 24 and backup circuit 34. CPU 21, cache 26, memory controller 27, and the like are also circuits. Furthermore, memory cell 42 is also a circuit.

[0047] The control circuit 23, the arithmetic circuit 25, the cache 26, the memory controller 27, and the flip-flop circuit 24 are provided in the layer 20. The backup circuit 34 is provided in the layer 30. Since the flip-flop circuit 24 is provided in the layer 20 and the backup circuit 34 is provided in the layer 30, the register circuit 50 is provided across the layers 20 and 30.

[0048] like Figure 1 As shown, the register circuits 50 are dispersed. This can reduce the dead space of the layer 20 and make the semiconductor device 10 compact.

[0049] The backup circuit 34 preferably has an area that overlaps with the flip-flop circuit 24. This shortens the connection distance (wiring length) between the flip-flop circuit 24 and the backup circuit 34. Consequently, the wiring resistance and parasitic capacitance of the wiring electrically connecting the flip-flop circuit 24 and the backup circuit 34 can be reduced. Consequently, the time required to charge and discharge this wiring is reduced, enabling high-speed operation of the register circuit 50. Furthermore, the power consumption of the semiconductor device 10 can be reduced.

[0050] The control circuit 23 has the function of controlling the driving of the CPU 21. The control circuit 23 can control the driving of the CPU 21 by supplying control signals to other circuits included in the CPU 21. The control signals can be clock signals or timing signals. The control circuit 23 is also called a CPU control circuit.

[0051] The flip-flop circuit 24 has a function of holding data used for calculation by the CPU 21 and outputting the data according to, for example, a control signal generated by the control circuit 23. The backup circuit 34 has a function of backing up the data held in the flip-flop circuit 24.

[0052] The flip-flop circuit 24 is volatile, and the data it holds disappears when the power supply voltage to the CPU 21 is stopped. On the other hand, the backup circuit 34 is nonvolatile, and can retain data for a long time even when the power supply voltage to the CPU is stopped. Therefore, by providing the backup circuit 34 in the register circuit 50 and backing up the data in the flip-flop circuit 24, even if the data in the flip-flop circuit 24 is lost, it can be restored. This allows power gating of the CPU 21, thereby enabling the semiconductor device 10 to achieve low power consumption.

[0053] The arithmetic circuit 25 performs various arithmetic operations, including arithmetic and logical operations. The cache memory 26 temporarily stores frequently used data. The memory controller 27 controls the driving of the driver circuit 22. For example, the memory controller 27 can control the driving of the driver circuit 22 by supplying a control signal to the driver circuit 22. As described above, the control signal may be a clock signal or a timing signal. The memory controller 27 is also referred to as a drive control circuit, a storage control circuit, or a storage drive control circuit.

[0054] The driver circuit 22 has a function of writing data to the memory cell 42 by supplying a signal to the memory cell 42 and reading data from the memory cell 42. The driver circuit 22 is also called a memory driver circuit, a memory cell driver circuit, or a memory cell array driver circuit.

[0055] The circuits and the like provided in layer 20 are preferably driven at high speed. Therefore, the transistors included in the circuits and the like provided in layer 20 are preferably transistors with high field-effect mobility. For example, Si transistors can be suitably used as such transistors. Specifically, transistors having a channel formation region containing highly crystalline silicon such as single-crystal silicon or polycrystalline silicon can be used. For example, the circuits and the like provided in layer 20 are preferably provided with a CMOS (Complementary Metal Oxide Semiconductor).

[0056] Backup circuit 34 preferably retains data for a long period of time. This reduces the frequency of data rewriting in backup circuit 34, enabling semiconductor device 10 to achieve low power consumption. Backup circuit 34 preferably uses transistors with lower off-state current than Si transistors, for example. Examples of such transistors include OS transistors.

[0057] As described above, when the structure of transistors included in backup circuit 34 is different from the structure of transistors included in circuits other than backup circuit 34, backup circuit 34 is provided in a layer different from the other circuits. For example, circuits other than backup circuit 34 may be provided in layer 20, while backup circuit 34 may be provided in layer 30. In this case, the number of transistors and other components provided in layer 30 is smaller than the number of transistors and other components provided in layer 20. Therefore, the dead space in layer 30 is larger than that in layer 20.

[0058] In the semiconductor device 10, a switch circuit 52 is provided in the layer 30 in which the backup circuit 34 is provided. A plurality of switch circuits 52 may be provided in the layer 30. The plurality of switch circuits 52 are collectively referred to as a switch circuit group 51. Figure 1 In the embodiment, the switch circuit group 51 is set as one area, but a plurality of areas separated from each other may be set as the switch circuit group 51 .

[0059] The switch circuit group 51 may have a region overlapping with the CPU 21 . Alternatively, the switch circuit group 51 may have a region overlapping with the drive circuit 22 . Figure 1 The example shown shows that the switch circuit group 51 has a region overlapping with the control circuit 23. Alternatively, the switch circuit group 51 may have a region overlapping with circuits included in the CPU 21 other than the control circuit 23. Alternatively, the switch circuit group 51 may not overlap with the control circuit 23.

[0060] The switch circuit 52 has a function of supplying a signal supplied from the driver circuit 22 to either the memory cell array 41_1 or the memory cell array 41_2. For example, the switch circuit 52 has a function of selecting the memory cell array 41 to which data is written or the memory cell array 41 from which data is read.

[0061] By dividing the memory cell array 41 into multiple components and providing the switch circuit group 51, the area occupied by the driver circuit 22 can be suppressed from increasing, and the load applied to the driver circuit 22 can be reduced. Consequently, the semiconductor device 10 can be made compact and capable of high-speed operation. Furthermore, at least a portion of the switch circuit group 51 can be included in the CPU 21. In other words, at least one switch circuit 52 can be provided in the CPU 21.

[0062] By placing the switch circuit group 51 in the layer 30 where the backup circuit 34 is located, the dead space of the layer 30 can be reduced compared to, for example, placing the switch circuit group 51 in the layer 20, thereby making the semiconductor device 10 compact. Furthermore, the transistors placed in the switch circuit group 51 can be OS transistors. Therefore, for example, the selection result of the memory cell array 41 for writing data or reading data from the memory cell array 41 can be maintained in the switch circuit 52 for a long period of time. Therefore, for example, while data is being written to or read from the memory cells 42 located in the same memory cell array 41, there is no need to supply a selection signal to the switch circuit 52. Consequently, the semiconductor device 10 can be a low-power semiconductor device.

[0063] The CPU 21 may be, for example, a GPU (Graphics Processing Unit). The GPU may include a register circuit 50 including the flip-flop circuit 24 and the backup circuit 34 , and a switch circuit group 51 may be provided in the same layer as the backup circuit 34 .

[0064] Here, the longer the period during which data is written to or read from the memory cells 42 in the same memory cell array 41, the more effectively the power consumption of the semiconductor device 10 can be reduced. Therefore, for example, the memory cells 42 in the same memory cell array 41 preferably store the same type of data. In other words, the memory cells 42 in different memory cell arrays 41 preferably store different types of data. For example, the first data stored in the memory cell 42_1 and the second data stored in the memory cell 42_2 preferably differ in type.

[0065] For example, one of the first data and the second data may be program data, and the other of the first data and the second data may be data generated by a user of the semiconductor device 10. For example, the other of the first data and the second data may be data generated by a user by operating an application and stored in a file. Here, for example, one of the first data and the second data may not be stored in a storage device, while the other of the first data and the second data may be stored in a storage device. Examples of storage devices include recording media drives such as hard disk drives (HDD) and solid-state drives (SSD), flash memories, Blu-ray Discs (registered trademark), and DVDs (Digital Versatile Discs).

[0066] In this specification and the like, data stored in a file may be referred to as file data.

[0067] Furthermore, data may be stored in different memory cell arrays 41 for each application. For example, program data and file data generated by a first application may be first data, and program data and file data generated by a second application may be second data.

[0068] Furthermore, for example, frequently used data may be stored in both the storage unit 42_1 and the storage unit 42_2. For example, frequently used data among data used by the operating system may be stored in both the storage unit 42_1 and the storage unit 42_2.

[0069] Here, the number of memory cells 42 may be different for each memory cell array 41. For example, the number of memory cells 42_1 may be different from the number of memory cells 42_2. For example, if the number of memory cells 42_1 is smaller than the number of memory cells 42_2, the smaller of the first and second data may be stored in memory cell 42_1, while the larger data may be stored in memory cell 42_2. This may extend the period during which data is written to and read from memory cells 42 in the same memory cell array 41.

[0070] Figure 2 is with Figure 1 1 and 2 are block diagrams showing configuration examples of the drive circuit 22 , the memory cell array 41_1 , the memory cell array 41_2 , and the switch circuit group 51 in more detail. Figure 2 An example is shown in which the memory cells 42_1 and the memory cells 42_2 are arranged in a matrix of m rows and n columns (m and n are integers greater than or equal to 1). Here, the memory cell 42_1 in the 1st row and 1st column, the memory cell 42_1 in the mth row and nth column, the memory cell 42_2 in the 1st row and 1st column, and the memory cell 42_2 in the mth row and nth column are respectively referred to as memory cell 42_1[1,1], memory cell 42_1[m,n], memory cell 42_2[1,1], and memory cell 42_2[m,n].

[0071] In each of the memory cells 42_1 and the memory cells 42_2, the memory cells 42 in the same row can be electrically connected to the same wiring 61 and wiring 63. For example, the memory cell 42_1 in the first row can be electrically connected to the wiring 61_1[1] and the wiring 63_1[1], the memory cell 42_1 in the second row can be electrically connected to the wiring 61_1[2] and the wiring 63_1[2], and the memory cell 42_1 in the mth row can be electrically connected to the wiring 61_1[m] and the wiring 63_1[m]. Similarly, the memory cell 42_2 in the first row can be electrically connected to the wiring 61_2[1] and the wiring 63_2[1], the memory cell 42_2 in the second row can be electrically connected to the wiring 61_2[2] and the wiring 63_2[2], and the memory cell 42_2 in the mth row can be electrically connected to the wiring 61_2[m] and the wiring 63_2[m]. The wiring 61 and the wiring 63 serve as word lines.

[0072] In addition, the memory cells 42 in the same column can be electrically connected to the same wiring 65 and wiring 67. For example, the memory cell 42_1 in the first column can be electrically connected to the wiring 65_1[1] and the wiring 67_1[1], the memory cell 42_1 in the second column can be electrically connected to the wiring 65_1[2] and the wiring 67_1[2], and the memory cell 42_1 in the nth row can be electrically connected to the wiring 65_1[n] and the wiring 67_1[n]. Similarly, the memory cell 42_2 in the first column can be electrically connected to the wiring 65_2[1] and the wiring 67_2[1], the memory cell 42_2 in the second column can be electrically connected to the wiring 65_2[2] and the wiring 67_2[2], and the memory cell 42_2 in the nth row can be electrically connected to the wiring 65_2[n] and the wiring 67_2[n]. The wiring 65 and the wiring 67 serve as bit lines.

[0073] The switch circuit group 51 includes m switch circuits 52a, m switch circuits 52b, n switch circuits 52c, and n switch circuits 52d as switch circuits 52. Here, the m switch circuits 52a and 52b are respectively denoted as switch circuits 52a[1] to switch circuits 52a[m] and switch circuits 52b[1] to switch circuits 52b[m] for distinction. Furthermore, the n switch circuits 52c and 52d are respectively denoted as switch circuits 52c[1] to switch circuits 52c[n] and switch circuits 52d[1] to switch circuits 52d[n] for distinction.

[0074] Switch circuit 52a[i] (i is an integer from 1 to m) is electrically connected to wiring 62[i]. Switch circuit 52b[i] is electrically connected to wiring 64[i]. Switch circuit 52c[j] (j is an integer from 1 to n) is electrically connected to wiring 66[j]. Switch circuit 52d[j] is electrically connected to wiring 68[j]. Wiring 62 and wiring 64 function as word lines, while wiring 66 and wiring 68 function as bit lines.

[0075] exist Figure 2 In FIG. 2 , a word line driving circuit 22 a , a word line driving circuit 22 b , a bit line driving circuit 22 c , a bit line driving circuit 22 d , and a switch driving circuit 22 e are shown as the driving circuit 22 .

[0076] The word line driver circuit 22a has the function of selecting the memory cells 42 to which data is written, row by row. The word line driver circuit 22a generates a signal and supplies it to the memory cells 42 via wiring 62 and wiring 61, thereby selecting the memory cells 42 to which data is written. Herein, wiring 61 and wiring 62 are also referred to as write word lines, and the word line driver circuit 22a is also referred to as a write word line driver circuit. Furthermore, these signals are also referred to as write signals.

[0077] The word line driver circuit 22b has the function of selecting the memory cells 42 from which data is to be read, row by row. The word line driver circuit 22b generates a signal and supplies it to the memory cells 42 via wiring 64 and wiring 63, thereby selecting the memory cells 42 from which data is to be read. Herein, wiring 63 and wiring 64 are also referred to as read word lines, and the word line driver circuit 22b is also referred to as a read word line driver circuit. Furthermore, these signals are also referred to as read signals.

[0078] Bit line driver circuit 22c has the function of writing data into memory cell 42 selected by word line driver circuit 22a. Specifically, bit line driver circuit 22c has the function of writing data into memory cell 42 selected by word line driver circuit 22a via wiring 66 and wiring 65. Herein, wiring 65 and wiring 66 are also referred to as write bit lines, and bit line driver circuit 22c is also referred to as a write bit line driver circuit. Furthermore, data written into memory cell 42 by bit line driver circuit 22c is also referred to as write data.

[0079] The bit line driver circuit 22d has the function of amplifying data output from the memory cell 42 to the wiring 67 and supplied to the bit line driver circuit 22d via the wiring 68. The bit line driver circuit 22d has the function of amplifying this data and outputting it, for example, to the outside of the semiconductor device 10, thereby reading the data stored in the memory cell 42. Furthermore, the bit line driver circuit 22d has the function of precharging the wiring 68 and the wiring 67 by supplying a precharge signal before reading data from the memory cell 42. Herein, the wiring 67 and the wiring 68 are also referred to as read bit lines, and the bit line driver circuit 22d is also referred to as a read bit line driver circuit. Furthermore, the data read from the memory cell 42 by the bit line driver circuit 22d is also referred to as read data.

[0080] The switch circuit 52a has a function of supplying a write signal supplied from the wiring 62 to one of the memory cell 42_1 and the memory cell 42_2. The switch circuit 52b has a function of supplying a read signal supplied from the wiring 64 to one of the memory cell 42_1 and the memory cell 42_2. The switch circuit 52c has a function of supplying write data supplied from the wiring 66 to one of the memory cell 42_1 and the memory cell 42_2. The switch circuit 52d has a function of supplying one of the data output from the memory cell 42_1 and the data output from the memory cell 42_2 to the bit line driver circuit 22d.

[0081] The switch driver circuit 22e controls the operation of the switch circuit 52. Specifically, the switch driver circuit 22e controls the operation of the switch circuit 52 by supplying a selection signal SEL to the switch circuit 52. For example, the switch circuit 52a outputs a write signal supplied from the wiring 62 to one of the wirings 61_1 and 61_2 in accordance with the selection signal SEL. The switch circuit 52b outputs a read signal supplied from the wiring 64 to one of the wirings 63_1 and 63_2 in accordance with the selection signal SEL. The switch circuit 52c outputs write data supplied from the wiring 66 to one of the wirings 65_1 and 65_2 in accordance with the selection signal SEL. The switch circuit 52d outputs read data supplied from the wiring 67_1 and read data supplied from the wiring 67_2 to the wiring 68 in accordance with the selection signal SEL.

[0082] In the drawings of this specification, signals are represented by arrows.

[0083] As described above, by providing the switching circuit 52 in the semiconductor device 10, the memory cell array 41 can be divided into multiple pieces. By providing the switching circuit 52 in the semiconductor device 10 and dividing the memory cell array 41 into multiple pieces, the area occupied by the word line driver circuit 22a, word line driver circuit 22b, bit line driver circuit 22c, and bit line driver circuit 22d can be reduced, and the load applied to these driver circuits can be reduced. Consequently, the semiconductor device 10 can be made compact and capable of high-speed operation.

[0084] [Switching Circuit] Figure 3A 、 Figure 3B 、 Figure 3C and Figure 3D 52a, 52b, 52c, and 52d, respectively. The switch circuits 52a, 52b, 52c, and 52d each include a circuit 53. Figure 3A 、 Figure 3B 、 Figure 3C and Figure 3D The switch circuit 52 is shown as an example in which the circuit 53 includes a circuit 53_1 and a circuit 53_2 .

[0085] The circuit 53_1 includes a transistor 54_1, a transistor 55_1, and a capacitor 56_1. The circuit 53_2 includes a transistor 54_2, a transistor 55_2, and a capacitor 56_2. The circuit 53 may not include the capacitor 56.

[0086] In the switch circuit 52a, one of the source and drain of the transistor 54_1 and one of the source and drain of the transistor 54_2 are electrically connected to the word line driver circuit 22a via the wiring 62. In the switch circuit 52b, one of the source and drain of the transistor 54_1 and one of the source and drain of the transistor 54_2 are electrically connected to the word line driver circuit 22b via the wiring 64. In the switch circuit 52c, one of the source and drain of the transistor 54_1 and one of the source and drain of the transistor 54_2 are electrically connected to the bit line driver circuit 22c via the wiring 66. In the switch circuit 52d, one of the source and drain of the transistor 54_1 is electrically connected to the wiring 67_1, and one of the source and drain of the transistor 54_2 is electrically connected to the wiring 67_2.

[0087] In switch circuits 52a, 52b, and 52c, the signal supplied to one of the source and drain of transistor 54_1 and one of the source and drain of transistor 54_2 is referred to as signal IN. Signal IN can be used as a write signal in switch circuit 52a, as a read signal in switch circuit 52b, and as write data in switch circuit 52c.

[0088] In the switch circuit 52d, a signal supplied to one of the source and drain of the transistor 54_1 is referred to as a signal IN_1, and a signal supplied to one of the source and drain of the transistor 54_2 is referred to as a signal IN_2. The signals IN_1 and IN_2 may be read data.

[0089] In the switch circuits 52a, 52b, 52c, and 52d, the gate of the transistor 54_1 is electrically connected to one of the source and drain of the transistor 55_1 and one electrode of the capacitor 56_1. Furthermore, the gate of the transistor 54_2 is electrically connected to one of the source and drain of the transistor 55_2 and one electrode of the capacitor 56_2. Here, the node electrically connected to the gate of the transistor 54_1, one of the source and drain of the transistor 55_1, and one electrode of the capacitor 56_1 is referred to as node N_1. Furthermore, the node electrically connected to the gate of the transistor 54_2, one of the source and drain of the transistor 55_2, and one electrode of the capacitor 56_2 is referred to as node N_2.

[0090] The other of the source and drain of transistor 55_1, the other of the source and drain of transistor 55_2, and the gate of transistor 55_1 and the gate of transistor 55_2 are electrically connected to switch driver circuit 22e. Switch driver circuit 22e supplies a selection signal SEL_1 to the other of the source and drain of transistor 55_1 and a selection signal SEL_2 to the other of the source and drain of transistor 55_2. Switch driver circuit 22e also supplies a selection result write signal MEM to the gates of transistor 55_1 and transistor 55_2.

[0091] In the switch circuit 52a, the other of the source and drain of the transistor 54_1 and the other electrode of the capacitor 56_1 are electrically connected to the wiring 61_1, and the other of the source and drain of the transistor 54_2 and the other electrode of the capacitor 56_2 are electrically connected to the wiring 61_2. In the switch circuit 52b, the other of the source and drain of the transistor 54_1 and the other electrode of the capacitor 56_1 are electrically connected to the wiring 63_1, and the other of the source and drain of the transistor 54_2 and the other electrode of the capacitor 56_2 are electrically connected to the wiring 63_2. In the switch circuit 52c, the other of the source and drain of the transistor 54_1 and the other electrode of the capacitor 56_1 are electrically connected to the wiring 65_1, and the other of the source and drain of the transistor 54_2 and the other electrode of the capacitor 56_2 are electrically connected to the wiring 65_2. In the switch circuit 52 d , the other of the source and drain of the transistor 54_1 , the other electrode of the capacitor 56_1 , the other of the source and drain of the transistor 54_2 , and the other electrode of the capacitor 56_2 are electrically connected to the bit line driver circuit 22 d via a wiring 68 .

[0092] In switch circuits 52a, 52b, and 52c, the signal output from the other of the source and drain of transistor 54_1 is called signal OUT_1, and the signal output from the other of the source and drain of transistor 54_2 is called signal OUT_2. Signals OUT_1 and OUT_2 can be write signals in switch circuit 52a, read signals in switch circuit 52b, and write data in switch circuit 52c.

[0093] In the switch circuit 52d, a signal output from the other of the source and drain of the transistor 54_1 and the other of the source and drain of the transistor 54_2 is referred to as a signal OUT. The signal OUT may be read data.

[0094] When transistors 55_1 and 55_2 are n-channel transistors, by setting the selection result write signal MEM to a high potential and supplying the potential of the selection signal SEL_1 to the node N_1, the potential of the selection signal SEL_2 can be supplied to the node N_2. This writes the selection result indicated by the selection signal SEL to the switch circuit 52. Alternatively, by setting the selection result write signal MEM to a low potential, the selection result can be retained in the switch circuit 52.

[0095] Unless otherwise specified, the transistors in this specification and other descriptions are described assuming that they are n-channel transistors. Furthermore, even if the transistors are p-channel transistors, for example, by appropriately reversing the magnitude relationship of the potentials, the descriptions in this specification and other descriptions can be applied.

[0096] The switch circuits 52a, 52b, and 52c output the signal OUT_1 when, for example, the potential of the node N_1 is high and the potential of the node N_2 is low. Furthermore, the switch circuits 52a, 52b, and 52c output the signal OUT_2 when, for example, the potential of the node N_1 is low and the potential of the node N_2 is high. As described above, the signal IN is output as the signal OUT_1 or the signal OUT_2, for example, according to the selection signal SEL_1 and the selection signal SEL_2. The signal OUT_1 is supplied to Figure 1 and Figure 2 The memory cell 42_1 is shown. The signal OUT_2 is supplied to Figure 1 and Figure 2 The storage unit 42_2 is shown.

[0097] For example, when the potential of node N_1 is high and the potential of node N_2 is low, the switch circuit 52d outputs signal IN_1 as signal OUT. Also, when the potential of node N_1 is low and the potential of node N_2 is high, the switch circuit 52d outputs signal IN_2 as signal OUT. As described above, one of the signals IN_1 and IN_2 is output as signal OUT based on, for example, the selection signals SEL_1 and SEL_2. Signal IN_1 is output from Figure 1 and Figure 2 The memory cell 42_1 is shown as being supplied to the switch circuit 52d. The signal IN_2 is from Figure 1 and Figure 2 The storage cell 42_2 shown is supplied to the switch circuit 52d.

[0098] The off-state current of the OS transistor is extremely small. Therefore, by using the OS transistor as transistor 55, the potential of node N can be maintained for a long time. Thus, the selection result written to the switch circuit 52 can be maintained for a long time. For example, as described above, the selection result of the memory cell array 41 to which data is written or the memory cell array 41 to which data is read can be maintained in the switch circuit 52 for a long time. Therefore, while data is being written to or read from the memory cells 42 provided in the same memory cell array 41, the frequency of supplying the selection signal SEL to the switch circuit 52 can be reduced. Consequently, the semiconductor device 10 can be a low-power semiconductor device.

[0099] As described above, the longer the period during which data is written to or read from the memory cells 42 in the same memory cell array 41, the more effectively the power consumption of the semiconductor device 10 can be reduced. Therefore, for example, the memory cells 42 in the same memory cell array 41 preferably store the same type of data.

[0100] Figure 4A 2 is a timing chart showing an example of a driving method of the switch circuit 52 a , the switch circuit 52 b , and the switch circuit 52 c . Figure 4A FIG. 8 shows an example of the potential changes over time of the selection result write signal MEM, the selection signal SEL_1, the selection signal SEL_2, the node N_1, the node N_2, the signal IN, the signal OUT_1, and the signal OUT_2 from time T01 to time T12. Note that before time T01, the potentials of the selection result write signal MEM, the selection signal SEL_1, the selection signal SEL_2, the node N_1, the node N_2, the signal IN, the signal OUT_1, and the signal OUT_2 are all low.

[0101] At time T01, the potentials of the selection result write signal MEM and the selection signal SEL_1 are set to high. Setting the potential of the selection result write signal MEM to high turns on transistors 55_1 and 55_2. Consequently, node N_1 has a potential corresponding to the potential of the selection signal SEL_1, and node N_2 has a potential corresponding to the potential of the selection signal SEL_2. This writes the selection result to switch circuit 52. Specifically, the selection result of selection circuit 53_1 is written to switch circuit 52. Here, the potential of node N_1 may be, for example, the value obtained by subtracting the threshold voltage of transistor 55_1 from the potential of the selection signal SEL_1.

[0102] At time T02, the potentials of the selection result write signal MEM and the selection signal SEL_1 are set to low. By setting the potential of the selection result write signal MEM to low, the transistors 55_1 and 55_2 are turned off. Thus, the selection result is held in the switch circuit 52.

[0103] At time T03, the potential of signal IN becomes high. Consequently, the potential of signal OUT_1 becomes high. Meanwhile, the potential of signal OUT_2 remains low. As described above, based on the selection result held in switch circuit 52, signal IN is output as signal OUT_1.

[0104] Here, as the potential of one of the source and drain electrodes of transistor 54_1 rises, the potential of the other electrode of capacitor 56_1 also rises. Because transistor 55_1 is off and node N_1 is floating, the potential of node N_1 also rises due to capacitive coupling through capacitor 56_1. This suppresses the potential rise of the gate electrode of transistor 55_1, allowing, for example, the potential of signal OUT_1 to be lower than the potential of signal IN.

[0105] In this specification and other publications, bootstrapping is referred to as using capacitive coupling to increase the gate potential as the source or drain potential of a transistor increases. At time T03, the potential of node N_1 rises due to bootstrapping. Note that even if capacitor 56_1 is not included in circuit 53_1, the potential of node N_1 may rise due to, for example, the gate capacitance of transistor 54_1.

[0106] At time T04, the potential of the signal IN becomes low. As a result, the potential of the signal OUT_1 becomes low. In addition, the potential of the node N_1, which has risen due to bootstrapping, also falls.

[0107] At time T05, the potential of the signal IN becomes high again, and at time T06, the potential of the signal IN becomes low. Accordingly, the potentials of the node N_1 and the signal OUT_1 change in the same manner as from time T03 to time T04.

[0108] From time T05 to time T06, the switch circuit 52 holds the selection result. Therefore, the potential of the selection signal SEL_1 is low, and the signal IN is output from the switch circuit 52 as the signal OUT_1.

[0109] At time T07, the potentials of selection result write signal MEM and selection signal SEL_2 are set to high. Thus, similar to time T01, the selection result is written to switch circuit 52. Specifically, the selection result of selection circuit 53_2 is written to switch circuit 52. Here, the potential of node N_2 may be, for example, the value obtained by subtracting the threshold voltage of transistor 55_2 from the potential of selection signal SEL_2.

[0110] At time T08, the potentials of the selection result write signal MEM and the selection signal SEL_2 are set to a low level. Thus, the selection result is held in the switch circuit 52 as in the case of time T02.

[0111] At time T09, the potential of signal IN reaches a high level. Consequently, the potential of signal OUT_2 reaches a high level. Meanwhile, the potential of signal OUT_1 remains low. As described above, based on the selection result held in switch circuit 52, signal IN is output as signal OUT_2. Here, the potential of node N_2 rises due to bootstrapping using capacitive coupling of capacitor 56_2. Note that even if capacitor 56_2 is not provided in circuit 53_2, the potential of node N_2 may rise due to, for example, the gate capacitance of transistor 54_2.

[0112] At time T10, the potential of the signal IN becomes low. As a result, the potential of the signal OUT_2 becomes low. In addition, the potential of the node N_2, which has risen due to bootstrapping, also falls.

[0113] At time T11, the potential of the signal IN becomes high again, and at time T12, the potential of the signal IN becomes low. Accordingly, the potentials of the node N_2 and the signal OUT_2 change in the same manner as from time T09 to time T10.

[0114] At time T11 and time T12, the switch circuit 52 holds the selection result. Therefore, the potential of the selection signal SEL_2 becomes a low potential, and the signal IN is output from the switch circuit 52 as the signal OUT_2.

[0115] The above is an example of a driving method of the switch circuit 52a, the switch circuit 52b, and the switch circuit 52c.

[0116] Figure 4B 2 is a timing chart showing an example of a driving method of the switching circuit 52 d . Figure 4BFIG3 shows an example of the potential changes over time of the selection result write signal MEM, the selection signal SEL_1, the selection signal SEL_2, the node N_1, the node N_2, the signal IN_1, the signal IN_2, and the signal OUT from time T21 to time T32. Note that before time T21, the potentials of the selection result write signal MEM, the selection signal SEL_1, the selection signal SEL_2, the node N_1, the node N_2, the signal IN_1, the signal IN_2, and the signal OUT are all low.

[0117] The potentials of the selection result write signal MEM, the selection signal SEL, and the node N at time T21 and time T22 may be the same as those at time T01 and time T02. From time T21 to time T22, the selection result of the selection circuit 53_1 is written to the switch circuit 52d.

[0118] At time T23, the potentials of signals IN_1 and IN_2 become high. The potential of signal OUT becomes high, corresponding to the potential of signal IN_1, based on the selection result held in switch circuit 52d. Therefore, signal IN_1 is output as signal OUT. Here, the potential of node N_1 rises due to bootstrapping using capacitive coupling of capacitor 56_1. Note that, as described above, even if capacitor 56_1 is not provided in circuit 53_1, the potential of node N_1 may rise due to, for example, the gate capacitance of transistor 54_1.

[0119] At time T24, the potentials of the signals IN_1 and IN_2 become low. When the potential of the signal IN_1 becomes low, the potential of the signal OUT also becomes low. In addition, the potential of the node N_1, which has risen due to bootstrapping, also falls.

[0120] At time T25, the potential of signal IN_2 becomes high. On the other hand, the potential of signal IN_1 remains low. The potential of signal OUT remains low, corresponding to the potential of signal IN_1, based on the selection result held in switch circuit 52d.

[0121] At time T26 , the potential of the signal IN_2 becomes a low potential.

[0122] The potentials of the selection result write signal MEM, the selection signal SEL, and the node N at time T27 and time T28 may be the same as those at time T07 and time T08. From time T27 to time T28, the selection result of the selection circuit 53_2 is written to the switch circuit 52d.

[0123] At time T29, the potential of signal IN_1 becomes high. On the other hand, the potential of signal IN_2 remains low. The potential of signal OUT remains low, corresponding to the potential of signal IN_2, based on the selection result held in switch circuit 52d.

[0124] At time T30 , the potential of the signal IN_1 becomes a low potential.

[0125] At time T31, the potential of signal IN_2 becomes high. Meanwhile, the potential of signal IN_1 remains low. The potential of signal OUT becomes high, corresponding to the potential of signal IN_2, based on the selection result maintained in switch circuit 52d. Therefore, signal IN_2 is output as signal OUT. Here, the potential of node N_2 rises due to bootstrapping using capacitive coupling of capacitor 56_2. Note that, as described above, even if capacitor 56_2 is not provided in circuit 53_2, the potential of node N_2 may rise due to, for example, the gate capacitance of transistor 54_2.

[0126] At time T32, the potential of the signal IN_2 becomes low. When the potential of the signal IN_2 becomes low, the potential of the signal OUT also becomes low. In addition, the potential of the node N_2, which has risen due to bootstrapping, also falls.

[0127] The above is an example of a driving method of the switch circuit 52d.

[0128] As described above, the switch circuit 52 provided between the memory cell 42 and the driver circuit 22 has the function of maintaining the selection result. While the switch circuit 52 maintains the selection result, for example, the potentials of both the selection signal SEL_1 and the selection signal SEL_2 can be set to low. In other words, the selection signal SEL_1 and the selection signal SEL_2 do not need to be supplied to the switch circuit 52. Therefore, the semiconductor device 10 can be a low-power semiconductor device.

[0129] In particular, by using an OS transistor as transistor 55, the off-state current of transistor 55 can be made extremely low. As described above, the potential of node N can be maintained for a long time. Therefore, the selection result written to switch circuit 52 can be maintained for a long time. For example, the selection result of memory cell array 41 to which data is written or memory cell array 41 to which data is read can be maintained in switch circuit 52 for a long time. Therefore, while data is being written to or read from memory cells 42 in the same memory cell array 41, the frequency of supplying selection signal SEL to switch circuit 52 can be reduced. Consequently, semiconductor device 10 can be a low-power semiconductor device.

[0130] As described above, the longer the period during which data is written to or read from the memory cells 42 in the same memory cell array 41, the more effectively the power consumption of the semiconductor device 10 can be reduced. Specifically, the longer the period from when the selection result write signal MEM is set to a high potential until the next time the selection result write signal MEM is set to a high potential, the more effectively the power consumption of the semiconductor device 10 can be reduced. Therefore, for example, the memory cells 42 in the same memory cell array 41 preferably store the same type of data.

[0131] Although Figure 1 and Figure 2 Although an example in which the semiconductor device 10 includes two memory cell arrays 41 is shown, the semiconductor device 10 may include three or more memory cell arrays 41 . Figure 5 yes Figure 2 In the modified example of the structure shown in FIG. 1 , a memory cell array 41 with two rows and two columns is provided in the semiconductor device 10. Figure 5 In FIG. 2 , only the bit line driving circuit 22c is shown as the driving circuit 22. Figure 5 In FIG. 5 , only the switch circuit 52 c is shown as the switch circuit 52 .

[0132] exist Figure 5 , the memory cell arrays 41 in the first row and first column, the second row and first column, the second row and first column, and the second row and second column are respectively referred to as memory cell array 41_11, memory cell array 41_21, memory cell array 41_12, and memory cell array 41_22. Furthermore, the memory cells 42 provided in the memory cell arrays 41_11, 41_21, 41_12, and 41_22 are respectively referred to as memory cell 42_11, 42_21, 42_12, and 42_22. Furthermore, the wiring 65 electrically connected to the memory cells 42_11, 42_21, 42_12, and 42_22 is respectively referred to as wiring 65_11, wiring 65_21, wiring 65_12, and wiring 65_22.

[0133] like Figure 5 As shown in FIG. 5 , the switch circuit 52 c is electrically connected to the wiring 65_11, the wiring 65_21, the wiring 65_12, and the wiring 65_22. In other words, the switch circuit 52 c can be electrically connected to the four wirings 65. Figure 5 Although not shown in the drawings, the switch circuit 52 a may be electrically connected to the four wirings 62 , the switch circuit 52 b may be electrically connected to the four wirings 64 , and the switch circuit 52 d may be electrically connected to the four wirings 67 .

[0134] Thus, the switch circuits 52a, 52b, 52c, and 52d can be electrically connected to the same number of wirings 61, 63, 65, and 67 as the number of memory cell arrays 41. Alternatively, the semiconductor device 10 may include three or more rows of memory cell arrays 41 or three or more columns of memory cell arrays 41. In this case, the switch circuits 52a, 52b, 52c, and 52d can also be electrically connected to the same number of wirings 61, 63, 65, and 67 as the number of memory cell arrays 41.

[0135] Figure 6 It shows Figure 5 A circuit diagram of a configuration example of a switch circuit 52c is shown. Figure 6 The switch circuit 52c shown as the circuit 53 includes the circuit 53_11, the circuit 53_21, the circuit 53_12 and the circuit 53_22. Note that the switch circuit 52a and the switch circuit 52b can also be based on Figure 3A and Figure 3B Have the same structure.

[0136] The circuit 53_11 includes a transistor 54_11, a transistor 55_11, and a capacitor 56_11. The circuit 53_21 includes a transistor 54_21, a transistor 55_21, and a capacitor 56_21. The circuit 53_12 includes a transistor 54_12, a transistor 55_12, and a capacitor 56_12. The circuit 53_22 includes a transistor 54_22, a transistor 55_22, and a capacitor 56_22.

[0137] One of the source and drain of the transistor 54_11, one of the source and drain of the transistor 54_21, one of the source and drain of the transistor 54_12, and one of the source and drain of the transistor 54_22 are electrically connected to the bit line driver circuit 22 c through the wiring 66. Therefore, for example, one of the source and drain of all the transistors 54 can be electrically connected to one wiring 66.

[0138] The gate of the transistor 54_11 is electrically connected to one of the source and drain of the transistor 55_11 and one electrode of the capacitor 56_11. The gate of the transistor 54_21 is electrically connected to one of the source and drain of the transistor 55_21 and one electrode of the capacitor 56_21. The gate of the transistor 54_12 is electrically connected to one of the source and drain of the transistor 55_12 and one electrode of the capacitor 56_12. The gate of the transistor 54_22 is electrically connected to one of the source and drain of the transistor 55_22 and one electrode of the capacitor 56_22.

[0139] Here, the node electrically connected to the gate of the transistor 54_11, one of the source and drain of the transistor 55_11, and one electrode of the capacitor 56_11 is referred to as node N_11. Furthermore, the node electrically connected to the gate of the transistor 54_21, one of the source and drain of the transistor 55_21, and one electrode of the capacitor 56_21 is referred to as node N_21. Furthermore, the node electrically connected to the gate of the transistor 54_12, one of the source and drain of the transistor 55_12, and one electrode of the capacitor 56_12 is referred to as node N_12. Furthermore, the node electrically connected to the gate of the transistor 54_22, one of the source and drain of the transistor 55_22, and one electrode of the capacitor 56_22 is referred to as node N_22.

[0140] The other of the source and drain of the transistor 55_11, the other of the source and drain of the transistor 55_21, the other of the source and drain of the transistor 55_12, and the other of the source and drain of the transistor 55_22 are electrically connected to the switch drive circuit 22e. In addition, the gate of the transistor 55_11, the gate of the transistor 55_21, the gate of the transistor 55_12, and the gate of the transistor 55_22 are electrically connected to the switch drive circuit 22e.

[0141] The switch drive circuit 22e supplies the selection signal SEL_11 to the other of the source and drain of the transistor 55_11. The switch drive circuit 22e supplies the selection signal SEL_21 to the other of the source and drain of the transistor 55_21. The switch drive circuit 22e supplies the selection signal SEL_12 to the other of the source and drain of the transistor 55_12. The switch drive circuit 22e supplies the selection signal SEL_22 to the other of the source and drain of the transistor 55_22.

[0142] The switch driver circuit 22e supplies the selection result write signal MEM to the gates of the transistors 55_11, 55_21, 55_12, and 55_22. Therefore, the switch driver circuit 22e can supply the same selection result write signal MEM to the gates of all transistors 55, for example.

[0143] The other of the source and drain of the transistor 54_11 and the other electrode of the capacitor 56_11 are electrically connected to the wiring 65_11. The other of the source and drain of the transistor 54_21 and the other electrode of the capacitor 56_21 are electrically connected to the wiring 65_21. The other of the source and drain of the transistor 54_12 and the other electrode of the capacitor 56_12 are electrically connected to the wiring 65_12. The other of the source and drain of the transistor 54_22 and the other electrode of the capacitor 56_22 are electrically connected to the wiring 65_22.

[0144] The signal output from the other of the source and drain of the transistor 54_11 is referred to as signal OUT_11. The signal output from the other of the source and drain of the transistor 54_21 is referred to as signal OUT_21. The signal output from the other of the source and drain of the transistor 54_12 is referred to as signal OUT_12. The signal output from the other of the source and drain of the transistor 54_22 is referred to as signal OUT_22.

[0145] Figure 6 The switch circuit 52c shown in the figure outputs the signal OUT_11 when the potential of the node N_11 is high and the potentials of the nodes N_21, N_12 and N_22 are low. Figure 6 The switch circuit 52c shown in the figure outputs a signal OUT_21 when the potential of the node N_21 is high and the potentials of the nodes N_11, N_12 and N_22 are low. Figure 6 The switch circuit 52c shown in the figure outputs the signal OUT_12 when the potential of the node N_12 is high and the potentials of the node N_11, the node N_21 and the node N_22 are low. Figure 6 The switch circuit 52 c shown outputs the signal OUT_22 when the potential of the node N_22 is high and the potentials of the nodes N_11 , N_21 , and N_12 are low, for example.

[0146] Figure 7 4 is a circuit diagram showing a configuration example of a switch circuit 52 d when the semiconductor device 10 includes the memory cell array 41_11 , the memory cell array 41_21 , the memory cell array 41_12 , and the memory cell array 41_22 . Figure 7 The switch circuit 52d shown as the circuit 53 includes a circuit 53_11, a circuit 53_21, a circuit 53_12 and a circuit 53_22. Figure 6 The switch circuit 52c shown has a different structure, and the description of the same structure will be appropriately omitted.

[0147] One of the source and drain of the transistor 54_11 is electrically connected to the wiring 67_11. One of the source and drain of the transistor 54_21 is electrically connected to the wiring 67_21. One of the source and drain of the transistor 54_12 is electrically connected to the wiring 67_12. One of the source and drain of the transistor 54_22 is electrically connected to the wiring 67_22.

[0148] The other of the source and drain of the transistor 54_11, the other of the source and drain of the transistor 54_21, the other of the source and drain of the transistor 54_12, and the other of the source and drain of the transistor 54_22 are electrically connected to the bit line driver circuit 22 d via the wiring 68. Therefore, for example, the other of the source and drain of all the transistors 54 can be electrically connected to one wiring 68.

[0149] The signal supplied to one of the source and drain of the transistor 54_11 is referred to as signal IN_11. The signal supplied to one of the source and drain of the transistor 54_21 is referred to as signal IN_21. The signal supplied to one of the source and drain of the transistor 54_12 is referred to as signal IN_12. The signal supplied to one of the source and drain of the transistor 54_22 is referred to as signal IN_22.

[0150] Figure 7 The switch circuit 52d shown in the figure outputs the signal IN_11 as the signal OUT when the potential of the node N_11 is high and the potentials of the nodes N_21, N_12, and N_22 are low. Figure 7 The switch circuit 52d shown in the figure outputs the signal IN_21 as the signal OUT when the potential of the node N_21 is high and the potentials of the nodes N_11, N_12 and N_22 are low. Figure 7 The switch circuit 52d shown in the figure outputs the signal IN_12 as the signal OUT when the potential of the node N_12 is high and the potentials of the node N_11, the node N_21 and the node N_22 are low. Figure 7 The switch circuit 52 d shown outputs the signal IN_22 as the signal OUT when the potential of the node N_22 is high and the potentials of the nodes N_11 , N_21 , and N_12 are low, for example.

[0151] As described above, the switch circuits 52c and 52d can be provided with the same number of circuits 53 as the memory cell array 41. Alternatively, the switch circuits 52a and 52b can be provided with the same number of circuits 53 as the memory cell array 41.

[0152] [Register circuit] Figure 8A is a circuit diagram showing a configuration example of register circuit 50. As described above, register circuit 50 includes flip-flop circuit 24 and backup circuit 34. Flip-flop circuit 24 includes node D1, node Q1, node TD, node SE, node RT, node CK, and clock buffer circuit 24A.

[0153] Node D1 is a data input node, node Q1 is a data output node, and node TD is an input node for scan test data. Node SE is an input node for signal SCE. Node CK is an input node for clock signal GCLK1. Clock signal GCLK1 is input to clock buffer circuit 24A. Node RT is an input node for a reset signal.

[0154] The flip-flop circuit 24 is electrically connected to a power line PL. A power supply potential is supplied to the flip-flop circuit 24 via the power line PL. The power line PL can be supplied with a high potential or a low potential, for example. For example, by supplying a high potential to the power line PL, data is retained at the node Q1. When the potential of the power line PL drops to a low potential, the data retained at the node Q1 is lost. Furthermore, the flip-flop circuit 24 is supplied with a potential VSS. The potential VSS can be, for example, a low potential.

[0155] The circuit structure of the trigger circuit 24 is not limited to Figure 8A . You can use trigger circuits prepared in standard circuit libraries.

[0156] The backup circuit 34 includes a node TD_IN, a node N11 , a transistor M11 , a transistor M12 , a transistor M13 , and a capacitor C11 .

[0157] Node TD_IN is an input node for test data. Node N11 is a holding node for backup circuit 34. Capacitor C11 is a storage capacitor for holding the voltage at node N11. One electrode of capacitor C11 is electrically connected to node N11. The other electrode of capacitor C11 can be supplied with potential VSS.

[0158] Transistor M11 controls the conduction state between node Q1 and node N11. Transistor M12 controls the conduction state between node N11 and node TD. Transistor M13 controls the conduction state between node TD_IN and node TD. Transistors M11 and M13 are turned on / off by signal BKH, while transistor M12 is turned on / off by signal RCH.

[0159] As described above, the off-state current of the OS transistor is extremely small. Therefore, by using OS transistors as the transistors M11 and M12, the potential of the node N11 can be maintained for a long time. This makes the backup circuit 34 non-volatile.

[0160] Figure 8B is a diagram showing a configuration example of the backup circuit 34 and Figure 8A The circuit diagram of the nodes shown in FIG. 1 and the layers in which these are provided are shown. Figure 8BAs shown, transistors M11 to M13 are provided in layer 30. Therefore, when transistors M11 and M12 are OS transistors, transistor M13 may also be an OS transistor.

[0161] The backup circuit 34 has a much smaller number of components than the flip-flop circuit 24. Therefore, stacking the backup circuit 34 eliminates the need to change the circuit structure and layout of the flip-flop circuit 24. This allows for widespread use of the backup circuit 34. Furthermore, since the backup circuit 34 can be positioned so as to overlap with the area where the flip-flop circuit 24 is formed, even with the backup circuit 34, the area overhead of the register circuit 50 can be reduced to zero. Therefore, by placing the backup circuit 34 within the register circuit 50, power gating of the CPU 21 is possible. This power gating requires minimal energy, enabling efficient power gating of the CPU 21.

[0162] Although parasitic capacitance generated by transistor M11 is added to node Q1 when backup circuit 34 is provided, this parasitic capacitance is smaller than the parasitic capacitance of the logic circuit connected to node Q1 and therefore does not affect the operation of flip-flop circuit 24. Even with backup circuit 34, the performance of register circuit 50 is not substantially degraded.

[0163] As the low power consumption state (non-operating state) of the CPU 21 , for example, a clock gating state, a power gating state, and a sleep state can be set.

[0164] When the CPU 21 is switched from the normal operating state to the power gating state, the data of the flip-flop circuit 24 is backed up to the backup circuit 34. When the CPU 21 is restored from the power gating state to the normal operating state, the data of the backup circuit 34 is written back to the flip-flop circuit 24.

[0165] Figure 9 yes Figure 8B A modified example of the structure shown in FIG. 5 is provided in which the switch circuit group 51 is provided in such a manner as to have an area overlapping with the flip-flop circuit 24. For example, a portion of the switch circuit 52 provided in the layer 30 may be provided in such a manner as to overlap with the flip-flop circuit 24. Note that although Figure 9 The middle switch circuit group 51 is not included in the backup circuit 34 , but may be included in the backup circuit 34 .

[0166] Figure 10 2 is a timing chart showing an example of a driving method of the register circuit 50 . Figure 10FIG4 shows an example of the potential changes over time of power line PL, node CK, node Q1, node SE, node TD, signal BKH, signal RCH, and node N11 from time T41 to time T47. As described above, power line PL is electrically connected to flip-flop circuit 24. Node CK, node Q1, node SE, and node TD are provided in flip-flop circuit 24. Signal BKH, signal RCH, and node N11 are provided in backup circuit 34.

[0167] Prior to time T41, the system is in normal operation. Power line PL is input with potential VDD. Potential VDD can be high. Flip-flop circuit 24 operates normally. At this time, signals SCE, BKH, and RCH are low. Because node SE is low, flip-flop circuit 24 retains the data at node D1. Furthermore, at time T41, node N11 of backup circuit 34 is low.

[0168] The backup operation will be described. At time T41, the potential of signal BKH is set to a high level. This turns on transistor M11 of backup circuit 34, and data at node Q1 of flip-flop circuit 24 is written to node N11 of backup circuit 34. When node Q1 of flip-flop circuit 24 is low, node N11 remains low. When node Q1 is high, node N11 reaches a high level.

[0169] At time T42 , the potential of signal BKH is set to a low potential. This turns off transistor M11 and holds the potential of node N11 . Consequently, the data at node Q1 of flip-flop circuit 24 is held at node N11 of backup circuit 34 .

[0170] The operation during power gating will be described. After time T43, the potential of power line PL drops to VSS. As a result, the data on node Q1 disappears. Node N11 continues to hold the data on node Q1 at time T43.

[0171] The operation during recovery will be described. After time T44, the potential of the power supply line PL rises to the potential VDD.

[0172] At time T45, the potential of signal RCH is set to a high level. This turns on transistor M12, and the charge in capacitor C11 is distributed between node N11 and node TD. When node N11 is at a high level, the voltage at node TD rises. Since node SE is at a high level, the data at node TD is written to the input-side latch circuit of flip-flop circuit 24.

[0173] At time T46, the clock signal GCLK1 is input to the node CK. As a result, the data of the input-side latch circuit is written to the node Q1. In other words, the data of the node N11 is written to the node Q1.

[0174] At time T47, the potentials of the node SE and the signal RCH are set to low levels, thereby completing the recovery operation.

[0175] The backup circuit 34 using OS transistors has low dynamic and static power consumption, making it very suitable for normally-off computing. Even if the register circuit 50 is installed, the performance of the CPU 21 is hardly degraded and the dynamic power consumption is hardly increased.

[0176] Thus, by providing the backup circuit 34 in the register circuit 50, data can be retained even when the power supply voltage to the register circuit 50 is stopped. This allows power gating of the CPU 21. Consequently, the semiconductor device 10 can be a low-power semiconductor device. Furthermore, the backup circuit 34 can be provided in a stacked manner with a circuit composed of Si transistors, such as the flip-flop circuit 24. Therefore, the backup circuit 34 can be provided without increasing the circuit area.

[0177] [Storage Unit] Figure 11A 4 is a circuit diagram showing a configuration example of the memory cell 42. The memory cell 42 includes a transistor 43 and a transistor 44.

[0178] One of the source and drain of transistor 43 is electrically connected to wiring 63. The other of the source and drain of transistor 43 is electrically connected to wiring 67. The gate of transistor 43 is electrically connected to one of the source and drain of transistor 44. The other of the source and drain of transistor 44 is electrically connected to wiring 65. The gate of transistor 44 is electrically connected to wiring 61. Here, the node electrically connected to the gate of transistor 43 and one of the source and drain of transistor 44 is referred to as node N12.

[0179] When data is written to memory cell 42, transistor 44 is turned on, and charge is supplied from wiring 65 to node N12. When data is stored in memory cell 42, transistor 44 is turned off, and the charge at node N12 is retained. Here, using a transistor with low off-state current as transistor 44 reduces leakage of charge at node N12, allowing the charge at node N12 to be retained for a long period of time. Examples of transistors with low off-state current include the aforementioned OS transistors.

[0180] Therefore, it is preferable to use an OS transistor as the transistor 44 because data can be retained for a long time in the memory cell 42. In this case, the transistor 43 may also be an OS transistor.

[0181] Figure 11B4 is a circuit diagram showing a structural example of a memory cell 42, and shows a layer in which a transistor 43 is provided and a layer in which a transistor 44 is provided. The transistor 43 can be provided in the layer 40_1. The transistor 44 can be provided in the layer 40_2 on the layer 40_1. For example, both the layer 40_1 and the layer 40_2 include Figure 1 In other words, the memory cell 42 has Figure 11B In the case of the structure shown, the layer 40 may have a two-layer stacked structure. Alternatively, the layer 40_2 may be provided below the layer 40_1. In other words, the transistor 44 may be provided below the transistor 43.

[0182] By providing transistors 43 and 44 in different layers, memory cell 42 can be miniaturized or highly integrated compared to providing transistors 43 and 44 in the same layer. Alternatively, transistors 43 and 44 can be provided in the same layer. In this case, since transistors 43 and 44 can be formed in the same process, the number of manufacturing steps for semiconductor device 10 can be reduced.

[0183] Figure 11C is a circuit diagram showing a structural example of the memory cell 42, and shows Figure 11A The memory cell 42 shown in the figure includes an example of a capacitor 45. One electrode of the capacitor 45 is electrically connected to the node N12. The other electrode of the capacitor 45 has a common constant potential, for example.

[0184] By providing the capacitor 45 in the memory cell 42, the amount of charge that can be held in the node N12 can be increased, thereby allowing the memory cell 42 to hold data for a long time.

[0185] Figure 11D 4 is a circuit diagram showing a structural example of a memory cell 42, and shows a layer provided with a transistor 43, a layer provided with a transistor 44, and a layer provided with a capacitor 45. Figure 11B In the illustrated example as well, the transistor 43 may be provided in the layer 40_1 , and the transistor 44 may be provided in the layer 40_2 .

[0186] The capacitor 45 may be provided in the layer 40_3 located between the layer 40_1 and the layer 40_2. For example, the layer 40_1, the layer 40_2, and the layer 40_3 are all included in Figure 1 In other words, the memory cell 42 has Figure 11D In the case of the structure shown, layer 40 may have a two-layer stacked structure. Note that layer 40_3 may be provided under layer 40_1 or on layer 40_2. In other words, capacitor 45 may be provided under transistor 43 or on transistor 44.

[0187] By providing capacitor 45 in a layer different from transistors 43 and 44, memory cell 42 can be miniaturized or highly integrated, compared to a case where capacitor 45 is provided in the same layer as transistors 43 or 44. Alternatively, capacitor 45 can be provided in the same layer as transistors 43 or 44. Alternatively, transistors 43, 44, and capacitor 45 can all be provided in the same layer. In this case, capacitor 45 can be formed in the same process as one or both of transistors 43 and 44, thereby reducing the number of manufacturing steps for semiconductor device 10.

[0188] Figure 12 It shows 11A to 11D FIG. 4 is a timing chart showing an example of a method for driving the memory cell 42 . Figure 12 An example of the changes over time of wiring 61, wiring 65, wiring 63, wiring 67, and node N12 from time T51 to time T55 is shown. Note that before time T51, the potentials of wiring 61 and wiring 65 are low. On the other hand, the potentials of wiring 63 and wiring 67 are high.

[0189] At time T51, the wiring 65 reaches a potential corresponding to the data. Here, the data written to the memory cell 42 is set to binary digital data. When data "0" is written to the memory cell 42, the potential of the wiring 65 remains low. On the other hand, when data "1" is written to the memory cell 42, the potential of the wiring 65 reaches high.

[0190] Furthermore, at time T51, the potential of wiring 61 is set to a high potential, turning on transistor 44. Consequently, the potential of node N12 becomes the potential corresponding to the data. Consequently, the data is written to memory cell 42. Furthermore, since the potentials of wiring 63 and wiring 67 are both high, the drain potential and source potential of transistor 43 are substantially equal. Consequently, regardless of the potential of node N12, no current flows between the drain and source of transistor 43.

[0191] At time T52, the potential of the wiring 61 is set to a low potential, so that the transistor 44 is turned off. As a result, the potential of the node N12 is maintained, and the data is retained in the memory cell 42. Figure 12 An example is shown in which the potential of the wiring 65 becomes low after the potential of the wiring 61 becomes low.

[0192] At time T53, the wiring 67 is precharged to the potential VPRE. The potential VPRE may be, for example, a high potential.

[0193] At time T54, the potential of wiring 63 is low. Here, as described above, wiring 67 is precharged to a high potential. Consequently, a potential difference is generated between the drain and source of transistor 43. Consequently, a current flows between the drain and source of transistor 43 according to the potential of the gate of transistor 43, i.e., the potential of node N12. When the value of the data stored in memory cell 42 is "1," this current is greater than when it is "0," and the potential of wiring 67 decreases, for example, to a low potential. The data stored in memory cell 42 is read by amplifying the potential change of wiring 67 using a sense amplifier electrically connected to wiring 67.

[0194] When the value of the data held in the memory cell 42 is "0," the current flowing between the drain and source of the transistor 43 is smaller than when the value is "1." Therefore, the potential of the wiring 67 is higher than when the value of the data held in the memory cell 42 is "0." When the value of the data held in the memory cell 42 is "0," the potential of the wiring 67 hardly changes from, for example, the potential VPRE.

[0195] Furthermore, in the memory cells 42 in the unselected rows, the potential of the wiring 63 is maintained at a high potential. Consequently, in the memory cells 42 in the unselected rows, both the drain and source potentials of the transistor 43 are high, and the drain and source potentials of the transistor 43 are substantially equal. Consequently, regardless of the potential of the node N12, no current flows between the drain and source of the transistor 43.

[0196] At time T55, the potential of the wiring 63 is set to a high potential. As a result, the potential of the wiring 67 becomes a high potential regardless of the potential of the node N12. In this way, the operation of reading data from the memory cell 42 is completed.

[0197] The above is an example of a driving method of the memory cell 42 .

[0198] As described above, since the off-state current of the OS transistor is extremely small, the potential of node N12 can be maintained for a long time by using the OS transistor as transistor 44. This eliminates the need to rewrite data (refresh operation) in memory cell 42. Alternatively, the frequency of refresh operations can be minimized. Consequently, the power consumption of semiconductor device 10 can be reduced.

[0199] Figure 13A It shows Figure 11B FIG. 4 is a perspective view showing a more specific structural example of the memory cell 42. As described above, the memory cell 42 includes the transistor 43 and the transistor 44 thereon. Figure 13A Wire 61, wire 63, wire 65, and wire 67 are shown. Figure 13AConductive layer 120, conductive layer 220, semiconductor layer 170, and semiconductor layer 270 are shown. Conductive layer 120 and semiconductor layer 170 are provided in transistor 43, and conductive layer 220 and semiconductor layer 270 are provided in transistor 44. Note that for clarity, insulating layers such as interlayer films are not shown, and wiring 63, wiring 67, part of wiring 65, and wiring 61 are indicated by dotted lines.

[0200] The conductive layer 120 includes a region serving as the gate electrode of the transistor 43 and a region serving as either the source electrode or the drain electrode of the transistor 44. In other words, the conductive layer 120 includes a region serving as both the gate electrode of the transistor 43 and either the source electrode or the drain electrode of the transistor 44.

[0201] The conductive layer 220 has a region serving as a gate electrode of the transistor 44 and is electrically connected to a wiring 61 formed over the conductive layer 220. Alternatively, the conductive layer 220 and the wiring 61 may be formed as the same component.

[0202] Openings are provided in wiring 63 and wiring 67, and semiconductor layer 170 is provided so as to have regions located inside these openings. Semiconductor layer 170 has regions in contact with wiring 63 and wiring 67 inside these openings.

[0203] Semiconductor layer 270 is provided so as to have a region in contact with the top surface of conductive layer 120. Furthermore, an opening is provided in wiring 65, and semiconductor layer 270 is provided so as to have a region located within the opening. Semiconductor layer 270 has a region in contact with wiring 65 within the opening.

[0204] Figure 13A The example in which the width of the wiring 63 is constant in the longitudinal direction is shown, but Figure 13B As shown in FIG. 1 , a structure in which the width of the wiring 63 is increased near the opening may be adopted. The same structure can be applied to the wiring 67 and the wiring 65.

[0205] Figure 14A is a plan view showing a structural example of the transistor 43, Figure 14B 4 is a plan view showing a structural example of the transistor 44. Note that in the plan view, some components are omitted for clarity. Figure 14A and Figure 14B The plan view shown is also the same in the configuration examples of other memory cells 42 described in this embodiment.

[0206] Figure 14C is equivalent to Figure 14A and Figure 14B A diagram of a cross section of line segment A1-A2 is shown. Figure 14D is equivalent to Figure 14A and Figure 14B A diagram of a cross section of line segment B1-B2 is shown.

[0207] Memory cell 42 includes an insulating layer 160, a transistor 43 provided over insulating layer 160, and a transistor 44 provided over transistor 43. Insulating layers 180, 185, 280, and 285 serving as interlayer films may be provided between transistors and between various wirings.

[0208] Insulating layer 160, insulating layer 180, insulating layer 185, and transistor 43 are provided in layer 40_1. Insulating layer 280, insulating layer 285, and transistor 44 are provided in layer 40_2. Note that insulating layer 160 does not necessarily need to be provided in layer 40_1. Furthermore, wiring 61 provided over transistor 44 may also be included in layer 40_2.

[0209] Transistor 43 includes a semiconductor layer 170, an insulating layer 130, and a conductive layer 120. Semiconductor layer 170 serves as a semiconductor layer, insulating layer 130 serves as a gate insulating layer, and conductive layer 120 serves as a gate electrode. Wiring 63 also includes a region serving as one of a source electrode and a drain electrode of transistor 43. Wiring 67 also includes a region serving as the other of a source electrode and a drain electrode of transistor 43.

[0210] Opening 190 is provided to reach insulating layer 160, penetrating wiring 67, insulating layer 180, and wiring 63. The top surface of opening 190 is a generally circular columnar shape. This structure enables miniaturization or high integration of memory cells. Furthermore, the side surfaces of opening 190 are preferably perpendicular to the top surface of insulating layer 160.

[0211] At least a portion of semiconductor layer 170 is provided inside opening 190. Furthermore, semiconductor layer 170 includes a region in contact with the side surface of wiring 63, a region in contact with the side surface of wiring 67, a region in contact with the top surface of insulating layer 160, and a region in contact with the side surface of insulating layer 180, within opening 190.

[0212] Insulating layer 130 is provided so that at least a portion thereof covers opening 190. Conductive layer 120 is provided so that at least a portion thereof is located within opening 190. Conductive layer 120 is preferably provided so as to be embedded in opening 190, and its planar shape is preferably substantially circular to improve integration.

[0213] By adopting such a structure, parasitic capacitance between the conductive layer 120 and the wiring 63 can be reduced.

[0214] like Figure 14EAs shown, when opening 190 is not formed in wiring 63, the top surface of wiring 63 is exposed at the bottom of opening 190. Therefore, parasitic capacitance Cp is generated near the bottom of opening 190. This parasitic capacitance Cp uses one region of conductive layer 120 as one electrode, one region of insulating layer 130 as a dielectric, and one region of wiring 63 facing the bottom surface of conductive layer 120 as the other electrode. In this case, semiconductor layer 170 serves as one or both of the dielectric and the other electrode.

[0215] In one embodiment of the present invention, by providing opening 190 so as to penetrate wiring 63, a region of wiring 63 facing the bottom surface of conductive layer 120 can be formed. That is, in the case of capacitance C = ε × S / d (ε: dielectric constant, S: electrode area, d: dielectric thickness), decreasing the value of electrode area S (S is 0) reduces the value of C.

[0216] exist Figure 14E In the region shown where parasitic capacitance Cp is formed, the dielectric thickness d is small, and parasitic capacitance Cp is a relatively large electrostatic capacitance. Parasitic capacitance Cp is a portion of the parasitic capacitance between conductive layer 120 and wiring 63. Therefore, by adopting a structure that does not form parasitic capacitance Cp, the parasitic capacitance between conductive layer 120 and wiring 63 can be reduced.

[0217] Note that the region of semiconductor layer 170 facing the bottom surface of conductive layer 120 is not in contact with an n-type component (e.g., wiring 63), so its conductivity is i-type (intrinsic) and its resistance is high. Therefore, it can be said that the region of semiconductor layer 170 facing the bottom surface of conductive layer 120 is unlikely to become a component of parasitic capacitance (the other electrode).

[0218] Transistor 44 includes a semiconductor layer 270, an insulating layer 230, and a conductive layer 220. Insulating layer 230 serves as a gate insulating layer, and conductive layer 220 serves as a gate electrode. Furthermore, conductive layer 120 includes a region serving as one of a source electrode and a drain electrode of transistor 44. Furthermore, wiring 65 includes a region serving as the other of a source electrode and a drain electrode of transistor 44.

[0219] An opening 290 is provided to reach conductive layer 120, penetrating wiring 65 and insulating layer 280. The top surface of opening 290 is a generally circular columnar shape. This structure enables miniaturization or high integration of memory cells. Note that the side surfaces of opening 290 are preferably perpendicular to the top surface of conductive layer 120.

[0220] At least a portion of semiconductor layer 270 is provided inside opening 290. Semiconductor layer 270 has a region in contact with the top surface of conductive layer 120, a region in contact with the side surface of wiring 65, and a region in contact with the side surface of insulating layer 280 inside opening 290.

[0221] Insulating layer 230 is provided so that at least a portion of it covers opening 290. Conductive layer 220 is provided so that at least a portion of it is located within opening 290. Furthermore, conductive layer 220 is preferably provided so as to be embedded in opening 290. To improve integration, its planar shape is preferably substantially circular. Wiring 61 is provided on conductive layer 220 and insulating layer 285. Alternatively, conductive layer 220 and wiring 61 may be formed as the same component.

[0222] The diameter of opening 190 is substantially the same as the diameter of opening 290, and opening 190 and opening 290 are preferably provided so as to overlap. Furthermore, in memory cell 42, the width of wiring 63 is substantially the same as the width of wiring 61, and wiring 63 and wiring 61 are preferably provided so as to overlap. Furthermore, in memory cell 42, the width of wiring 67 is substantially the same as the width of wiring 65, and wiring 67 and wiring 65 are preferably provided so as to overlap.

[0223] By adopting this structure, two transistors can be provided in a cell without significantly increasing the cell area. Therefore, the memory cells 42 can be arranged at a high density to increase the storage capacity of the semiconductor device 10. In other words, the memory cells 42 provided in the semiconductor device 10 can be highly integrated.

[0224] In addition, one of the source and drain electrodes of transistor 44 also serves as the gate electrode of transistor 43, that is, transistor 44 is directly connected to transistor 43 rather than through wiring, etc. This minimizes the resistance between them, allowing, for example, rapid data writing.

[0225] Figure 15A It shows Figure 11D 1 is a perspective view of a more specific structural example of the memory cell 42. Note that for clarity, insulating layers such as interlayer films are not shown, and the wiring 61 is shown with dotted lines. In addition, a portion of the capacitor 45 is shown with dotted lines, and a cross section is shown.

[0226] Figure 15B is equivalent to Figure 14A and Figure 14B A diagram of a cross section of line segment A1-A2 is shown. Figure 15C is equivalent to Figure 14A and Figure 14B FIG. 1 is a cross-sectional view of the line segment B1-B2 shown. In addition, Figure 15B and Figure 15C Shown by dotted lines Figure 15A The disconnection position of the capacitor 45 is shown. Note that the Figure 13A 、 Figure 14C and Figure 14D Description of each component having the same structure as shown in FIG.

[0227] Figure 15A 、 Figure 15B and Figure 15C The memory cell 42 shown includes a capacitor 45 in addition to the transistors 43 and 44. The capacitor 45 includes a conductive layer 320, an insulating layer 330, and a wiring 310. The conductive layer 320 serves as one electrode, the insulating layer 330 serves as a dielectric, and the wiring 310 serves as the other electrode.

[0228] An insulating layer 380 is provided over transistor 43, and wiring 310 is provided over insulating layer 380. An opening 390 is provided so as to penetrate wiring 310 and insulating layer 380, and insulating layer 330 is provided so as to cover opening 390. At the bottom of opening 390, an opening is provided in insulating layer 330 that reaches conductive layer 120. Conductive layer 320 is provided so as to fit into opening 390 and to contact conductive layer 120 at the bottom of opening 390. An insulating layer 385 serving as an interlayer film is provided outside opening 390 over insulating layer 330. Here, insulating layer 380, insulating layer 385, and capacitor 45 are provided in layer 40_3.

[0229] Transistor 44 is provided on insulating layer 385 and conductive layer 320. Semiconductor layer 270 of transistor 44 has a region in contact with conductive layer 320 at the bottom of opening 290. In other words, conductive layer 320 can be said to have a region serving as one of the source and drain electrodes of transistor 44. Furthermore, conductive layer 320 can be said to function as a conductor that connects one of the source and drain electrodes of transistor 44 to the gate electrode (conductive layer 120) of transistor 43.

[0230] [Transistor_1] Next, transistors 43 and 44 will be described in detail. Note that as described above, although transistors 43 and 44 differ in wiring connection configurations, they have basically the same structure in terms of operation, so transistor 44 will be described here.

[0231] like Figure 14C and Figure 14DAs shown in , the transistor 44 may include a conductive layer 120, a wiring 65 on the insulating layer 280, a semiconductor layer 270 arranged in contact with the top surface of the conductive layer 120 exposed in the opening 290, the side surface of the insulating layer 280 in the opening 290, the side surface of the wiring 65 in the opening 290 and at least a portion of the top surface of the wiring 65, an insulating layer 230 arranged in contact with the top surface of the semiconductor layer 270, and a conductive layer 220 arranged in contact with the top surface of the insulating layer 230.

[0232] At least part of the components of transistor 44 is provided inside opening 290 . Here, the bottom of opening 290 is the top surface of conductive layer 120 , and the side surfaces of opening 290 are also the side surfaces of insulating layer 280 and wiring 65 .

[0233] The top surface of the opening 290 is in a substantially circular columnar shape. This structure allows for miniaturization or high integration of semiconductor devices. Note that the side surfaces of the opening 290 are preferably perpendicular to the top surface of the wiring 63.

[0234] In order to increase the overlapping area between the transistor 44 and the transistor 43 , the planar shape of the opening 290 is preferably the same as or similar to the planar shape of the opening 190 forming the transistor 43 .

[0235] The portions of semiconductor layer 270, insulating layer 230, and conductive layer 220 disposed within opening 290 reflect the shape of opening 290. Therefore, semiconductor layer 270 is disposed so as to cover the bottom and side surfaces of opening 290, insulating layer 230 is disposed so as to cover semiconductor layer 270, and conductive layer 220 is disposed so as to fit into the recess of insulating layer 230 reflecting the shape of opening 290.

[0236] Note that this embodiment shows an example in which the opening 290 and the conductive layer 220 have a substantially circular shape when viewed from above, but the present invention is not limited to this. For example, the shape of the opening 290 and the conductive layer 220 when viewed from above may also be an ellipse, a polygon such as a square, or a shape with rounded corners. In this case, the maximum width of the opening 290 can be appropriately calculated based on the shape of the opening 290 when viewed from above. Furthermore, the maximum width of the conductive layer 220 can be appropriately calculated based on the shape of the conductive layer 220 when viewed from above.

[0237] For example, when the opening 290 is a quadrangle when viewed from a planar perspective, the maximum width of the opening 290 is preferably the length of the diagonal of the quadrangle. Furthermore, when the conductive layer 220 is a quadrangle when viewed from a planar perspective, the maximum width of the conductive layer 220 may be the length of the diagonal of the quadrangle. Furthermore, for example, when the opening 290 and the conductive layer 220 are elliptical, polygonal, or have curved corners when viewed from a planar perspective, the maximum width of the opening 290 and the conductive layer 220 may be the diameter of the smallest circle (also referred to as the smallest containing circle) that includes the shape of the opening 290 when viewed from a planar perspective.

[0238] The above description of the shape of opening 290 can also be applied to opening 190 . Furthermore, the above description of the shape of conductive layer 220 can also be applied to conductive layer 120 .

[0239] Here, Figure 16A Show Figure 14C and Figure 14D The semiconductor layer 270 and its vicinity are shown in FIG. Figure 16B A plan view including the wiring 65 is shown.

[0240] like Figure 16A As shown, the semiconductor layer 270 includes a region 270i, and regions 270na and 270nb provided so as to sandwich the region 270i.

[0241] Region 270na is a region in semiconductor layer 270 that contacts conductive layer 120. At least a portion of region 270na is used as one of the source region and drain region of transistor 44. Region 270nb is a region in semiconductor layer 270 that contacts wiring 65. At least a portion of region 270nb is used as the other of the source region and drain region of transistor 44. Figure 16B As shown, the wiring 65 is in contact with the entire periphery of the semiconductor layer 270. Therefore, the other of the source region and the drain region of the transistor 44 may be formed on the entire periphery of the portion of the semiconductor layer 270 formed in the same layer as the wiring 65.

[0242] Region 270i is a region of semiconductor layer 270 sandwiched between region 270na and region 270nb. Region 270i includes an area along the side surfaces of opening 290. At least a portion of region 270i serves as a channel formation region for transistor 44. In other words, the channel formation region of transistor 44 is formed in a portion of semiconductor layer 270 located between conductive layer 120 and wiring 65. Alternatively, the channel formation region of transistor 44 can be said to be located in or near a region of semiconductor layer 270 that is in contact with insulating layer 280. Furthermore, the channel formation region of transistor 44 can be said to include an area along the side surfaces of opening 290.

[0243] Similarly, the channel formation region of transistor 43 is formed in a portion of semiconductor layer 170 located between wiring 63 and wiring 67. Alternatively, the channel formation region of transistor 43 can be said to be located in a region of semiconductor layer 170 that is in contact with insulating layer 180 or in a region near the region. Furthermore, the channel formation region of transistor 43 can be said to include a region along the side surfaces of opening 190.

[0244] The channel length of transistor 44 is the distance between the source region and the drain region. In other words, the channel length of transistor 44 is determined by the thickness of insulating layer 280 on conductive layer 120. Figure 16A , the dotted double-headed arrow indicates the channel length L of transistor 44. When viewed in cross section, channel length L is the distance between the end of the region where semiconductor layer 270 and conductive layer 120 are in contact, and the end of the region where semiconductor layer 270 and wiring 65 are in contact. In other words, channel length L corresponds to the length of the side surface of insulating layer 280 on the side of opening 290 when viewed in cross section.

[0245] In conventional transistors, the channel length is set based on the exposure limit of photolithography, but in the present invention, the channel length can be set based on the thickness of insulating layer 280. Therefore, the channel length of transistor 44 can be set to a very fine structure below the exposure limit of photolithography (for example, less than 60 nm, less than 50 nm, less than 40 nm, less than 30 nm, less than 20 nm, or less than 10 nm and greater than 1 nm or greater than 5 nm). As a result, the on-state current of transistor 44 increases, thereby improving the frequency characteristics. As a result, a semiconductor device with a high operating speed can be provided.

[0246] Furthermore, as described above, a channel formation region, a source region, and a drain region can be formed within opening 290. Therefore, compared to conventional transistors in which a channel formation region, a source region, and a drain region are provided separately when viewed from above, the area occupied by transistor 44 can be reduced. This allows for a highly integrated semiconductor device, thereby increasing the storage capacity per unit area.

[0247] In this manner, a transistor having a channel formation region along the side surface of the insulating layer 280 in the opening 290 can be referred to as a vertical transistor or a VFET (Vertical Field Effect Transistor).

[0248] In this specification and the like, a vertical transistor including a metal oxide in a channel formation region is referred to as a vertical OS transistor.

[0249] In addition, with Figure 16B Similarly, on a plane including the channel formation region of the semiconductor layer 270, the semiconductor layer 270, the insulating layer 230, and the conductive layer 220 are arranged in a concentric circle. Therefore, the side surface of the conductive layer 220 arranged in the center is opposite to the side surface of the semiconductor layer 270 via the insulating layer 230. In other words, the entire periphery of the semiconductor layer 270 becomes the channel formation region when viewed from the plane. At this time, for example, the channel width of the transistor 44 is determined by the length of the periphery of the semiconductor layer 270. That is, it can be said that the channel width of the transistor 44 is determined by the maximum width of the opening 290 (the maximum diameter when the shape of the opening 290 when viewed from the plane is circular). In Figure 16A and Figure 16B In FIG, the double-dot chain line double arrow indicates the maximum width D of the opening 290. Figure 16B In FIG, a double-dot chain arrow indicates the channel width W of the transistor 44. By increasing the maximum width D of the opening 290, the channel width per unit area can be increased, thereby increasing the on-state current.

[0250] When forming opening 290 using photolithography, the maximum width D of opening 290 is set based on the exposure limit of the photolithography. Furthermore, the maximum width D of opening 290 is set based on the thicknesses of semiconductor layer 270, insulating layer 230, and conductive layer 220 disposed within opening 290. The maximum width D of opening 290 is preferably, for example, not less than 5 nm, not less than 10 nm, or not less than 20 nm, and not more than 100 nm, not more than 60 nm, not more than 50 nm, not more than 40 nm, or not more than 30 nm. Note that if opening 290 is circular in plan view, the maximum width D of opening 290 corresponds to the diameter of opening 290, and channel width W can be calculated as "D×π."

[0251] In the semiconductor device of one embodiment of the present invention, the channel length L of transistor 44 is preferably smaller than at least the channel width W of transistor 44. The channel length L of transistor 44 is greater than or equal to 0.1 times and less than or equal to 0.99 times, and preferably greater than or equal to 0.5 times and less than or equal to 0.8 times, the channel width W of transistor 44. By adopting this structure, a transistor having excellent electrical characteristics and high reliability can be realized.

[0252] Furthermore, by forming the opening 290 to have a substantially circular shape when viewed from above, the semiconductor layer 270, the insulating layer 230, and the conductive layer 220 are arranged concentrically. This makes the distance between the conductive layer 220 and the semiconductor layer 270 substantially uniform, allowing a substantially uniform gate electric field to be applied to the semiconductor layer 270.

[0253] In the channel formation region of a transistor using a metal oxide as a semiconductor layer, it is preferable that the number of oxygen vacancies or the concentration of impurities such as hydrogen, nitrogen, and metal elements is low compared to the source and drain regions. In addition, hydrogen near oxygen vacancies may form defects (hereinafter sometimes referred to as V O H) and generate electrons that become carriers, so in the channel formation region V O H is also preferably reduced. Thus, the channel formation region of the transistor is a high-resistance region with a low carrier concentration. Therefore, the channel formation region of the transistor can be said to be i-type (intrinsic) or substantially i-type.

[0254] In addition, the source region and drain region of a transistor using a metal oxide as a semiconductor layer are regions where there are more oxygen vacancies than in the channel formation region, and V O The high concentration of H or impurities such as hydrogen, nitrogen, or metal elements increases the carrier concentration, thereby reducing resistance. That is, the source and drain regions of the transistor are n-type regions with higher carrier concentrations and lower resistance than the channel formation region.

[0255] Note, for example, that in Figure 16A In the embodiment, the opening 290 is provided so that the side surface of the opening 290 is perpendicular to the top surface of the wiring 63, but the present invention is not limited thereto. For example, the side surface of the opening 290 may also have an inverse tapered shape.

[0256] The band gap of the metal oxide used as the semiconductor layer 270 is preferably greater than 2 eV, more preferably greater than 2.5 eV. By using a metal oxide with a large band gap as the semiconductor layer 270, the off-state current of the transistor can be reduced. By using a transistor with a small off-state current for a memory cell, the stored content can be maintained for a long time. In other words, since no refresh operation is required or the frequency of the refresh operation is extremely low, the power consumption of the semiconductor device can be substantially reduced. In addition, the frequency of the refresh operation required for a general DRAM (Dynamic Random Access Memory) is about 1 time / 60 msec, and the frequency of the refresh operation of the semiconductor device of one embodiment of the present invention can be about 1 time / 10 sec, that is, 10 times or more or 100 times the frequency of the refresh line operation can be achieved. In addition, by using a semiconductor device of one embodiment of the present invention, the frequency of the refresh operation can be set to more than 1 time / 1 sec and less than 1 time / 100 sec, preferably more than 1 time / 5 sec and less than 1 time / 50 sec.

[0257] Note that as the semiconductor layer 270 , a single layer or a stacked layer of a metal oxide described in [Metal Oxide] to be described later can be used.

[0258] Specifically, the following metal oxide compositions can be used as the semiconductor layer 270: In:M:Zn = 1:3:2 [atomic ratio] or a composition close thereto, In:M:Zn = 1:3:4 [atomic ratio] or a composition close thereto, In:M:Zn = 1:1:0.5 [atomic ratio] or a composition close thereto, In:M:Zn = 1:1:1 [atomic ratio] or a composition close thereto, In:M:Zn = 1:1:1.2 [atomic ratio] or a composition close thereto, In:M:Zn = 1:1:2 [atomic ratio] or a composition close thereto, or In:M:Zn = 4:2:3 [atomic ratio] or a composition close thereto. Note that these compositions fall within a range of ±30% of the desired atomic ratio. Gallium is preferably used as the element M.

[0259] In addition, when depositing a metal oxide by sputtering, the above-mentioned atomic number ratio is not limited to the atomic number ratio of the deposited metal oxide, but may also be the atomic number ratio of the sputtering target used for depositing the metal oxide.

[0260] The composition of the metal oxide used in the semiconductor layer 270 can be analyzed using, for example, energy dispersive X-ray spectroscopy (EDX), X-ray photoelectron spectroscopy (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES). Alternatively, a combination of the above methods can be used for analysis. Note that elements with low content may sometimes be affected by the accuracy of the analysis, and the actual content may be different from the content obtained by analysis. For example, when the content of element M is low, the content of element M obtained by analysis may sometimes be lower than the actual content.

[0261] The metal oxide can be formed using sputtering or atomic layer deposition (ALD) as appropriate. Note that when forming the metal oxide using sputtering, the composition of the formed metal oxide may differ from that of the sputtering target. In particular, the zinc content of the formed metal oxide may be reduced to approximately 50% of the zinc content in the sputtering target.

[0262] The semiconductor layer 270 is preferably crystalline. Examples of crystalline oxide semiconductors include CAAC-OS (c-axis aligned crystalline oxide semiconductor), nc-OS (nanocrystalline oxide semiconductor), polycrystalline oxide semiconductors, and single crystal oxide semiconductors. CAAC-OS or nc-OS is preferably used as the semiconductor layer 270, with CAAC-OS being particularly preferred.

[0263] CAAC-OS preferably has multiple layered crystal regions with their c-axes oriented in the normal direction of the surface on which they are formed. For example, semiconductor layer 270 preferably has layered crystals that are roughly parallel to the sidewalls of opening 290, and particularly, layered crystals that are roughly parallel to the side surfaces of insulating layer 280. This structure allows the layered crystals of semiconductor layer 270 to be roughly parallel to the channel length direction of transistor 44, thereby increasing the on-state current of the transistor.

[0264] CAAC-OS has a dense structure with high crystallinity and is a metal oxide with few impurities and defects (e.g., oxygen vacancies). In particular, by heat-treating the metal oxide after formation at a temperature at which the metal oxide does not undergo polycrystallization (e.g., 400°C to 600°C), CAAC-OS can be given a dense structure with even higher crystallinity. By further increasing the density of CAAC-OS, the diffusion of impurities or oxygen in the CAAC-OS can be further reduced.

[0265] Furthermore, since clear grain boundaries are difficult to observe in CAAC-OS, the decrease in electron mobility caused by these grain boundaries is less likely to occur. Consequently, metal oxides containing CAAC-OS have stable physical properties. Consequently, metal oxides containing CAAC-OS have heat resistance and high reliability.

[0266] Furthermore, when a crystalline oxide such as CAAC-OS is used as the semiconductor layer 270, oxygen extraction from the semiconductor layer 270 via the source electrode or the drain electrode can be suppressed. Therefore, even during heat treatment, oxygen extraction from the semiconductor layer 270 can be suppressed, and the transistor 44 is thus highly stable against the high temperatures (so-called thermal budget) encountered during the manufacturing process.

[0267] The crystallinity of the semiconductor layer 270 can be analyzed, for example, by an X-ray diffraction (XRD) pattern, a transmission electron microscope (TEM) image, or an electron diffraction (ED) pattern, or by combining a plurality of these methods.

[0268] Note that in Figure 14C and Figure 14D The semiconductor layer 270 is shown as a single layer structure in FIG. 1 , but the present invention is not limited thereto. The semiconductor layer 270 may also have a stacked structure of multiple oxide layers with different chemical compositions. For example, a structure in which multiple types of the above-mentioned metal oxides are appropriately stacked may be used.

[0269] When semiconductor layer 270 has a three-layer stacked structure, for example, a metal oxide having a composition of In:Ga:Zn = 1:1:1 [atomic ratio] or a similar composition, a metal oxide having a composition of In:Zn = 1:1 [atomic ratio] or a similar composition, or a metal oxide having a composition of In:Zn = 4:1 [atomic ratio] or a similar composition, and a metal oxide having a composition of In:Ga:Zn = 1:1:1 [atomic ratio] or a similar composition may be provided in this order from the conductive layer 120 side. This structure increases the on-state current of transistor 44, thereby achieving a transistor structure with less variation and higher reliability.

[0270] As the insulating layer 230, a single layer or a stack of insulating materials described in the "Insulator" section described later can be used. For example, silicon oxide or silicon oxynitride can be used as the insulating layer 230. Silicon oxide and silicon oxynitride are preferred because they are thermally stable.

[0271] Alternatively, a material having a high relative dielectric constant, so-called high-k material, described in the section "Insulator" to be described later, may be used as the insulating layer 230. For example, hafnium oxide or aluminum oxide may be used.

[0272] The thickness of the insulating layer 230 is preferably 0.5 nm to 15 nm, more preferably 0.5 nm to 12 nm, and even more preferably 0.5 nm to 10 nm. At least a portion of the insulating layer 230 may be a region having the above thickness.

[0273] The concentration of impurities such as water and hydrogen in the insulating layer 230 is preferably reduced. This can prevent impurities such as water and hydrogen from entering the channel formation region of the semiconductor layer 270 .

[0274] like Figure 14C and Figure 14D As shown in FIG. 2 , a portion of insulating layer 230 is located outside opening 290, that is, on wiring 65 and insulating layer 280. In this case, insulating layer 230 preferably covers the side edges of semiconductor layer 270. This prevents short circuits between conductive layer 220 and semiconductor layer 270. Furthermore, insulating layer 230 preferably covers the side edges of wiring 65. This prevents short circuits between conductive layer 220 and wiring 65.

[0275] Note that in Figure 14C and Figure 14D The insulating layer 230 is shown as a single-layer structure, but the present invention is not limited thereto. The insulating layer 230 may also have a stacked-layer structure.

[0276] A single layer or a stack of conductors described in [Conductor] below can be used as the conductive layer 220. For example, a highly conductive material such as tungsten can be used as the conductive layer 220.

[0277] Furthermore, it is preferable to use a conductive material that is not easily oxidized or a conductive material that has the function of inhibiting oxygen diffusion as the conductive layer 220. Examples of such conductive materials include conductive materials containing nitrogen (e.g., titanium nitride or tantalum nitride) and conductive materials containing oxygen (e.g., ruthenium oxide). This can suppress a decrease in the conductivity of the conductive layer 220.

[0278] Note that in Figure 14C and Figure 14DThe conductive layer 220 is shown as a single-layer structure, but the present invention is not limited thereto and may also have a stacked-layer structure.

[0279] A single layer or a stack of conductors described in [Conductor] below can be used as the wiring 65. For example, a highly conductive material such as tungsten can be used as the wiring 65.

[0280] As with conductive layer 220, wiring 65 is preferably made of a conductive material that is not easily oxidized or has a function of inhibiting oxygen diffusion. For example, titanium nitride or tantalum nitride can be used. This structure can prevent excessive oxidation of wiring 65 by semiconductor layer 270.

[0281] Alternatively, for example, tungsten may be stacked on titanium nitride. By stacking tungsten in this manner, the electrical conductivity of the wiring 65 can be improved.

[0282] Furthermore, when the wiring 65 has a stacked structure of a first conductive layer and a second conductive layer, for example, the first conductive layer may be formed using a highly conductive conductive material, and the second conductive layer may be formed using a conductive material containing oxygen. By using a conductive material containing oxygen as the second conductive layer of the wiring 65 that contacts the insulating layer 230, diffusion of oxygen from the insulating layer 230 into the first conductive layer of the wiring 65 can be suppressed. For example, tungsten is preferably used as the first conductive layer of the wiring 65, and silicon-added indium tin oxide is preferably used as the second conductive layer of the wiring 65.

[0283] When semiconductor layer 270 contacts conductive layer 120, metal compounds or oxygen vacancies are formed, reducing the resistance of region 270na of semiconductor layer 270. By reducing the resistance of semiconductor layer 270 in contact with conductive layer 120, the contact resistance between semiconductor layer 270 and conductive layer 120 can be reduced. Similarly, when semiconductor layer 270 contacts wiring 65, region 270nb of semiconductor layer 270 also reduces the resistance. This reduces the contact resistance between semiconductor layer 270 and wiring 65.

[0284] Since insulating layer 280 serves as an interlayer film, its relative dielectric constant is preferably low. Using a material with a low relative dielectric constant for the interlayer film can reduce the electrostatic capacitance of parasitic capacitance generated between wirings. As insulating layer 280, a single layer or a stack of insulators containing a material with a low relative dielectric constant, as described in the "Insulator" section below, can be used. Silicon oxide and silicon oxynitride are preferred due to their thermal stability.

[0285] Furthermore, the concentration of impurities such as water and hydrogen in the insulating layer 280 is preferably reduced. This can prevent impurities such as water and hydrogen from entering the channel formation region of the semiconductor layer 270 .

[0286] In addition, as the insulating layer 280, it is preferable to use an insulator containing oxygen that is released by heating (hereinafter sometimes referred to as excess oxygen). By heat-treating the insulating layer 280 containing excess oxygen, oxygen can be supplied from the insulating layer 280 to the channel formation region of the semiconductor layer 270, thereby reducing oxygen vacancies and V O H. This can stabilize the electrical characteristics of the transistor 44 and improve reliability.

[0287] Alternatively, an insulator having the function of capturing or fixing hydrogen, as described in the "Insulator" section below, may be used as insulating layer 280. This structure allows hydrogen in semiconductor layer 270 to be captured or fixed, thereby reducing the hydrogen concentration in semiconductor layer 270. Examples of insulating layer 280 include magnesium oxide and aluminum oxide.

[0288] Note that in Figure 14C and Figure 14D The insulating layer 280 is shown as a single-layer structure, but the present invention is not limited thereto and may also have a stacked-layer structure.

[0289] [Transistor_2] Figure 17A A plan view of a transistor 800 is shown which has a structure different from the above-described structural example. Figure 17B Shown along Figure 17A Cross-sectional view along the dotted line C1-C2 in FIG. Figure 17B It is also a cross-sectional view of the transistor 800 along the channel length direction. Figure 17C Shown along Figure 17A Cross-sectional view along the dotted line C3-C4. Figure 17C It is also a cross-sectional view of the transistor 800 in the channel width direction. Figure 17D Shown along Figure 17A Cross-sectional view along the dotted line C5-C6. Figure 17D It is also a cross-sectional view of the channel width direction of the transistor 800. Note that Figure 17A In the plan view, some components are omitted for clarity.

[0290] The transistor 800 includes a conductive layer 805 (conductive layer 805a and conductive layer 805b) arranged in a manner embedded in an insulating layer 816, an insulating layer 816 and an insulating layer 821 on the conductive layer 805, an insulating layer 822 on the insulating layer 821, an insulating layer 824 on the insulating layer 822, a semiconductor layer 820 on the insulating layer 824, a conductive layer 842a (conductive layer 842a1 and conductive layer 842a2) and a conductive layer 842b (conductive layer 842b1 and conductive layer 842b2) on the semiconductor layer 820, an insulating layer 871a on the conductive layer 842a, an insulating layer 871b on the conductive layer 842b, an insulating layer 850 on the semiconductor layer 820, and a conductive layer 860 (conductive layer 860a and conductive layer 860b) on the insulating layer 850.

[0291] An insulating layer 875 is provided on the insulating layer 871a and the insulating layer 871b, and an insulating layer 885 is provided on the insulating layer 875. The insulating layer 855, the insulating layer 850, and the conductive layer 860 are provided within the openings provided in the insulating layer 885 and the insulating layer 875. Furthermore, an insulating layer 882 is provided on the insulating layer 885 and the conductive layer 860. Furthermore, an insulating layer 883 is provided on the insulating layer 882. Furthermore, the insulating layer 815 is provided under the insulating layer 816 and the conductive layer 805. Furthermore, an insulating layer 855 is provided between the conductive layer 842a2, the conductive layer 842b2, the insulating layer 871a, the insulating layer 871b, the insulating layer 875, the insulating layer 885, and the insulating layer 850.

[0292] The insulating layer 815, the insulating layer 816, the conductive layer 805, the insulating layer 821, the insulating layer 822, the insulating layer 824, the semiconductor layer 820, the conductive layer 842a, the conductive layer 842b, the insulating layer 871a, the insulating layer 871b, the insulating layer 875, the insulating layer 885, the insulating layer 855, the insulating layer 850, the conductive layer 860, the insulating layer 882 and the insulating layer 883 can all have a single-layer structure or a stacked-layer structure.

[0293] The semiconductor layer 820 includes a region serving as a channel formation region of the transistor 800. Furthermore, the conductive layer 860 includes a region serving as a first gate electrode (upper gate electrode) of the transistor 800. The insulating layer 850 includes a region serving as a first gate insulating layer of the transistor 800. Furthermore, the conductive layer 805 includes a region serving as a second gate electrode (lower gate electrode) of the transistor 800. The insulating layer 824, the insulating layer 822, and the insulating layer 821 all include a region serving as a second gate insulating layer of the transistor 800.

[0294] The conductive layer 842a has a region serving as one of a source electrode and a drain electrode of the transistor 800. The conductive layer 842b has a region serving as the other of a source electrode and a drain electrode of the transistor 800.

[0295] The semiconductor layer 820 includes a channel formation region of the transistor 800 and a source region and a drain region disposed so as to sandwich the channel formation region. At least a portion of the channel formation region overlaps with the conductive layer 860. The source region overlaps with the conductive layer 842a, and the drain region overlaps with the conductive layer 842b. Note that the source and drain regions may be swapped.

[0296] A metal oxide can be used as the semiconductor layer 820. For example, the semiconductor layer 820 can be made of the same material as that used for the semiconductor layer 170 and the semiconductor layer 270 described above.

[0297] The conductive layer 842a has a stacked structure consisting of a conductive layer 842a1 and a conductive layer 842a2 on the conductive layer 842a1. The conductive layer 842b has a stacked structure consisting of a conductive layer 842b1 and a conductive layer 842b2 on the conductive layer 842b1. The conductive layers 842a1 and 842b1 in contact with the semiconductor layer 820 are preferably conductive layers that are not easily oxidized, such as metal nitrides. This prevents oxygen contained in the semiconductor layer 820 from excessively oxidizing the conductive layers 842a and 842b. Furthermore, the conductive layers 842a2 and 842b2 are preferably conductive layers, such as metal layers, having higher conductivity than the conductive layers 842a1 and 842b1. This allows the conductive layers 842a and 842b to function as highly conductive wiring or electrodes.

[0298] For example, tantalum nitride or titanium nitride can be used for the conductive layers 842a1 and 842b1, and tungsten can be used for the conductive layers 842a2 and 842b2.

[0299] The openings provided in insulating layer 885 and insulating layer 875 overlap the region between conductive layer 842a2 and conductive layer 842b2. When viewed from above, the side surfaces of the opening in insulating layer 885 coincide with or substantially coincide with the side surfaces of conductive layer 842a2 and conductive layer 842b2. Furthermore, portions of conductive layer 842a1 and conductive layer 842b1 are formed so as to protrude into the aforementioned openings. Here, a portion of the top surface of conductive layer 842a1 contacts conductive layer 842a2, and a portion of the top surface of conductive layer 842b1 contacts conductive layer 842b2. Therefore, in the aforementioned openings, insulating layer 855 contacts another portion of the top surface of conductive layer 842a1, another portion of the top surface of conductive layer 842b1, and the side surfaces of conductive layer 842a2 and conductive layer 842b2. In addition, the insulating layer 850 is in contact with the top surface of the semiconductor layer 820 , the side surface of the conductive layer 842 a 1 , the side surface of the conductive layer 842 b 1 , and the side surface of the insulating layer 855 .

[0300] The insulating layer 855 is preferably an insulating layer that is not easily oxidized, such as a nitride. The insulating layer 855 is formed into a sidewall shape by anisotropic etching, for example, in contact with the sidewalls of the opening provided in the insulating layer 885 (here, the sidewalls of the opening correspond to, for example, the side surfaces of the insulating layer 885). The insulating layer 855 is formed in contact with the side surfaces of the conductive layer 842a2 and the side surfaces of the conductive layer 842b2, and has the function of protecting the conductive layers 842a2 and 842b2. In order to supply oxygen to the semiconductor layer 820, it is preferable to perform a heat treatment in an oxygen-containing atmosphere after separating the conductive layer 842a1 and the conductive layer 842b1 and before depositing the insulating layer 850. At this time, by forming the insulating layer 855 in contact with the side surfaces of the conductive layer 842a2 and the side surfaces of the conductive layer 842b2, the conductive layer 842a2 and the conductive layer 842b2 can be prevented from being excessively oxidized. For example, silicon nitride can be used as the insulating layer 855.

[0301] The insulating layer 850 in contact with the channel formation region in the semiconductor layer 820 preferably has a function of trapping or fixing hydrogen. This can reduce the hydrogen concentration in the channel formation region of the semiconductor layer 820. This can reduce the V O H, and the channel formation region can be made i-type or substantially i-type.

[0302] The insulating layer 850 serves as a gate insulating layer. The insulating layer 850, together with the insulating layer 855 and the conductive layer 860, is provided in an opening formed in the insulating layer 885. To achieve miniaturization of the transistor 800, the thickness of the insulating layer 850 is preferably small. The thickness of the layer constituting the insulating layer 850 is preferably 0.1 nm or more and 10 nm or less, more preferably 0.1 nm or more and 5.0 nm or less, further preferably 0.5 nm or more and 5.0 nm or less, further preferably 1.0 nm or more and less than 5.0 nm, and still further preferably 1.0 nm or more and 3.0 nm or less. It is sufficient that at least a portion of each layer constituting the insulating layer 850 includes a region having the above-mentioned thickness.

[0303] In order to reduce the thickness of the insulating layer 850, it is preferable to use the ALD method for deposition. In addition, for example, in order to arrange the insulating layer 850 and the insulating layer 855 in the opening portion of the insulating layer 885, it is preferable to use the ALD method for deposition. ALD methods include thermal ALD (Thermal ALD) method, which uses only thermal energy to react precursors and reactants, and PEALD (Plasma Enhanced ALD) method, which uses reactants excited by plasma. In the PEALD method, deposition at a lower temperature can be performed by using plasma, so it is sometimes preferred.

[0304] The thickness of the insulating layer 855 is preferably 0.5 nm to 20 nm, more preferably 0.5 nm to 10 nm, and even more preferably 0.5 nm to 3 nm. By setting the insulating layer 855 to have this thickness, excessive oxidation of the conductive layer 842a2 and the conductive layer 842b2 can be suppressed. It is sufficient that at least a portion of the insulating layer 855 includes a region having the above thickness. If the thickness of the insulating layer 855 is too large, the deposition time of the insulating layer 855 using the ALD method becomes longer, resulting in reduced productivity. Therefore, the thickness of the insulating layer 855 is preferably within the above range.

[0305] For example, Figure 17A The semiconductor device shown preferably has a structure that inhibits hydrogen from mixing into the transistor 800. For example, it is preferable to provide an insulator having the function of inhibiting hydrogen diffusion in a manner that covers one or both of the upper and lower portions of the transistor 800. Therefore, the insulating layer 815, the insulating layer 821, the insulating layer 822, the insulating layer 882, and the insulating layer 883 preferably all include an insulator having the function of inhibiting the diffusion of impurities such as water, hydrogen, and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and zirconium (hafnium zirconium oxide), gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon oxynitride can be used. For example, the insulating layer 883 and the insulating layer 821 preferably use silicon nitride, which has a higher hydrogen barrier property. In addition, for example, the insulating layer 882 preferably uses aluminum oxide, which has a high ability to capture or fix hydrogen. For example, the insulating layer 822 preferably uses hafnium oxide, which has a high ability to capture or fix hydrogen and is a high dielectric constant (high-k) material. Thus, by adopting a structure in which the upper and lower sides of the transistor 800 are surrounded by an insulating layer that has the function of inhibiting the diffusion of impurities such as water and hydrogen, as well as oxygen, it is possible to reduce the diffusion of excess oxygen and hydrogen into the metal oxide, thereby improving the electrical characteristics and reliability of the semiconductor device.

[0306] Here, it is preferred that the region of insulating layer 875 that does not overlap with semiconductor layer 820 is in contact with insulating layer 822, the side edges of insulating layer 875 are in contact with insulating layer 855, and the upper edges of insulating layer 855 and insulating layer 850 are in contact with insulating layer 882. With this structure, in the region sandwiched between insulating layer 883 and insulating layer 821, insulating layer 885 is separated from semiconductor layer 820 by insulating layer 875, and insulating layer 885 is separated from insulating layer 850 by insulating layer 855. This prevents impurities such as water and hydrogen contained in insulating layer 885 from diffusing into semiconductor layer 820 and insulating layer 850. Furthermore, hydrogen contained in insulating layer 850 can be trapped and fixed by insulating layer 882. This structure further reduces the diffusion of hydrogen into the metal oxide. Consequently, the electrical characteristics and reliability of the semiconductor device can be improved.

[0307] In the transistor 800, the conductive layer 805 is arranged so as to overlap with the semiconductor layer 820 and the conductive layer 860. Here, the conductive layer 805 is preferably provided so as to be embedded in the opening formed in the insulating layer 816. Figure 17A and Figure 17C As shown in FIG. 8 , the conductive layer 805 is preferably extended in the channel width direction. By adopting this structure, the conductive layer 805 can be used as a wiring when a plurality of transistors are provided.

[0308] like Figure 17B and Figure 17C As shown, conductive layer 805 preferably includes conductive layer 805a and conductive layer 805b. Conductive layer 805a is provided so as to contact the bottom surface and sidewalls of the aforementioned opening. Conductive layer 805b is provided so as to fit into the recessed portion of conductive layer 805a formed along the aforementioned opening. Here, the height of the top surface of conductive layer 805 is equal to or substantially equal to the height of the top surface of insulating layer 816.

[0309] By using a conductive material that inhibits hydrogen diffusion as the conductive layer 805a, impurities such as hydrogen contained in the conductive layer 805b can be prevented from diffusing into the semiconductor layer 820, for example, through the insulating layer 816. Furthermore, by using a conductive material that inhibits oxygen diffusion as the conductive layer 805a, oxidation of the conductive layer 805b and a reduction in conductivity can be suppressed. Examples of conductive materials that inhibit oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. The conductive layer 805a can have a single layer structure or a stacked layer structure of the above conductive materials. For example, the conductive layer 805a preferably includes titanium nitride.

[0310] The conductive layer 805b is preferably made of a conductive material mainly composed of tungsten, copper, or aluminum. For example, the conductive layer 805b preferably contains tungsten.

[0311] The conductive layer 805 can be used as a second gate electrode. In this case, by independently changing the potential supplied to the conductive layer 805 without interlocking it with the potential supplied to the conductive layer 860, the threshold voltage (Vth) of the transistor 800 can be controlled. In particular, by supplying a negative potential to the conductive layer 805, the Vth of the transistor 800 can be increased and the off-state current can be reduced. Therefore, compared to when no negative potential is applied to the conductive layer 805, when a negative potential is applied to the conductive layer 805, the drain current when the potential supplied to the conductive layer 860 is 0V can be reduced.

[0312] The resistivity of the conductive layer 805 is designed taking into account the potential applied to the conductive layer 805, and the thickness of the conductive layer 805 is set based on this resistivity. Furthermore, the thickness of the insulating layer 816 is substantially the same as that of the conductive layer 805. It is preferable to reduce the thickness of the conductive layer 805 and the insulating layer 816 within the design allowable range of the conductive layer 805. Reducing the thickness of the insulating layer 816 can reduce the absolute amount of impurities such as hydrogen contained in the insulating layer 816, thereby suppressing the diffusion of these impurities into the semiconductor layer 820.

[0313] The insulating layer 824 in contact with the semiconductor layer 820 preferably includes, for example, silicon oxide or silicon oxynitride. This allows oxygen to be supplied from the insulating layer 824 to the semiconductor layer 820, thereby reducing oxygen vacancies.

[0314] The insulating layer 824 is preferably processed into an island shape, similar to the semiconductor layer 820. Thus, when multiple transistors 800 are provided, each transistor 800 includes an insulating layer 824 of substantially the same size. This ensures that the amount of oxygen supplied from the insulating layer 824 to the semiconductor layer 820 in each transistor 800 is substantially equal. This can suppress variations in the electrical characteristics of the transistors 800 within the substrate plane. However, this is not limiting; a structure in which the insulating layer 824 is not patterned, similar to the insulating layer 822, can also be employed.

[0315] In this specification, "island-shaped" refers to a state in which two or more layers formed of the same material in the same process are physically separated. For example, an island-shaped light-emitting layer means that the light-emitting layer is physically separated from the adjacent light-emitting layer.

[0316] A conductive material that is not easily oxidized or a conductive material that has a function of inhibiting oxygen diffusion is preferably used for the conductive layers 842a, 842b, and 860. Examples of such conductive materials include conductive materials containing nitrogen and conductive materials containing oxygen. This can suppress the conductivity of the conductive layers 842a, 842b, and 860.

[0317] Insulating layers 871a and 871b are inorganic insulating layers that serve as etching stop layers and protect conductive layers 842a2 and 842b2 during processing. Since insulating layers 871a and 871b are in contact with conductive layers 842a2 and 842b2, they are preferably made of an inorganic insulator that is less likely to oxidize conductive layers 842a and 842b. For example, insulating layers 871a and 871b preferably have a stacked-layer structure of a nitride insulator and an oxide insulator.

[0318] In this specification, etc., a transistor structure in which a channel forming region is surrounded by the electric field of at least the first gate electrode is referred to as a surrounded channel (S-channel) structure. In addition, the S-channel structure disclosed in this specification, etc. is different from a Fin-type structure and a planar structure. On the other hand, the S-channel structure disclosed in this specification, etc. can be regarded as a type of Fin-type structure. In this specification, etc., a Fin-type structure refers to a structure in which a gate electrode is arranged in a manner surrounding at least two or more surfaces of a channel (specifically, two surfaces, three surfaces, or four surfaces, etc.). By adopting a Fin-type structure and an S-channel structure, resistance to short channel effects can be improved. In other words, a transistor that is not prone to short channel effects can be realized.

[0319] By adopting the above-mentioned S-channel structure as the transistor 800, the channel formation region can be electrically surrounded. The S-channel structure is a structure that electrically surrounds the channel formation region, so it can be said that the structure is essentially the same as the GAA (Gate All Around: full surround gate) structure or the LGAA (Lateral Gate All Around: lateral full surround gate) structure. By making the transistor 800 have an S-channel structure, a GAA structure, or a LGAA structure, the channel formation region formed at or near the interface between the semiconductor layer 820 and the gate insulating layer can be regarded as the entire bulk of the semiconductor layer 820. Therefore, the current density flowing through the transistor can be increased, so it can be expected that the on-state current of the transistor can be increased or the field effect mobility of the transistor can be increased.

[0320] In this embodiment, the insulating layer 824 is configured as an island. Figure 17C As shown, at least a portion of the bottom surface of the conductive layer 860 can be disposed below the bottom surface of the semiconductor layer 820. Thus, the conductive layer 860 can be disposed opposite the top surface and side surfaces of the semiconductor layer 820, so that the electric field of the conductive layer 860 can act on the top surface and side surfaces of the semiconductor layer 820. Thus, by adopting a structure in which the insulating layer 824 is disposed in an island shape, the transistor 800 can have an S-channel structure.

[0321] The conductive layer 860 preferably includes a conductive layer 860a and a conductive layer 860b disposed on the conductive layer 860a. For example, the conductive layer 860a is preferably disposed so as to surround the bottom and side surfaces of the conductive layer 860b. In this case, a conductive material that is not easily oxidized or a conductive material that has the function of inhibiting oxygen diffusion is preferably used as the conductive layer 860a. By providing the conductive layer 860a with the function of inhibiting oxygen diffusion, for example, the oxygen contained in the insulating layer 885 can be prevented from oxidizing the conductive layer 860b and causing a decrease in conductivity. Examples of conductive materials that have the function of inhibiting oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide.

[0322] The conductive layer 860b is preferably made of a highly conductive conductor. For example, the conductive layer 860b can be made of a conductive material primarily composed of tungsten, copper, or aluminum. Furthermore, the conductive layer 860b can have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the aforementioned conductive materials.

[0323] The dielectric constant of the insulating layer 816 and the insulating layer 885 is preferably lower than that of the insulating layer 822. By using a material with a low dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced.

[0324] The transistor 800 having the above structure can be used, for example, as a transistor provided in the layer 30. Therefore, the transistors included in the switch circuit 52, specifically the transistors 54 and 55, can be transistors having the same structure as the transistor 800. Furthermore, the transistors included in the backup circuit 34, specifically the transistors M11 to M13, can be transistors having the same structure as the transistor 800.

[0325] In addition, the transistors provided in layer 30 may also have the same structure as transistor 43 or transistor 44. That is, the transistors provided in layer 30 may also be vertical transistors. For example, transistor 54, transistor 55, and transistors M11 to M13 may also be vertical transistors. In addition, transistor 43 and transistor 44 may also be transistors having the same structure as transistor 800. In addition, one of transistor 43 and transistor 44 may also be a vertical transistor, and the other of transistor 43 and transistor 44 may also be a transistor having the same structure as transistor 800. For example, transistor 43 may also be a vertical transistor, and transistor 44 may also be a transistor having the same structure as transistor 800.

[0326] <Semiconductor Device Structure Example_2> Figure 18 1 is a cross-sectional view showing a structural example of the layer 20, the layer 30, the layer 40_1, and the layer 40_2 included in the semiconductor device 10. Figure 18, the transistor 57 is shown as a transistor provided in the layer 20 , the transistor 54 is shown as a transistor provided in the layer 30 , the transistor 43 is shown as a transistor provided in the layer 40_1 , and the transistor 44 is shown as a transistor provided in the layer 40_2 .

[0327] The transistor 57 is provided on the substrate 311 and includes a conductive layer 316 serving as a gate electrode, an insulating layer 315 serving as a gate insulating layer, an insulating layer 317 formed on the side of the conductive layer 316, a semiconductor region 313 including a portion of the substrate 311, a low resistance region 314a serving as one of a source region and a drain region, and a low resistance region 314b serving as the other of the source region and the drain region. The transistor 57 may be a p-channel transistor or an n-channel transistor. For example, the transistor 57 may be Figure 1 The transistor included in the driving circuit 22 shown in FIG. Alternatively, for example, the transistor included in the CPU 21 may be a transistor having the same structure as the transistor 57. As the substrate 311, for example, a single crystal silicon substrate may be used.

[0328] Here, in Figure 18 In the transistor 57 shown, the semiconductor region 313 (a portion of the substrate 311) forming the channel has a convex shape. In addition, a conductive layer 316 is provided in a manner that covers the side and top surfaces of the semiconductor region 313 via an insulating layer 315. In addition, a material that adjusts the work function can also be used for the conductive layer 316. This transistor 57 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. In addition, an insulating layer used as a mask for forming the convex portion can also be included in a manner that contacts the upper portion of the convex portion. In addition, although the case where a portion of the semiconductor substrate is processed to form the convex portion is shown here, an SOI (Silicon on Insulator) substrate can also be processed to form a semiconductor film having a convex shape.

[0329] Notice, Figure 18 The structure of the transistor 57 shown is only an example and is not limited to the above structure. An appropriate transistor may be used depending on the circuit structure, driving method, etc.

[0330] A wiring layer, including interlayer films, wiring, and plugs, may be provided between the various structures. Furthermore, the wiring layer may be provided in multiple layers depending on the design. Furthermore, in this specification and other contexts, wiring and plugs electrically connected to the wiring may be considered a single component. In other words, a portion of a conductive layer may be used as wiring, and a portion of a conductive layer may be used as a plug.

[0331] For example, an insulating layer 321, an insulating layer 301, an insulating layer 324, and an insulating layer 326 are sequentially stacked as interlayer films over the transistor 57. Furthermore, for example, a conductive layer 328 is embedded in the insulating layer 321 and the insulating layer 301. Furthermore, for example, a conductive layer 331 is embedded in the insulating layer 324 and the insulating layer 326. Furthermore, the conductive layers 328 and 331 function as plugs or wiring.

[0332] Furthermore, the insulating layer used as an interlayer film can be used as a planarization film to cover the concavo-convex shape thereunder. For example, to improve the flatness of the top surface of the insulating layer 301, the top surface can also be planarized by, for example, a chemical mechanical polishing (CMP) method.

[0333] Alternatively, a wiring layer may be provided over the insulating layer 326 and the conductive layer 331. Figure 18 In the embodiment, an insulating layer 350, an insulating layer 357, and an insulating layer 352 are stacked in this order over the insulating layer 326 and the conductive layer 331. A conductive layer 356 is formed between the insulating layer 350, the insulating layer 357, and the insulating layer 352. The conductive layer 356 is used as a plug or wiring.

[0334] Figure 18 The transistor 54 provided in the layer 30 is shown to have Figure 17B 800. Layer 30 includes an insulating layer 815, an insulating layer 816, an insulating layer 821, an insulating layer 822, an insulating layer 875, an insulating layer 885, an insulating layer 882, an insulating layer 883, and an insulating layer 887 stacked in this order. The insulating layer 887 can be made of the same material as that used for the insulating layer 816.

[0335] exist Figure 18 In the illustrated example, openings reaching the conductive layer 356 are provided in the insulating layer 815, the insulating layer 816, the insulating layer 821, the insulating layer 822, the insulating layer 875, the insulating layer 885, the insulating layer 882, the insulating layer 883, and the insulating layer 887, and a conductive layer 891 is provided so as to fit into these openings. Furthermore, openings reaching the conductive layer 842a are provided in the insulating layer 871a, the insulating layer 875, the insulating layer 885, the insulating layer 882, the insulating layer 883, and the insulating layer 887, and a conductive layer 891 is provided so as to fit into these openings. Furthermore, openings reaching the conductive layer 860 are provided in the insulating layer 882, the insulating layer 883, and the insulating layer 887, and a conductive layer 895 is provided so as to fit into these openings. Furthermore, openings reaching the conductive layer 842b are provided in the insulating layer 871b, the insulating layer 875, the insulating layer 885, the insulating layer 882, the insulating layer 883, and the insulating layer 887, and the conductive layer 897 is provided so as to fit into the openings.

[0336] A conductive layer 892 is provided over the conductive layer 891, the conductive layer 893, and the insulating layer 887. A conductive layer 896 is provided over the conductive layer 895 and the insulating layer 887. A conductive layer 898 is provided over the conductive layer 897 and the insulating layer 887.

[0337] As mentioned above, in Figure 18 In the illustrated example, the low-resistance region 314b and the conductive layer 842a are electrically connected via the conductive layer 328, the conductive layer 356, the conductive layer 891, the conductive layer 892, and the conductive layer 893. Furthermore, the conductive layer 860 and the conductive layer 896 are electrically connected via the conductive layer 895. Furthermore, the conductive layer 842b and the conductive layer 898 are electrically connected via the conductive layer 897.

[0338] Conductive layers 891 to 898 are used as plugs or wiring. Conductive layers 891, 893, 895, and 897 preferably include a first conductive layer provided along the side and bottom surfaces of the opening, and a second conductive layer provided further inside the opening than the first conductive layer and embedded in the opening.

[0339] As the first conductive layer, a conductive material that does not readily diffuse hydrogen and oxygen is preferably used. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide is preferably used. Furthermore, a conductive material that inhibits the permeation of impurities such as water and hydrogen can be used in a single layer or a stacked layer. By adopting such a structure, it is possible to prevent impurities such as water and hydrogen from entering the semiconductor layer 820 through the conductive layer 891, the conductive layer 893, the conductive layer 895, or the conductive layer 897.

[0340] It is preferable to use a highly conductive material as the second conductive layer because this can reduce the resistance of the conductive layers 891, 893, 895, and 897. For example, a conductive material mainly composed of tungsten, copper, or aluminum can be used as the second conductive layer.

[0341] A highly conductive material is preferably used for the conductive layers 892, 896, and 898. For example, a conductive material mainly composed of tungsten, copper, or aluminum can be used for the conductive layers 892, 896, and 898.

[0342] Figure 18 Show for example Figure 14C The transistor 43 shown is provided in layer 40_1 and Figure 14C The transistor 44 is shown as an example provided in the layer 40_2. The layer 40_1 is stacked with the insulating layer 160, the insulating layer 180, the insulating layer 130, and the insulating layer 185 in this order. Figure 18 In the illustrated layer 40_2 , a wiring 65 is provided on the insulating layer 280 , and an insulating layer 230 and an insulating layer 285 are sequentially stacked on the wiring 65 .

[0343] As described above, the wiring 61 is provided on the conductive layer 220 and the insulating layer 285 . Figure 18 2 shows an example in which an insulating layer 287 is provided over the insulating layer 285 and the wiring 61. Figure 18 In the illustrated example, the wiring 61 and the insulating layer 287 are not included in the layer 40_2, but may be included in the layer 40_2. The insulating layer 287 can be made of the same material as that used for the insulating layer 160, for example.

[0344] exist Figure 18 In the illustrated example, openings reaching conductive layer 898 are provided in insulating layers 160, 180, 130, 185, and 280, and conductive layer 899 is provided to fit within these openings. Wiring 65 is provided on conductive layer 899 and insulating layer 280.

[0345] As mentioned above, in Figure 18 In the example shown, the conductive layer 842b and the wiring 65 are electrically connected via the conductive layer 897, the conductive layer 898, and the conductive layer 899. Figure 18 1 shows an example in which the other of the source electrode and the drain electrode of the transistor 54 is electrically connected to the wiring 65. Figure 18 For example, the setting Figure 3C FIG. 5 shows an example of a structure of a transistor 54 in a switch circuit 52c. In this case, at least part of the conductive layer 328, the conductive layer 356, the conductive layer 891, the conductive layer 892, the conductive layer 893, and the conductive layer 842a can be used as a wiring 66.

[0346] Conductive layer 899 is used as a plug or wiring. Conductive layer 899 can have the same structure as conductive layers 891, 893, 895, and 897. Conductive layer 899 can include, for example, a first conductive layer provided along the side and bottom surfaces of the opening, and a second conductive layer located further inside the opening than the first conductive layer and embedded in the opening.

[0347] Figure 19 4 is a cross-sectional view illustrating a structural example of the layer 20 , the layer 30 , the layer 40_1 , and the layer 40_2 included in the semiconductor device 10 . Figure 19 Show Figure 18 The transistor 54 shown is an example of a vertical transistor. Specifically, Figure 19 An example is shown in which the transistor 54 has the same structure as the transistor 43 .

[0348] Figure 19The transistor 54 shown includes a conductive layer 463, a semiconductor layer 470, an insulating layer 430, a conductive layer 467, and a conductive layer 420. These layers correspond to the wiring 63, the semiconductor layer 170, the insulating layer 130, the wiring 67, and the conductive layer 120 included in the transistor 43, respectively.

[0349] exist Figure 19 In the layer 30 shown, an insulating layer 460, an insulating layer 480, an insulating layer 430, and an insulating layer 485 are stacked in this order. These insulating layers can be made of the same materials as those used for the insulating layer 160, the insulating layer 180, the insulating layer 130, and the insulating layer 185. Figure 19 In the layer 30 shown, an insulating layer 487 is provided on the insulating layer 485. The insulating layer 487 may be, for example, a layer of Figure 18 The structures of the insulating layer 882, the insulating layer 883 and the insulating layer 887 are shown.

[0350] exist Figure 19 In the illustrated example, openings reaching conductive layer 356 are provided in insulating layer 460, insulating layer 480, insulating layer 430, insulating layer 485, and insulating layer 487, and conductive layer 891 is provided so as to fit into these openings. Furthermore, openings reaching conductive layer 463 are provided in insulating layer 480, insulating layer 430, insulating layer 485, and insulating layer 487, and conductive layer 893 is provided so as to fit into these openings. Furthermore, openings reaching conductive layer 420 are provided in insulating layer 487, and conductive layer 895 is provided so as to fit into these openings. Furthermore, openings reaching conductive layer 467 are provided in insulating layer 430, insulating layer 485, and insulating layer 487, and conductive layer 897 is provided so as to fit into these openings.

[0351] A conductive layer 892 is provided over the conductive layer 891, the conductive layer 893, and the insulating layer 487. A conductive layer 896 is provided over the conductive layer 895 and the insulating layer 487. A conductive layer 898 is provided over the conductive layer 897 and the insulating layer 487.

[0352] As mentioned above, in Figure 19 In the example shown, the low resistance region 314b and the conductive layer 463 are electrically connected via the conductive layers 328, 356, 891, 892, and 893. Furthermore, the conductive layer 420 and the conductive layer 896 are electrically connected via the conductive layer 895.

[0353] Furthermore, the conductive layer 467 and the conductive layer 898 are electrically connected via the conductive layer 897. As described above, the conductive layer 898 is electrically connected to the wiring 65 via the conductive layer 899. Therefore, the conductive layer 467 and the wiring 65 are electrically connected via the conductive layers 897, 898, and 899.

[0354] Figure 20 It shows Figure 18 The illustrated cross-sectional view is an example of a semiconductor device 10 including a layer 40_3 between layers 40_1 and 40_2 . Figure 21 It shows Figure 19 The illustrated cross-sectional view shows an example of a semiconductor device 10 including a layer 40_3 . Figure 20 and Figure 21 Show Figure 15B The capacitor 45 is shown as an example provided in the layer 40_3. The layer 40_3 includes an insulating layer 380, an insulating layer 330, and an insulating layer 385 stacked in this order.

[0355] Figure 22 For example, it is shown Figure 18 The semiconductor device 10 shown is a cross-sectional view of an example including two layers 40_1 and two layers 40_2. Figure 22 In the semiconductor device 10 shown, layers 40_1 and 40_2 are sequentially stacked. <1> , layer 40_2 <1> , layer 40_1 <2> and layer 40_2 <2> . Note that in Figure 22 , the configuration in layer 40_1 is not shown. <1> The lower layer 30 and layer 20.

[0356] exist Figure 22 In layer 40_1 <1> and layer 40_1 <2> Among the components commonly provided in the <1> The symbols of the components in <1> " and the pair is set on layer 40_1 <2> The symbols of the components in <2> Similarly, for layer 40_2 <1> and layer 40_2 <2> The common components are also distinguished.

[0357] exist Figure 22 In the semiconductor device 10 shown, the insulating layer 230 <1> and insulating layer 285 <1> There is a reach wiring 65 <1> An opening is formed, and a conductive layer 901 is provided so as to fit within the opening. Conductive layer 901 serves as a plug or wiring. Conductive layer 901 can have the same structure as conductive layers 891, 893, 895, 897, and 899. Conductive layer 901 can include, for example, a first conductive layer provided along the side surfaces and bottom surface of the opening, and a second conductive layer provided further inward of the opening than the first conductive layer and so as to fit within the opening.

[0358] Conductive layer 901 and insulating layer 285 <1> A conductive layer 898 is provided on <2> Conductive layer 898 <2> Can be used with wiring 61 <1> The same material and the same process are used to form the wiring 61. <1> Can be set in layer 40_1 <2> . Insulation layer 285 <1> , conductive layer 898 <2> and wiring 61 <1> An insulating layer 160 is provided on <2> . Insulation layer 285 <2> and wiring 61 <2> An insulating layer 287 is provided thereon.

[0359] Wiring 65 <1> With wiring 65 <2> Through the conductive layer 901, the conductive layer 898 <2> and conductive layer 899 <2> In addition, the conductive layer 898 may not be provided in the semiconductor device 10. <2> and the conductive layer 901. In this case, by insulating layer 230 <1> , insulation layer 285 <1> , insulation layer 160 <2> , insulation layer 180 <2> , insulation layer 130 <2> , insulation layer 185 <2> and insulating layer 280 <2> Set up the reach wiring 65 <1> The conductive layer 899 is provided so as to be embedded in the opening. <2> , can make the wiring 65 <1> With wiring 65 <2> Electrical connection.

[0360] Alternatively, three or more layers 40_1 and three or more layers 40_2 may be provided. <2> and conductive layer 220 <2> With the insulating layer 287 and the wiring 61 <2> Between the stacking setting and layer 40_1 <2> The same structure layer and layer 40_2 <2> The layers of the same structure may include three or more layers 40_1 and three or more layers 40_2.

[0361] Figure 23 For example, it is shown Figure 20 The semiconductor device 10 shown is a cross-sectional view of an example including two layers 40_1, two layers 40_2, and two layers 40_3. Figure 23 In the semiconductor device 10 shown, layers 40_1 and 40_2 are sequentially stacked. <1> , layer 40_3 <1> , layer 40_2 <1> , layer 40_1 <2> , layer 40_3 <2> and layer 40_2 <2> . Note that in Figure 23 , the configuration in layer 40_1 is not shown. <1> The lower layer 30 and layer 20.

[0362] exist Figure 23 In, with Figure 22 Similarly, the layer 40_1 is distinguished <1> With layer 40_1 <2> Common components and layer 40_2 <1> With layer 40_2 <2> In addition, the same distinction is made between layers 40_3 <1> and layer 40_3 <2> The common components set in.

[0363] Alternatively, three or more layers 40_1, three or more layers 40_2, and three or more layers 40_3 may be provided. <2> and conductive layer 220 <2> With the insulating layer 287 and the wiring 61 <2> Between the stacking setting and layer 40_1 <2> The same structure layer as layer 40_3 <2> The same structure layer and layer 40_2 <2> The layers of the same structure may include three or more layers 40_1 , three or more layers 40_2 , and three or more layers 40_3 .

[0364] like Figure 22 and Figure 23 As shown, by stacking multiple layers 40, the number of memory cells 42 provided in the semiconductor device 10 can be increased without increasing the area of ​​the memory cell array 41 when viewed from a planar perspective. This allows for increased storage capacity without increasing the size of the semiconductor device 10. This allows for miniaturization and high integration of the semiconductor device 10.

[0365] <Materials Constituting Semiconductor Devices> Hereinafter, constituent materials that can be used for semiconductor devices will be described.

[0366] [Substrate] As a substrate, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate can be used. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Furthermore, as semiconductor substrates, for example, semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide can be used. Furthermore, semiconductor substrates having an insulating region within the above-mentioned semiconductor substrates, such as SOI (Silicon On Insulator) substrates, can also be used. As conductive substrates, graphite substrates, metal substrates, alloy substrates, and conductive resin substrates can be used. Alternatively, substrates containing metal nitrides and substrates containing metal oxides can be used. Furthermore, insulating substrates provided with a conductive layer or semiconductor layer, semiconductor substrates provided with a conductive layer or insulating layer, and conductive substrates provided with a semiconductor layer or insulating layer can also be used. Alternatively, substrates having elements provided on these substrates can also be used. Examples of the element provided over the substrate include a capacitor, a resistor, a switching element, a light-emitting element, and a memory element.

[0367] [Insulator] Examples of the insulator include oxides, nitrides, oxynitrides, oxynitrides, metal oxides, metal oxynitrides, and metal oxynitrides having insulating properties.

[0368] For example, when carrying out miniaturization and high integration of transistor, due to the thin film of gate insulating layer, problems such as leakage current sometimes occur. By using high-k material as the insulating layer used as gate insulating layer, it is possible to realize low voltage when transistor is working while maintaining physical thickness. In addition, the equivalent oxide thickness (EOT) of the insulating layer used as gate insulating layer can be reduced. On the other hand, by using the material with low relative dielectric constant for the insulating layer used as interlayer film, the electrostatic capacitance of the parasitic capacitance generated between wiring can be reduced. Therefore, it is preferred to select material according to the function of insulating layer. In addition, the material with low relative dielectric constant is also the material with large dielectric strength.

[0369] Examples of materials with a high relative dielectric constant (high-k) include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0370] As materials with low relative dielectric constants, for example, inorganic insulating materials such as silicon oxide, silicon oxynitride and silicon nitride oxide, resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate and acrylic resin can be cited. In addition, as inorganic insulating materials with low relative dielectric constants other than those mentioned above, for example, silicon oxide with fluorine added, silicon oxide with carbon added, and silicon oxide with carbon and nitrogen added can be cited. In addition, silicon oxide with pores can be cited. In addition, these silicon oxides can also contain nitrogen.

[0371] In addition, by surrounding a transistor using a metal oxide with an insulating layer that has the function of suppressing the transmission of impurities and oxygen, the electrical characteristics of the transistor can be stabilized. As an insulating layer that has the function of suppressing the transmission of impurities and oxygen, for example, a single layer or a stack of insulating layers containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used. Specifically, as an insulating layer that has the function of suppressing the transmission of impurities and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon oxynitride, and silicon nitride can be used.

[0372] Furthermore, an insulating layer in contact with a semiconductor, such as a gate insulating layer, or an insulating layer provided near a semiconductor layer, preferably has a region containing excess oxygen. For example, when an insulating layer having a region containing excess oxygen is in contact with a semiconductor layer, or when an insulating layer having a region containing excess oxygen is provided near a semiconductor layer, oxygen vacancies in the semiconductor layer can be reduced. Examples of insulating layers that are prone to forming regions containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide having vacancies.

[0373] In addition, examples of the insulating layer having oxygen barrier properties include oxides containing one or both of aluminum and hafnium, oxides containing hafnium and silicon (hafnium silicate), magnesium oxide or gallium oxide, silicon nitride, and silicon oxynitride. In addition, examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate).

[0374] Examples of the insulating layer having hydrogen barrier properties include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, and silicon oxynitride.

[0375] The insulating layer having oxygen barrier properties and the insulating layer having hydrogen barrier properties can be said to be insulating layers having barrier properties against one or both of oxygen and hydrogen.

[0376] Insulating layers capable of capturing or fixing hydrogen include oxides containing magnesium or oxides containing one or both of aluminum and hafnium. These oxides are more preferably amorphous. Oxides with amorphous structures sometimes have the property of trapping or fixing hydrogen via dangling bonds in their oxygen atoms. While these metal oxides preferably have an amorphous structure, they may also partially have crystalline regions.

[0377] Note that in this specification, etc., a blocking insulating film refers to an insulating film having a barrier property. In addition, the barrier property refers to the property that the corresponding substance is not easily diffused (also referred to as the property that the corresponding substance is not easily permeable, the property of low permeability of the corresponding substance, or the function of inhibiting the diffusion of the corresponding substance). In addition, the function of capturing or fixing (also referred to as impurity absorption) the corresponding substance can be replaced by the term barrier property. In addition, hydrogen recorded as the corresponding substance refers to, for example, hydrogen atoms, hydrogen molecules, water molecules, and OH - At least one of substances that bond with hydrogen, etc. Furthermore, unless otherwise specified, impurities described as corresponding substances refer to impurities in the channel formation region or the semiconductor layer, and include, for example, at least one of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. Furthermore, oxygen described as a corresponding substance refers to, for example, at least one of oxygen atoms and oxygen molecules. Specifically, oxygen barrier properties refer to the property of not easily diffusing at least one of oxygen atoms and oxygen molecules.

[0378] [Conductor] As the conductor, it is preferred to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium and lanthanum, an alloy with the above metal elements as a component, or an alloy combining the above metal elements, etc. As the alloy with the above metal elements as a component, it is also possible to use a nitride of the alloy or an oxide of the alloy. For example, it is preferred to use tantalum nitride, titanium nitride, tungsten, a nitride comprising titanium and aluminum, a nitride comprising tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide comprising strontium and ruthenium, or an oxide comprising lanthanum and nickel, etc. In addition, it is also possible to use a semiconductor with high conductivity represented by polycrystalline silicon containing impurity elements such as phosphorus or a silicide such as nickel silicide.

[0379] In addition, conductive materials containing nitrogen, such as tantalum nitride, titanium nitride, molybdenum nitride, tungsten nitride, ruthenium nitride, tantalum and aluminum nitride, or titanium and aluminum nitride, conductive materials containing oxygen, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel, and materials containing metal elements such as titanium, tantalum, or ruthenium are conductive materials that are not easily oxidized, have the function of suppressing oxygen diffusion, or maintain conductivity even when absorbing oxygen, and are therefore preferred. Note that as conductive materials containing oxygen, indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium tin oxide with silicon added, indium zinc oxide, and indium zinc oxide containing tungsten oxide can be cited. In this specification, etc., a conductive film deposited using a conductive material containing oxygen is sometimes referred to as an oxide conductive film.

[0380] Furthermore, conductive materials mainly composed of tungsten, copper, or aluminum are preferred because of their high conductivity.

[0381] Furthermore, a plurality of conductive layers formed from the above-mentioned materials may be stacked. For example, a laminated structure may be formed by combining a material containing the above-mentioned metal element with a conductive material containing oxygen. Alternatively, a laminated structure may be formed by combining a material containing the above-mentioned metal element with a conductive material containing nitrogen. Alternatively, a laminated structure may be formed by combining a material containing the above-mentioned metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0382] Furthermore, when a metal oxide is used in the channel formation region of a transistor, the conductive layer serving as the gate electrode preferably has a stacked structure comprising a material containing the aforementioned metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen is preferably positioned on the channel formation region side. Positioning the conductive material containing oxygen on the channel formation region side facilitates the supply of oxygen released from the conductive material to the channel formation region.

[0383] In particular, as a conductive layer used as a gate electrode, it is preferable to use a conductive material containing a metal element contained in the metal oxide forming the channel and oxygen. In addition, a conductive material containing the above-mentioned metal elements and nitrogen can also be used. For example, a conductive material containing nitrogen such as titanium nitride or tantalum nitride can also be used. In addition, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide added with silicon can also be used. In addition, indium gallium zinc oxide containing nitrogen can also be used. By using the above-mentioned materials, hydrogen contained in the metal oxide forming the channel can sometimes be captured. Alternatively, hydrogen mixed from an external insulating layer can sometimes be captured.

[0384] [Metal oxides] Metal oxides sometimes have lattice defects. Lattice defects refer to point defects such as atomic vacancies and foreign atoms, line defects such as dislocations, surface defects such as grain boundaries, and volume defects such as voids. Lattice defects are also primarily caused by differences in the ratio of the number of atoms of the constituent elements (excess or deficiency of constituent atoms) and impurities.

[0385] When metal oxides are used in the semiconductor layers of transistors, lattice defects in the metal oxides can lead to carrier generation and trapping. Therefore, using metal oxides with many lattice defects in the semiconductor layers of transistors can lead to unstable electrical characteristics of the transistors. Therefore, metal oxides used in the semiconductor layers of transistors preferably have fewer lattice defects.

[0386] In a transistor using a metal oxide, in particular, if oxygen vacancies (V O ) and impurities, the electrical characteristics are easily changed, sometimes reducing reliability. In addition, hydrogen near the oxygen vacancy forms a defect where hydrogen enters the oxygen vacancy (hereinafter sometimes referred to as V O H) and may generate electrons that become carriers. Therefore, when the channel formation region in the metal oxide contains oxygen vacancies, the transistor tends to have a normally-on characteristic. Therefore, in the channel formation region of the metal oxide, it is preferred to minimize oxygen vacancies and impurities. In other words, it is preferred that the carrier concentration of the channel formation region of the metal oxide is reduced and the metal oxide is i-type (intrinsic) or substantially i-type.

[0387] The type of lattice defects that are likely to exist in a metal oxide and the amount of the lattice defects that exist vary depending on the structure of the metal oxide, the method of depositing the metal oxide, and the like.

[0388] The structures of metal oxides are classified into single crystal structures and other structures (non-single crystal structures). Examples of non-single crystal structures include CAAC structures, polycrystalline structures, NC structures, amorphous-like (A-like) structures, and amorphous structures. The A-like structure has a structure between the NC structure and the amorphous structure. Note that the classification of crystal structures will be described later.

[0389] In addition, metal oxides with an a-like structure and metal oxides with an amorphous structure contain voids or low-density regions. In other words, the crystallinity of metal oxides with an a-like structure and metal oxides with an amorphous structure is lower than that of metal oxides with an nc structure and metal oxides with a CAAC structure. In addition, the hydrogen concentration in metal oxides with an a-like structure is higher than that of metal oxides with an nc structure and metal oxides with a CAAC structure. Therefore, lattice defects are easily generated in metal oxides with an a-like structure and metal oxides with an amorphous structure.

[0390] Therefore, it is preferable to use a highly crystalline metal oxide for the semiconductor layer of a transistor. For example, a metal oxide having a CAAC structure or a single-crystalline metal oxide is preferably used. By using such a metal oxide in a transistor, a transistor with excellent electrical characteristics can be realized. In addition, a transistor with high reliability can be realized.

[0391] In addition, the channel formation region of the transistor preferably uses a metal oxide that increases the on-state current of the transistor. In order to increase the on-state current of the transistor, it is sufficient to improve the mobility of the metal oxide used for the transistor. In order to improve the mobility of the metal oxide, it is necessary to improve the transmission of carriers (electrons in the case of n-channel transistors) or reduce the scattering factors that affect the transmission of carriers. In addition, carriers flow from the source to the drain through the channel formation region. Therefore, by providing a channel formation region in which carriers easily flow in the channel length direction, the on-state current of the transistor can be increased.

[0392] Here, the metal oxide having a channel formation region preferably uses a metal oxide with high crystallinity. Furthermore, the crystal preferably has a crystal structure having multiple layers (e.g., a first layer, a second layer, and a third layer). In other words, the crystal has a layered crystal structure (also referred to as a layered crystal or a layered structure). At this time, the c-axis direction of the crystal is the direction in which multiple layers are stacked. Metal oxides having this crystal include, for example, single crystal oxide semiconductors and CAAC-OS.

[0393] Furthermore, the c-axis of the crystals is preferably oriented in the normal direction to the metal oxide's formed surface or film surface. Thus, the multiple layers are arranged parallel or substantially parallel to the metal oxide's formed surface or film surface. In other words, the multiple layers extend in the channel length direction.

[0394] For example, the three-layered crystal structure has the following structure: The first layer has an atomic coordination structure in which the metal contained in the first layer is present in an oxygen octahedron at the center. Furthermore, the second layer has an atomic coordination structure in which the metal contained in the second layer is present in an oxygen trigonal bipyramid or tetrahedron at the center. Furthermore, the third layer has an atomic coordination structure in which the metal contained in the third layer is present in an oxygen trigonal bipyramid or tetrahedron at the center.

[0395] Examples of the crystal structure of the above-mentioned crystal include a YbFe2O4 type structure, a Yb2Fe3O7 type structure, and modified structures thereof.

[0396] Furthermore, it is preferred that the first to third layers all consist of a single metal element or multiple metal elements having the same valence, and oxygen. Note that it is preferred that the valence of the one or more metal elements constituting the first layer be the same as the valence of the one or more metal elements constituting the second layer. Alternatively, the first and second layers may contain the same metal element. Furthermore, it is preferred that the valence of the one or more metal elements constituting the first layer be different from the valence of the one or more metal elements constituting the third layer.

[0397] By adopting the above structure, the crystallinity of the metal oxide can be improved, thereby increasing the mobility of the metal oxide. Therefore, by using the metal oxide in the channel formation region of the transistor, the on-state current of the transistor can be increased, thereby improving the electrical characteristics of the transistor.

[0398] As a metal oxide of one embodiment of the present invention, for example, indium oxide, gallium oxide and zinc oxide can be mentioned. The metal oxide of one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn). In addition, the metal oxide preferably contains two or three selected from indium, element M and zinc. Note that element M is a metal element or semi-metal element with a high bonding energy with oxygen, for example, a metal element or semi-metal element with a higher bonding energy with oxygen than indium. As element M, specifically, aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium and antimony can be mentioned. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin and yttrium, and further preferably gallium. When the element M included in the metal oxide is gallium, the metal oxide of one embodiment of the present invention preferably contains one or more selected from indium, gallium and zinc. Note that in this specification and the like, metal elements and semi-metal elements may be collectively referred to as “metal elements”, and “metal elements” described in this specification and the like may include semi-metal elements.

[0399] As a metal oxide of one embodiment of the present invention, for example, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide, also referred to as AZO), indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO), etc. can be used. Alternatively, examples include indium tin oxide, gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide) containing silicon. Alternatively, the above oxides having an amorphous structure may be used. For example, indium oxide having an amorphous structure or indium tin oxide having an amorphous structure may be used.

[0400] By increasing the atomic number ratio of indium relative to the total atomic number of all metal elements in the metal oxide, the field-effect mobility of the transistor can be increased.

[0401] Note that the metal oxide may also contain one or more metal elements with a large period number instead of indium. Alternatively, the metal oxide may also contain one or more metal elements with a large period number in addition to indium. There is a tendency that the greater the orbital overlap of the metal elements, the greater the carrier conduction in the metal oxide. Therefore, by including a metal element with a large period number, the field effect mobility of the transistor can sometimes be improved. As metal elements with a large period number, metal elements belonging to the 5th period and metal elements belonging to the 6th period can be cited. As the metal element, specifically, yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium and europium can be cited. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium and europium are called light rare earth elements.

[0402] Furthermore, the metal oxide may also contain one or more non-metallic elements. The inclusion of non-metallic elements in the metal oxide can sometimes improve the field-effect mobility of the transistor. Examples of non-metallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0403] Furthermore, by increasing the atomic ratio of zinc relative to the total atomic number of all metal elements in the metal oxide, the metal oxide can be made highly crystalline, thereby suppressing the diffusion of impurities in the metal oxide. Consequently, variations in the electrical characteristics of the transistor can be suppressed, improving reliability.

[0404] Furthermore, by increasing the atomic ratio of the element M relative to the total atomic number of all metal elements in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Consequently, carrier generation due to oxygen vacancies is suppressed, thereby enabling the realization of a transistor with low off-state current. Furthermore, fluctuations in the electrical characteristics of the transistor are suppressed, thereby improving reliability.

[0405] Furthermore, by increasing the atomic number ratio of In relative to the total atomic number of all metal elements in the metal oxide, the transistor can obtain a large on-state current and high-frequency characteristics.

[0406] In this embodiment, In—Ga—Zn oxide is sometimes used as an example of a metal oxide for description.

[0407] In order to form the metal oxide having the layered crystal structure, it is preferable to deposit atoms layer by layer. In the metal oxide deposition method according to one embodiment of the present invention, since the ALD method is used, the metal oxide having the layered crystal structure can be easily formed.

[0408] Examples of the ALD method include a thermal ALD method in which a precursor and a reactant react using only thermal energy and a plasma ALD method (PEALD: Plasma Enhanced ALD) method using a reactant excited by plasma.

[0409] The ALD method can deposit atoms layer by layer, which has the following effects: it can deposit very thin films; it can deposit structures with high aspect ratios; it can deposit with few defects such as pinholes; it can deposit with high coverage; it can deposit at low temperatures, etc. In addition, in the PEALD method, deposition can be performed at lower temperatures by utilizing plasma, so it is sometimes preferred. In addition, the precursors used in the ALD method sometimes contain elements such as carbon or chlorine. Therefore, the film set by the ALD method sometimes contains more elements such as carbon or chlorine than the film set by other deposition methods. In addition, the quantification of these elements can be performed using XPS or SIMS. Note that the deposition method of the metal oxide as one embodiment of the present invention utilizes the ALD method, but due to the use of one or both of the conditions of high substrate temperature during deposition and impurity removal treatment, the amount of carbon and chlorine contained in the film is sometimes less than when the ALD method is used without the above conditions.

[0410] The ALD method is, for example, different from a deposition method in which particles released from a target are deposited, and is a film-forming method in which a film is formed due to a reaction on the surface of the object being processed. Therefore, the ALD method is a deposition method that is not easily affected by the shape of the object being processed and has good step coverage. In particular, the ALD method has good step coverage and thickness uniformity, so for example, the ALD method is suitable for covering the surface of an opening with a high aspect ratio. However, the deposition rate of the ALD method is relatively slow, so it is sometimes preferably used in combination with other deposition methods such as a sputtering method or a CVD method having a fast deposition rate. For example, a method in which a first metal oxide is deposited using a sputtering method and a second metal oxide is deposited on the first metal oxide using the ALD method can be cited. For example, when the first metal oxide has a crystalline portion, the second metal oxide sometimes grows crystals using the crystalline portion as a core.

[0411] The ALD method can control the composition of the resulting film according to the amount of source gas introduced. For example, when the ALD method is used, a film of any composition can be deposited by adjusting at least one of the amount of source gas introduced, the number of introductions (also called the number of pulses), and the time required for one pulse (also called the pulse time). In addition, for example, when the ALD method is used, a film whose composition continuously changes can be deposited by changing the source gas while deposition is performed. When deposition is performed while changing the source gas, since the time required for conveying or adjusting the pressure is not required, the deposition time can be shortened compared to the case where deposition is performed using multiple deposition chambers. Therefore, the productivity of semiconductor devices can sometimes be improved.

[0412] [[Transistor including an oxide semiconductor]] Next, the case where a metal oxide (oxide semiconductor) is used for a transistor will be described.

[0413] By using a metal oxide (oxide semiconductor) of one embodiment of the present invention in a transistor, a transistor with high field-effect mobility can be realized. In addition, a transistor with high reliability can be realized. In addition, miniaturized or highly integrated transistors can be realized. For example, a transistor with a channel length of 2 nm or more and 30 nm or less can be manufactured.

[0414] It is preferable to use an oxide semiconductor with a low carrier concentration for the channel formation region of the transistor. For example, the carrier concentration of the channel formation region of the oxide semiconductor can be 1×10 18 cm -3 Below, preferably 1×10 17 cm -3 Below, more preferably 1×10 15 cm -3 Below, more preferably 1×10 13 cm -3 Below, more preferably 1×10 11 cm -3 Below, more preferably less than 1×10 10 cm -3 , and is 1×10 -9 cm -3 Note that when the carrier concentration of an oxide semiconductor is to be reduced, the impurity concentration in the oxide semiconductor can be reduced to reduce the defect state density. In this specification, etc., a state with a low impurity concentration and a low defect state density is referred to as high-purity intrinsic or substantially high-purity intrinsic. In addition, an oxide semiconductor with a low carrier concentration is sometimes referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.

[0415] Since a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film has a low defect state density, the trap state density may also be low.

[0416] Furthermore, charges trapped in trap states of an oxide semiconductor take a long time to disappear, and may behave like fixed charges. Consequently, the electrical characteristics of a transistor whose channel formation region is formed in an oxide semiconductor with a high trap state density may be unstable.

[0417] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In addition, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the nearby film. Examples of impurities include hydrogen, carbon, and nitrogen. Note that impurities in an oxide semiconductor refer to, for example, elements other than the main components of the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic% can be considered an impurity.

[0418] In addition, the band gap of the oxide semiconductor is preferably larger than the band gap of silicon (typically 1.1 eV), preferably 2 eV or more, more preferably 2.5 eV or more, and even more preferably 3.0 eV or more. By using an oxide semiconductor with a band gap larger than that of silicon, the off-state current (also called Ioff) of the transistor can be reduced.

[0419] In addition, in Si transistors, the short channel effect (also known as the Short Channel Effect: SCE) appears as the miniaturization of transistors progresses. Therefore, the miniaturization of Si transistors is very difficult. One of the reasons for the short channel effect is that silicon has a small band gap. On the other hand, OS transistors use oxide semiconductors, which are semiconductor materials with a large band gap, thereby suppressing the short channel effect. In other words, OS transistors are transistors with no short channel effect or very little short channel effect.

[0420] The short-channel effect refers to the degradation of electrical properties that occurs with transistor miniaturization (reduction in channel length). Specific examples of the short-channel effect include a decrease in threshold voltage, an increase in the subthreshold swing value (sometimes referred to as the S value), and an increase in leakage current. The S value refers to the change in gate voltage in the subthreshold region that causes a single-digit change in drain current at a fixed drain voltage.

[0421] In addition, characteristic length is widely used as an indicator of resistance to short channel effects. Characteristic length refers to the curvature of the potential in the channel formation region. The smaller the characteristic length, the more rapidly the potential rises, so it can be said that the resistance to short channel effects is high.

[0422] OS transistors are accumulation-type transistors, while Si transistors are inversion-type transistors. Therefore, compared to Si transistors, the characteristic lengths between the source region and the channel formation region, and the characteristic lengths between the drain region and the channel formation region, of OS transistors are smaller. Therefore, compared to Si transistors, OS transistors have a higher resistance to short channel effects. In other words, when manufacturing transistors with short channel lengths, OS transistors are more preferable than Si transistors.

[0423] When the carrier concentration of the oxide semiconductor is reduced until the channel formation region becomes i-type or substantially i-type, in a short channel transistor, the lower end of the conduction band of the channel formation region is lowered due to the conduction-band-lowering (CBL) effect, thereby reducing the energy difference between the lower end of the conduction band of the source region or the drain region and the channel formation region to more than 0.1eV and less than 0.2eV. Therefore, the OS transistor can also be regarded as a transistor in which the channel formation region becomes n-type. - type region and the source and drain regions become n + n in the type region + / n - / n + Accumulation-type junction-less transistor structure or n + / n - / n + Accumulation-type non-junction transistor structure.

[0424] Because the OS transistor has the above-mentioned structure, it can have good electrical characteristics even if the semiconductor device is miniaturized or highly integrated. For example, even if the channel length or gate length of the OS transistor is less than 20nm, less than 15nm, less than 10nm, less than 7nm or less than 6nm and more than 1nm, more than 3nm or more than 5nm, good electrical characteristics can be obtained. On the other hand, a short channel effect occurs in Si transistors, so it is sometimes difficult to set the gate length to less than 20nm or less than 15nm. Therefore, compared with Si transistors, OS transistors can be suitable for transistors with short channel lengths. Note that the gate length refers to the length of the gate electrode in the direction in which carriers migrate in the channel formation region when the transistor is operating.

[0425] Furthermore, miniaturizing the OS transistor can improve its high-frequency characteristics. Specifically, the transistor's cutoff frequency can be increased. When the gate length of the OS transistor is within the above range, the transistor's cutoff frequency can be, for example, above 50 GHz, preferably above 100 GHz, and more preferably above 150 GHz at room temperature.

[0426] As described above, OS transistors have advantages over Si transistors, such as a small off-state current and the ability to manufacture transistors with a short channel length.

[0427] [[Impurities in metal oxides]] Here, the influence of various impurities in metal oxides (oxide semiconductors) will be described.

[0428] When the oxide semiconductor contains silicon or carbon, which is one of the elements in Group 14, defect states are formed in the oxide semiconductor. Therefore, the carbon concentration in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×10 20 atoms / cm 3 Below, preferably 5×10 19 atoms / cm 3 Below, more preferably 3×10 19 atoms / cm 3 Below, more preferably 1×10 19 atoms / cm 3 Below, more preferably 3×10 18 atoms / cm 3 Below, more preferably 1×10 18 atoms / cm 3 The silicon concentration in the channel formation region of the oxide semiconductor measured by SIMS was set to 1×10 20 atoms / cm 3 Below, preferably 5×10 19 atoms / cm 3 Below, more preferably 3×10 19 atoms / cm 3 Below, more preferably 1×10 19 atoms / cm 3 Below, more preferably 3×10 18 atoms / cm 3 Below, more preferably 1×10 18 atoms / cm 3 the following.

[0429] In addition, when the oxide semiconductor contains nitrogen, electrons as carriers are generated, the carrier concentration is increased, and it is easy to be converted to n-type. As a result, the transistor using the oxide semiconductor containing nitrogen as a semiconductor tends to have a normally-on characteristic. Alternatively, when the oxide semiconductor contains nitrogen, a trap state is sometimes formed. As a result, the electrical characteristics of the transistor are sometimes unstable. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×10 20 atoms / cm3 Below, preferably 5×10 19 atoms / cm 3 Below, more preferably 1×10 19 atoms / cm 3 Below, more preferably 5×10 18 atoms / cm 3 Below, more preferably 1×10 18 atoms / cm 3 Below, more preferably 5×10 17 atoms / cm 3 the following.

[0430] In addition, hydrogen contained in the oxide semiconductor reacts with oxygen bonded to metal atoms to generate water, and thus oxygen vacancies are sometimes formed. When hydrogen enters the oxygen vacancy, electrons as carriers are sometimes generated. In addition, sometimes electrons as carriers are generated because part of the hydrogen is bonded to oxygen bonded to metal atoms. Therefore, transistors using oxide semiconductors containing hydrogen tend to have normally-on characteristics. Therefore, it is preferable to reduce the hydrogen in the channel formation region of the oxide semiconductor as much as possible. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor measured by SIMS is set to less than 1×10 20 atoms / cm 3 , preferably less than 5×10 19 atoms / cm 3 , more preferably less than 1×10 19 atoms / cm 3 , more preferably less than 5×10 18 atoms / cm 3 , more preferably less than 1×10 18 atoms / cm 3 .

[0431] In addition, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect states may sometimes be formed to generate carriers. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have a normally-on characteristic. Therefore, the concentration of the alkali metal or alkaline earth metal in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×10 18 atoms / cm 3 Below, preferably 2×10 16 atoms / cm 3 the following.

[0432] By using an oxide semiconductor in which impurities are sufficiently reduced for a channel formation region of a transistor, the transistor can have stable electrical characteristics.

[0433] [Other semiconductor materials] The semiconductor layer 270 may be alternatively referred to as a semiconductor layer having a channel formation region of the transistor. Semiconductor materials that can be used for the semiconductor layer are not limited to the aforementioned metal oxides. Semiconductor materials having a band gap (not being zero-band gap semiconductors) may also be used as the semiconductor layer. For example, single element semiconductors, compound semiconductors, or layered materials (also referred to as atomic layer materials, two-dimensional materials, etc.) are preferably used as the semiconductor material.

[0434] Here, in this specification, etc., layered materials are a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked together through bonds weaker than covalent and ionic bonds, such as van der Waals forces. Layered materials have high electrical conductivity per layer, that is, high two-dimensional conductivity. By using a material that functions as a semiconductor and has high two-dimensional conductivity in the channel formation region, a transistor with a large on-state current can be provided.

[0435] Examples of single-element semiconductors that can be used as semiconductor materials include silicon and germanium. Examples of silicon that can be used in semiconductor layers include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low-temperature polysilicon (LTPS).

[0436] Examples of compound semiconductors that can be used as semiconductor materials include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide. Boron nitride that can be used in the semiconductor layer preferably has an amorphous structure. Boron arsenide that can be used in the semiconductor layer preferably includes crystals having a cubic structure.

[0437] Examples of layered materials include graphene, silicene, boron carbonitride, and chalcogenides. In boron carbonitride, a layered material, carbon, nitrogen, and boron atoms are arranged in a hexagonal lattice structure on a plane. Chalcogenides are compounds containing chalcogen elements. Chalcogen elements are a general term for elements belonging to Group 16, which includes oxygen, sulfur, selenium, tellurium, polonium, and lead. Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.

[0438] As the semiconductor layer, for example, a transition metal chalcogenide used as a semiconductor is preferably used. Specifically, transition metal chalcogenides that can be used as semiconductor layers include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2). By using the above-mentioned transition metal chalcogenides for the semiconductor layer, a semiconductor device with a large on-state current can be provided.

[0439] The configuration, structure, method, and the like described in this embodiment can be used in combination with the configuration, structure, method, and the like described in other embodiments as appropriate.

[0440] (Implementation Method 2) In this embodiment, a configuration example of a semiconductor device different from the configuration described in Embodiment 1 is described with reference to the drawings. Specifically, a configuration example of a memory device, which is one embodiment of a semiconductor device, is described with reference to the drawings.

[0441] Figure 24A and Figure 24B 9 is a perspective view showing an example of the structure of a semiconductor device 970A. The semiconductor device 970A includes a layer 960 and a layer 930 on the layer 960.

[0442] The CPU 21A and the driving circuit 22 are provided in the layer 960. The CPU 21A includes Figure 1 The control circuit 23, the operation circuit 25, the memory controller 27 and the register circuit 50 shown in the figure are not provided in the CPU 21A. Figure 1 The cache memory 26 shown in FIG. 960 corresponds to the layers 20 and 30 shown in the first embodiment.

[0443] Layer 930 includes memory cell array 41L1, memory cell array 41L2, and memory cell array 41L3 as memory cell arrays 41. Memory cells 42 are arranged in a matrix in each of memory cell array 41L1, memory cell array 41L2, and memory cell array 41L3. Layer 930 corresponds to layer 40 described in Embodiment 1. Alternatively, at least one of memory cell array 41L1, memory cell array 41L2, and memory cell array 41L3 may be divided into a plurality of memory cell arrays.

[0444] The CPU 21A and each memory cell array 41 have overlapping areas. Figure 24B Layer 960 and layer 930 are shown separately in FIG.

[0445] By overlapping the layer 930 including the memory cell array 41 and the CPU 21A, the distance between the two can be shortened. This can increase the communication speed between the two. In addition, the shorter connection distance can reduce power consumption.

[0446] Layer 930, which includes memory cell array 41, and layer 960, which includes CPU 21A, can be stacked using the following methods: directly stacking layer 930 on layer 960 (also known as monolithic stacking); or forming layer 960 and layer 930 on separate substrates, laminating the two substrates together, and electrically connecting them using a through-hole or conductive film bonding technique (e.g., Cu-Cu bonding). The former method eliminates the need to consider misalignment during lamination, thus reducing both chip size and manufacturing costs.

[0447] Here, the memory cell array 41L1, the memory cell array 41L2, and the memory cell array 41L3 can all be used as cache memory. In this case, for example, the memory cell array 41L1, the memory cell array 41L2, and the memory cell array 41L3 can be used as an L1 cache (also called a first-level cache), an L2 cache (also called a second-level cache), and an L3 cache (also called a third-level cache), respectively. Of the three memory cell arrays 41, the memory cell array 41L3 has the largest capacity and the lowest access frequency. Furthermore, the memory array 41L1 has the smallest capacity and the highest access frequency.

[0448] Alternatively, you can Figure 1 The cache memory 26 shown is provided in the CPU 21A. In this case, the cache memory 26 can be used as an L1 cache, for example. In this case, each memory cell array 41 provided in the layer 930 can be used as a lower-level cache or main memory. The main memory is a memory with a larger capacity and a lower access frequency than the cache memory.

[0449] Note that although the case where three memory cell arrays 41 are used as cache memory is shown here, the number may be one, two, or four or more.

[0450] Whether the memory cell array 41 is used as a cache or a main memory is determined by the memory controller 27. The memory controller 27 can use a part of the plurality of memory cells 42 included in the semiconductor device 970A as a RAM in accordance with a signal supplied from the CPU 21A.

[0451] In the semiconductor device 970A, some of the plurality of memory cells 42 can be used as cache memory and others as main memory. In other words, the semiconductor device 970A can function both as a cache memory and as a main memory. The semiconductor device 970A according to one embodiment of the present invention can be used as a general-purpose memory, for example.

[0452] Alternatively, a plurality of memory cell arrays 41 may be stacked. Figure 25 It is a perspective view of the semiconductor device 970B.

[0453] The semiconductor device 970B includes a layer 930L1 on the layer 960, a layer 930L2 on the layer 930L1, and a layer 930L3 on the layer 930L2. The layer 930L1 includes a memory cell array 41L1_1 and a memory cell array 41L1_2 as the memory cell array 41L1. The layer 930L2 includes a memory cell array 41L2_1 and a memory cell array 41L2_2 as the memory cell array 41L2. The layer 930L3 includes a memory cell array 41L3_1 and a memory cell array 41L3_2 as the memory cell array 41L3. That is, Figure 25 The example in which the memory cell array 41L1, the memory cell array 41L2, and the memory cell array 41L3 are each divided into two is shown. Alternatively, at least one of the memory cell array 41L1, the memory cell array 41L2, and the memory cell array 41L3 may be divided into three or more.

[0454] By sequentially stacking layer 930L1, layer 930L2, and layer 930L3 on layer 960, memory cell array 41L1, which is physically closest to CPU 21A, can be used for a higher-level cache. Furthermore, memory cell array 41L3, which is farthest away, can be used for a lower-level cache or main memory. By stacking memory cell array 41L1, memory cell array 41L2, and memory cell array 41L3 in this manner, the capacity of each memory cell array 41 can be increased. Consequently, semiconductor device 970B can have high processing capabilities.

[0455] The configuration, structure, method, and the like described in this embodiment can be used in combination with the configuration, structure, method, and the like described in other embodiments as appropriate.

[0456] (Implementation 3) This embodiment mode describes electronic components, electronic devices, mainframe computers, space equipment, and data centers (also referred to as DCs) that can use the semiconductor devices described in the above embodiment modes. Electronic components, electronic devices, mainframe computers, space equipment, and data centers that use a semiconductor device according to one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[0457] [Electronic components] Figure 26A A perspective view of a substrate (circuit board 704 ) on which an electronic component 700 is mounted is shown. Figure 26A The electronic component 700 shown includes a semiconductor device 710 within a mold 711. Figure 26A 700 is partially omitted to illustrate its interior. Electronic component 700 includes lands 712 on the outside of mold 711. Lands 712 are electrically connected to electrode pads 713, which are electrically connected to semiconductor device 710 via wires 714. Electronic component 700 is mounted on, for example, a printed circuit board 702. By combining multiple electronic components and electrically connecting them on printed circuit board 702, a circuit board 704 is completed.

[0458] In addition, the semiconductor device 710 includes a driver circuit layer 715 and a memory layer 716. The memory layer 716 has a structure in which a plurality of memory cell arrays are stacked. The structure in which the driver circuit layer 715 and the memory layer 716 are stacked can adopt a monolithic stacked structure. In a monolithic stacked structure, it is possible to connect the layers without using through-electrode technologies such as TSV (Through Silicon Via) or bonding technologies such as Cu-Cu direct bonding. When having a monolithic stacked structure of the driver circuit layer 715 and the memory layer 716, for example, a so-called on-chip memory structure can be realized in which a memory is directly formed on a processor. By adopting an on-chip memory structure, high-speed operation of the interface between the processor and the memory can be achieved.

[0459] Furthermore, the use of an on-chip memory structure allows for smaller interconnects, for example, compared to technologies using through-hole electrodes such as TSVs, thereby increasing the number of pins. This increase in pins allows for parallel operation, thereby increasing the memory bandwidth.

[0460] In addition, it is preferred that multiple memory cell arrays in the memory layer 716 are formed using OS transistors and the multiple memory cell arrays are stacked in a monolithic manner. When multiple memory cell arrays are stacked in a monolithic manner, either or both of the bandwidth of the memory and the access delay of the memory can be improved. Bandwidth refers to the amount of data transmitted per unit time, and access delay refers to the time between access and the start of data exchange. When Si transistors are used in the memory layer 716, it is more difficult to implement a monolithic stacked structure compared to OS transistors. Therefore, in a monolithic stacked structure, OS transistors are superior to Si transistors.

[0461] In addition, the semiconductor device 710 may be referred to as a bare die. In this specification, etc., a bare die refers to a chip obtained by forming a circuit pattern on a disk-shaped substrate (also called a wafer) in the manufacturing process of a semiconductor chip, for example, and cutting it into rectangular pieces. Examples of semiconductor materials that can be used for bare chips include silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). For example, a bare die obtained from a silicon substrate (also called a silicon wafer) is sometimes referred to as a silicon chip.

[0462] then, Figure 26B A perspective view of an electronic component 730 is shown. Electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi Chip Module). In electronic component 730, an interposer 731 is provided on a package substrate 732 (printed circuit board). A semiconductor device 735 and a plurality of semiconductor devices 710 are provided on interposer 731.

[0463] Electronic component 730 illustrates an example of using semiconductor device 710 as a high bandwidth memory (HBM). Alternatively, semiconductor device 735 can be used in integrated circuits such as a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), or an FPGA (Field Programmable Gate Array).

[0464] The package substrate 732 may be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate, and the interposer 731 may be, for example, a silicon interposer or a resin interposer.

[0465] The interposer 731 has a plurality of wirings and has the function of electrically connecting a plurality of integrated circuits with different terminal spacings. The plurality of wirings are composed of a single layer or multiple layers. In addition, the interposer 731 has the function of electrically connecting the integrated circuit provided on the interposer 731 to the electrodes provided on the package substrate 732. Therefore, the interposer is sometimes also referred to as a "rewiring substrate" or "intermediate substrate". In addition, sometimes a through electrode is provided in the interposer 731, and the integrated circuit is electrically connected to the package substrate 732 through the through electrode. In addition, when a silicon interposer is used, TSV can also be used as a through electrode.

[0466] To achieve a wide memory bandwidth in HBM, numerous wiring connections are required. Therefore, the interposer on which HBM is mounted must be able to form fine wiring at a high density. Therefore, a silicon interposer is preferred for HBM mounting.

[0467] Furthermore, SiPs and MCMs using silicon interposers are less susceptible to reliability degradation caused by differences in thermal expansion coefficients between the integrated circuits and the interposer. Furthermore, due to the high surface flatness of the silicon interposer, poor connections between the integrated circuits mounted on the silicon interposer and the silicon interposer are less likely to occur. Silicon interposers are particularly well-suited for 2.5D packaging (2.5D assembly), in which multiple integrated circuits are arranged horizontally on the interposer.

[0468] On the other hand, when using silicon interposers and TSVs to electrically connect multiple integrated circuits with different terminal pitches, space is required, such as the width of the terminal pitch. Therefore, when reducing the size of the electronic component 730, the width of the terminal pitch becomes a problem, and it is sometimes difficult to provide the large amount of wiring required to achieve a wider memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferred. Alternatively, a composite structure combining a memory cell array stacked using TSVs and a memory cell array stacked monolithically can be used.

[0469] Alternatively, a heat sink (heat dissipation plate) may be provided overlapping the electronic component 730. When a heat sink is provided, it is preferable to make the heights of the integrated circuits provided on the interposer 731 uniform. For example, in the electronic component 730 shown in this embodiment, it is preferable to make the heights of the semiconductor device 710 and the semiconductor device 735 uniform.

[0470] In order to mount the electronic component 730 on another substrate, an electrode 733 may be provided on the bottom of the package substrate 732 . Figure 26B The example of electrodes 733 formed using solder balls is shown. By arranging solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, electrodes 733 can be formed using conductive pins. Arranging conductive pins in a matrix on the bottom of the package substrate 732 enables PGA (Pin Grid Array) mounting.

[0471] The electronic component 730 can be mounted on another substrate using various mounting methods, not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded Package), and QFN (Quad Flat Non-leaded Package).

[0472] [Electronic equipment] then, Figure 27A A perspective view of electronic device 6500 is shown. Figure 27A The electronic device 6500 shown is a portable information terminal that can be used as a smartphone. The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and a control device 6509. The control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a storage device. The semiconductor device of one embodiment of the present invention can be applied to, for example, the control device 6509. This allows for miniaturization of the electronic device 6500.

[0473] Figure 27B The electronic device 6600 shown is an information terminal that can be used as a notebook personal computer. The electronic device 6600 includes a housing 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display unit 6615, and a control device 6616. The control device 6616 may include, for example, one or more of a CPU, a GPU, and a storage device. A semiconductor device according to one embodiment of the present invention can be applied to the control device 6616, for example. This allows for miniaturization of the electronic device 6600.

[0474] [Mainframe computer] then, Figure 27C A perspective view of a mainframe computer 5600 is shown. Figure 27C In the illustrated mainframe computer 5600, a plurality of rack-mount computers 5620 are housed in a rack 5610. The mainframe computer 5600 may also be referred to as a supercomputer.

[0475] Computer 5620 may have, for example, Figure 27D The structure of the stereogram shown. Figure 27D In the embodiment, computer 5620 includes motherboard 5630, which includes multiple slots 5631 and multiple connection terminals. A personal computer card 5621 is inserted into slot 5631. Personal computer card 5621 includes connection terminals 5623, 5624, and 5625, which are connected to motherboard 5630.

[0476] Figure 27EThe illustrated personal computer card 5621 is an example of a processing board including a CPU, a GPU, a storage device, etc. The personal computer card 5621 includes a board 5622. In addition, the board 5622 includes a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629. Note that Figure 27E Semiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 are shown. For description of these semiconductor devices, refer to the description of the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 described below.

[0477] The connection terminal 5629 has a shape that can be inserted into the slot 5631 of the motherboard 5630, and is used as an interface for connecting the personal computer card 5621 and the motherboard 5630. An example of the standard of the connection terminal 5629 is PCIe.

[0478] The connection terminals 5623, 5624, and 5625 can be used, for example, as interfaces for supplying power to the PC card 5621 or inputting signals. Furthermore, for example, they can be used as interfaces for outputting signals calculated by the PC card 5621. Examples of the standards for the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Furthermore, when video signals are output from the connection terminals 5623, 5624, and 5625, examples of the standards include HDMI (registered trademark).

[0479] The semiconductor device 5626 includes terminals (not shown) for inputting and outputting signals. By inserting the terminals into sockets (not shown) included in the board 5622 , the semiconductor device 5626 and the board 5622 can be electrically connected.

[0480] The semiconductor device 5627 includes a plurality of terminals. For example, by soldering the terminals to wiring included in the board 5622 by reflow soldering, the semiconductor device 5627 and the board 5622 can be electrically connected. Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU. For example, the electronic component 730 can be used as the semiconductor device 5627.

[0481] The semiconductor device 5628 includes a plurality of terminals. For example, by soldering these terminals to wiring included in the board 5622 by reflow soldering, the semiconductor device 5628 and the board 5622 can be electrically connected. For example, a memory device can be used as the semiconductor device 5628. For example, the electronic component 700 can be used as the semiconductor device 5628.

[0482] The mainframe computer 5600 can be used as a parallel computer. By using the mainframe computer 5600 as a parallel computer, for example, large-scale calculations required for learning and inference of artificial intelligence can be performed.

[0483] [Space Equipment] The semiconductor device of one embodiment of the present invention can be applied to space equipment (for example, equipment having functions of processing and storing information).

[0484] A semiconductor device according to one embodiment of the present invention may include an OS transistor. This OS transistor exhibits minimal fluctuations in electrical characteristics due to exposure to radiation. In other words, it exhibits high resistance to radiation and can be suitably used in environments where radiation is likely to enter. For example, an OS transistor can be suitably used in space.

[0485] exist Figure 28 , an artificial satellite 6800 is shown as an example of a space device. The artificial satellite 6800 includes a main body 6801, a solar cell panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Figure 28 An example of a planet 6804 in outer space is shown. Note that outer space refers to an altitude of 100 km or higher, for example, but the outer space described in this specification may also include the thermosphere, mesosphere, and stratosphere.

[0486] In addition, although Figure 28 Although not shown, a battery management system (also called BMS) or a battery control circuit may be provided in the secondary battery 6805. When an OS transistor is used for the battery management system or the battery control circuit, power consumption is low and high reliability is achieved even in outer space, which is preferable.

[0487] Furthermore, outer space is an environment with a radiation dose over 100 times greater than that on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and muon rays.

[0488] When sunlight hits the solar panels 6802, they generate the electricity necessary to operate the satellite 6800. However, if sunlight does not reach the solar panels, or if the amount of sunlight hitting the solar panels is low, the amount of electricity generated decreases. Consequently, there is a possibility that the required electricity for satellite 6800 will not be generated. To enable satellite 6800 to operate even when the generated electricity is low, satellite 6800 is preferably equipped with a secondary battery 6805. Solar panels are sometimes referred to as solar cell modules.

[0489] Satellite 6800 can generate a signal. This signal is transmitted via antenna 6803 and can be received by a receiver on the ground or another satellite. By receiving the signal transmitted by satellite 6800, the position of the receiver receiving the signal can be measured. Thus, satellite 6800 can form a satellite positioning system.

[0490] Furthermore, control device 6807 has the function of controlling artificial satellite 6800. Control device 6807 is configured using, for example, one or more of a CPU, a GPU, and a storage device. Furthermore, a semiconductor device according to one embodiment of the present invention is preferably used for control device 6807. Compared to Si transistors, OS transistors exhibit less variation in electrical characteristics due to exposure to radiation. This means that OS transistors are highly reliable and can be suitably used even in environments where radiation is likely to enter.

[0491] Additionally, artificial satellite 6800 may include sensors. For example, by including a visible light sensor, artificial satellite 6800 may be capable of detecting sunlight reflected from objects on the ground. Alternatively, by including a thermal infrared sensor, artificial satellite 6800 may be capable of detecting thermal infrared radiation emitted from the Earth's surface. Thus, artificial satellite 6800 may be used, for example, as an Earth observation satellite.

[0492] Note that in this embodiment, an artificial satellite is described as an example of space equipment, but the present invention is not limited to this. For example, a semiconductor device according to one embodiment of the present invention can be suitably applied to space equipment such as a spacecraft, a space capsule, and a space probe.

[0493] As described above, OS transistors have superior effects compared to Si transistors, such as achieving a wider memory bandwidth and having high radiation resistance.

[0494] [Data Center] For example, a semiconductor device according to one embodiment of the present invention can be applied to storage systems used in data centers. Data centers are required to manage data over the long term, ensuring data immutability. This long-term data management requires large-scale facilities, such as storage and servers to store large amounts of data, ensuring a stable power supply to maintain data, and ensuring the cooling equipment required for data storage.

[0495] By using a storage device according to one embodiment of the present invention in a storage system employed in a data center, it is possible to reduce the power required to retain data and to miniaturize the storage device used to retain data. Consequently, it is possible to miniaturize the storage system, the power supply required to retain data, and the cooling equipment required. This can save space in the data center.

[0496] Furthermore, the storage device according to one embodiment of the present invention has low power consumption, thereby reducing circuit heat generation. This reduces the negative impact of heat generation on the circuit itself, peripheral circuits, and modules. Furthermore, by using the storage device according to one embodiment of the present invention, a data center that can operate stably even in high-temperature environments can be realized, thereby improving the reliability of the data center.

[0497] Figure 29 A storage system that may be used in a data center is shown. Figure 29 The storage system 7000 shown includes a plurality of servers 7001sb as a host 7001 and a plurality of storage devices 7003md as storage 7003. The host 7001 and storage 7003 are connected via a storage area network 7004 and a storage control circuit 7002.

[0498] The host 7001 corresponds to a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

[0499] In storage 7003, the use of flash memory shortens data access speed, that is, shortens the time required to store and output data. However, this time is much longer than the time required by DRAM, which can be used as a cache in the storage. In storage systems, to address the problem of long access speeds to storage 7003, a cache is generally provided in the storage to shorten the time required to store and output data.

[0500] The cache memory is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003 and then output to the host 7001 or the storage 7003.

[0501] When OS transistors are used as transistors for storing cache data to hold a potential corresponding to the data, the refresh frequency can be reduced to reduce power consumption. In addition, miniaturization can be achieved by stacking memory cell arrays.

[0502] Note that by using a semiconductor device according to one embodiment of the present invention in one or more of electronic components, electronic devices, mainframe computers, space equipment, and data centers, it is expected that power consumption can be reduced. Therefore, it is currently believed that as energy requirements increase with the performance and integration of semiconductor devices, the use of a semiconductor device according to one embodiment of the present invention can also reduce greenhouse gas emissions such as carbon dioxide (CO2). In addition, the semiconductor device according to one embodiment of the present invention has low power consumption and is therefore also effective as a measure to combat global warming.

[0503] The configuration, structure, method, and the like described in this embodiment can be used in combination with the configuration, structure, method, and the like described in other embodiments as appropriate.

[0504] (Implementation 4) In this embodiment, an application example of a storage device according to one embodiment of the present invention will be described.

[0505] Generally speaking, various memory devices are used in semiconductor devices such as computers according to their applications. Figure 30A Various memory devices used in semiconductor devices are shown in a hierarchical manner. Memory devices in the upper layers are required to have faster operating speeds, while memory devices in the lower layers are required to have larger storage capacities and higher recording densities. Figure 30A In the example, from the top layer, it includes memory installed as register circuits in arithmetic processing devices such as a CPU, L1 cache, L2 cache, L3 cache, main memory, and storage. Note that although the example shown here includes only the L3 cache, caches at lower levels may also be included.

[0506] Because memory incorporated into a CPU or other processing unit as register circuits is used, for example, to temporarily store calculation results, it is frequently accessed by the processing unit. Consequently, faster operating speed is required over storage capacity. Furthermore, register circuits also have the function of storing, for example, configuration information for the processing unit.

[0507] Cache memory copies and stores a portion of the data held in main memory. By copying and storing frequently used data in cache memory, data access speed can be improved. Cache memory requires less storage capacity than main memory, but it requires a higher operating speed. Furthermore, data that has been overwritten in cache memory is copied and stored in main memory.

[0508] The main memory has a function of holding programs and data read from storage.

[0509] Storage is used to store data that requires long-term preservation and various programs used by processing devices. Therefore, storage requires large storage capacity and high recording density over high operating speed. For example, high-capacity non-volatile storage devices such as 3D NAND can be used.

[0510] The memory device (OS memory) using metal oxide according to one embodiment of the present invention has a high operating speed and can retain data for a long time. Figure 30A As shown, the storage device according to one embodiment of the present invention can be used in both a hierarchy including cache and a hierarchy including main memory. In addition, the storage device according to one embodiment of the present invention can also be used in a hierarchy including storage.

[0511] also, Figure 30B An example is shown in which an SRAM (Static RAM) is used for a part of the cache and an OS memory according to one embodiment of the present invention is used for the other part.

[0512] The lowest-level cache can be called an LLC (Last Level Cache). The LLC does not need to operate faster than the caches above it, but is required to have a larger storage capacity. The OS memory of one embodiment of the present invention has a fast operating speed and can retain data for a long time, making it suitable for use in the LLC. Note that the OS memory of one embodiment of the present invention can also be used in the FLC (Final Level Cache).

[0513] For example, Figure 30B As shown in FIG. 1 , SRAM can be used for upper-level cache (L1 cache, L2 cache, etc.) and the OS memory of one embodiment of the present invention can be used for LLC. Figure 30B As shown, DRAM can be used in addition to the OS memory as the main memory.

[0514] The configuration, structure, method, and the like described in this embodiment can be used in combination with the configuration, structure, method, and the like described in other embodiments as appropriate.

[0515] (Additional Notes Regarding Descriptions in This Manual, etc.) Hereinafter, comments will be added to the description of the above-mentioned embodiment and each configuration in the embodiment.

[0516] The structure shown in each embodiment can be appropriately combined with the structure shown in other embodiments to constitute one mode of the present invention. In addition, when multiple structural examples are shown in one embodiment, these structural examples can be appropriately combined.

[0517] In addition, the content (or part thereof) described in a certain embodiment may be applied, combined or replaced with other content (or part thereof) described in that embodiment and / or the content (or part thereof) described in one or more other embodiments.

[0518] The contents described in the embodiments refer to the contents described using various drawings in each embodiment or the contents described using the text described in the specification.

[0519] In addition, more figures can be formed by combining a figure (or part thereof) shown in a certain embodiment with other parts of the figure, other figures (or parts thereof) shown in the embodiment and / or figures (or parts thereof) shown in one or more other embodiments.

[0520] In this specification and other documents, components are categorized by function and represented as separate blocks in block diagrams. However, in actual circuits, for example, it is difficult to categorize components by function. Sometimes, a single circuit may involve multiple functions, or multiple circuits may involve a single function. Therefore, the division of blocks in block diagrams is not limited to the components described in this specification and may vary depending on the circumstances.

[0521] In the drawings, dimensions, layer thicknesses, and regions may be exaggerated for clarity. Therefore, the present invention is not limited to the dimensions shown in the drawings. The drawings show arbitrary dimensions for clarity and are not limited to the shapes or numerical values ​​shown. For example, nonuniformities in signals, voltages, or currents due to noise or timing variations may be present.

[0522] In this specification and other documents, when describing the connection relationship of a transistor, the terms "one of the source and drain" (the first electrode or first terminal) and "the other of the source and drain" (the second electrode or second terminal) are used. This is because the source and drain of a transistor are interchangeable depending on the structure and operating conditions of the transistor. Note that the source and drain of a transistor can be appropriately referred to as source (drain) terminals or source (drain) electrodes, etc., depending on the situation.

[0523] In this specification, the terms "electrode" and "wiring" do not limit the functions of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where multiple "electrodes" or "wiring" are formed as a single entity.

[0524] In this specification and other publications, the terms "voltage" and "potential" may be interchanged as appropriate. Voltage refers to the potential difference from a reference potential. For example, when the reference potential is ground voltage (ground voltage), voltage can be referred to as "potential." Ground potential does not necessarily mean 0V. Note that potential is relative; for example, the potential supplied to wiring may vary depending on the reference potential.

[0525] In this specification, the terms "film" and "layer" may be interchanged depending on the situation or condition. For example, "conductive layer" may be replaced with "conductive film" or "insulating film" may be replaced with "insulating layer".

[0526] In this specification, etc., a switch refers to an element that controls whether current flows by switching to a conductive state (on state) or a non-conductive state (off state). Alternatively, a switch refers to an element that selects and switches a current path.

[0527] In this specification, etc., for example, the channel length refers to the distance between the source and the drain in the region where the semiconductor (or the portion of the semiconductor through which current flows when the transistor is in an on state) and the gate overlap, or in the region where the channel is formed, in a top view of the transistor.

[0528] In this specification, etc., for example, the channel width refers to the length of the region where the semiconductor (or the portion of the semiconductor through which current flows when the transistor is in the on state) and the gate electrode overlap, or the portion where the source and drain electrodes face each other in the region where the channel is formed.

[0529] In this specification, "A and B are connected" includes not only direct connection between A and B but also electrical connection between A and B. Here, the phrase "electrically connecting A and B" means that when an object having some kind of electrical interaction exists between A and B, electrical signals can be transmitted and received between A and B. Example

[0530] In this embodiment, a memory device is manufactured and its evaluation results are described.

[0531] In the storage device manufactured in this embodiment, Figure 11A 、 Figure 11B 、 14A to 14D The memory cells of the structure shown are arranged in a matrix to form a memory cell array. Figure 14A The wiring 63 shown has Figure 14E In addition, the transistors 43 and 44 included in the memory cell are OS transistors.

[0532] In this embodiment, a TEG (Test Element Group) device including the above-mentioned memory cell array is manufactured. Figure 31 : is a block diagram showing the structure of a TEG device. In the TEG device, 128 rows and 128 columns of memory cells are arranged in a matrix. Here, the memory cells at the 64th row and 64th column, the 64th row and 65th column, the 65th row and 64th column, and the 65th row and 65th column are respectively referred to as memory cell 42[1,1], memory cell 42[1,2], memory cell 42[2,1], and memory cell 42[2,2]. In addition, the memory cells other than the above are referred to as memory cell 42D. The circuit structure of memory cell 42[1,1], memory cell 42[1,2], memory cell 42[2,1], memory cell 42[2,2], and memory cell 42D adopts Figure 11A and Figure 11B In addition, a precharge circuit 47 and a source follower circuit 49 are provided in the TEG device.

[0533] Memory cell 42[1,1], memory cell 42[1,2], and memory cell 42D in the 64th row are electrically connected to wiring 61[1] as wiring 61, and to wiring 63[1] as wiring 63. Memory cell 42[2,1], memory cell 42[2,2], and memory cell 42D in the 65th row are electrically connected to wiring 61[2] as wiring 61, and to wiring 63[2] as wiring 63. Memory cells 42D in rows 1 to 63 and rows 66 to 128 are electrically connected to wiring 61D as wiring 61, and to wiring 63D as wiring 63. Wiring 63D is supplied with potential VDD as a high potential.

[0534] Memory cell 42[1,1], memory cell 42[2,1], and memory cell 42D in the 64th column are electrically connected to wiring 65[1] as wiring 65, and are also electrically connected to wiring 67[1] as wiring 67. Memory cell 42[1,2], memory cell 42[2,2], and memory cell 42D in the 65th column are electrically connected to wiring 65[2] as wiring 65, and are also electrically connected to wiring 67[2] as wiring 67. Memory cells 42D in columns 1 to 63 and columns 66 to 128 are electrically connected to wiring 65D as wiring 65, and are also electrically connected to wiring 67D as wiring 67. Like wiring 63D, potential VDD is supplied to wiring 65D and wiring 67D.

[0535] Wiring 67[1] and wiring 67[2] are electrically connected to the precharge circuit 47 and the source follower circuit 49. The precharge circuit 47 is electrically connected to wiring 77. The source follower circuit 49 is electrically connected to wiring 69[1] and wiring 69[2].

[0536] The precharge circuit 47 has a function of controlling the precharge performed before reading data from the wiring 67[1] and the wiring 67[2]. Specifically, the precharge circuit 47 has a function of supplying the potential of the wiring 77 to the wiring 67[1] and the wiring 67[2] during precharge. The source follower circuit 49 has a function of outputting data input from the wiring 67[1] to the wiring 69[1] and outputting data input from the wiring 67[2] to the wiring 69[2].

[0537] Figure 32 It is a timing diagram showing the change of the potential of wiring 61[1], wiring 63[1], wiring 69[1] and wiring 69[2]. Figure 32 In the figure, the horizontal axis represents elapsed time [ms]. The vertical axis represents potential, with each scale interval representing 1 V. In this embodiment, data is written to and read from memory cells 42 [1, 1], 42 [1, 2], 42 [2, 1], and 42 [2, 2] during period P1, and data is similarly written to and read from memory cells 42 [1, 1], 42 [1, 2], and during period P2.

[0538] During period P1, first, the potentials of wiring 61[1] and wiring 63[1] are set to a high potential, and the potentials of wiring 61[2] and wiring 63[2] are set to a low potential. Furthermore, the potential of wiring 65[1] is set to a low potential, and the potential of wiring 65[2] is set to a high potential. As a result, digital data "0" is written to memory cell 42[1,1], and digital data "1" is written to memory cell 42[1,2].

[0539] Next, after the potentials of wiring 61[1] and wiring 63[1] are set to a low potential, the potentials of wiring 61[2] and wiring 63[2] are set to a high potential. Furthermore, the potential of wiring 65[1] is set to a high potential, and the potential of wiring 65[2] is set to a low potential. Thus, digital data with a value of "1" is written to memory cell 42[2,1], and digital data with a value of "0" is written to memory cell 42[2,2].

[0540] Next, after the potentials of wiring 61[2] and wiring 63[2] are set to low, the potential of wiring 63[1] is set to high. Thus, the data written to memory cell 42[1,1] and the data written to memory cell 42[1,2] are read out, respectively. The data read out from memory cell 42[1,1] is output to wiring 69[1], and the data read out from memory cell 42[1,2] is output to wiring 69[2].

[0541] Next, after the potential of wiring 63[1] is set to a low potential, the potential of wiring 63[2] is set to a high potential. Thus, the data written to memory cell 42[2,1] and the data written to memory cell 42[2,2] are read out, respectively. The data read out from memory cell 42[2,1] is output to wiring 69[1], and the data read out from memory cell 42[2,2] is output to wiring 69[2].

[0542] Then, the potential of the wiring 63[2] is set to a low potential. The above is the operation in the period P1.

[0543] During period P2, the potential changes of wiring 61[1], wiring 61[2], wiring 63[1], and wiring 63[2] are the same as during period P1. Thus, during period P2, data is written to and read from memory cells 42[1,1], 42[1,2], 42[2,1], and 42[2,2] in the same manner as during period P1. Here, during period P2, digital data with a value of "1" is written to memory cells 42[1,1] and 42[2,2], and digital data with a value of "0" is written to memory cells 42[1,2] and 42[2,1]. That is, the data written to storage cell 42[1,1], storage cell 42[1,2], storage cell 42[2,1] and storage cell 42[2,2] during period P2 are digital data obtained by inverting the values ​​of the data written to storage cell 42[1,1], storage cell 42[1,2], storage cell 42[2,1] and storage cell 42[2,2] during period P1.

[0544] like Figure 32 As shown, in all of the memory cells 42[1,1], 42[1,2], 42[2,1], and 42[2,2], when digital data with a value of "0" is read, the potential of the wiring 69[1] or 69[2] becomes a low potential, and when digital data with a value of "1" is read, the potential of the wiring 69[1] or 69[2] becomes a high potential. As described above, it was confirmed that the TEG manufactured in this embodiment is functioning normally. Specifically, it was confirmed that the data written to the memory cells can be accurately read.

[0545] In this embodiment, a 32kB memory device is manufactured. After writing data to the memory cells included in the memory device, the data is read out at a predetermined time to evaluate the probability that the written value data is read out (normal bit rate). Here, when writing data, for example, Figure 11A and Figure 11BIn the example shown, a high potential is applied to wiring 61, and a low potential is applied to wiring 63. Furthermore, when reading data, a low potential is applied to wiring 61, and a high potential is applied to wiring 63. The data writing and reading times are both 285 ns. The temperature is room temperature.

[0546] Figure 33 : is a graph showing the normal bit rate for each data retention time (the time elapsed after the data writing is completed). Figure 33 As shown, it was confirmed that the data retention time was 100% when the data retention time was 38 seconds or less, and no bit errors occurred. In addition, it was confirmed that even if the data retention time exceeded 38 seconds, a high normal bit rate of 99.7% or more was maintained.

[0547] In addition, in this embodiment, a memory device including a CPU and a memory unit on the CPU is manufactured as a chip. Figure 18 The transistor 57 shown in FIG. 1 and the transistor 54 on the transistor 57. The memory cell includes the transistor 43 on the transistor 54 and the transistor 44. The wiring 63 included in the transistor 43 has Figure 14E The structure shown.

[0548] Transistor 57 is a Si transistor with a channel length of 130 nm. Transistor 54 is a planar OS transistor with a channel length of 200 nm. Transistors 43 and 44 are vertical OS transistors with a channel length of 95 nm. Furthermore, the shape of openings 190 and 290, when viewed from above, is a circle with a diameter of 60 nm.

[0549] Figure 34A : is a photograph showing the planar layout of the chip. The chip manufactured in this embodiment has an area 71 including a CPU and a memory cell, and an area 73 including a power supply circuit.

[0550] Figure 34B It is magnified Figure 34A A photograph of the area 70 is shown. Figure 34A As shown, region 70 is included in region 71 .

[0551] Figure 34C It is from Figure 34B Summary shows a photograph of layers including transistor 57 which is a Si transistor. Figure 34D It is from Figure 34B A photograph of the layers including the transistor 54 as a planar OS transistor is shown in summary. Figure 34E It is from Figure 34B A photograph of a layer including the transistor 43 as a vertical OS transistor and a layer including the transistor 44 as a vertical OS transistor is summarized.

[0552] Figure 35AThis is a STEM (Scanning Transmission Electron Microscopy) image of the chip. Figure 35A As shown, it was confirmed that the transistor 57 of the Si transistor, the transistor 54 of the planar OS transistor, and the transistors 43 and 44 of the vertical OS transistors could be formed into desired shapes.

[0553] Figure 35B Is enlarged including Figure 35A The STEM images of the regions of transistors 43 and 44 are shown. Figure 35B Insulation layer 187 is equivalent to Figure 18 The layers of insulating layer 185 and insulating layer 280 are shown.

[0554] like Figure 35B As shown, it was confirmed that in transistor 43, opening 190 reaching wiring 63 was formed in insulating layer 180 and wiring 67, and semiconductor layer 170, insulating layer 130, and conductive layer 120 were formed so as to have a region located within opening 190. Furthermore, it was confirmed that in transistor 44, opening 290 reaching conductive layer 120 was formed in insulating layer 187 and wiring 65, and semiconductor layer 270, insulating layer 230, and conductive layer 220 were formed so as to have a region located within opening 290. Furthermore, it was confirmed that the top surface of conductive layer 120 was in contact with the bottom surface of semiconductor layer 270 within opening 290. [Explanation of symbols]

[0555] 10: Semiconductor device, 20: Layer, 21A: CPU, 21: CPU, 22a: Word line driver circuit, 22b: Word line driver circuit, 22c: Bit line driver circuit, 22d: Bit line driver circuit, 22e: Switch driver circuit, 22: Driver circuit, 23: Control circuit, 24A: Clock buffer circuit, 24: Flip-flop circuit, 25: Arithmetic circuit, 26: Cache, 27: Memory controller, 30: Layer, 34: Backup circuit, 40_1: Layer, 40_2: Layer, 40_3: Layer, 40: Layer, 41_1: Memory cell array, 41_11: Memory cell array, 41_12: Memory cell array, 41_2: Memory cell array, 41_21: Memory cell array, 41 _22: memory cell array, 41: memory cell array, 42[1,1]: memory cell, 42[1,2]: memory cell, 42[2,1]: memory cell, 42[2,2]: memory cell, 42_1: memory cell, 42_11: memory cell, 42_12: memory cell, 42_2: memory cell, 42_21: memory cell, 42_22: memory cell, 42D: memory cell, 42: memory cell, 43: transistor, 44: transistor, 45: capacitor, 47: precharge circuit, 49: source follower circuit, 50: register circuit, 51: switch circuit group, 52a: switch circuit, 52a[1]: switch circuit, 52a[i]: switch circuit, 52a[ m]: switch circuit, 52b: switch circuit, 52b[1]: switch circuit, 52b[i]: switch circuit, 52b[m]: switch circuit, 52c: switch circuit, 52c[1]: switch circuit, 52c[j]: switch circuit, 52c[n]: switch circuit, 52d: switch circuit, 52d[1]: switch circuit, 52d[j]: switch circuit, 52d[n]: switch circuit, 52: switch circuit, 53_1: circuit, 53_11: circuit, 53_12: circuit, 53_2: circuit, 53_21: circuit, 53_22: circuit, 53: circuit, 54_1: transistor, 54_11: transistor, 54_12: transistor, 54_2: transistor, 54 _21: Transistor, 54_22: Transistor, 54: Transistor, 55_1: Transistor, 55_11: Transistor, 55_12: Transistor, 55_2: Transistor, 55_21: Transistor, 55_22: Transistor, 55: Transistor, 56_1: Capacitor, 56_11: Capacitor, 56_12: Capacitor, 56_2: Capacitor, 56_21: Capacitor, 56_22: Capacitor, 56: Capacitor, 57: Transistor, 61[1]: Wiring, 61[2]: Wiring, 61_1: Wiring, 61_2: Wiring, 61D: Wiring, 61: Wiring, 62[i]: Wiring, 62: Wiring, 63[1]: Wiring, 63[2]: Wiring, 63_1: Wiring,63_2: Wiring, 63D: Wiring, 63: Wiring, 64[i]: Wiring, 64: Wiring, 65[1]: Wiring, 65[2]: Wiring, 65_1: Wiring, 65_11: Wiring, 65_12: Wiring, 65_2: Wiring, 65_21: Wiring, 65_22: Wiring, 65D: Wiring, 65: Wiring, 66[j]: Wiring, 66: Wiring, 67[1]: Wiring, 67[2]: Wiring, 67_1: Wiring, 67_11: Wiring, 67_12: Wiring, 67_2: Wiring, 67_21: Wiring, 67_22: Wiring, 67D: Wiring, 67: Wiring, 68[j]: Wiring, 68: Wiring, 69[1]: Wiring, 69[2]: Wiring , 70: Region, 71: Region, 73: Region, 77: Wiring, 120: Conductive layer, 130: Insulating layer, 160: Insulating layer, 170: Semiconductor layer, 180: Insulating layer, 185: Insulating layer, 187: Insulating layer, 190: Opening, 220: Conductive layer, 230: Insulating layer, 270i: Region, 270na: Region, 270nb: Region, 270: Semiconductor layer, 280: Insulating layer, 285: Insulating layer, 287: Insulating layer, 290: Opening, 301: Insulating layer, 310: Wiring, 311: Substrate, 313: Semiconductor region, 314a: Low resistance region, 314b: Low resistance region, 315: Insulating layer, 316: Conductive layer, 317: Insulating layer , 320: conductive layer, 321: insulating layer, 324: insulating layer, 326: insulating layer, 328: conductive layer, 330: insulating layer, 331: conductive layer, 350: insulating layer, 352: insulating layer, 356: conductive layer, 357: insulating layer, 380: insulating layer, 385: insulating layer, 390: opening, 420: conductive layer, 430: insulating layer, 460: insulating layer, 463: conductive layer, 467: conductive layer, 470: semiconductor layer, 480: insulating layer, 485: insulating layer, 487: insulating layer, 700: electronic component, 702: printed circuit board, 704: circuit board, 710: semiconductor device, 711: mold, 712: connection pad, 713: electrode pad, 71 4: Lead, 715: Driving circuit layer, 716: Storage layer, 730: Electronic component, 731: Interposer, 732: Package substrate, 733: Electrode, 735: Semiconductor device, 800: Transistor, 805a: Conductive layer, 805b: Conductive layer, 805: Conductive layer, 815: Insulating layer, 816: Insulating layer, 820: Semiconductor layer, 821: Insulating layer, 822: Insulating layer, 824: Insulating layer, 842a: Conductive layer, 842b: Conductive layer, 850: Insulating layer, 855: Insulating layer, 860a: Conductive layer, 860b: Conductive layer, 860: Conductive layer, 871a: Insulating layer, 871b: Insulating layer, 875: Insulating layer, 882: Insulating layer, 883: Insulating layer,885: Insulating layer, 887: Insulating layer, 891: Conductive layer, 892: Conductive layer, 893: Conductive layer, 895: Conductive layer, 896: Conductive layer, 897: Conductive layer, 898: Conductive layer, 899: Conductive layer, 901: Conductive layer, 930: Layer, 960: Layer, 970A: Semiconductor device, 970B: Semiconductor device, 5600: Mainframe computer, 5610: Rack, 5620: Computer, 5621: Personal computer card, 5622: Board, 5623: Connecting terminal, 5624: Connecting terminal, 5625: Connecting terminal, 5626: Semiconductor device, 5627: Semiconductor device, 5628: Semiconductor device, 5629: Connecting terminal, 5630: Motherboard, 5631: Slot, 6500: Electronic device, 650 1: Housing, 6502: Display, 6503: Power button, 6504: Button, 6505: Speaker, 6506: Microphone, 6507: Camera, 6508: Light source, 6509: Control device, 6600: Electronic device, 6611: Housing, 6612: Keyboard, 6613: Pointing device, 6614: External connection port, 6615: Display, 6616: Control device, 6800: Artificial satellite, 6801: Main body, 6802: Solar panel, 6803: Antenna, 6804: Planet, 6805: Secondary battery, 6807: Control device, 7000: Storage system, 7001sb: Server, 7001: Host, 7002: Storage control circuit, 7003md: Storage device, 7003: Storage.

Claims

1. A semiconductor device comprising: CPU; Switching circuit; a first memory cell array; as well as a second memory cell array, Wherein, the CPU includes a control circuit and a register circuit, The register circuit includes a trigger circuit and a backup circuit, In the first memory cell array, the first memory cells are arranged in a matrix. In the second memory cell array, the second memory cells are arranged in a matrix. The control circuit and the trigger circuit are arranged in the first layer, The switch circuit and the backup circuit are arranged in a second layer above the first layer, The first memory cell array and the second memory cell array are arranged in a third layer on the second layer, The switch circuit has a function of supplying a signal to one of the first storage unit and the second storage unit. The control circuit and the trigger circuit include transistors whose channel formation regions include silicon. Furthermore, the switch circuit and the backup circuit include transistors having a channel formation region containing a metal oxide.

2. The semiconductor device according to claim 1, The switch circuit includes a first transistor, a second transistor, a third transistor and a fourth transistor, One of the source and the drain of the first transistor and one of the source and the drain of the second transistor are supplied with the signal, The gate of the first transistor is electrically connected to one of the source and the drain of the third transistor, The gate of the second transistor is electrically connected to one of the source and the drain of the fourth transistor, The other of the source and the drain of the third transistor is supplied with the first selection signal. The other of the source and the drain of the fourth transistor is supplied with the second selection signal, The signal is output from the other of the source and the drain of the first transistor or the other of the source and the drain of the second transistor according to the first selection signal and the second selection signal. In the case where the signal is output from the other of the source and the drain of the first transistor, the signal is supplied to the first memory cell, And in the case where the signal is output from the other of the source and the drain of the second transistor, the signal is supplied to the second memory cell.

3. The semiconductor device according to claim 2, The switch circuit includes a first capacitor and a second capacitor, One electrode of the first capacitor is electrically connected to the gate of the first transistor, The other electrode of the first capacitor is electrically connected to the other of the source and the drain of the first transistor, One electrode of the second capacitor is electrically connected to the gate of the third transistor, And the other electrode of the second capacitor is electrically connected to the other of the source and the drain of the third transistor.

4. The semiconductor device according to any one of claims 1 to 3, wherein the first storage unit comprises a fifth transistor, The second storage unit includes a sixth transistor, Furthermore, the fifth transistor and the sixth transistor include metal oxide in their channel formation regions.

5. The semiconductor device according to claim 4, wherein the third layer comprises an insulating layer, The insulating layer includes a first opening and a second opening, The channel formation region of the fifth transistor has a region along the side surface of the first opening. Furthermore, a channel formation region of the sixth transistor includes a region along a side surface of the second opening.

6. A semiconductor device comprising: CPU; Switching circuit; a first memory cell array; as well as a second memory cell array, Wherein, the CPU includes a control circuit and a register circuit, The register circuit includes a trigger circuit and a backup circuit, In the first memory cell array, the first memory cells are arranged in a matrix. In the second memory cell array, the second memory cells are arranged in a matrix. The first storage unit includes a first transistor and a second transistor, The second storage unit includes a third transistor and a fourth transistor, The control circuit and the trigger circuit are arranged in the first layer, The switch circuit and the backup circuit are arranged in a second layer above the first layer, The first transistor and the third transistor are provided in a third layer on the second layer, The second transistor and the fourth transistor are provided in a fourth layer on the third layer, The switch circuit has a function of supplying a signal to one of the first storage unit and the second storage unit. The control circuit and the trigger circuit include transistors whose channel formation regions include silicon. The switch circuit and the backup circuit include transistors having a channel formation region containing a metal oxide. Furthermore, the first to fourth transistors include metal oxide in their channel formation regions.

7. The semiconductor device according to claim 6, The switch circuit includes a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor, One of the source and the drain of the fifth transistor and one of the source and the drain of the sixth transistor are supplied with the signal, The gate of the fifth transistor is electrically connected to one of the source and the drain of the seventh transistor, The gate of the sixth transistor is electrically connected to one of the source and the drain of the eighth transistor, The other of the source and the drain of the seventh transistor is supplied with the first selection signal. The other of the source and the drain of the eighth transistor is supplied with the second selection signal. The signal is output from the other of the source and the drain of the fifth transistor or the other of the source and the drain of the sixth transistor according to the first selection signal and the second selection signal. In the case where the signal is output from the other of the source and the drain of the fifth transistor, the signal is supplied to the first memory cell, And in the case where the signal is output from the other of the source and the drain of the sixth transistor, the signal is supplied to the second memory cell.

8. The semiconductor device according to claim 7, The switch circuit includes a first capacitor and a second capacitor, One electrode of the first capacitor is electrically connected to the gate of the fifth transistor, The other electrode of the first capacitor is electrically connected to the other of the source and the drain of the fifth transistor, One electrode of the second capacitor is electrically connected to the gate of the seventh transistor, And the other electrode of the second capacitor is electrically connected to the other of the source and the drain of the seventh transistor.

9. The semiconductor device according to claim 6, wherein the third layer comprises a first insulating layer, The fourth layer includes a second insulating layer, The first insulating layer includes a first opening and a second opening, The second insulating layer includes a third opening and a fourth opening, The channel formation region of the first transistor has a region along the side surface of the first opening. The channel formation region of the second transistor has a region along the side surface of the second opening. The channel formation region of the third transistor has a region along the side surface of the third opening. Furthermore, a channel formation region of the fourth transistor includes a region along a side surface of the fourth opening.

10. The semiconductor device according to any one of claims 1 to 3 or 6 to 9, The first storage unit has a function of storing first data, The second storage unit has a function of storing second data. Furthermore, the type of the first data is different from that of the second data.

11. The semiconductor device according to claim 10, The first data or the second data is program data.

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