Low pin count scan without dedicated scan enable pins

Abstract

The invention relates to a low pin count scan without dedicated scan enable pins. According to one embodiment, a method for testing using a scan chain without an independent scan enable pin is presented. The method includes selectively indicating a capture phase and a load / unload phase of the scan chain based on encoding of a scan enable signal in the desired signal and the masking signal; the test parameters are loaded to the scan chain in the loading stage / unloading stage; operating the scan chain in the function mode in the capture phase; and generating an error signal based on comparing the output of the unload phase scan chain with a desired signal, wherein the masking signal is used to mask the output of the scan chain within a period with an invalid result.

Description

Technical Field

[0001] The present disclosure relates generally to design for test (DFT) and, in particular embodiments, to DFT devices, circuits, and methods of operation with low pin count scan and no dedicated scan enable pins. Background Art

[0002] Integrated circuits (ICs) are typically tested for faults. In particular, the logic circuits of an integrated circuit are typically tested using a method commonly referred to as scan testing. During scan testing, a test pattern is shifted in through one or more chains of flip-flops (i.e., scan chains) to stimulate one or more logic circuits. The results of the stimulated logic circuits are loaded into the scan chains and shifted out for evaluation. When the shifted-out pattern matches the expected pattern (based on the normal operation of one or more logic circuits), no fault is detected and the circuit is likely to be free of defects. When the shifted-out pattern does not match the expected pattern, a fault is detected.

[0003] Achieving higher scan compression is at the heart of integrated circuit (IC) testing. This goal is becoming increasingly important because it directly impacts the cost of test and, therefore, the profitability of IC designs. Scan compression technology allows more IC functionality to be tested with fewer test vectors. As ICs grow in complexity and density, the amount of test data required to ensure quality and reliability is also increasing. This creates challenges in storing test data and the time required to apply the tests. Higher scan compression addresses this challenge by reducing the amount of test data required, which can significantly reduce test application time and test data volume. The reduction in test time and data directly translates into cost savings, as less time spent on automatic test equipment (ATE) reduces the cost per chip, thereby increasing overall design revenue by achieving higher manufacturing throughput.

[0004] With the emergence of new technologies and applications, such as those found in the automotive industry, the demand for multi-site testing has surged. Multi-site testing can test multiple devices or chips in parallel at the same time, thereby improving throughput and efficiency. This approach is particularly beneficial when producing large quantities of automotive-related chips, which require strict quality standards due to their critical safety applications. However, multi-site testing requires that large amounts of scan data be delivered to multiple dies simultaneously without compromising speed or reliability. Along with this challenge, new fault models have emerged due to the increasing complexity of automotive electronics and the demand for high reliability, resulting in an explosive growth in the amount of test data. Therefore, the multi-site testing requirements and new fault models in automotive applications are driving the need for enhanced scan compression technology solutions that can handle the sharply increased scan volume.

[0005] Given these challenges, it would be beneficial to have technical solutions to manage and mitigate lengthy test application times without sacrificing test coverage or fault detection capabilities to meet the growing testing demands and maintain the integrity and reliability of complex systems in safety-critical areas such as automotive electronics. Summary of the Invention

[0006] Technical advantages are generally achieved by embodiments of the present disclosure, which describe a design of a device for test (DFT) apparatus, circuits, and methods of operation with low pin count scan and no dedicated scan enable pins.

[0007] A first aspect relates to a method for testing a scan chain without a separate scan enable pin. The method includes selectively indicating a capture phase and a load / unload phase of the scan chain based on encoding of a scan enable signal in a desired signal and a mask signal; loading test parameters into the scan chain during the load / unload phase; operating the scan chain in a functional mode during the capture phase; and generating an error signal based on comparing an output of the scan chain during the unload phase with the desired signal, wherein the mask signal is used to mask the output of the scan chain during cycles with invalid results.

[0008] A second aspect relates to a method for testing using a scan chain without a separate scan enable pin. The method includes preloading a first number of shift cycles into a shift counter circuit, the first number of shift cycles corresponding to a test pattern set; preloading a second number of capture cycles into a capture counter circuit, the second number of capture cycles corresponding to the test pattern set; initiating a load phase / unload phase of the test by maintaining an internally generated scan enable signal at a high logic level, wherein the shift counter circuit counts the number of preloaded shift cycles; in response to the shift counter circuit completing the preload count, transitioning the internally generated scan enable signal to a logic level, wherein the transition initiates a capture phase of the test; and in response to the capture counter circuit completing the preload count, initiating a subsequent load phase / unload phase of the test by transitioning the internally generated scan enable signal to a high logic level.

[0009] A third aspect relates to a method for testing using a scan chain in a digital circuit without an independent scan enable pin. The method includes specifying a first pin assignment having N input pins and R merged input pins, N and R being integers, N corresponding to the number of input pins for carrying scan input chain test data, and R corresponding to the number of input pins for carrying merged expected test results and mask instruction signals; specifying a second pin assignment having N input pins and M output pins, M being an integer and corresponding to the number of output pins for carrying scan output chain test data; inserting a comparator circuit and a decoding logic circuit into the digital circuit; generating an N by M codec; integrating the N by M codec and inserting the scan chain, wherein the device registers are spliced ​​into multiple scan chains and coupled between a compression circuit and a decompression circuit; and using 2 provided by the R merged input pins. R One of the three states decodes the internally generated scan enable signal. N The first state is the decoded output from the decode logic circuit.

[0010] Embodiments may be implemented in hardware, software, or any combination thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] For a more complete understanding of the present disclosure and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 is a block diagram of the architecture used to test the scan chain;

[0013] Figure 2 is a block diagram of the on-chip comparator circuit;

[0014] Figure 3 is a block diagram of a logic circuit of an embodiment;

[0015] Figure 4 is a block diagram of an embodiment circuit configured to identify a shift phase and a capture phase;

[0016] Figure 5 is a block diagram of an on-chip comparator circuit of an embodiment;

[0017] Figure 6 is a block diagram of a comparator circuit of an embodiment;

[0018] Figure 7 is an example table that maps five binary input states to data having one of three states;

[0019] Figure 8 is a flow chart of an embodiment method;

[0020] Figure 9 is a flow chart of an embodiment method; and

[0021] Figure 10 is a flow chart of an embodiment method. DETAILED DESCRIPTION

[0022] The present disclosure provides many applicable inventive concepts that can be embodied in a variety of specific contexts. Specific embodiments merely illustrate specific configurations and do not limit the scope of the claimed embodiments. Unless otherwise indicated, features from different embodiments may be combined to form additional embodiments. Various embodiments are illustrated in the accompanying drawings, where like components and elements are identified by like reference numerals, and repeated descriptions are omitted for brevity.

[0023] The changes or modifications described in one embodiment may also be applied to other embodiments. In addition, various changes, substitutions and modifications may be made herein without departing from the spirit and scope of this disclosure as defined in the appended claims.

[0024] Although aspects of the present invention are primarily described in the context of design for test (DFT), it should be understood that these aspects of the invention may also be applied to other aspects of circuit design. Embodiments of the present disclosure are applicable to combinational and sequential compression and may be applied to factory testing using, for example, automatic test pattern generation (ATPG) tools, or field testing using, for example, a logic built-in self-test (LBIST) controller. In particular, aspects of the present disclosure may be applied to DC-DC active matrix organic light emitting diode (AMOLED) display drivers, power management integrated circuits (PMICs), rectifier-type applications, and the like.

[0025] Advances in semiconductor technology, particularly in industries requiring high reliability, such as automotive and medical devices, have led to new fault models that go beyond traditional stuck-at and transition faults. Complex fault models such as small delay defects (SDD) and cell-aware fault models are being developed to capture subtle defects that occur at smaller geometries and can significantly impact the performance and reliability of ICs. These contemporary fault models account for variations in the manufacturing process and subtle interactions between transistors within a cell that can cause failures. While these advanced fault models provide higher quality test, they also contribute to a significant increase in scan volume. This is due to the generation of additional test patterns to cover these finer defects. The resulting expanded scan data must be applied during test to ensure that the IC meets stringent quality requirements, increasing the amount of data that needs to be managed during test.

[0026] The additional test modes required by these new fault models translate directly into increased test time for each device. Since testing is performed at various stages throughout the manufacturing process, and potentially at the end of the production line for quality inspection, the increased test time becomes a recurring cost for each device shipped. This impacts the overall cost base of the IC and can reduce profit margins, so semiconductor companies must seek ways to reduce test time without compromising quality. Test time can be reduced through more advanced scan compression techniques, improved test equipment, enhanced design for testability (DFT) practices, and optimizing test schedules to minimize overhead.

[0027] Advantageously, embodiments of the present disclosure allow for significant test cost savings, which is reflected in increased product lifecycle revenue.The proposed compression architecture does not sacrifice scan data and is flexible enough to work with existing scan architectures.

[0028] In integrated circuit test environments constrained by a limited number of external pins (e.g., available at the chip boundary or package), a decompressor is typically used to internally fan out these few input test signals across multiple scan chains to maximize scan test coverage. A midlayer then bridges the gap between the decompressor and compressor to process test data from the scan chain expansion network.

[0029] The middle layer may include various functional components such as logic gates, multiplexers, buffers, or any other form of digital circuitry to facilitate the processing of test data within the scan chain. It may also involve error detection and correction mechanisms, signal routing, control logic for scan chain selection, or any other related technical functions that support the test infrastructure within the integrated circuit.

[0030] The compressor consolidates the responses from these scan chains to compress them into a number of outputs corresponding to a limited number of external pins. This strategic arrangement allows for extensive internal testing without a direct correlation between the number of scan chains and the number of external pins, thereby optimizing pin utilization during the test phase. Using previously assigned scan enable pins as internal test signals within a limited number of external pins reduces overall scan testing and improves test compression.

[0031] Figure 1A block diagram of an architecture for testing a scan chain 100, for example, in a digital circuit, is shown. The scan chain 100 includes a first scan flip-flop 102, a second scan flip-flop 104, a third scan flip-flop 106, a first multiplexer 108, a second multiplexer 110, a third multiplexer 112, and combinational logic 114, which may or may not be arranged as shown. The scan flip-flop 100 may include additional components not shown, such as additional scan flip-flops and associated multiplexers for each scan flip-flop.

[0032] The first scan flip-flop 102 , the second scan flip-flop 104 , and the third scan flip-flop 106 are arranged in the scan chain 100 to test one or more logic components of the combinational logic 114 in the digital circuit using, for example, ATPG technology.

[0033] The data input (D) of the first scan flip-flop 102 is coupled to the output of the first multiplexer 108, the data input (D) of the second scan flip-flop 104 is coupled to the output of the second multiplexer 110, and the data input (D) of the third scan flip-flop 106 is coupled to the output of the third multiplexer 112. The outputs of the first scan flip-flop 102 and the second scan flip-flop 104 are coupled to the combinatorial logic 114. Each of the multiplexers 108, 110, and 112 includes a functional input terminal, a test input terminal, a select terminal, and an output terminal. The functional input terminals of the second multiplexer 110 and the third multiplexer 112 are coupled to the combinatorial logic 114.

[0034] The value at the select terminal of each multiplexer 108, 110, and 112 determines whether the functional signal or the test input signal (SCAN_IN) is selected at its output terminal by the scan enable signal (SCAN_EN). The output signal (SCAN_OUT) of the third scan flip-flop 106 provides the digital circuit with the test mode result during the test mode.

[0035] A clock signal (SCAN_CLK) is coupled to the clock input of each of the first scan flip-flop 102, the second scan flip-flop 104, and the third scan flip-flop 106. The clock signal controls the timing of operations and synchronizes the movement of data in the scan chain 100. In test mode, the scan chain 100 uses the clock signal to serially shift test data into and out of the scan flip-flops. When the clock signal is applied, the test data moves from one scan flip-flop to the next. In functional mode, the clock signal is used to control the normal operation of the digital circuit, ensuring that data moves through the circuit and that the scan flip-flops are synchronized.

[0036] The transition from functional mode to test mode, and vice versa, can be achieved by changing the input at the select terminal of the corresponding multiplexer via the scan enable signal (SCAN_EN). This provides an efficient mechanism for testing the combinational logic 114 within the digital circuit during normal operation and when performing fault detection and diagnosis. The workflow between functional mode and test mode is different, which is determined by the logic level of the scan enable signal at the select terminal of each multiplexer 108, 110 and 112. During functional mode (i.e., when the scan enable signal is de-asserted), the multiplexers 108, 110 and 112 select the functional input. This allows the digital circuit to operate normally by passing the input signal through the combinational logic 114 and the scan chain 100. The first scan flip-flop 102, the second scan flip-flop 104 and the third scan flip-flop 106 produce the functional output of the combinational logic 114.

[0037] During test mode (i.e., when the scan enable signal is asserted), multiplexers 108, 110, and 112 select the test inputs. A predefined test pattern is fed into the scan chain 100 as a test input signal (SCAN_IN). After the test pattern is fully shifted into the scan chain, a clock signal then shifts the result of the test pattern out as an output signal (SCAN_OUT). The outputs of the scan flip-flops 102, 104, and 106, triggered by the clock signal, provide test data that reflects the state of the combinational logic under test 114.

[0038] During test mode, scan testing is typically divided into three phases: scan-in, capture, and scan-out. During the scan-in phase, a test pattern is provided to the scan chain. The test pattern passes through the scan chain 100, where the third scan flip-flop 106 captures and stores the output of the scan chain 100. During the scan-out phase, the output signal (SCAN_OUT) is compared with the expected value to identify a difference, indicating a fault or error in the scan chain 100.

[0039] A persistent bottleneck in efficiently managing scan test is the limited number of available scan pins, which restricts the amount of scan data that can be loaded onto the device per cycle. Given this limitation, IC designers and test engineers are faced with the challenge of increasing the amount of scan data that can be fed into and out of the chip during a given test cycle. This constraint often requires different approaches to data compression and scan architecture optimization. Advances in multiplexing techniques, serial scan methods, and on-chip decompression hardware have been explored to maximize the utilization of available pins. Each technique aims to amplify the amount of data passing through each scan pin, thereby achieving broader test coverage while adhering to pin count constraints. Therefore, strategies that allow for higher compression of test data and more efficient data delivery systems are critical to reducing test time, saving costs, and ensuring that delivered devices meet the high quality standards required by advanced applications.

[0040] The test process consists of distinct loading, capture, and unloading phases. Each phase corresponds to a different step in the test process and is controlled by the state of the scan enable signal. During the loading phase, the scan enable signal (SCAN_EN) is set to a high logic level. In this state, test data is loaded into the scan chain via the SCAN_IN pin. This action prepares the internal triggers of the scan chain 100 for the specific test data pattern required for the upcoming capture phase.

[0041] After the test data is loaded, the system transitions to the capture phase. In this phase, the scan enable signal (SCAN_EN) is set to a low logic level for one or two clock pulses. During this period, the integrated circuit operates in its functional mode (normal operation) to capture functional data within the flip-flops that were previously loaded with test data.

[0042] After capturing the functional data, the unloading phase begins, where the scan enable signal is asserted again (SCAN_EN) (i.e., high logic level). The data captured in the flip-flop is now serially shifted out to the external pins for analysis. During this shifting process, new test data for the next test cycle can be loaded simultaneously, thereby optimizing test efficiency.

[0043] During these phases, especially during loading and unloading, the scan enable signal (SCAN_EN) maintains a static or pseudo-static behavior; it remains high during both the loading and unloading phases and drops low only during the capture phase. Its predictability means that the scan enable signal (SCAN_EN) does not need to be associated with different functions at different clock cycles.

[0044] Therefore, the scan enable signal (SCAN_EN) is responsible for switching between functional and test modes of operation by controlling the state of a multiplexer that directs either functional signals or test modes to the scan flip-flop. During the scan phase (both scan-in and scan-out), the scan enable signal (SCAN_EN) remains static, either always active or always inactive. Therefore, dedicating an entire pin solely to the scan enable signal (SCAN_EN) can result in inefficient use, especially considering that pins on an integrated circuit are a resource that can increase design complexity and production costs.

[0045] Aspects of the present disclosure propose a scan compression architecture that eliminates the traditional reliance on an external scan enable (SE) pin fed with a scan enable signal (SCAN_EN) from an external device or circuit. In embodiments, the approach involves internal (i.e., on-chip) decoding of the capture window from the existing scan input state, thereby more efficiently squeezing device compression within a limited pin count and reducing test costs. The proposed architecture derives the internal scan enable signal (SCAN_EN) for automatic test pattern generation (ATPG) without additional pins.

[0046] Figure 2 The figure shows a block diagram of an on-chip comparator circuit 200. In an embodiment, the on-chip comparator circuit 200 is coupled to the output of the scan chain 100. The on-chip comparator circuit 200 receives, for example, the output signal (SCAN_OUT) of the scan chain 100 (or from a compressor) as a scan input (SCAN_IN). The scan input is compared with an expected signal (EXPECT) to determine whether the digital circuit is functioning properly. A mask signal (MASK) is used to indicate which cycles of the scan chain or compressor output should be ignored.

[0047] On-chip comparator circuit 200 includes an XOR gate 202, an AND gate 204 having an inverting input, an OR gate 206, and a flip-flop 208, which may or may not be arranged as shown. On-chip comparator circuit 200 may include additional components not shown. For example, on-chip comparator circuit 200 may include an additional OR gate coupled to the output of AND gate 204 and an accumulator signal for testing multiple scan chains having the same circuit.

[0048] XOR gate 202 is a digital logic gate with two inputs and one output. It outputs a high logic level signal only when the two inputs have different logic values. A first input of XOR gate 202 is coupled to, for example, the output signal (SCAN_OUT) of scan chain 100 (or the output of a compressor), while a second input is coupled to an expected signal (EXPECT), which serves as a reference for comparison.

[0049] The output of XOR gate 202 is coupled to the non-inverting input of AND gate 204. The mask signal (MASK) is provided to the inverting input of AND gate 204. When the output of XOR gate 202 is at a high logic level and the mask signal (MASK) is at a low logic level, AND gate 204 outputs a logic high signal.

[0050] The output of AND gate 204 is coupled to a first input of OR gate 206. A second input of OR gate 206 is coupled to an output (Q) of flip-flop 208. The output of OR gate 206 is coupled to an input (D) of flip-flop 208. When at least one input of OR gate 206 is at a high logic level, the output of OR gate 206 is at a high logic level.

[0051] In an embodiment, flip-flop 208 is a D-type flip-flop. When a clock pulse occurs, flip-flop 208 stores data at its input (D). The stored data is available at its output (Q).

[0052] XOR gate 202 compares the output signal (SCAN_OUT) of scan chain 100 with the expected signal (EXPECT). If the two are equal (meaning both bits are logic low or both bits are logic high), XOR gate 202 outputs a logic low signal. If they are different, the XOR gate outputs a logic high signal to indicate the difference.

[0053] AND gate 204 allows certain bits to be masked (ignored) during the comparison. When the mask signal (MASK) is at a high logic level, the inverting input becomes a low logic level, allowing AND gate 204 to pass the output of XOR gate 202 (indicating a mismatch) to OR gate 206. If masking of a particular bit is not desired, the mask signal (MASK) will be at a low logic level to prevent any difference signals from passing through.

[0054] OR gate 206, along with flip-flop 208, acts as an accumulator of differences. If any previous difference was detected and stored in flip-flop 208 (indicating its output (Q) was a high logic level), it will ensure that the output of OR gate 206 remains at a high logic level even if the current comparison does not show a difference. In this way, any detected error is captured and stored until the error can be processed. The output (Q) of flip-flop 208 can be read, for example, via an Internal Joint Test Action Group (IJTAG) interface as a pass / fail indicator for each scan chain.

[0055] By comparing each scanned bit to an expected signal and selectively ignoring bits as needed using mask signals, the on-chip comparator circuit 200 can allow real-time error detection during scan chain testing. The accumulation function ensures that even transient errors are caught and not overwritten by subsequent correct comparisons.

[0056] The error detection mechanism provided in the on-chip comparator circuit 200 can be summarized using Table I.

[0057] SCAN_IN EXPECT MASK SSSSSSSS EEEEEEEE 00000000 SSSSSSSS EXEEXEEE 01001000 SSSSSSSS XXXXXXXX 11111111

[0058] Table I

[0059] Table 1 includes three columns. The first column indicates the output of the scan chain 100 or compressor as the scan input signal (SCAN_IN). The second column indicates various possible expected signals (EXPECT). The third column indicates various possible mask signals (MASK). In Table 1, eight chains with single-cycle data are shown; however, it should be understood that the number of chains is not limiting, and fewer or more chains are contemplated in embodiments.

[0060] The scan input signal (SCAN_IN) of the on-chip comparator circuit 200 of each scan chain is represented by 'S', which can be a high logic level ('1') or a low logic level ('0'). The expected signal (EXPECT) is represented by 'E', which can be a high logic level or a low logic level. When the expected signal (EXPECT) is to be ignored during the cycle, the expected signal (EXPECT) is represented by 'X', which can be a high logic level or a low logic level without affecting the output of the on-chip comparator circuit 200. When the scan input signal (SCAN_IN) is not to be ignored during the cycle, the mask signal (MASK) is at a low logic level ('0'). Conversely, when the scan input signal (SCAN_IN) is to be ignored during the cycle, the mask signal (MASK) is at a high logic level ('1').

[0061] The first row corresponds to the case where the scan input signal (SCAN_IN) is compared with the expected signal (EXPECT) without masking. The third row corresponds to the case where the scan input signal (SCAN_IN) will be masked (i.e., the output of the scan chain is invalid) regardless of whether the expected signal (EXPECT) is '1' or '0'. The second row corresponds to the case where several scan chains are masked (i.e., some scan chains provide undetermined outputs and will not be compared with the expected value). The scan input signal (SCAN_IN) will only be compared with the expected signal (EXPECT) when the mask signal (MASK) is equal to a low logic level. For the second row, the expected signal (EXPECT) can be set to '1' or '0' during the period when the scan input signal (SCAN_IN) will be ignored because the mask signal (MASK) for that period is set to a high logic level ('1').

[0062] Thus, it can be observed that when the scan input signal (SCAN_IN) is to be ignored, the expect signal (EXPECT) becomes redundant because the mask signal (MASK) determines the output of the on-chip comparator circuit 200. Therefore, the capture or load phase can be indicated by encoding the operation of the scan enable signal (SCAN_EN) using a combination of the expect signal (EXPECT) and the mask signal (MASK).

[0063] Table II below indicates the proposed encoding of the scan enable signal (SCAN_EN) within the expect signal (EXPECT) and the mask signal (MASK).

[0064] SCAN_IN EXPECT MASK SSSSSSSS EEEEEEEE 00000000 SSSSSSSS EXEEXEEE 01001000 SSSSSSSS 11111111 11111111 SSSSSSSS 00000000 11111111

[0065] Table II

[0066] The first two rows of Table II are similar to the first two rows of Table I. However, the third row of Table I is split into two different categories in the third and fourth rows of Table II, corresponding to the case where all scan input signals (SCAN_IN) are masked.

[0067] In the third row of Table II, the expected signal (EXPECT) of all scan chains is set to a high logic level '1', and the mask signal (MASK) is set to a high logic level '1'. In the fourth row of Table II, the expected signal (EXPECT) of all scan chains is set to a high logic level '0', and the mask signal (MASK) is set to a high logic level '1'.

[0068] In an embodiment, setting the expectation signal (EXPECT) and the mask signal (MASK) to a high logic level '1' is decoded as the scan enable signal (SCAN_EN) being at a low logic level '0', which indicates a capture phase. In an embodiment, setting the expectation signal (EXPECT) to a low logic level '0' and setting the mask signal (MASK) to a high logic level (1) is decoded as the scan enable signal (SCAN_EN) being at a high logic level '1', which indicates a load phase / unload phase.

[0069] In an embodiment, setting the expectation signal (EXPECT) and the mask signal (MASK) to a high logic level '1' is decoded as the scan enable signal (SCAN_EN) being at a high logic level '1', which indicates the load phase / unload phase. In an embodiment, setting the expectation signal (EXPECT) to a low logic level '0' and setting the mask signal (MASK) to a low logic level '0' is decoded as the scan enable signal (SCAN_EN) being at a high logic level '1', which indicates the capture phase.

[0070] Therefore, by selectively assigning a state to an expect signal (EXPECT) when a mask signal (MASK) is asserted, a capture phase or a load phase / unload phase can be indicated to the scan chain without requiring a separate scan enable (SE) pin.

[0071] Figure 3 A block diagram of an embodiment logic circuit 300 is shown, which can be implemented to decode an expect signal (EXPECT) and a mask signal (MASK) to determine whether the phase corresponds to capture or load / unload. The logic circuit 300 includes a first AND gate 302, a second AND gate 304, and a NAND gate 306, which may or may not be arranged as shown.

[0072] The first AND gate 302 is an N-input AND gate, where N is an integer greater than 1. The value of N corresponds to the number of scan chains tested by the on-chip comparator circuit 200 (i.e., N is equal to the number of scan chains tested minus 1). For example, if the number of scan chains tested by the on-chip comparator circuit 200 is 8, then N is equal to 7. Each input of the N-input AND gate of the first AND gate 302 is coupled to a desired input of a corresponding scan chain. The first AND gate 302 is configured to output a high logic level only in response to a desired value being equal to a high logic level. If any input signal to the first AND gate 302 is a low logic level, the output of the first AND gate 302 is also a low logic level.

[0073] The second AND gate 304 is an N-input AND gate, where N is an integer greater than 1. The value of N corresponds to the number of scan chains tested by the on-chip comparator circuit 200. For example, if the number of scan chains tested by the on-chip comparator circuit 200 is 8, then N is equal to 8. Each input of the N-input AND gate of the second AND gate 304 is coupled to the mask input of the corresponding scan chain. The second AND gate 304 is configured to output a high logic level only in response to all mask values ​​being equal to a high logic level. If any of the input signals of the second AND gate 304 is a low logic level, the output of the second AND gate 304 is a low logic level.

[0074] The outputs of the first AND gate 302 and the second AND gate 304 are respectively coupled to the inputs of a NAND gate 306. In response to (i) all desired values ​​being equal to a high logic level and (ii) all masked values ​​being equal to a high logic level, the output of the NAND gate 306 is a low logic level. Conversely, in response to (i) all desired values ​​being equal to a low logic level and (ii) all masked values ​​being equal to a high logic level, the output of the NAND gate 306 is a high logic level. The output of the NAND gate 306 is provided as, for example, a scan enable signal (SCAN_EN) for the scan chain 100.

[0075] It should be understood that the logic circuit 300 can be implemented using other logic gates. For example, the first AND gate 302 can be implemented using a cascade of two-input AND gates (rather than an N-input AND gate). Therefore, as long as the output of the logic circuit 300 (i) provides a low logic level when the expected signal (EXPECT) and the mask signal (MASK) are at a high logic level on all input pins, and (ii) provides a high logic level when the expected signal (EXPECT) is at a low logic level on all input pins and when the mask signal (MASK) is at a high logic level on all input pins, the arrangement of the logic gates can be changed.

[0076] Figure 4 A block diagram of an embodiment circuit 400 configured to identify a shift phase and a capture phase is shown. In an embodiment, circuit 400 includes a finite state machine (FSM) 402 coupled to a shift counter circuit 404 and a capture counter circuit, which may or may not be arranged as shown. Circuit 400 may include additional components not shown.

[0077] The FSM circuit 402 has two states. In the first state 408, the output of the FSM circuit 402 is a scan enable signal (SCAN_EN) having a high logic level. In the second state 410, the output of the FSM circuit 402 is a scan enable signal (SCAN_EN) having a low logic level. The shift counter circuit 404 and the capture counter circuit 406 use a handshaking feature to control the scan enable signal (SCAN_EN) by counting down from a preloaded counter value and signaling the end of the counter to the FSM circuit 402.

[0078] In an embodiment, the shift counter circuit 404 is preset with the number of shift cycles for each test mode. Conversely, the capture counter circuit 406 is responsible for determining the required capture cycle. The two counter circuits, shift counter circuit 404 and capture counter circuit 406, cooperate through a handshake mechanism to manage the scan enable signal (SCAN_EN). Each time the scan process is initiated, the shift counter circuit 404 and capture counter circuit 406 are preloaded with initial values. Therefore, the counters count these specified preload cycles, which prompts them to output a binary 0 or 1.

[0079] During the load phase / unload phase, the scan enable signal (SCAN_EN) remains at a high logic level while the shift counter circuit 404 counts to the preload number. When the shift counter circuit 404 reaches the preload number, the scan enable signal (SCAN_EN) transitions from a high logic level to a low logic level to begin the capture phase. The capture counter circuit 406 counts to the preload number, and the scan enable signal (SCAN_EN) remains at a low logic level during this period. When the capture counter circuit 406 reaches the preload number, the scan enable signal (SCAN_EN) transitions from a low logic level to a high logic level. The process then repeats in the next load phase / unload phase.

[0080] For example, if the scan chain length is N, the shift counter circuit 404 will maintain the scan enable signal (SCAN_EN) at a high logic level for N cycles during the shift (i.e., load / unload) phase and then switch it to a low logic level. At the same time, the capture counter circuit 406 will ensure that the scan enable signal (SCAN_EN) remains at a low logic level during the capture phase for M cycles and then switches to a high logic level again. When each counter reaches its preset limit, it switches the state of the scan enable signal (SCAN_EN). The test pattern set defines specific numbers M and N, and since these values ​​are known in advance, they can be loaded directly into the counters. The JTAG interface can be used as a pipeline to input these counter values.

[0081] The FSM circuit 402 begins in the shift phase in a first state 408, which causes the shift counter circuit 404 to count down or count up N cycles preloaded into the test pattern in the shift counter circuit 404. When the FSM circuit 402 receives a signal from the shift counter circuit 404 indicating that N cycles have passed, the FSM circuit 402 transitions to a second state 410, which causes the capture counter circuit 406 to count down or count up M cycles for the test pattern preloaded into the capture counter circuit 406. When the FSM circuit 402 receives a signal from the capture counter circuit 406 indicating that M cycles have passed, the FSM circuit 402 transitions back to the first state 408, and the process repeats.

[0082] Figure 5 A block diagram of an embodiment on-chip comparator circuit 500 is shown. Reference is made to the on-chip comparator circuit disclosed in US Patent No. 11,782,092 ("Jain"), the entire contents of which are incorporated herein by reference.

[0083] In an embodiment, Jain discloses an efficient test data communication and processing method to facilitate on-chip testing by combining signals and selectively comparing or masking test data as needed, potentially reducing the pin count required for testing.

[0084] The process involves a digital circuit receiving multiple test data chains (N scan input chains) from off-chip devices and performing tests on them to generate results. A combined signal containing the expected test result and masking instructions is sent to fewer pins on the chip than the number of test chains (X pins). This combined signal is decoded into individual outputs matching each test chain, which are then compared with the actual test result using a comparator or masked as instructed.

[0085] The method is modified to include decompression of scan input chains, serial loading of test registers with data from the chains, storing the test results in the test registers, and compressing the test results into N output chains. Furthermore, provision is made for an X calculation based on the number of test chains, using a single-bit output for comparison results, and storing the comparison results on-chip for output after a set number of comparisons.

[0086] The digital circuitry includes input pins for receiving test data, test registers, decoding logic for combining signals, and on-chip comparators for comparison and masking actions. Additional components include logic for decompressing and compressing test data, memory for storing comparison results, and outputs for relaying these results, which can consist of single bits.

[0087] The on-chip comparator circuit 500 may include a digital circuit 502 or an electronic device. As will be appreciated, it may be advantageous to perform various functional, performance, quality, or stress tests on the digital circuit 502. Testing may be performed using off-chip test equipment 550 (or off-device), such as automatic test equipment (ATE) using, for example, input pins. A first input pin 504 may receive a first scan input chain. As will be appreciated, various embodiments may include more input pins. Additional input pins may receive additional scan input chains from the off-chip test equipment 550. More pins for inputting data may provide more scan input chains, shortening the length of the scan input chains and enabling faster data input.

[0088] Digital circuit 502 may include a clock input 506 for receiving a clock signal. The clock signal may be received from off-chip test equipment 550. The scan input chain received at the input may be in compressed form. Decompression logic may expand the data signal received from the input pin. The number of internal data streams that may be extracted from the data signal received from the off-chip test equipment may depend on the number of pins available for transmitting data.

[0089] Data received via input pins can be provided to test registers on digital circuit 502. For example, first test register 508 can receive a segment of scan input data. Various embodiments may include different numbers of test registers for receiving different numbers of scan input chains. Multiple test registers may be required for each scan input chain because decompression logic may expand each scan input chain. The number of available scan input chains may depend on the number of pins available to receive data from off-chip test equipment (such as ATE).

[0090] The first test register 508 may include flip-flops for storing received data. Different numbers of flip-flops may be used in different embodiments. The number of flip-flops of the test register may depend on the length of the scan input chain.

[0091] Data can be loaded serially into the test registers. In each cycle of a clock signal (e.g., a clock signal received at clock input 506), one bit of data can be loaded into each test register. In an embodiment with multiple test registers, each register can be loaded serially in parallel. For example, in an embodiment with 1000 test registers, each of the 1000 test registers can be loaded with one bit of data in the first cycle. Each time a shift operation is scanned, additional bits can be loaded and shifted. Taking the first test register as an example, the first cycle data can be loaded into the first flip-flop 508A of the first test register 508. In the second cycle, the data can be shifted to the second flip-flop. The data can keep shifting until the Nth flip-flop 508B of the first test register is filled. Additional test registers can also be loaded simultaneously in the same manner.

[0092] After the test data is loaded into the test registers, the data stored in the test registers can be used to perform various tests on the digital circuit 502. For example, the data can be used to test for stuck-at faults in the internal logic circuitry. The data from the test registers can be carried to other parts of the digital circuit 502 using internal logic 503. This can be performed using scan load, unload, and capture operations.

[0093] The test register may include input and output shift modes for serially shifting and outputting data. The test register may also include parallel input and parallel output modes for loading data into or from all flip-flops of the test register in parallel. After being loaded with data from off-chip test equipment (such as ATE), the data from the test register may be output in parallel from the data from the flip-flops to perform the test operation. When the test is complete, the result may be loaded into the test register. The test result data may be loaded into the test register in parallel.

[0094] In an embodiment, digital circuit 502 may include comparator circuit 510. Comparator circuit 510 may be used to compare an expected test result of a test operation with an actual test result. Comparator circuit 510 may communicate with test registers, such as the first test register and any additional test registers, to receive test result data from the test registers after the test result data is loaded into the test registers.

[0095] In various embodiments, the compressor logic can compress the data from the test registers before providing it to the comparator circuit 510. Thus, the comparator circuit 510 can receive the scan output chain. The test registers can operate in a shift mode to serially output the test results to the compression logic and then to the comparator circuit 510.

[0096] Comparator circuit 510 can receive expected test results from off-chip test equipment. There may be situations where it is undesirable to compare one or more data bits. Masked comparisons may be necessary when there is some uncertainty in the captured data for the relevant period or when the data may be invalid for a variety of reasons. A timing anomaly provides one possible example of this situation.

[0097] The data input from off-chip test equipment (such as ATE) for comparison with the test results may include one of three states: high, low, or masked. As will be readily understood, more than one binary pin is required to carry information for the three states of each scan chain.

[0098] Taking the three-scan chain embodiment as an example, each of the three scan chains can include a high or low state depending on the desired result or mask state. The state can be determined by a signal received from an off-chip test device. The signals of the three three-state scan chains cannot be carried on three pins in one cycle. Using two pins (i.e., six pins) for each scan chain consumes pin resources that can be used to load scan input data and speed up test time. By encoding the desired result data with mask data on a shared pin, the number of pins required to carry these three states can be reduced.

[0099] For example, three scan chains with three possible states yield 27 possible combinations for the three scan chains. This data can be transmitted using a combined desired test result and mask instruction signal, using only five pins (instead of six). The decoding logic can then extract the appropriate data or mask signal. Furthermore, the extra pins can be used for other purposes. The more scan chains there are, the more advantageous this approach becomes, as more pins can be freed up for other uses.

[0100] Digital circuit 502 may include input pin 512 and input pin 514. Expected test results may be loaded onto digital circuit 502 from input pin 512. In an embodiment, additional input and mask pins may be used to input combined expected test result and mask instruction signals.

[0101] For example, five pins can be used to receive the combined expected test result and masking instruction signal. The combined expected test result and masking instruction signal can be provided to the decoding logic 516. When the expected test result is not masked, the decoded expected result can be provided to the comparator circuit 510 to be compared with the actual test result. As will be understood, masking can be achieved by using AND / OR gating to convert the received data into a constant value.

[0102] The comparison result can be output at output port 518. Using comparator circuit 510 on digital circuit 502 to perform the comparison of expected results with actual test results can reduce the number of output pins required to output data. This is achieved by using input pins to transmit expected test result data to digital circuit 502 (rather than using output pins to transmit actual results to off-chip test equipment (such as ATE)).

[0103] For example, the results from 20 (or more) scan chains can be output by a single output port instead of 20 (or more) output ports. This swapping takes advantage of the speed advantage of input pins relative to output pins, improving overall test time speed. Using a combined expected test result and mask instruction signal to transmit data on shared pins can free up additional pins instead of having dedicated pins for masking and expected test results.

[0104] Figure 6 A block diagram of an embodiment comparator circuit 600 is shown, which can be implemented as comparator circuit 510. Comparator circuit 600 includes an input 602 for receiving test data results. This can be received directly from a test register. The test data results can be received from compression logic. The number of inputs to comparator circuit 600 for receiving test data results can correspond to the number of scan chains being compared.

[0105] The comparator circuit 600 includes an input 604 for receiving a decoded expected test result. This may originate from the decode logic 516. The comparator circuit 600 may include additional inputs for receiving a decoded expected result and a mask indication for additional comparisons (scan chains).

[0106] The test result received at input 602 and the expected result received at input 604 may be provided to an XOR gate 608. The mask indicator received at input 606 may be provided to an AND gate 610 along with the output of XOR gate 608.

[0107] Comparator circuit 600 can include additional XOR gates for receiving expected test results and actual test results from additional scan chains, and additional AND gates for receiving additional masking inputs. In various embodiments, the results can be aggregated, for example, using OR gate 612. Input 611 can carry the comparison result from the first scan chain. Input 613 can carry the comparison result from the Nth scan chain. If the expected result from any scan chain deviates from the actual test result, this can allow the output of OR gate 612 to be asserted. The output of OR gate 612 can be provided to flip-flop 610A.

[0108] In an embodiment, the output of flip-flop 610A can be fed back to OR gate 612 so that when a deviation is detected, the output can be held until the flip-flop is reset. This allows all results to be tracked through a single flip-flop.

[0109] Figure 7 An example table 700 is shown that maps five binary input states to data having one of three states. A typical three-scan chain design includes three input pins and three output pins (i.e., six pins total) with 27 states (i.e., 3 3 =27). Use Figure 5 and Figure 6 The scan architecture proposed for the circuit in provides an encoding for generating 27 valid states using five pins, because the on-chip decoding logic extracts the correct mask and compares the bits of each scan chain.

[0110] Therefore, use Figure 5 and Figure 6 The three-scan chain design of the circuit in [1] is implemented using three scan input channels and five scan data channels configured as eight input pins. Encoding and decoding are performed in each cycle without cross-cycle interference.

[0111] The scan output values ​​of table 700 may correspond to decode outputs from decode logic 516 configured for a design with three scan chains.

[0112] For example, SO0 of table 700 may correspond to a first decoded output of decoding logic 516 , SO1 of table 700 may correspond to a second decoded output of decoding logic 516 , and SO2 of table 700 may correspond to a third decoded output of decoding logic 516 .

[0113] For ease of explanation, '0' may correspond to a low state of a desired test result, '1' corresponds to a high state, and 'M' corresponds to a masked state. The cells of the scan pins in table 700 may correspond to input pins of a digital circuit.

[0114] For example, RSI0 may correspond to the first data input pin, RSI1 may correspond to the second data input pin, RSI2 may correspond to the third data input pin, RSI3 may correspond to the fourth data input pin, and RSI4 may correspond to the fifth input pin.

[0115] All 27 possible states of the decoded output can correspond to one of the 32 possible states allowed by the five input pins. Various embodiments can use more input pins to provide expected results and masking instructions for more test chains. The number of pins used to encode the combined expected test result and masking instruction signal can be described by the following equation: Input pins = log2(3 S ). Input pins refers to the number of pins used to receive the combined expected test result and mask instruction signal, and S refers to the number of three-state outputs from the decoding logic 516, which can be equal to the number of scan output chains of the test results received from the comparator circuit 600.

[0116] In an embodiment, more than one output pin may be used to carry decoded output data, which may include one of three states. Also, the function ceiling[*] maps a value * to the smallest integer greater than or equal to *.

[0117] For example, when * = 4.7, ceiling[*] equals 5. Therefore, the number of input pins can depend on the number of three-state outputs required. Using the above equation, 16 input pins can be used to receive the combined desired test results and mask instruction signals for 10 scan chains. Since the exemplary three-scan chain design only requires 27 states, the above 32 states (i.e., 2) using five input pins are sufficient. 5 available states) resulting in five unused states.

[0118] exist Figure 5 In the case of a single scan chain, the number of pins on the input side increases from two pins (i.e., SCAN_IN and SCAN_OUT) to three pins. Despite the increase in pin count, a significant improvement in frequency shifting is achieved by relocating all components to the input side of the circuit. This configuration leverages the faster performance of the SCAN_IN process compared to SCAN_OUT, thereby improving the overall efficiency and speed of scan operations.

[0119] The 'scan enable' function in a scan chain design has two different states. The first state, or State 1, is active during the shift phase, which is the interval when the scan data is fully loaded into the system. Conversely, the second state, or State 0, indicates that the 'scan input / output' pins are inactive when not participating in data transfer.

[0120] refer to Figure 7 , it can be clarified that any point from State 0 to State 26 represents the shift window. During this period, the decode logic 516 decodes the 'scan enable' signal to a logic high. This is when data is actively shifted through the scan chain. The sequence then progresses through five states, specifically, from State 27 to State 31, previously designated as unused or idle states in scan operations.

[0121] In an embodiment, the present disclosure proposes reusing one of these idle states (e.g., state 27) as an indicator of the capture window. This adaptation will be decoded by the decoding logic 516, and during this state, the 'scan enable' signal is represented as a logic level low. Adopting this strategy allows the five pins involved in loading the 'scan in' data to be used to extract the 'scan enable' signal at the same time. The main benefit of this configuration is that it successfully eliminates the requirement for a dedicated pin specifically for 'scan enable', simplifying the design and potentially reducing the associated cost.

[0122] More generally, since 2 N The number of states is never a multiple of three ('0' state, '1' state and 'M' state), so the proposed decoding framework necessarily results in a small number of unused states.

[0123] Figure 8 A flow chart of an embodiment method 800 is illustrated. Method 800 can be implemented using, for example, an on-chip comparator circuit 200 coupled to a scan chain 100. Method 800 is implemented without a separate scan enable signal provided externally by the test equipment to the digital circuit under test. In an embodiment, an automatic test pattern generation (ATPG) tool runs tests on the digital circuit.

[0124] At step 802, a capture phase or a load / unload phase is selectively indicated to the scan chain based on encodings in the desired signal and the mask signal. In one embodiment, encoding a high logic level in the desired signal and the mask signal indicates the load / unload phase, while encoding a low logic level in the desired signal and a high logic level in the mask signal indicates the capture phase. In one embodiment, the scan chain is tested over a plurality of cycles determined by a test protocol, with the states of the desired signal and mask signal inputs being variably set during each cycle according to the test protocol.

[0125] At step 804 , a scan out signal is received from the scan chain at a scan input of an on-chip comparator circuit.

[0126] At step 806, the scan-in signal is compared to the expected signal using an XOR gate to generate a comparison result. In an embodiment, a difference is determined when the scan-out signal and the expected signal are different, which is indicated by a high logic level result of the XOR gate.

[0127] At step 808, selected bits of the comparison result are masked using an AND gate with one inverting input based on the mask signal. In an embodiment, when both inputs of the AND gate indicate a mismatch, the difference is passed to an OR gate with one input inverted by the mask signal.

[0128] The difference in the OR gate is accumulated and stored in a flip-flop coupled to the OR gate at step 810. Accumulation includes maintaining a high logic level at the output of the OR gate if any difference was previously stored in the flip-flop.

[0129] At step 812, an error status is read from the flip-flop output to determine the functionality of the digital circuit. In an embodiment, an Internal Joint Test Action Group (IJTAG) interface is used to read the error status from the flip-flop.

[0130] Figure 9 A flow chart of an embodiment method 900 is illustrated. Method 900 can be implemented using, for example, circuit 400 coupled to scan chain 100. Method 900 is implemented without a separate scan enable signal provided externally by the test equipment to the digital circuit under test. The method is repeated for multiple iterations corresponding to different segments of the test pattern. In an embodiment, an automatic test pattern generation (ATPG) tool runs tests on the digital circuit.

[0131] At step 902, a certain number of shift cycles corresponding to a test pattern is preloaded into the shift counter circuit. In an embodiment, the preloaded shift cycles are defined based on a test pattern set and are loaded into the shift counter circuit using a JTAG interface.

[0132] At step 904, a certain number of capture cycles corresponding to the test pattern is preloaded into the capture counter circuit. In an embodiment, the preloaded capture cycles are defined based on a test pattern set and are loaded into the capture counter circuit using a JTAG interface.

[0133] At step 906, the load phase / unload phase is initiated by maintaining the internally generated scan enable signal at a high logic level by the finite state machine circuit, during which the shift counter circuit counts the number of preloaded shift cycles. In one embodiment, the shift counter circuit implements an up-counting or down-counting mechanism depending on the test mode specifics.

[0134] At step 908, after the count by the shift counter circuit, the internally generated scan enable signal is transitioned to a low logic level. This transition corresponds to initiating the capture phase. In one embodiment, the FSM circuit receives an end-of-count signal from the shift counter circuit that transitions the FSM circuit from a first state corresponding to the load / unload phase to a second state corresponding to the capture phase.

[0135] At step 910 , the internally generated scan enable signal is held at a low logic level while the capture counter circuit counts the preloaded capture cycle number. In an embodiment, the capture counter circuit implements an up or down counting mechanism according to the test mode details.

[0136] At step 912, after the count by the capture counter circuit is completed, the internally generated scan enable signal is transitioned to a high logic level to initiate a subsequent load phase / unload phase. In an embodiment, the FSM circuit receives a count end signal from the capture counter circuit, which transitions the FSM circuit from the second state to the first state.

[0137] In an embodiment, each transition of the internally generated scan enable signal corresponds to a switch between two states in the FSM circuit. In an embodiment, the shift counter and capture counter circuits use a handshake feature to signal count completion to the FSM circuit to control the logic level transitions of the internally generated scan enable signal. In an embodiment, steps 902 to 912 are repeated for each test pattern in a series of test patterns designed to verify the functionality of the digital circuit.

[0138] Figure 10 A flow chart of an embodiment method 1000 is illustrated. Method 1000 can be implemented using, for example, an on-chip comparator circuit 500 coupled to a scan chain 100. Method 1000 is implemented without a separate scan enable signal provided externally by the test equipment to the digital circuit under test. In an embodiment, an automatic test pattern generation (ATPG) tool runs tests on the digital circuit.

[0139] At step 1002, a first pin assignment is specified having N input pins and R merged input pins. N and R are integers, N corresponding to the number of input pins used to carry scan input chain test data, and R corresponding to the number of input pins used to carry merged expected test results and mask instruction signals. In an embodiment, R is equal to or greater than log2(3 N ).

[0140] At step 1004, a second pin assignment is specified having N input pins and M output pins. M is an integer and corresponds to the number of output pins used to carry scan output chain test data. In an embodiment, the scan output chain test data is encoded from the M pins and mapped to R pin test data.

[0141] At step 1006, an N by M codec is generated. In an embodiment, pins of a digital circuit are configured in an N by M diagnostic mode to perform testing on the digital circuit.

[0142] The N by M codec is integrated and inserted into scan chains at step 1008. Device registers are spliced ​​into multiple scan chains and coupled between compression circuitry and decompression circuitry.

[0143] In step 1010, using the 2 provided by the R combined input pins R One of the three states decodes the internally generated scan enable signal. N The first state is the decoded output from the decode logic circuit.

[0144] It should be noted that all steps outlined in the flowcharts of methods 800, 900, and 1000 are not necessarily required but may be optional. In addition, changing the arrangement of steps, removing one or more steps and path connections, and adding steps and path connections may similarly be considered.

[0145] A first aspect relates to a method for testing a scan chain without a separate scan enable pin. The method includes selectively indicating a capture phase and a load / unload phase of the scan chain based on encoding of a scan enable signal in a desired signal and a mask signal; loading test parameters into the scan chain during the load / unload phase; operating the scan chain in a functional mode during the capture phase; and generating an error signal based on comparing an output of the scan chain during the unload phase with the desired signal, wherein the mask signal is used to mask the output of the scan chain during cycles with invalid results.

[0146] In a first implementation form of the method according to the first aspect, the scan chain is tested in a plurality of cycles determined by a test protocol, wherein the desired signal and the mask signal are variably set according to the test protocol during each cycle.

[0147] In the second implementation form of the method according to the first aspect or any previous implementation form of the first aspect, the method further comprises generating a scan enable signal internally by an internal logic circuit to operate the scan chain based on the desired signal and the mask signal.

[0148] In a third implementation form of the method according to the first aspect or any previous implementation form of the first aspect, encoding a high logic level in the desired signal and the mask signal indicates a loading phase / unloading phase. Encoding a low logic level in the desired signal and a high logic level in the mask signal indicates a capturing phase.

[0149] In a fourth implementation form of the method according to the first aspect or any previous implementation form of the first aspect, the method further comprises comparing the output of the scan chain during the unloading phase with an expected signal.

[0150] In a fifth implementation form of the method according to the first aspect or any previous implementation form of the first aspect, encoding of the scan enable signal in the desired signal and the mask signal comprises determining logic levels of the desired signal and the mask signal and internally generating the scan enable signal based on the logic levels.

[0151] In a sixth implementation form of the method according to the first aspect or any previous implementation form of the first aspect, the scan chain is coupled to an external test device.The method further comprises providing the test pattern set to the scan chain in the absence of an external scan enable signal.

[0152] A second aspect relates to a method for testing using a scan chain without a separate scan enable pin. The method includes preloading a first number of shift cycles into a shift counter circuit, the first number of shift cycles corresponding to a test pattern set; preloading a second number of capture cycles into a capture counter circuit, the second number of capture cycles corresponding to the test pattern set; initiating a load phase / unload phase of the test by maintaining an internally generated scan enable signal at a high logic level, wherein the shift counter circuit counts the number of preloaded shift cycles; in response to the shift counter circuit completing the preload count, transitioning the internally generated scan enable signal to a logic level, wherein the transition initiates a capture phase of the test; and in response to the capture counter circuit completing the preload count, initiating a subsequent load phase / unload phase of the test by transitioning the internally generated scan enable signal to a high logic level.

[0153] In a first implementation form of the method according to the second aspect, the first number of shift cycles is defined based on a test pattern set and loaded into the shift counter circuit using a JTAG interface.

[0154] In a second implementation form of the method according to the second aspect or any previous implementation form of the second aspect, the second number of capture cycles is defined based on a test pattern set and is loaded into the capture counter circuit using a JTAG interface.

[0155] In a third implementation form of the method according to the second aspect or any previous implementation form of the second aspect, the method further comprises implementing an up or down counting mechanism in the shift counter circuit according to the test mode details.

[0156] In a fourth implementation form of the method according to the second aspect or any previous implementation form of the second aspect, the method further comprises implementing an up or down counting mechanism in the capture counter circuit according to the test mode details.

[0157] In a fifth implementation form of the method according to the second aspect or any previous implementation form of the second aspect, each transition of the internally generated scan enable signal corresponds to a switch between two states in a finite state machine (FSM) circuit.

[0158] In a sixth implementation form of the method according to the second aspect or any previous implementation form of the second aspect, the scan chain is coupled to external test equipment, the method further comprising providing the set of test patterns to the scan chain in the absence of an external scan enable signal.

[0159] A third aspect relates to a method for testing using a scan chain in a digital circuit without an independent scan enable pin. The method includes specifying a first pin assignment having N input pins and R merged input pins, N and R being integers, N corresponding to the number of input pins for carrying scan input chain test data, and R corresponding to the number of input pins for carrying merged expected test results and mask instruction signals; specifying a second pin assignment having N input pins and M output pins, M being an integer and corresponding to the number of output pins for carrying scan output chain test data; inserting a comparator circuit and a decoding logic circuit into the digital circuit; generating an N by M codec; integrating the N by M codec and inserting the scan chain, wherein the device registers are spliced ​​into multiple scan chains and coupled between a compression circuit and a decompression circuit; and using 2 provided by the R merged input pins. R One of the three states decodes the internally generated scan enable signal. N The first state is the decoded output from the decode logic circuit.

[0160] In a first implementation form of the method according to the third aspect, the method further comprises configuring the pins of the digital circuit to an N times M diagnostic mode to perform testing on the digital circuit.

[0161] In the second implementation form of the method according to the third aspect or any previous implementation form of the third aspect, an automatic test pattern generation (ATPG) tool runs the tests on the digital circuit.

[0162] In a third implementation form of the method according to the third aspect or any previous implementation form of the third aspect, the method further comprises encoding scan output chain test data from the M pins and mapping the encoding into R pin test data.

[0163] In a fourth implementation form of the method according to the third aspect or any previous implementation form of the third aspect, R is equal to or greater than log2(3 N ).

[0164] In a fifth implementation form of the method according to the third aspect or any previous implementation form of the third aspect, the scan chain is coupled to external test equipment, the method further comprising providing the set of test patterns to the scan chain in the absence of an external scan enable signal.

[0165] Although the description has been described in detail, it should be understood that various changes, substitutions and modifications may be made without departing from the spirit and scope of the present disclosure as defined by the appended claims. In the various figures, the same elements are represented by the same reference numerals. In addition, the scope of the present disclosure is not intended to be limited to the specific embodiments described herein, as those of ordinary skill in the art will readily appreciate from this disclosure that currently existing or later developed processes, machines, manufactures, material compositions, means, methods or steps may perform substantially the same functions or achieve substantially the same results as the corresponding embodiments described herein. Therefore, the appended claims are intended to include these processes, machines, manufactures, material compositions, means, methods or steps within their scope.

[0166] Accordingly, the specification and drawings should be regarded as a brief description of the disclosure as defined by the appended claims and should cover any and all modifications, variations, combinations or equivalents that fall within the scope of the disclosure.

Claims

1. A method for testing using a scan chain without an independent scan enable pin, the method comprising: selectively indicating a capture phase and a load phase / unload phase for the scan chain based on encoding of a scan enable signal in the desired signal and the mask signal; loading test parameters into the scan chain during the loading phase / unloading phase; operating the scan chain in a functional mode during the capture phase; as well as An error signal is generated based on comparing an output of the scan chain during an unload phase with the expected signal, wherein the mask signal is used to mask the output of the scan chain during cycles with invalid results. 2 . The method of claim 1 , wherein the scan chain is tested over a plurality of cycles determined by a test protocol, wherein the desired signal and the mask signal are variably set according to the test protocol during each cycle.

3. The method according to claim 1, further comprising: A scan enable signal is internally generated by an internal logic circuit to operate the scan chain based on the desired signal and the mask signal.

4. The method of claim 1 , wherein encoding a high logic level in the desired signal and the mask signal indicates the load phase / unload phase, and wherein encoding a low logic level in the desired signal and the high logic level in the mask signal indicates the capture phase.

5. The method according to claim 1, further comprising: The output of the scan chain during the unload phase is compared to the expected signal.

6. The method of claim 1 , wherein encoding the scan enable signal in the desired signal and the mask signal comprises: A logic level of the desired signal and a logic level of the mask signal are determined, and the scan enable signal is internally generated based on the logic level of the desired signal and the logic level of the mask signal.

7. The method of claim 1 , wherein the scan chain is coupled to external test equipment, the method further comprising: A set of test patterns is provided to the scan chain in the absence of an external scan enable signal.

8. A method for testing using a scan chain without independent scan enable pins, the method comprising: preloading a first number of shift cycles into a shift counter circuit, the first number of shift cycles corresponding to a set of test patterns; preloading a second number of capture cycles into a capture counter circuit, the second number of capture cycles corresponding to the set of test patterns; initiating a load phase / unload phase of the test by holding an internally generated scan enable signal at a high logic level, wherein the shift counter circuit counts the preloaded number of shift cycles; in response to completion of the preload count by the shift counter circuit, transitioning the internally generated scan enable signal to a logic level, wherein the transition initiates a capture phase of the test; as well as In response to completion of the preload count by the capture counter circuit, a subsequent load phase / unload phase of the test is initiated by transitioning the internally generated scan enable signal to the high logic level.

9. The method of claim 8, wherein the first number of shift cycles is defined based on the test pattern set and loaded into the shift counter circuit using a JTAG interface.

10. The method of claim 8, wherein the second number of capture cycles is defined based on the test pattern set and is loaded into the capture counter circuit using a JTAG interface.

11. The method according to claim 8, further comprising: An up or down counting mechanism is implemented in the shift counter circuit according to the test mode details.

12. The method according to claim 8, further comprising: An up or down counting mechanism is implemented in the capture counter circuit according to the test mode details.

13. The method of claim 8, wherein each transition of the internally generated scan enable signal corresponds to a switch between two states in a finite state machine (FSM) circuit.

14. The method of claim 8, wherein the scan chain is coupled to external test equipment, the method further comprising: The set of test patterns is provided to the scan chain in the absence of an external scan enable signal.

15. A method for testing a digital circuit using a scan chain without an independent scan enable pin, the method comprising: specifying a first pin assignment having N input pins and R merged input pins, N and R being integers, N corresponding to the number of input pins for carrying scan input chain test data, and R corresponding to the number of input pins for carrying merged expected test result and mask instruction signals; specifying a second pin assignment having N input pins and M output pins, where M is an integer and corresponds to the number of output pins used to carry scan output chain test data; inserting a comparator circuit and a decoding logic circuit into the digital circuit; Generate N by M codec; integrating the N by M codec and inserting into scan chains, wherein device registers are spliced ​​into multiple scan chains and coupled between compression circuitry and decompression circuitry; as well as Using the 2 combined input pins provided by the R R One of the three states decodes the internally generated scan enable signal. N The first state is the decoded output from the decode logic circuit.

16. The method according to claim 15, further comprising: Pins of the digital circuit are configured in an N by M diagnostic mode to perform a test on the digital circuit.

17. The method of claim 15, wherein an automatic test pattern generation (ATPG) tool runs the test on the digital circuit.

18. The method according to claim 15, further comprising: Scan output chain test data from M pins is encoded and mapped into R pin test data.

19. The method of claim 15, wherein R is equal to or greater than log2(3 N ).

20. The method of claim 15, wherein the scan chain is coupled to external test equipment, the method further comprising: A set of test patterns is provided to the scan chain in the absence of an external scan enable signal.

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