Method, apparatus, device and medium for very high frequency omnidirectional beacon signal processing

Abstract

The invention relates to the technical field of signal processing, and discloses a very high frequency omnidirectional beacon signal processing method, device, equipment and medium, and the method comprises the steps: carrying out the separation based on an obtained very high frequency omnidirectional beacon signal, and obtaining a variable phase signal and a reference phase signal; interpolating the variable phase signal, and performing zero-crossing detection based on the interpolated variable phase signal to obtain first zero-crossing information; performing zero-crossing detection on the reference phase signal to obtain second zero-crossing information; and determining a phase difference based on the first zero-crossing information and the second zero-crossing information, and obtaining a very high frequency omnidirectional beacon azimuth based on the phase difference. Through signal separation, interpolation and zero crossing point time difference measurement, the solution of the VOR azimuth angle is realized, the realization algorithm is simple, and the algorithm flexibility is high; the azimuth angle resolution can reach 0.1 degree through interpolation processing, the direction finding precision is high, the zero-cross detection can avoid the influence of amplitude fluctuation, the zero-cross detection only depends on phase information, the anti-noise capability is high, and the reliability is high.

Description

Technical Field

[0001] The present invention relates to the field of signal processing technology, and in particular to a method, device, equipment and medium for very high frequency omnidirectional beacon signal processing. Background Art

[0002] In recent years, civil aviation technology has made significant progress, and civil air transport has become one of the world's primary and important means of transportation. Along with this development, the safety of civil aviation transport has always been a matter of great importance to the International Civil Aviation Organization (ICAO) and the civil aviation departments of various countries. The Very High Frequency Omnidirectional Radio Range (VOR) is a short-range regional radio navigation system operating in the very high frequency band. The VOR azimuth refers to the angle between the aircraft and the VOR beacon, measured clockwise from the magnetic north direction of the aircraft's location.

[0003] In the related art, an analog method is used to measure the VOR azimuth angle, which has the problem of low angle measurement accuracy. Summary of the Invention

[0004] In view of this, the present invention provides a method, apparatus, device and medium for very high frequency omnidirectional range (VOR) signal processing to solve the problem of low angle measurement accuracy when measuring VOR azimuth angle using an analog method.

[0005] In a first aspect, the present invention provides a method for very high frequency omnidirectional beacon signal processing, the method comprising: separating a variable phase signal and a reference phase signal based on an acquired very high frequency omnidirectional beacon signal; interpolating the variable phase signal, and performing zero-crossing detection based on the interpolated variable phase signal to obtain first zero-crossing information; performing zero-crossing detection on the reference phase signal to obtain second zero-crossing information; determining a phase difference based on the first zero-crossing information and the second zero-crossing information, and obtaining the very high frequency omnidirectional beacon azimuth based on the phase difference.

[0006] In an optional embodiment, the separation of the variable phase signal and the reference phase signal based on the acquired very high frequency omnidirectional beacon signal includes: converting the very high frequency omnidirectional beacon signal into a demodulated intermediate frequency signal, mixing, multi-stage filtering and extraction on the demodulated intermediate frequency signal to obtain a first signal; performing cascaded integrator comb filtering and extraction on the first signal to obtain the variable phase signal; and performing bandpass filtering and frequency modulation demodulation on the first signal to obtain the reference phase signal.

[0007] In an optional embodiment, the zero-crossing detection includes: based on a counter and multiple shift registers, obtaining the jump points of positive and negative changes in the signal for performing the zero-crossing detection, and characterizing the zero-crossing information based on the timestamps corresponding to the jump points; wherein the shift register is used to store adjacent amplitude values ​​of the signal for performing the zero-crossing detection.

[0008] In an optional embodiment, the shift register is configured to include a first shift register, a second shift register, a third shift register, a fourth shift register, a fifth shift register and a sixth shift register, and the zero-crossing detection further includes: if the values ​​of the first shift register, the second shift register and the third shift register are less than or equal to zero, and the values ​​of the fourth shift register, the fifth shift register and the sixth shift register are greater than or equal to zero, characterizing the zero-crossing information based on the timestamp corresponding to the counter.

[0009] In an optional embodiment, converting the very high frequency omnidirectional beacon signal into a demodulatable intermediate frequency signal includes: performing high-frequency amplification and down-conversion processing on the very high frequency omnidirectional beacon signal to generate a preset frequency signal; and performing analog-to-digital conversion on the preset frequency signal to obtain the demodulatable intermediate frequency signal.

[0010] In an optional embodiment, the mixing, multi-stage filtering and extraction of the demodulated intermediate frequency signal to obtain the first signal includes: mixing the demodulated intermediate frequency signal with a preset signal to obtain a mixed signal, wherein the demodulated intermediate frequency signal has the same sampling rate as the preset signal; performing first-stage filtering and first-stage extraction on the mixed signal, wherein the filtering parameters of the first-stage filtering match the extraction multiple of the first-stage extraction; performing second-stage filtering and second-stage extraction on the signal obtained by the first-stage filtering and first-stage extraction to obtain the first signal.

[0011] In an optional embodiment, the FM demodulation includes: creating a first FM demodulation shift register and a second FM demodulation register, storing the first signal at the first moment after the band-pass filtering based on the first FM demodulation register, and storing the first signal at the second moment after the corresponding band-pass filtering based on the second FM demodulation register, wherein the second moment is the moment before the first moment; calculating the difference between the first FM demodulation shift register and the second FM demodulation register in each clock cycle, and right-shifting the first FM demodulation shift register and the second FM demodulation shift register; filtering the difference based on a Hilbert filter to obtain a first component of a complex envelope signal and a second component of a complex envelope signal; calculating an envelope signal based on the first component of the complex envelope signal and the second component of the complex envelope signal, and characterizing the reference phase signal based on the envelope signal.

[0012] In a second aspect, the present invention provides a device for processing very high frequency omnidirectional beacon signals, the device comprising: a separation module for separating a variable phase signal and a reference phase signal based on an acquired very high frequency omnidirectional beacon signal; a first detection module for interpolating the variable phase signal, and performing zero-crossing detection based on the interpolated variable phase signal to obtain first zero-crossing information; a second detection module for performing zero-crossing detection on the reference phase signal to obtain second zero-crossing information; and a generation module for determining a phase difference based on the first zero-crossing information and the second zero-crossing information, and obtaining the very high frequency omnidirectional beacon azimuth based on the phase difference.

[0013] In a third aspect, the present invention provides a computer device comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the method for very high frequency omnidirectional beacon signal processing of the above-mentioned first aspect or any corresponding embodiment thereof by executing the computer instructions.

[0014] In a fourth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the method for VOR signal processing of the first aspect or any corresponding embodiment thereof.

[0015] In a fifth aspect, the present invention provides a computer program product comprising computer instructions for causing a computer to execute the method for VOR signal processing according to the first aspect or any corresponding embodiment thereof.

[0016] The VOR azimuth angle is calculated through signal separation, interpolation and zero-crossing time difference measurement, with a simple algorithm and high flexibility. Interpolation processing enables the azimuth angle resolution to reach 0.1 degrees, with high direction-finding accuracy. Zero-crossing detection can avoid the influence of amplitude fluctuations and relies only on phase information, with strong anti-noise capability and high reliability. In addition, signal separation, interpolation and zero-crossing detection can be achieved through a field programmable gate array, and the calculation is completed in a single cycle with a fast response speed. The VOR azimuth angle value can be quickly output, which can meet the low complexity and real-time requirements of aviation navigation. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in related technologies, the following briefly introduces the drawings required for use in the specific embodiments or related technical descriptions. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1 A schematic diagram showing the VOR azimuth angles;

[0019] Figure 2 A schematic flow chart showing a method for processing a VOR signal according to an embodiment of the present invention is shown;

[0020] Figure 3 A schematic flow chart showing a method for processing a VOR signal according to an embodiment of the present invention is shown;

[0021] Figure 4 Shown is a schematic diagram of the process flow of FPGA processing;

[0022] Figure 5 shows a schematic waveform diagram of a reference phase signal and a variable phase signal;

[0023] Figure 6 A schematic structural diagram of a device for VOR signal processing provided by an embodiment of the present invention is shown;

[0024] Figure 7 Schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0025] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative efforts shall fall within the scope of protection of the present invention.

[0026] Approach and landing are complex phases of civil aircraft flight. Approximately 41.5% of all accidents occur during approach and landing. This data clearly demonstrates the prominence and importance of flight safety during approach and landing. The Very High Frequency Omnidirectional Range (VOR), an aviation radio navigation system, was established to ensure safe flight during approach and landing for civil aircraft. A VOR consists of a receiver and antenna.

[0027] The signal radiated into space by a VOR beacon is a complex frequency-amplitude modulated (FM-AM) wave signal. It includes a reference phase signal used for azimuth and other measurements, a variable phase signal, and a signal used for VOR beacon identification and communication. The variable phase signal always lags behind the reference phase signal. When a VOR receiver receives the "full VOR signal"—a composite of the reference and variable phase signals—it processes and detects the reference and variable phase signals, separates them, compares their phases, and calculates the VOR azimuth by taking the difference, θ, and adding 180°.

[0028] Figure 1 A schematic diagram showing the VOR azimuth is shown in FIG. Figure 1 As shown, VOR 102 radiates signals into space. During the approach of aircraft 101, the VOR receiver receives the "full VOR signal" composed of the reference phase signal and the variable phase signal, processes and detects it, and separates it into the reference signal (REF) and the variable phase signal (VAR). Figure 1 The red line waveform represents REF, and the blue line waveform represents VAR. Figure 1 α is used to represent the VOR azimuth, 0°<α<360°.

[0029] According to an embodiment of the present invention, a method embodiment for very high frequency omnidirectional beacon signal processing is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0030] In this embodiment, a method for processing a very high frequency omnidirectional range (VOR) signal is provided, which can be used in a VOR receiver or other device capable of receiving a VOR signal. Figure 2 FIG. 1 is a flow chart showing a method for processing a VOR signal according to an embodiment of the present invention, as shown in FIG. Figure 2 As shown, the process includes the following steps:

[0031] Step S201 : Separate the acquired VOR signal to obtain a variable phase signal and a reference phase signal.

[0032] In this step, the VOR signal includes a variable phase signal and a reference phase signal. The reference phase signal is a signal obtained by frequency modulating a 30Hz signal to a 9960Hz subcarrier. The frequency modulation index is 16 and the frequency deviation is ±480Hz. The frequency modulated subcarrier then modulates the carrier amplitude. The reference phase signal U R The signal waveform of (t) is as follows:

[0033] U R (t) = U Rm ×[1+m×cos(Ω s t+m p cos(Ωt))]×cos(ωt)

[0034] Among them, U Rm It is used to characterize the reference signal amplitude, ω is used to characterize the carrier angular frequency, m is used to characterize the amplitude modulation, Ω is used to characterize the 30Hz angular frequency, s Used to characterize the 9960Hz subcarrier angular frequency, m p Used to characterize the frequency modulation index.

[0035] The variable phase signal is obtained by taking out a part of the power from the high frequency transmitter of the reference phase signal, removing the amplitude modulation part, performing power amplification, and outputting a pure carrier without modulation. The carrier of the variable phase signal is of the same frequency and phase as the carrier of the reference phase signal. Then it is added to the goniometer, which decomposes the carrier into 30Hz sine and cosine modulated sideband waves. The resulting variable phase signal U V The signal waveform of (t) is as follows:

[0036] U V (t) = U Vm ×[sinθ×cosΩt+cosθ×sinΩt]×cosωt

[0037] =U Vm ×cos(Ωt-θ)×cosωt

[0038] Where U Vm It is used to represent the amplitude of the variable phase signal, and θ is used to represent the azimuth, with magnetic north being 0°.

[0039] In step S201, the acquired VOR signal is the aforementioned reference signal U R (t) and variable phase signal U V (t), so the spatial radiation field is equal to the reference signal U R (t) and variable phase signal U V (t), that is,

[0040] U ∑(t) =U V (t)+U R (t)

[0041] =U Rm ×[1+m A ×cos(Ωt-θ)+m×cos(Ω s t+m p cos(Ωt))]

[0042] ×cos(ωt)

[0043] Where U ∑(t) Used to characterize the acquired VOR signal,

[0044] The VOR signal receiving circuit includes a radio frequency receiving front end, digital down-conversion and amplitude demodulation, audio signal demodulation, and azimuth signal demodulation. The acquired VOR signal is amplified and down-converted to a 21.4MHz intermediate frequency signal. The 21.4MHz intermediate frequency signal is sampled by analog-to-digital conversion and down-converted by bandpass filtering to a digital intermediate frequency signal. The digital intermediate frequency signal is then digitally down-converted to a digital signal with a carrier frequency of 100kHz. The digital signal is then subjected to orthogonal amplitude demodulation to demodulate the VOR baseband signal. The VOR baseband signal U VOR It can be expressed by the following formula:

[0045] U VOR =U Rm ×[1+m A ×cos(Ωt-θ)+m×cos(Ω s t+m p cos(Ωt))]

[0046] The VOR baseband signal uses bandpass filters corresponding to the frequency range according to different frequency ranges, which can realize the separation of each frequency signal and complete the demodulation of the reference phase signal and the variable phase signal.

[0047] In this step, a bandpass filter bank can be used to separate the reference phase signal and the variable phase signal. Alternatively, quadrature demodulation can be used to extract the reference phase using a phase-locked loop, which is then mixed with the original signal to separate the variable phase component.

[0048] Step S202 : interpolate the variable phase signal, and perform zero-crossing detection based on the interpolated variable phase signal to obtain first zero-crossing information.

[0049] In this step, the variable phase signal is interpolated to increase the sampling rate, thereby improving the VOR azimuth resolution. The azimuth resolution can be calculated using the following formula:

[0050]

[0051] Specifically, if the sampling rate of the interpolated variable phase signal is 100 kHz, the azimuth angle resolution of the 30 Hz variable phase signal is 360 / (100000 / 30)=0.108 degrees.

[0052] Zero-crossing detection involves detecting the zero point when the signal waveform undergoes transitions from the positive half-cycle to the negative half-cycle, or vice versa, passing through zero. For the interpolated variable-phase signal, the zero-crossing point from negative to positive can be detected. A comparator and clock timer can be used to record the moment of zero-crossing, generating a timestamp representing the zero-crossing point of the interpolated variable-phase signal. Based on the first zero-crossing information, a timestamp representing the zero-crossing point of the interpolated variable-phase signal is generated.

[0053] Step S203: Perform zero-crossing detection on the reference phase signal to obtain second zero-crossing information.

[0054] Similarly, in this step, the reference phase signal obtained by separation is subjected to zero-crossing detection to obtain a timestamp representing the reference phase signal passing through zero.

[0055] Step S204: determining a phase difference based on a time difference between the first zero-crossing information and the second zero-crossing information, and obtaining a VOR azimuth angle based on the phase difference.

[0056] In this step, the time difference is obtained by subtracting the timestamp represented by the first zero-crossing information from the timestamp represented by the second zero-crossing information. The VOR azimuth α is calculated as follows:

[0057]

[0058] Among them, Δt is used to represent the time difference obtained by subtracting the timestamp represented by the first zero-crossing information from the timestamp represented by the second zero-crossing information; the signal sampling rate can be the sampling rate of the interpolated variable phase signal or the sampling rate of the reference phase signal; the signal frequency can be the frequency of the reference phase signal or the frequency of the interpolated variable phase signal.

[0059] The method for processing very high frequency omnidirectional range (VOR) signals provided in this embodiment achieves VOR azimuth angle calculation through signal separation, interpolation, and zero-crossing time difference measurement. The algorithm is simple and highly flexible. Interpolation processing enables an azimuth angle resolution of 0.1 degrees, resulting in high direction-finding accuracy. Zero-crossing detection avoids the influence of amplitude fluctuations, relies solely on phase information, and has strong noise immunity and high reliability. Furthermore, signal separation, interpolation, and zero-crossing detection can be implemented through a field programmable gate array (FPGA). Operations are completed in a single cycle, resulting in a fast response speed and the ability to quickly output VOR azimuth angle values, meeting the low complexity and real-time requirements of aviation navigation.

[0060] This embodiment also provides a method for processing a very high frequency omnidirectional range (VOR) signal, which can be used in a VOR receiver or other device capable of receiving a VOR. Figure 3 FIG. 1 is a flow chart showing a method for processing a VOR signal according to an embodiment of the present invention, as shown in FIG. Figure 3 As shown, the process includes the following steps:

[0061] Step S301 : Separate the acquired VOR signal to obtain a variable phase signal and a reference phase signal.

[0062] Specifically, the above step S301 includes:

[0063] Step S3011: convert the VOR signal into a demodulatable intermediate frequency signal, perform mixing, multi-stage filtering and extraction on the demodulatable intermediate frequency signal to obtain a first signal.

[0064] In this step, the VOR signal is down-converted to a demodulatable 21.4 MHz intermediate frequency signal through mixing. After mixing, multi-stage anti-aliasing filtering, and decimation, a first signal is output. The first signal includes a 30 Hz variable phase signal and a 30 Hz reference phase signal modulated by 9960 Hz. The sampling rate of the first signal is the first sampling rate.

[0065] Step S3012: Perform cascaded integrator comb filtering and decimation based on the first signal to obtain a variable phase signal.

[0066] In this step, a cascade integrator comb (CIC) filter with a preset decimation factor can be used to filter the first signal having the first sampling rate to obtain a variable phase signal. The sampling rate of the decimated variable phase signal is the value obtained by dividing the first sampling rate by the preset decimation factor.

[0067] Specifically, the CIC filter used may be configured to have 5 stages and 20-fold decimation. Thus, the sampling rate of the variable phase signal after decimation is a value obtained by dividing the first sampling rate by 20.

[0068] Step S3013: Perform bandpass filtering and FM demodulation based on the first signal to obtain a reference phase signal.

[0069] In this step, a bandpass filter can be used to separate the 9960 Hz signal. The bandpass filter can be a 31-order Finite Impulse Response (FIR) bandpass filter. The 9960 Hz signal is then frequency modulated and demodulated to obtain a reference phase signal.

[0070] Step S302: interpolate the variable phase signal, and perform zero-crossing detection based on the interpolated variable phase signal to obtain first zero-crossing information. Figure 2 Step S202 of the illustrated embodiment will not be described in detail here.

[0071] Step S303: Perform zero-crossing detection on the reference phase signal to obtain second zero-crossing information. Figure 2 Step S203 of the illustrated embodiment will not be described in detail here.

[0072] Step S304: Determine the phase difference based on the first zero-crossing information and the second zero-crossing information, and obtain the VOR azimuth based on the phase difference. Figure 2 Step S204 of the illustrated embodiment will not be described in detail here.

[0073] In this way, CIC filtering can reduce the amount of calculation, multi-stage extraction can reduce the requirements for ADC sampling rate, and improve hardware efficiency; based on the first signal, the variable phase signal and the reference phase signal are separated through independent path processing, which can avoid cross-modulation errors.

[0074] In some optional embodiments, zero-crossing detection includes: obtaining the jump points of positive and negative changes of the signal for zero-crossing detection based on a counter and multiple shift registers, and characterizing the zero-crossing information based on the timestamps corresponding to the jump points; wherein the shift register is used to store adjacent amplitude values ​​of the signal for zero-crossing detection.

[0075] In this embodiment, a 32-bit counter can be created, and the value of the counter increases by one for each clock cycle. For example, when the output value of the 30Hz variable phase signal is valid, the value of the counter increases by 1, or when the output value of the 30Hz reference phase signal is valid, the value of the counter increases by 1. The sampling rate of the 30Hz variable phase signal is 100KHz, that is, the repetition period is 10 microseconds, so the time it takes for the 32-bit counter to cycle once is approximately 11.9 hours, which can meet the system requirements. The shift register is used to store adjacent amplitude values ​​of the signal for zero-crossing detection, and the shift register shifts one bit to the right for each clock cycle. The number of shift registers is an even number, so multi-cycle amplitude comparison can be performed.

[0076] The zero-crossing point is the transition point of the signal from negative to positive. When a sign bit transition is detected, for example, when the signal amplitude changes from negative to positive, the counter records the current clock cycle number as a timestamp.

[0077] In this way, transient noise interference can be suppressed by comparing the amplitudes of multiple cycles.

[0078] In some optional embodiments, the shift register is configured to include a first shift register, a second shift register, a third shift register, a fourth shift register, a fifth shift register and a sixth shift register, and the zero-crossing detection further includes: if the values ​​of the first shift register, the second shift register and the third shift register are less than or equal to zero, and the values ​​of the fourth shift register, the fifth shift register and the sixth shift register are greater than or equal to zero, the zero-crossing information is represented based on the timestamp corresponding to the counter.

[0079] In this embodiment, zero-crossing detection can be implemented in an FPGA through a shift register. The first shift register is characterized based on REG1, the second shift register is characterized based on REG2, the third shift register is characterized based on REG3, the fourth shift register is characterized based on REG4, the fifth shift register is characterized based on REG5, and the sixth shift register is characterized based on REG6. REG1 to REG6 are used to store adjacent amplitude values ​​of the 30Hz signal in sequence, and the shift register shifts one position to the right for each clock cycle. When the values ​​of REG1, REG2 and REG3 are less than or equal to 0, and the values ​​of REG4, REG5 and REG6 are greater than or equal to 0, the value of the counter counter is written to the FIFO for caching. That is, at this moment, the 30Hz variable phase signal or the reference phase signal is passing through zero.

[0080] In this way, the anti-interference capability of the zero-crossing detection scheme can be further enhanced, and the false triggering of a single sampling point can be effectively suppressed.

[0081] In some optional embodiments, converting a very high frequency omnidirectional beacon signal into a demodulatable intermediate frequency signal includes: performing high-frequency amplification and down-conversion processing on the very high frequency omnidirectional beacon signal to generate a preset frequency signal; and performing analog-to-digital conversion on the preset frequency signal to obtain a demodulatable intermediate frequency signal.

[0082] In this embodiment, the VOR signal operates in a frequency range of 108.1 to 118 MHz. After amplification, mixing, and filtering by the RF module, the VOR signal is converted into an intermediate frequency (IF) signal with a center frequency of 21.4 MHz, i.e., a preset frequency signal. The 21.4 MHz IF signal is sampled by an analog-to-digital converter (ADC) chip with a sampling rate of 65 MHz. The 21.4 MHz @ 65 Msps IF signal is then mixed, filtered, and decimated by the FPGA signal processing module. The VOR azimuth is calculated and output.

[0083] By downconverting the 108.1-118 MHz high-frequency signal to a 21.4 MHz intermediate frequency (IF), the complexity of subsequent ADC sampling and digital processing is significantly reduced. The 65 MHz sampling rate meets the Nyquist criterion for 21.4 MHz signals while leaving ample processing margin for the FPGA. Furthermore, the fixed IF architecture adapts to all VOR frequencies, improving system compatibility. Furthermore, the FPGA directly processes the 65 Msps digital IF signal, implementing parallel computations for mixing, filtering, and decimation through a pipeline. This results in low azimuth output latency, meeting the real-time requirements of aviation navigation.

[0084] In some optional embodiments, mixing, multi-stage filtering and extraction are performed on the demodulated intermediate frequency signal to obtain the first signal, which includes: mixing the demodulated intermediate frequency signal with a preset signal to obtain a mixed signal, wherein the sampling rate of the demodulated intermediate frequency signal is the same as that of the preset signal; performing first-stage filtering and first-stage extraction on the mixed signal, wherein the filtering parameters of the first-stage filtering match the extraction multiple of the first-stage extraction; performing second-stage filtering and second-stage extraction on the signal obtained by the first-stage filtering and the first-stage extraction to obtain the first signal.

[0085] In this embodiment, the preset signal is used to represent a single-frequency signal with a sampling rate of 65 MHz and a center frequency of 21.4 MHz, generated by direct digital synthesis (DDS) in an FPGA. The preset signal is mixed with a demodulated 21.4 MHz intermediate frequency signal.

[0086] The mixed signal is subjected to the first-stage filtering and the first-stage decimation. A 31-order FIR filter can be used to complete the filtering of the mixed signal. The filter parameter design matches the decimation multiple, which can be set to 65 times. In this way, the sampling rate of the signal after the first-stage filtering and decimation is 1MHz.

[0087] For the signal with a sampling rate of 1MHz after the first stage filtering and decimation, the second stage filtering and decimation can be performed. A 31-order FIR filter can be used to complete the filtering of the signal. After filtering, 10 times decimation can be performed. The sampling rate of the signal after decimation is 100KHz, which is the first sampling rate of the aforementioned first signal.

[0088] This approach achieves efficient spectrum shifting and downsampling through digital mixing that matches the sampling rate and a two-stage cascaded filtering and decimation design. The first-stage filtering parameters strictly match the decimation factor to avoid spectral aliasing, while the second-stage further refines the processing to reduce the overall computational effort. Furthermore, multi-stage decimation reduces data volume, significantly reducing FPGA hardware resource usage.

[0089] In some optional embodiments, FM demodulation includes: creating a first FM demodulation shift register and a second FM demodulation register, storing the first signal at the first moment after bandpass filtering based on the first FM demodulation register, and storing the first signal at the second moment after bandpass filtering based on the second FM demodulation register, wherein the second moment is the moment before the first moment; in each clock cycle, calculating the difference between the first FM demodulation shift register and the second FM demodulation shift register, right-shifting the first FM demodulation shift register and the second FM demodulation shift register; filtering the difference based on a Hilbert filter to obtain a first component of a complex envelope signal and a second component of a complex envelope signal; calculating an envelope signal based on the first component of the complex envelope signal and the second component of the complex envelope signal, and characterizing a reference phase signal based on the envelope signal.

[0090] In this embodiment, the first FM demodulation shift register can be characterized based on d1, and the second FM demodulation register can be characterized based on d2. d1 and d2 are used to store FM (Frequency Modulation) signals, d1 stores the FM signal at the current moment, and d2 stores the FM signal at the previous moment. Specifically, in each clock cycle, d1 and d2 are right-shifted at the same time, the value of d1 is shifted to d2, the new value is shifted to d1, and the value of d1 is subtracted from the value of d2 to obtain the difference between d1 and d2. The first component of the complex envelope signal is characterized based on di, and the second component of the complex envelope signal is characterized based on dq. Envelope signal = (di^2+dq^2)^0.5. The obtained envelope signal is the reference 30Hz signal.

[0091] In this way, a double shift register structure is adopted to realize the integration operation with single cycle delay through clock-driven difference and right shift operations, thereby optimizing the hardware implementation.

[0092] In some optional embodiments, after converting the VHF omnidirectional beacon signal into a demodulated intermediate frequency signal, Figure 4 A schematic diagram of the FPGA processing flow is shown in FIG. Figure 4 As shown, the following processing is performed based on FPGA:

[0093] Step S401: Generate a preset signal through DDS, mix the demodulated intermediate frequency signal with the preset signal to obtain a mixed signal with a sampling rate of 65 MHz;

[0094] Step S402, performing first-stage filtering and 65-fold decimation on the mixed signal;

[0095] Step S403, performing a second-stage filtering and 10-fold decimation on the signal obtained in step S402 to obtain a first signal with a sampling rate of 100 kHz, and then proceeding to steps S404 and S407;

[0096] Step S404 , filtering the first signal with a sampling rate of 100 kHz using a CIC filter with a decimation of 20 to obtain a variable phase signal with a sampling rate of 5 kHz;

[0097] Step S405, performing 20 times interpolation on the 5 kHz variable phase signal to obtain a variable phase signal with a sampling rate of 100 kHz;

[0098] Step S406: Based on the counter and the six shift registers, perform zero-crossing detection on the variable phase signal with a sampling rate of 100 kHz to obtain six zero-crossing points of the variable phase signal and the count values ​​of the zero-crossing points, and then proceed to step S410;

[0099] Step S407, using a bandpass filter to separate the 9960 Hz signal from the first signal with a sampling rate of 100 kHz;

[0100] Step S408, demodulating the signal obtained in step S407 using a non-coherent demodulation algorithm;

[0101] Step S409: Perform zero-crossing detection on the signal obtained in step S408 based on the counter and the six shift registers to obtain six zero-crossing points of the reference phase signal and the count value of the zero-crossing points, and then proceed to step S410;

[0102] Step S410 , calculating the VOR azimuth based on the six zero-crossing points and the count value of the zero-crossing points of the variable phase signal and the count value of the zero-crossing points of the reference phase signal.

[0103] Figure 5 FIG. 1 shows a waveform diagram of a reference phase signal and a variable phase signal. Figure 5 As shown, Figure 5 In the figure, the blue waveform represents the 30Hz reference signal waveform, and the red waveform represents the 30Hz variable signal waveform. A1 is the coordinate origin, and A1, A2, A3, A4, A5, and A6 represent the six zero-crossing points of the reference signal. B1, B2, B3, B4, B5, and B6 represent the six zero-crossing points of the variable signal waveform.

[0104] Since the above signals are all 30MHz signals, the calculation of the VOR azimuth angle can be converted into calculating the phase difference between the signals at points A1 and B1, or calculating the phase difference between the signals at points A2 and B2, or calculating the phase difference between the signals at points A3 and B3, or calculating the phase difference between the signals at points A4 and B4, or calculating the phase difference between the signals at points A5 and B5, or calculating the phase difference between the signals at points A6 and B6.

[0105] Specifically, the VOR azimuth angle can be calculated based on the difference in count values ​​corresponding to the zero-crossing points. For example, the phase difference between the signals at points A3 and B3 is expressed as PB3-PA3, and the phase difference between the signals at points A5 and B5 is expressed as PB5-PA5. The frequency of the above waveform is 30Hz and the sampling rate is 100KHz. Therefore, the VOR azimuth angle is calculated as follows:

[0106] VOR azimuth = 2π / (100000 / 30)*(PB3-PA3)

[0107] Among them, 100000 is the sampling rate of 10 kHz, and 30 is the frequency of the reference phase signal or the variable phase signal.

[0108] The method for VOR processing provided by the embodiment of the present invention achieves a simple algorithm, high reliability, and high algorithm flexibility; the system has a fast response speed and can quickly output the VOR azimuth value of the signal; the direction finding resolution can reach 0.1 degrees, and the direction finding accuracy can reach ±0.5 degrees.

[0109] This embodiment also provides a device for VOR signal processing, which is used to implement the above-mentioned embodiments and preferred implementations. Details already described will not be repeated here. As used below, the term "module" may refer to a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, implementation using hardware, or a combination of software and hardware, is also possible and contemplated.

[0110] This embodiment provides a device for processing VHF omnidirectional beacon signals. Figure 6FIG. 1 shows a schematic diagram of a structure of a device for VOR signal processing provided by an embodiment of the present invention, as shown in FIG. Figure 6 Shown, including:

[0111] The separation module 601 is configured to separate the acquired VOR signal into a variable phase signal and a reference phase signal.

[0112] The first detection module 602 is configured to interpolate the variable phase signal, and perform zero-crossing detection based on the interpolated variable phase signal to obtain first zero-crossing information.

[0113] The second detection module 603 is configured to perform zero-crossing detection on the reference phase signal to obtain second zero-crossing information.

[0114] The generating module 604 is configured to determine a phase difference based on the first zero-crossing information and the second zero-crossing information, and obtain a VOR azimuth angle based on the phase difference.

[0115] In some optional embodiments, the separation module 601 includes:

[0116] The first separation unit is used to convert the VOR signal into a demodulated intermediate frequency signal, and perform mixing, multi-stage filtering and extraction on the demodulated intermediate frequency signal to obtain a first signal.

[0117] The second separation unit is used to perform cascaded integrator comb filtering and extraction based on the first signal to obtain a variable phase signal.

[0118] The third separation unit is configured to perform bandpass filtering and frequency modulation demodulation based on the first signal to obtain a reference phase signal.

[0119] In some optional implementations, the second detection module 603 includes:

[0120] The first unit of the second detection module is used to obtain the jump points of positive and negative changes of the signal for zero-crossing detection based on a counter and multiple shift registers, and characterize the zero-crossing information based on the timestamps corresponding to the jump points; wherein the shift register is used to store adjacent amplitude values ​​of the signal for zero-crossing detection.

[0121] In some optional implementations, the second detection module 603 further includes:

[0122] The second unit of the second detection module is used to configure the shift register to include a first shift register, a second shift register, a third shift register, a fourth shift register, a fifth shift register and a sixth shift register. If the values ​​of the first shift register, the second shift register and the third shift register are less than or equal to zero, and the values ​​of the fourth shift register, the fifth shift register and the sixth shift register are greater than or equal to zero, the zero-crossing information is represented based on the timestamp corresponding to the counter.

[0123] In some optional embodiments, the first separation unit includes:

[0124] The first separation first subunit is used to perform high-frequency amplification and down-conversion processing on the VHF omnidirectional beacon signal to generate a preset frequency signal; and perform analog-to-digital conversion on the preset frequency signal to obtain a demodulated intermediate frequency signal.

[0125] In some optional embodiments, the first separation unit further comprises:

[0126] The first separation second sub-unit is used to mix the demodulated intermediate frequency signal with the preset signal to obtain a mixed signal, wherein the demodulated intermediate frequency signal has the same sampling rate as the preset signal; perform first-stage filtering and first-stage extraction on the mixed signal, wherein the filtering parameters of the first-stage filtering match the extraction multiple of the first-stage extraction; perform second-stage filtering and second-stage extraction on the signal obtained by the first-stage filtering and the first-stage extraction to obtain the first signal.

[0127] In some optional embodiments, the third separation unit includes:

[0128] The third separation first sub-unit is used to create a first FM demodulation shift register and a second FM demodulation register, store the first signal at the first moment after band-pass filtering based on the first FM demodulation register, and store the first signal at the second moment after band-pass filtering based on the second FM demodulation register, wherein the second moment is the moment before the first moment; calculate the difference between the first FM demodulation shift register and the second FM demodulation shift register in each clock cycle, right-shift the first FM demodulation shift register and the second FM demodulation shift register; filter the difference based on the Hilbert filter to obtain a first component of the complex envelope signal and a second component of the complex envelope signal; calculate the envelope signal based on the first component of the complex envelope signal and the second component of the complex envelope signal, and characterize the reference phase signal based on the envelope signal.

[0129] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0130] The device for VOR signal processing in this embodiment is presented in the form of a functional unit, where the unit refers to an application-specific integrated circuit (ASIC) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0131] The embodiment of the present invention also provides a computer device having the above Figure 6 The apparatus shown is used for VOR signal processing.

[0132] See also Figure 7 , Figure 7 is a structural diagram of a computer device provided by an optional embodiment of the present invention, such as Figure 7 As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components utilize different buses to communicate with each other and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in or on the memory to display the graphical information of a graphical user interface on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Equally, multiple computer devices can be connected, and each device provides part of the necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 7 A processor 10 is taken as an example.

[0133] The processor 10 may be a central processing unit, a network processor, or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic, or any combination thereof.

[0134] The aforementioned memory 20 stores instructions that can be executed by at least one processor 10, so that the aforementioned at least one processor 10 executes the method shown in the above embodiment.

[0135] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and application programs required for at least one function; the data storage area may store data created based on the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0136] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0137] The computer device further includes an input device 30 and an output device 40. The processor 10, the memory 20, the input device 30 and the output device 40 may be connected via a bus or other means. Figure 7 The bus connection is taken as an example.

[0138] The input device 30 can receive input digital or character information and generate key signal input related to user settings and function control of the computer device, such as a touch screen, a keypad, a mouse, a trackpad, a touch pad, an indicator stick, one or more mouse buttons, a trackball, a joystick, etc. The output device 40 can include a display device, an auxiliary lighting device (such as a light emitting diode) and a tactile feedback device (such as a vibration motor). The above-mentioned display device includes but is not limited to a liquid crystal display, a light emitting diode, a display and a plasma display. In some optional embodiments, the display device can be a touch screen.

[0139] The embodiment of the present invention also provides a computer-readable storage medium. The above-mentioned method according to the embodiment of the present invention can be implemented in hardware, firmware, or implemented as a computer code that can be recorded in a storage medium, or implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and downloaded through a network and will be stored in a local storage medium, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state drive, etc.; further, the storage medium can also include a combination of the above-mentioned types of memory. It can be understood that a computer, a processor, a microprocessor controller or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor or hardware, the method shown in the above embodiment is implemented.

[0140] A portion of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the form in which the computer program instruction exists in a computer-readable medium includes, but is not limited to, a source file, an executable file, an installation package file, etc. Accordingly, the way in which the computer program instruction is executed by the computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium may be any available computer-readable storage medium or communication medium that can be accessed by the computer.

[0141] Although the embodiments of the present invention have been described with reference to the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention. Such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A method for very high frequency omnidirectional beacon signal processing, characterized in that The method comprises: Based on the acquired VHF omnidirectional beacon signal, a variable phase signal and a reference phase signal are separated; interpolating the variable phase signal, and performing zero-crossing detection based on the interpolated variable phase signal to obtain first zero-crossing information; Performing the zero-crossing detection on the reference phase signal to obtain second zero-crossing information; A phase difference is determined based on the first zero-crossing information and the second zero-crossing information, and a very high frequency omnidirectional range beacon azimuth is obtained based on the phase difference.

2. The method according to claim 1, characterized in that The step of separating the variable phase signal and the reference phase signal based on the acquired VOR beacon signal includes: Converting the VHF omnidirectional beacon signal into a demodulated intermediate frequency signal, and performing mixing, multi-stage filtering, and decimation on the demodulated intermediate frequency signal to obtain a first signal; Performing cascaded integrator comb filtering and decimation on the first signal to obtain the variable phase signal; Bandpass filtering and frequency modulation demodulation are performed on the first signal to obtain the reference phase signal.

3. The method according to claim 1 or 2, characterized in that The zero-crossing detection includes: Based on a counter and a plurality of shift registers, a transition point of a positive or negative change of a signal for performing the zero-crossing detection is obtained, and zero-crossing information is represented based on a timestamp corresponding to the transition point; The shift register is used to store adjacent amplitude values ​​of the signal for performing the zero-crossing detection.

4. The method according to claim 3, characterized in that The shift register is configured to include a first shift register, a second shift register, a third shift register, a fourth shift register, a fifth shift register, and a sixth shift register, and the zero-crossing detection further includes: If the values ​​of the first shift register, the second shift register and the third shift register are less than or equal to zero, and the values ​​of the fourth shift register, the fifth shift register and the sixth shift register are greater than or equal to zero, the zero-crossing information is represented based on the timestamp corresponding to the counter.

5. The method according to claim 2, characterized in that The converting of the VHF omnidirectional beacon signal into a demodulated intermediate frequency signal comprises: Performing high-frequency amplification and down-conversion processing on the VHF omnidirectional beacon signal to generate a preset frequency signal; The preset frequency signal is analog-to-digital converted to obtain the demodulated intermediate frequency signal.

6. The method according to claim 2, characterized in that The step of mixing, multi-stage filtering, and decimating the demodulated intermediate frequency signal to obtain the first signal includes: Mixing the demodulated intermediate frequency signal with a preset signal to obtain a mixed signal, wherein the demodulated intermediate frequency signal and the preset signal have the same sampling rate; performing first-stage filtering and first-stage decimation on the mixed signal, wherein filtering parameters of the first-stage filtering match a decimation multiple of the first-stage decimation; The signal obtained by the first-stage filtering and the first-stage extraction is subjected to the second-stage filtering and the second-stage extraction to obtain the first signal.

7. The method according to claim 2, characterized in that The FM demodulation comprises: Creating a first FM demodulation shift register and a second FM demodulation register, storing the first signal at a first moment after the bandpass filtering based on the first FM demodulation register, and storing the first signal at a second moment after the bandpass filtering based on the second FM demodulation register, wherein the second moment is a moment before the first moment; In each clock cycle, calculating the difference between the first FM demodulation shift register and the second FM demodulation shift register, and right-shifting the first FM demodulation shift register and the second FM demodulation shift register; Filtering the difference based on a Hilbert filter to obtain a first component of a complex envelope signal and a second component of a complex envelope signal; An envelope signal is calculated based on the first component of the complex envelope signal and the second component of the complex envelope signal, and the reference phase signal is characterized based on the envelope signal.

8. A device for very high frequency omnidirectional beacon signal processing, characterized in that The device comprises: A separation module is used to separate the variable phase signal and the reference phase signal based on the acquired very high frequency omnidirectional beacon signal; A first detection module is configured to interpolate the variable phase signal and perform zero-crossing detection based on the interpolated variable phase signal to obtain first zero-crossing information; A second detection module is configured to perform the zero-crossing detection on the reference phase signal to obtain second zero-crossing information; A generating module is configured to determine a phase difference based on the first zero-crossing information and the second zero-crossing information, and obtain a very high frequency omnidirectional range beacon azimuth based on the phase difference.

9. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the method for VOR signal processing according to any one of claims 1 to 7 by executing the computer instructions.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the method for VOR signal processing according to any one of claims 1 to 7.

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