Processor test method, device, medium and program product

Abstract

The invention provides a processor testing method and device, a medium and a program product, and can be applied to the technical field of computers. The processor test method comprises the following steps: in response to a test instruction for a processor, generating a plurality of load states for simulating the load fluctuation of the processor; for each load state, inputting the acquired performance data of the processor and the load state into a parameter configuration model, and outputting a test parameter adaptive to the load state; according to the task processing type of the test parameter, distributing a test case constructed based on the test parameter to a matched logic partition in a processor for execution; and determining a test result of the processor in the load state by analyzing test data generated in the execution process.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a processor testing method, device, medium and program product. Background Art

[0002] As core components of electronic devices, comprehensive and accurate performance testing of processors is crucial during R&D, production, and application. Related technologies typically use fixed test cases to evaluate processor performance, conducting standardized tests using pre-set configuration parameters.

[0003] The related technologies have at least the following problems: relying on fixed test cases makes it difficult to adapt to the complex and changeable load fluctuation scenarios of the processor during actual operation, resulting in low test efficiency and low accuracy of test results. Summary of the Invention

[0004] In view of the above problems, the present invention provides a processor testing method, apparatus, device, medium and program product.

[0005] According to a first aspect of the present invention, a processor testing method is provided, comprising: in response to a test instruction for a processor, generating a plurality of load states for simulating load fluctuations of the above-mentioned processor; for each of the above-mentioned load states, configuring a model with the acquired performance data of the above-mentioned processor and the above-mentioned load state input parameters, and outputting test parameters adapted to the above-mentioned load state; distributing test cases constructed based on the above-mentioned test parameters to matching logical partitions in the above-mentioned processor for execution according to the task processing type of the above-mentioned test parameters; and determining the test results of the above-mentioned processor under the above-mentioned load state by analyzing the test data generated during the execution process.

[0006] The second aspect of the present invention provides a processor testing device, comprising: a state generation module for generating, in response to a test instruction for the processor, a plurality of load states for simulating the load fluctuations of the above-mentioned processor; a parameter output module for inputting the acquired performance data of the above-mentioned processor and the above-mentioned load state into a parameter configuration model for each of the above-mentioned load states, and outputting test parameters adapted to the above-mentioned load state; a use case distribution module for distributing the test cases constructed based on the above-mentioned test parameters to the matching logical partitions in the above-mentioned processor for execution according to the task processing type of the above-mentioned test parameters; and a result determination module for determining the test results of the above-mentioned processor under the above-mentioned load state by analyzing the test data generated during the execution process.

[0007] A third aspect of the present invention provides an electronic device, comprising: one or more processors; a memory for storing one or more computer programs, wherein the one or more processors execute the one or more computer programs to implement the steps of the above method.

[0008] The fourth aspect of the present invention further provides a computer-readable storage medium having a computer program or instructions stored thereon, which implements the steps of the above method when the computer program or instructions are executed by a processor.

[0009] The fifth aspect of the present invention further provides a computer program product, comprising a computer program or instructions, which implement the steps of the above method when executed by a processor.

[0010] According to an embodiment of the present invention, by simulating multiple load states of the processor in actual operation, and inputting the performance data and load state into the parameter configuration model, the test parameters adapted to the load state are output, thereby improving the adaptation accuracy of the test parameters and the load state. Based on the task processing type of the test parameters, the constructed test cases are distributed to the corresponding logical partitions in the processor for execution, which effectively enhances the targeted nature of the test. During the execution process, the generated test data is analyzed to evaluate the performance of the processor under different load states, thereby obtaining targeted test results. By simulating load fluctuations, the authenticity and coverage of the test scenarios are effectively improved. At the same time, the directional execution mechanism of the logical partitions is realized using test parameters adapted to the load state, further improving the efficiency of the test and the accuracy of the results. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above contents and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings.

[0012] Figure 1 An application scenario diagram of a processor testing method, apparatus, device, medium, and program product according to an embodiment of the present invention is shown.

[0013] Figure 2 A flowchart of a processor testing method according to an embodiment of the present invention is shown.

[0014] Figure 3 A schematic diagram showing test case distribution of a processor testing method according to an embodiment of the present invention is shown.

[0015] Figure 4 A flowchart of a processor test method according to an embodiment of the present invention is shown.

[0016] Figure 5 A schematic diagram of module interaction of a processor testing method according to an embodiment of the present invention is shown.

[0017] Figure 6 A structural block diagram of a processor testing device according to an embodiment of the present invention is shown.

[0018] Figure 7 A block diagram of an electronic device suitable for implementing a processor testing method according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0019] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present invention. In the following detailed description, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of embodiments of the present invention. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of the concept of the present invention.

[0020] The terms used herein are only for describing specific embodiments and are not intended to limit the present invention. The terms "comprise", "include", etc. used herein indicate the presence of the features, steps, operations and / or components, but do not exclude the presence or addition of one or more other features, steps, operations or components.

[0021] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0022] When expressions such as "at least one of A, B, and C, etc." are used, they should generally be interpreted in accordance with the meaning commonly understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).

[0023] In the technical solution of the present invention, the data involved (including but not limited to data used for analysis, stored data, displayed data, etc.) are all information and data authorized by the user or fully authorized by all parties, and the collection, storage, use, processing, transmission, provision, disclosure and application of the relevant data comply with relevant laws, regulations and standards, take necessary confidentiality measures, do not violate public order and good morals, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0024] An embodiment of the present invention provides a processor testing method, comprising: generating multiple load states for simulating processor load fluctuations in response to a test instruction for a processor; configuring a model with acquired processor performance data and load state input parameters for each load state, and outputting test parameters adapted to the load state; distributing test cases constructed based on the test parameters to matching logical partitions in the processor for execution according to the task processing type of the test parameters; and determining the test results of the processor under the load state by analyzing the test data generated during the execution process.

[0025] Figure 1 An application scenario diagram of a processor testing method, apparatus, device, medium, and program product according to an embodiment of the present invention is shown.

[0026] like Figure 1 As shown, the application scenario 100 according to this embodiment may include a first terminal device 101, a second terminal device 102, a third terminal device 103, and a server 105. A network 104 is used as a medium for providing a communication link between the first terminal device 101, the second terminal device 102, the third terminal device 103, and the server 105. The network 104 may include various connection types, such as wired or wireless communication links or optical fiber cables.

[0027] A user may use a first terminal device 101, a second terminal device 102, or a third terminal device 103 to interact with a server 105 via a network 104 to receive or send messages, etc. Various communication client applications may be installed on the first terminal device 101, the second terminal device 102, or the third terminal device 103, such as web browser applications, search applications, instant messaging tools, email clients, social platform software, etc. (for example only).

[0028] The first terminal device 101 , the second terminal device 102 , and the third terminal device 103 may be various electronic devices having display screens and supporting web browsing, including but not limited to smart phones, tablet computers, laptop computers, desktop computers, and the like.

[0029] The server 105 may be a server that provides various services, such as a background management server (for example only) that supports websites browsed by users using the first terminal device 101, the second terminal device 102, and the third terminal device 103. The background management server may analyze and process received data such as user requests, and feed back processing results (e.g., web pages, information, or data obtained or generated based on user requests) to the terminal devices.

[0030] It should be noted that the processor testing method provided in the embodiment of the present invention can generally be executed by the server 105. Accordingly, the processor testing device provided in the embodiment of the present invention can generally be set in the server 105. The processor testing method provided in the embodiment of the present invention can also be executed by a server or server cluster that is different from the server 105 and can communicate with the first terminal device 101, the second terminal device 102, the third terminal device 103 and / or the server 105. Accordingly, the processor testing device provided in the embodiment of the present invention can also be set in a server or server cluster that is different from the server 105 and can communicate with the first terminal device 101, the second terminal device 102, the third terminal device 103 and / or the server 105.

[0031] It should be understood that Figure 1 The number of the first terminal device, the second terminal device, the third terminal device, the network and the server is only . According to the implementation needs, there can be any number of the first terminal device, the second terminal device, the third terminal device, the network and the server.

[0032] The following will be based on Figure 1 The scene described by Figures 2 to 5 The processor testing method according to the embodiment of the present invention is described in detail.

[0033] Figure 2 A flowchart of a processor testing method according to an embodiment of the present invention is shown.

[0034] like Figure 2 As shown, this embodiment includes operations S210 to S240.

[0035] In operation S210 , a plurality of load states for simulating processor load fluctuations are generated in response to a test instruction for the processor.

[0036] In operation S220 , for each load state, the acquired performance data of the processor and the load state are input into a parameter configuration model, and a test parameter adapted to the load state is output.

[0037] In operation S230 , the test cases constructed based on the test parameters are distributed to matching logical partitions in the processor for execution according to the task processing type of the test parameters.

[0038] In operation S240 , a test result of the processor under the load state is determined by analyzing the test data generated during the execution process.

[0039] According to embodiments of the present invention, processors, as core components of electronic devices, have a significant impact on the overall system's operating efficiency and stability. Graphics Processing Units (GPUs) play a key role in parallel computing and graphics rendering. Comprehensive and accurate performance testing is crucial for processor R&D, production, and application. Simulating load fluctuations in real-world operating environments is crucial for evaluating a processor's overall capabilities.

[0040] After receiving test instructions for the processor, it generates multiple load states with different characteristics. These load states cover various scenarios that the processor may encounter in actual operation, including idle state, intermediate state, peak state, and load mutation, accurately simulating the load changes of the processor under different working intensities.

[0041] For each load state generated, the performance data of the processor under this load state is collected in real time. For the graph processor, the performance data includes key indicators such as core utilization, memory bandwidth, texture fill rate, and power consumption. Subsequently, these performance data are input into the pre-trained parameter configuration model together with the corresponding load state parameters. This parameter configuration model is based on a machine learning algorithm. By learning from a large amount of historical test data, it can automatically output test parameters that are highly adapted to the load state based on the current load characteristics and performance, such as test duration, data throughput, number of concurrent tasks, etc., to ensure that the test parameters can fully stimulate the performance of the processor under a specific load.

[0042] After obtaining the appropriate test parameters, the tasks are classified according to the corresponding task processing type. The processor is pre-divided into different logical partitions, each dedicated to processing tasks of a specific task processing type. For example, a graph processor has logical partitions for processing compute tasks and storage tasks. By matching task processing types with logical partition functions, constructed test cases are accurately distributed to the corresponding logical partitions for execution, ensuring efficient and targeted testing.

[0043] During test case execution, various test data are continuously collected, including task response time, resource utilization, and error rates. After the test is completed, this test data is deeply analyzed and mined using data analysis tools to compare the processor's performance under different load conditions, evaluate its stability, efficiency, and reliability in various load scenarios, and ultimately determine the comprehensive test results of the processor under load.

[0044] By simulating multiple load states of the processor in actual operation, inputting the performance data and load states into the parameter configuration model, and outputting test parameters that adapt to the load states, the adaptation accuracy of the test parameters and load states is improved. Based on the task processing type of the test parameters, the constructed test cases are distributed to the corresponding logical partitions in the processor for execution, which effectively enhances the targeted nature of the test. During the execution process, the generated test data is analyzed to evaluate the performance of the processor under different load states, and thus obtain targeted test results. By simulating load fluctuations, the authenticity and coverage of the test scenarios are effectively improved. At the same time, the use of test parameters that adapt to the load state to implement a directional execution mechanism for logical partitions further improves the efficiency of the test and the accuracy of the results.

[0045] According to an embodiment of the present invention, multiple load states include an idle state, an intermediate state, and a peak state; generating multiple load states for simulating processor load fluctuations includes: configuring initialization load parameters according to the hardware specifications of the processor; using a load generation model, under the constraints of the initialization load parameters, generating a load state sequence for simulating state switching between the idle state, the intermediate state, and the peak state to simulate the load fluctuation of the processor; wherein, in the process of testing the processor, the test is performed sequentially according to the order of change of the load state in the load state sequence.

[0046] Before testing a processor, you need to obtain its hardware specifications. This information includes, but is not limited to, key parameters such as the number of cores, frequency range, cache size, video memory capacity, and maximum power consumption limit. Based on these hardware specifications, we automatically configure initial load parameters. These parameters cover basic load intensity, load change step size, state switching interval, and other parameters. This ensures that the initial parameters match the processor's hardware capabilities, providing a reasonable constraint range for subsequent load generation.

[0047] For example, by reading the rated power consumption of the graph processor, we calculated the target load power and set a power cap using the hardware management interface. Furthermore, we used a timer to precisely control the test duration and initialized the environment before testing, including terminating irrelevant background processes and locking the graph processor frequency to its highest performance mode, to ensure test stability and accuracy.

[0048] Based on the configured initialization load parameters, the preset load generation model is called. This load generation model combines the hardware characteristics of the processor and the load variation patterns that may occur in actual application scenarios. Under the constraints of the initialization load parameters, it generates a load state sequence that includes idle state, intermediate state, and peak state. During the generation process, the load generation model will reasonably set the duration of each load state, the switching threshold between load states, and the transition method, so that the load state sequence can truly simulate the dynamic change process of the processor from low load to high load, and from stable operation to sudden peak in actual operation. For example, from the idle state with almost no tasks running, gradually transition to the intermediate state of medium-intensity computing, and then suddenly switch to the peak state of full-load operation, and then fall back to the intermediate state, forming a complete load fluctuation cycle.

[0049] Furthermore, when generating load state sequences, the load generation model can also reference processor work logs to simulate load states in different scenarios, such as cloud computing and artificial intelligence computing, generating load state sequences that are closer to real-world applications. For example, in cloud computing scenarios, the model simulates load fluctuations when multiple users perform concurrent tasks. In artificial intelligence computing scenarios, the model simulates large-scale matrix operations during model training and input-output-intensive loads during data preprocessing.

[0050] This load state sequence generation method based on actual application data makes performance test results more valuable, helping developers more accurately evaluate the processor's actual performance in target application scenarios. Furthermore, this scenario-based testing method can also expose potential performance bottlenecks in specific processor operating modes, providing data support for subsequent architectural optimization.

[0051] When testing a processor, the test process is executed in the order in which each load state changes within the generated load state sequence. When the load state sequence indicates entering a specific load state, the intensity and type of the test task are immediately adjusted to keep the processor at the load level corresponding to that load state, and performance data is stably collected while that load state persists. When the load state sequence indicates a load state switch, the test task is smoothly transitioned to ensure that the load changes conform to the sequence's prescribed rhythm. The processor's response during the state switch is also recorded, fully capturing the processor's performance under different load fluctuation scenarios.

[0052] By configuring the initial load parameters according to the processor hardware specifications, and then using the load generation model to generate a load state sequence that simulates the switching between idle state, intermediate state, and peak state under the constraints of the initial load parameters, we can accurately match the hardware characteristics, reproduce the actual load state switching scenario, improve the pertinence and authenticity of the load simulation, and provide reliable scenario support for comprehensive testing of processor performance.

[0053] According to an embodiment of the present invention, there are multiple test cases; according to the task processing type of the test parameters, the test cases constructed based on the test parameters are distributed to the matching logical partitions in the processor for execution, including: sending multiple test cases to the task scheduler to distribute each test case to the matching logical partition in the processor for execution according to the preset mapping relationship between the task processing type and the logical partition stored in the task scheduler, and the task processing type includes a computing type and a storage type.

[0054] After building multiple test cases, they are sent to the task scheduler. The task scheduler stores a complete set of pre-set mapping relationships, which clearly define the correspondence between different task processing types and the various logical partitions within the processor. Task processing types are primarily categorized into compute and storage. Compute covers tasks requiring extensive processing, while storage encompasses storage-related tasks such as data reading and writing, and cache operations.

[0055] Upon receiving a test case, the task scheduler first analyzes each test case's task processing type to determine whether it belongs to the compute or storage type. It then uses pre-defined mappings to find the logical partition that matches the task processing type. For example, a compute task is assigned to a logical partition dedicated to computational processing, while a storage task is assigned to a logical partition focused on data storage and access.

[0056] After matching, the task scheduler accurately distributes each test case to the corresponding logical partition, ensuring that each test case executes in the appropriate area of ​​the processor for its type. This precise, type-based distribution mechanism not only fully utilizes the specialized processing capabilities of different logical partitions, but also avoids resource waste caused by chaotic task allocation, thereby improving the efficiency and accuracy of the entire testing process.

[0057] Figure 3 A schematic diagram showing test case distribution of a processor testing method according to an embodiment of the present invention is shown.

[0058] like Figure 3 As shown, the task scheduler first parses the received test cases, identifies the task processing type, and determines whether it is a computational task (such as matrix multiplication and ray tracing) or a storage task (such as memory bandwidth testing and data persistence). Then, based on the preset mapping relationship, the task scheduler assigns computational tasks to dedicated partition 1 and storage tasks to partition 2 for execution.

[0059] The entire scheduling process uses a lightweight task processing type identification mechanism and a logical partition matching mechanism to ensure that tasks are quickly located in the appropriate processing area. Each partition focuses on processing tasks of the corresponding type based on its own hardware optimization characteristics.

[0060] By specifically matching task processing types with logical partitions, resource contention between different types of tasks is effectively reduced, enabling efficient utilization of both computing and storage resources, thereby improving overall task processing efficiency. Furthermore, the partitioned, focused processing mode reduces the system overhead associated with switching between different types of tasks and eliminates redundant operations in resource scheduling. Furthermore, targeted task allocation aligns hardware resource characteristics with task requirements, further optimizing system performance and stability.

[0061] According to an embodiment of the present invention, when the test case is used to test the performance of mixed-precision matrix multiplication, the method also includes: calling the mixed-precision calculation kernel module according to the dynamic matrix scale parameter in the test parameters to generate a test case; wherein the mixed-precision calculation kernel module realizes the generation of the test case through the following configuration: according to the rule of alternating execution of half-precision calculation and single-precision calculation, constructing a parallel matrix multiplication kernel so that the processor executes the parallel matrix multiplication kernel, and during the execution process, adaptively adjusting the thread grid dimension of the parallel matrix multiplication kernel to match the dynamic matrix scale parameter.

[0062] When testing mixed-precision matrix multiplication performance, the test case reads the dynamic matrix scale parameter included in the test parameters. The dynamic matrix scale parameter determines the dimension range and change rules of the matrix under test. Based on the dynamic matrix scale parameter, the pre-built mixed-precision computation kernel module is called, which is responsible for generating the corresponding test case.

[0063] The core configuration of the mixed-precision kernel module revolves around the construction and dynamic adjustment of parallel matrix multiplication kernels. The module first implements parallel computing logic within the underlying architecture, following the principle of alternating half-precision and single-precision computations. Specifically, the mixed-precision kernel module alternates between half-precision (e.g., FP16) and single-precision (e.g., FP32) for different computational stages or sub-matrix blocks during matrix multiplication. This leverages the efficiency of half-precision computation to improve processing speed while ensuring accuracy in critical areas through single-precision computation.

[0064] After generating a parallel matrix multiplication kernel, the mixed-precision computing kernel module monitors changes in the dynamic matrix scale parameter in real time. When the dynamic matrix scale parameter indicates that the matrix scale is expanding or shrinking, the mixed-precision computing kernel module adaptively adjusts the kernel's thread grid dimensions. Specifically, by changing the number of thread blocks, the number of threads contained in each thread block, and the collaboration method between threads, the parallel processing capability of the thread grid is matched to the current matrix scale. For example, when the dynamic matrix scale parameter indicates an increase in matrix dimension, the number of thread blocks is appropriately increased to improve parallelism; when the dynamic matrix scale parameter indicates a decrease in matrix dimension, thread allocation is optimized to reduce idle resources. With this configuration, the mixed-precision computing kernel module can generate test cases that adapt to the dynamic matrix scale parameter and accurately test the processor's performance in mixed-precision matrix multiplication scenarios.

[0065] According to an embodiment of the present invention, when the test case is used to test the video memory pressure, the method also includes: calling the video memory load module according to the video memory access parameters in the test parameters to generate the test case; wherein the video memory load module realizes the generation of the test case through the following configuration: allocating a non-aligned video memory buffer corresponding to the video memory access parameters, and constructing a multi-threaded cyclic read and write operation sequence so that the processor concurrently accesses the non-aligned video memory buffer according to the multi-threaded cyclic read and write operation sequence.

[0066] When a test case is used to test video memory stress, the test parameters are parsed for memory access parameters, including key metrics such as target memory occupancy, data transfer bandwidth, access frequency, and read / write ratio. Based on these memory access parameters, the memory load module is called, which generates corresponding test cases to simulate memory access scenarios of varying intensities and patterns.

[0067] The core configuration of the memory load module focuses on allocating unaligned memory buffers and constructing multi-threaded access sequences. The memory load module first allocates unaligned memory buffers in the video memory based on the memory size and distribution characteristics specified in the memory access parameters. The starting address and size of these unaligned memory buffers do not match the natural alignment boundaries of the video memory, simulating the irregular memory allocation patterns found in real applications and increasing the processing pressure on the memory controller.

[0068] After allocating the unaligned memory buffer, the memory load module constructs a multi-threaded cyclic read and write operation sequence. Based on the set number of threads and concurrency, each thread is assigned a specific memory access range and operation type (read or write), and the access logic for cyclic execution is designed. When the processor executes these test cases, multiple threads will concurrently access the unaligned memory buffer according to the multi-threaded cyclic read and write operation sequence. By continuously reading and writing operations, the memory bandwidth is occupied, memory page swaps are triggered, and the processing capabilities of the memory controller in high-concurrency, irregular access scenarios are tested. This comprehensively tests the processor's performance under different memory pressures, effectively increasing the depth of memory performance testing.

[0069] According to an embodiment of the present invention, when the test case is used to test the mixed load control performance, the method also includes: calling the parallel scheduling module to generate the test case according to the task execution ratio and asynchronous execution parameters in the test parameters; wherein the parallel scheduling module realizes the generation of the test case through the following configuration: based on the asynchronous execution parameters, the created computing task queue and memory operation queue are associated with the asynchronous execution mechanism of the processor, so that the processor executes the tasks in the computing task queue and the memory operation queue according to the task execution ratio.

[0070] When testing mixed-load control performance, the test case extracts the task execution ratio and asynchronous execution parameters from the test parameters. The task execution ratio specifies the ratio of the number of compute tasks to memory operation tasks, or the time allocation ratio. The asynchronous execution parameters include the task scheduling interval, the upper limit of concurrency, and the synchronization point setting. Based on the test parameters, the parallel scheduling module is called, which is responsible for generating the corresponding test case to simulate a mixed-load scenario with interwoven compute and memory operations.

[0071] The core configuration of the parallel scheduling module revolves around the association between the task queue and the processor's asynchronous mechanism. The parallel scheduling module first creates independent computing task queues and memory operation queues based on the test requirements. The computing task queue contains various computationally intensive tasks such as arithmetic operations and matrix processing, while the memory operation queue covers tasks that interact with the memory, such as data loading, storage, and copying. Subsequently, based on the asynchronous execution parameters, the parallel scheduling module associates the computing task queue and the memory operation queue with the processor's asynchronous execution mechanism. Specifically, by configuring the processor's asynchronous engine interface, computing tasks and memory operation tasks can be independently initiated and advanced in parallel, allowing subsequent tasks to be started without waiting for the completion of the preceding tasks.

[0072] During the task execution phase, the parallel scheduling module will dynamically adjust the dequeue rhythm and execution priority of tasks in the two queues based on the preset task execution ratio. For example, when the task execution ratio is set to 60% for computing tasks and 40% for video memory operation tasks, the parallel scheduling module will adjust the task distribution frequency to ensure that the two types of tasks executed by the processor in unit time meet this proportional relationship. At the same time, with the help of the characteristics of the asynchronous execution mechanism, the processor can process video memory operations in parallel in the background while executing computing tasks, so as to test the processor's resource coordination ability, task switching efficiency and overall performance in mixed load scenarios, thereby generating test cases that can accurately reflect the mixed load control performance and achieve accurate adaptation of test cases and processor parameters.

[0073] According to an embodiment of the present invention, the processor testing method also includes: when it is determined that multiple load states in the load state sequence have been tested and the cumulative test time has not reached the preset duration configured in the initialization load parameters, dynamically generating an updated state sequence through a load generation model; adding the updated state sequence to the end of the load state sequence in the form of a queue, continuing to execute the test until the cumulative test time reaches the preset duration, and outputting the test results.

[0074] During the test, the completion status of each load state in the load state sequence is monitored in real time, and the cumulative test duration is recorded. When it is confirmed that all load states in the load state sequence have been tested and the cumulative test duration has not reached the preset duration configured in the initialization load parameters, the load generation model is triggered to run again.

[0075] At this point, the load generation model dynamically generates a new, updated state sequence based on the characteristics of the load state of the completed test, feedback from processor performance data, and the remaining test duration. This updated state sequence will continue the previous load fluctuation pattern and may also introduce new load characteristic combinations to ensure comprehensiveness and continuity of the test.

[0076] The generated updated state sequence is added to the end of the original load state sequence in a queue, forming an extended load state sequence. The test is then continued in the order of the new sequence, repeating the process of load state switching, data acquisition, and analysis.

[0077] This dynamic expansion process will continue until the cumulative test duration reaches the preset duration. At this point, the test process is terminated, the test data and test results collected in all test phases are integrated, and the complete processor test results are finally output to ensure that the test results can reflect the long-term operating performance of the processor, effectively improving the integrity and continuity of the test.

[0078] Figure 4A flowchart of a processor test method according to an embodiment of the present invention is shown.

[0079] like Figure 4 As shown, this embodiment includes operations S411 to S417.

[0080] In operation S411, initialization load parameters are configured. In operation S412, a load state sequence is generated. In operation S413, tests are performed sequentially according to the order in which the load states in the load state sequence change.

[0081] In operation S414, it is determined whether the test is completed. If completed, operation S415 is executed. If not completed, the process returns to operation S413.

[0082] In operation S415, it is determined whether the accumulated test duration has reached the preset duration. If so, operation S417 is performed. If not, operation S416 is performed.

[0083] In operation S416, the load state sequence is updated. In operation S417, the test result is output.

[0084] According to an embodiment of the present invention, before performing processor testing, initial load parameters must be configured. Based on these initial load parameters, a load state sequence is generated using a load generation model, with the duration and state transition rules for each load state clearly defined. During testing, the corresponding tests are executed sequentially according to the order of the load states in the load state sequence, and performance data is recorded in real time.

[0085] After each test of all load states in the current load state sequence is completed, it is necessary to confirm whether the test is complete. If the test is not yet complete, the original sequence is continued. If the test is completed, the cumulative test duration is checked to see if it has reached the preset duration. If so, all data is integrated and the final test results are output. If not, the load generation model is called to generate a new load state sequence, which is appended to the end of the original sequence, and the test process continues.

[0086] By dynamically generating and updating the load state sequence mechanism, the test can cover a sufficient number of load scenarios, while strictly controlling the cumulative test duration within the preset duration, thus balancing the comprehensiveness of the test with the time cost.

[0087] According to an embodiment of the present invention, the processor testing method further includes: adding a disturbance factor for causing disturbance to the load state to the load running environment of the corresponding logical partition during the execution of the test case.

[0088] During test case execution, the processor monitors the current state of the load environment for the logical partition running the test task in real time, including task execution progress, resource utilization, data flow efficiency, and other information. Based on this real-time status, a variety of perturbation factors are dynamically generated. These perturbation factors cover sudden increases in computing tasks, fluctuations in data transmission latency, temporary resource preemption, and random adjustments to instruction execution priority. The intensity and action mode of each perturbation factor are adapted to the characteristics of the current load state.

[0089] These perturbation factors are then sequentially added to the load operating environment of the corresponding logical partition. For example, when the logical partition is at a peak load, a small resource preemption perturbation may be introduced to simulate the temporary occupation of resources by other processes. In the intermediate state, incremental perturbations of computing tasks may be added to test the processor's ability to adjust to sudden increases in load. The addition of perturbation factors is coordinated with the execution rhythm of the current test case, which neither interrupts the normal testing process nor realistically simulates the environmental fluctuations that may occur in actual operation, thereby more comprehensively testing the processor's stability and fault tolerance under complex load conditions.

[0090] According to an embodiment of the present invention, by analyzing the test data generated during the execution process, the test results of the processor under the load state are determined, including: in the process of testing the processor, multi-dimensional detection is performed on the performance data generated to obtain test data, and the multi-dimensional detection includes at least two of operating temperature detection, average power consumption detection and calculation error rate detection; the test data is compared and analyzed with the corresponding standard threshold in the preset threshold set to generate a test result.

[0091] During the processor testing process, a multi-dimensional data collection mechanism is simultaneously activated to monitor and record the performance data generated during the test in real time to form complete test data. These multi-dimensional tests cover at least the following two items: Operating temperature detection uses temperature sensors deployed in the processor core and peripheral circuits to continuously collect real-time temperature values ​​in different areas and generate temperature change curves. Average power consumption detection uses the power consumption monitoring module to record energy consumption data per unit time and calculate the average power consumption during the test period. Computational error rate detection compares the output results of the calculation tasks performed by the processor with the preset standard answers, counts the number of calculation errors, and calculates the error rate.

[0092] After acquiring multi-dimensional test data, the system calls upon a set of preset thresholds, which include standard thresholds corresponding to various test indicators, such as the processor's safe operating temperature limit (e.g., 85°C), normal power consumption range, and acceptable computational error rate threshold (e.g., 0.01%). The system then compares and analyzes the test data against the corresponding standard thresholds in the set one by one. If a particular test data item does not exceed the corresponding standard threshold, the indicator is deemed normal. If it exceeds the standard threshold, it is marked as abnormal and the degree of deviation is recorded.

[0093] By comprehensively comparing the results of various indicators, comprehensive test results are generated, which not only include the specific values ​​and compliance status of each detection indicator, but also analyze the possible impact of abnormal indicators and the correlation between indicators of different dimensions, thereby providing a basis for evaluating the comprehensive performance of the processor under the test load.

[0094] According to an embodiment of the present invention, performance data includes temperature data, power consumption data and error code data; wherein, temperature data is obtained through a temperature sensor built into the processor, power consumption data is obtained through a communication bus of a power management integrated circuit in the processor, and error code data is obtained through a video memory error correction counter of the processor.

[0095] The performance data collected during processor testing covers three core metrics: temperature, power consumption, and error code data. Each type of data is acquired through targeted collection methods. Temperature data is derived from the processor's built-in temperature sensors, which are located in key areas such as the core computing unit and memory controller. These sensors can sense temperature changes in various areas in real time, convert analog signals into digital data, and transmit them to the test system via the processor's internal monitoring interface, forming a complete record of temperature changes.

[0096] Power consumption data is acquired through the processor's power management integrated circuit (PMIC), which dynamically regulates the processor's power supply. The test system establishes data exchange with the PMIC via a communication bus, reading parameters such as supply voltage and current in real time. It then uses a power calculation formula to convert the energy consumption per unit time into power consumption data.

[0097] Error code data is primarily collected through the processor's memory error correction counter. If data errors occur during memory reads and writes, the processor's error correction mechanism automatically corrects them and uses the counter to record information such as the number, type, and location of errors. The test system reads the real-time data from this counter and compiles it into error code data, which reflects the stability of memory data transmission and storage. These three types of data together constitute the key basis for evaluating processor performance and stability, providing comprehensive raw information for subsequent testing and analysis.

[0098] According to an embodiment of the present invention, the processor testing method also includes: determining the coverage of the test case for the dynamic load scenario in the processor; inputting the coverage and the execution time of the test case in the logical partition into the target reward function and outputting the reward value; based on the reward value, dynamically optimizing the model parameters of the parameter configuration model.

[0099] When evaluating the effectiveness of a test case, its coverage of the processor's dynamic load scenarios must be determined. Specifically, the load states covered by the test case are compared against a set of pre-defined dynamic load scenarios to determine coverage. This comparison covers multiple dimensions, including load intensity range, state switching frequency, and concurrent task types. Ultimately, coverage is quantified as a percentage, reflecting the test case's coverage of actual dynamic load scenarios.

[0100] The calculated coverage and the actual execution time of the test case in the corresponding logical partition are then input into the target reward function. The target reward function sets weighting parameters based on the test requirements and comprehensively calculates coverage and execution time. Specifically, high coverage generally corresponds to a higher reward value, while excessive execution time will have the reward value reduced proportionally, thus balancing the comprehensiveness and efficiency of the test. After calculation, the target reward function outputs a specific reward value, which serves as a quantitative indicator to measure the quality of the current test case and its corresponding parameter configuration.

[0101] Based on the output reward value, the parameter configuration model's model parameters are dynamically optimized. If the reward value is high, it indicates that the test cases generated by the current parameter configuration perform well. The parameter configuration model will retain the core parameters and fine-tune the details to enhance the effect. If the reward value is low, the backpropagation algorithm is used to adjust the weight coefficients, threshold parameters, and other parameters in the parameter configuration model to optimize the parameter mapping relationship. This allows the parameter configuration model to more accurately balance coverage and execution efficiency when generating test parameters in the future, thereby improving the test results for dynamic load scenarios.

[0102] Figure 5 A schematic diagram of module interaction of a processor testing method according to an embodiment of the present invention is shown.

[0103] like Figure 5 As shown, when testing processor 503, main control module 501 is responsible for overall process control, including receiving the load status output by the load generation model, managing the test execution process, and outputting the final test results. Main control module 501 passes the constructed test case to task scheduler 502. Task scheduler 502 accurately allocates the test case to the corresponding computing unit of processor 503 for execution based on the matching rules between task processing type and logical partition.

[0104] During the test execution process, the processor 503, through the collaborative work of the core group 504, the memory controller 505, and the serial bus interface 506, collects key performance indicator data such as temperature, power consumption, and bit error rate in real time, and transmits the raw data to the data acquisition module 507. The data acquisition module 507 structures the data and stores it in the test database 508 for persistent storage.

[0105] After the test is complete, a visualization tool can be used to automatically generate a visual test report containing key indicators such as performance curves and power consumption trends based on historical data in the test database 508. The test system also has exception handling capabilities. For example, if the processor 503 temperature is detected to exceed a safety threshold, the main control module 501 will immediately trigger a dynamic frequency reduction protection mechanism, adjusting the clock frequency through the underlying driver interface to ensure system safety, and recording detailed information about the exception event in the system log for subsequent analysis.

[0106] During the test process, the unified scheduling of the main control module 501 realizes the automated collaborative work of task allocation, data collection, exception handling and other links, ensuring the efficiency and reliability of the test process and providing complete technical support for the performance evaluation of the processor 503.

[0107] According to an embodiment of the present invention, the processor testing method further includes: based on the core indicators in the test results, as well as the coverage and execution time of the test cases, a weighted scoring algorithm is used to screen out test parameters that meet preset conditions from multiple test parameters as recommended configuration parameters.

[0108] When screening recommended configuration parameters, core indicators are extracted from the test results. These core indicators include key performance data such as the processor's temperature peak, average power consumption, and calculation error rate under different load conditions. At the same time, the coverage and execution time of each test case are summarized to form a multi-dimensional evaluation data set.

[0109] Subsequently, a weighted scoring algorithm is invoked to assign appropriate weights to each evaluation metric. Core metrics are typically weighted higher to ensure that the recommended parameters prioritize meeting the processor's basic performance requirements. Coverage and execution time are weighted appropriately based on the emphasis of the test objectives, balancing comprehensiveness and efficiency. The weighted scoring algorithm normalizes the actual values ​​of each metric, multiplies them by the corresponding weight, and then accumulates the values ​​to produce a comprehensive score for each test parameter.

[0110] Finally, the comprehensive scores of all test parameters are screened based on preset criteria (such as comprehensive score thresholds, core indicator compliance requirements, or the top 10% of test parameters with the highest energy efficiency). Test parameters that meet the preset criteria are identified as recommended configuration parameters. These recommended configuration parameters not only ensure stable processor operation under load scenarios, but also balance comprehensive test coverage and execution efficiency, providing a reference for subsequent processor testing or actual applications.

[0111] Based on the above processor testing method, the present invention also provides a processor testing device. Figure 6 The device is described in detail.

[0112] Figure 6 A structural block diagram of a processor testing device according to an embodiment of the present invention is shown.

[0113] like Figure 6 As shown, the processor testing device 600 of this embodiment includes a state generating module 610 , a parameter output module 620 , a use case distributing module 630 and a result determining module 640 .

[0114] The state generation module 610 is used to generate multiple load states for simulating the load fluctuation of the processor in response to the test instruction for the processor. In one embodiment, the state generation module 610 can be used to perform the operation S210 described above, which will not be repeated here.

[0115] The parameter output module 620 is used to input the obtained performance data of the processor and the load state into the parameter configuration model for each of the above load states, and output test parameters adapted to the load state. In one embodiment, the parameter output module 620 can be used to perform the operation S220 described above, which will not be repeated here.

[0116] The use case distribution module 630 is used to distribute the test case constructed based on the test parameters to the matching logical partitions in the processor for execution according to the task processing type of the test parameters. In one embodiment, the use case distribution module 630 can be used to perform the operation S230 described above, which will not be repeated here.

[0117] The result determination module 640 is used to determine the test result of the processor under the load state by analyzing the test data generated during the execution process. In one embodiment, the result determination module 640 can be used to perform the operation S240 described above, which will not be repeated here.

[0118] According to embodiments of the present invention, any multiple modules among the state generation module 610, parameter output module 620, use case distribution module 630, and result determination module 640 may be combined into a single module, or any one of these modules may be split into multiple modules. Alternatively, at least part of the functionality of one or more of these modules may be combined with at least part of the functionality of other modules and implemented in a single module. According to embodiments of the present invention, at least one of the state generation module 610, parameter output module 620, use case distribution module 630, and result determination module 640 may be at least partially implemented as a hardware circuit, such as a field programmable gate array (FPGA), a programmable logic array (PLA), a system on a chip, a system on a substrate, a system on a package, an application-specific integrated circuit (ASIC), or may be implemented in hardware or firmware through any other reasonable means of circuit integration or packaging, or may be implemented in any one of software, hardware, and firmware, or any suitable combination of these. Alternatively, at least one of the state generation module 610 , the parameter output module 620 , the use case distribution module 630 and the result determination module 640 may be at least partially implemented as a computer program module, which may perform corresponding functions when executed.

[0119] Figure 7 A block diagram of an electronic device suitable for implementing a processor testing method according to an embodiment of the present invention is shown.

[0120] like Figure 7 As shown, an electronic device 700 according to an embodiment of the present invention includes a processor 701, which can perform various appropriate actions and processes based on programs stored in a read-only memory (ROM) 702 or programs loaded from a storage unit 708 into a random access memory (RAM) 703. The processor 701 may include, for example, a general-purpose microprocessor (e.g., a CPU), an instruction set processor and / or related chipsets and / or a special-purpose microprocessor (e.g., an application-specific integrated circuit (ASIC)), etc. The processor 701 may also include onboard memory for caching purposes. The processor 701 may include a single processing unit or multiple processing units for performing different actions of the method flow according to an embodiment of the present invention.

[0121] The RAM 703 stores various programs and data required for the operation of the electronic device 700. The processor 701, ROM 702, and RAM 703 are connected to each other via a bus 704. The processor 701 executes the programs in the ROM 702 and / or RAM 703 to perform the various operations of the method flow according to the embodiment of the present invention. It should be noted that the programs may also be stored in one or more memories other than the ROM 702 and RAM 703. The processor 701 may also execute the programs stored in one or more memories to perform the various operations of the method flow according to the embodiment of the present invention.

[0122] According to an embodiment of the present invention, electronic device 700 may further include an input / output (I / O) interface 705, which is also connected to bus 704. Electronic device 700 may also include one or more of the following components connected to I / O interface 705: an input section 706 including a keyboard, mouse, etc.; an output section 707 including devices such as a cathode ray tube (CRT), liquid crystal display (LCD), and speakers; a storage section 708 including a hard disk; and a communication section 709 including a network interface card such as a LAN card or modem. Communication section 709 performs communication processing via a network such as the Internet. A drive 710 is also connected to I / O interface 705 as needed. Removable media 711, such as a magnetic disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed in drive 710 as needed, so that computer programs read from the removable media can be installed into storage section 708 as needed.

[0123] The present invention also provides a computer-readable storage medium, which may be included in the device / apparatus / system described in the above embodiments, or may exist independently and not incorporated into the device / apparatus / system. The computer-readable storage medium carries one or more programs, which, when executed, implement the method according to the embodiments of the present invention.

[0124] According to an embodiment of the present invention, a computer-readable storage medium may be a non-volatile computer-readable storage medium, and may include, for example, but not limited to: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In the present invention, a computer-readable storage medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. For example, according to an embodiment of the present invention, a computer-readable storage medium may include the ROM 702 and / or RAM 703 described above, and / or one or more memories other than ROM 702 and RAM 703.

[0125] An embodiment of the present invention further includes a computer program product comprising a computer program containing program code for executing the method shown in the flowchart. When the computer program product is executed in a computer system, the program code is used to cause the computer system to implement the processor testing method provided by the embodiment of the present invention.

[0126] The computer program executes the above functions defined in the system / device of the embodiment of the present invention when executed by the processor 701. According to the embodiment of the present invention, the system, device, module, unit, etc. described above can be implemented by a computer program module.

[0127] In one embodiment, the computer program may be stored on a tangible storage medium such as an optical storage device or a magnetic storage device. In another embodiment, the computer program may be transmitted and distributed in the form of a signal on a network medium, downloaded and installed via the communication portion 709, and / or installed from a removable medium 711. The program code contained in the computer program may be transmitted using any appropriate network medium, including but not limited to wireless, wired, or any suitable combination thereof.

[0128] In such an embodiment, the computer program can be downloaded and installed from a network via the communication section 709 and / or installed from the removable medium 711. When the computer program is executed by the processor 701, the above-described functions defined in the system of the embodiment of the present invention are performed. According to the embodiment of the present invention, the systems, devices, means, modules, units, etc. described above can be implemented by computer program modules.

[0129] According to an embodiment of the present invention, the program code for executing the computer program provided by the embodiment of the present invention can be written in any combination of one or more programming languages. Specifically, these computer programs can be implemented using high-level procedural and / or object-oriented programming languages, and / or assembly / machine languages. Programming languages ​​include, but are not limited to, languages ​​such as Java, C++, Python, "C" or similar programming languages. The program code can be executed entirely on the user computing device, partially on the user device, partially on a remote computing device, or entirely on a remote computing device or server. In the case of a remote computing device, the remote computing device can be connected to the user computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computing device (for example, using an Internet service provider to connect via the Internet).

[0130] The flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present invention. In this regard, each box in the flowchart or block diagram can represent a module, program segment, or a part of code, and the above-mentioned module, program segment, or a part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, and the combination of boxes in the block diagram or flowchart, can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0131] It will be understood by those skilled in the art that the features described in the various embodiments of the present invention may be combined and / or coupled in various ways, even if such combinations or couplings are not explicitly described in the present invention. In particular, the features described in the various embodiments of the present invention may be combined and / or coupled in various ways without departing from the spirit and teachings of the present invention. All such combinations and / or couplings fall within the scope of the present invention.

[0132] The above describes embodiments of the present invention. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present invention. Although each embodiment has been described separately above, this does not mean that the measures in each embodiment cannot be advantageously used in combination. Without departing from the scope of the present invention, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present invention.

Claims

1. A processor testing method, characterized in that: The method comprises: generating, in response to a test instruction for a processor, a plurality of load states for simulating load fluctuations of the processor; For each load state, the acquired performance data of the processor and the load state input parameters are configured into a model, and test parameters adapted to the load state are output; Distributing the test cases constructed based on the test parameters to matching logical partitions in the processor for execution according to the task processing type of the test parameters; The test result of the processor under the load state is determined by analyzing the test data generated during the execution process.

2. The method according to claim 1, characterized in that The plurality of load states include an idle state, an intermediate state, and a peak state; and the generating of the plurality of load states for simulating the processor load fluctuation includes: Configuring initialization load parameters according to the hardware specifications of the processor; Using a load generation model, under the constraints of the initialization load parameters, a load state sequence is generated for simulating state switching between the idle state, the intermediate state, and the peak state, so as to simulate load fluctuations of the processor; Wherein, during the process of testing the processor, the tests are performed sequentially according to the change order of the load states in the load state sequence.

3. The method according to claim 1, characterized in that There are multiple test cases; and according to the task processing type of the test parameters, the test cases constructed based on the test parameters are distributed to matching logical partitions in the processor for execution, including: Sending multiple test cases to a task scheduler so as to distribute each test case to a matching logical partition in the processor for execution according to a preset mapping relationship between a task processing type stored in the task scheduler and the logical partition, wherein the task processing type includes a computing type and a storage type.

4. The method according to claim 3, characterized in that In the case where the test case is used to test mixed-precision matrix multiplication performance, the method further includes: According to the dynamic matrix scale parameter in the test parameters, calling the mixed precision calculation kernel module to generate the test case; Among them, the mixed precision calculation kernel module realizes the generation of the test case through the following configuration: according to the rule of alternating execution of half-precision calculation and single-precision calculation, a parallel matrix multiplication kernel is constructed to enable the processor to execute the parallel matrix multiplication kernel, and during the execution process, the thread grid dimension of the parallel matrix multiplication kernel is adaptively adjusted to match the dynamic matrix scale parameter.

5. The method according to claim 3, characterized in that When the test case is used to test video memory pressure, the method further includes: Calling a video memory load module according to the video memory access parameter in the test parameter to generate the test case; Among them, the video memory load module realizes the generation of the test case through the following configuration: allocating a non-aligned video memory buffer corresponding to the video memory access parameter, and constructing a multi-threaded cyclic read and write operation sequence so that the processor concurrently accesses the non-aligned video memory buffer according to the multi-threaded cyclic read and write operation sequence.

6. The method according to claim 3, characterized in that In the case where the test case is used to test mixed load control performance, the method further includes: According to the task execution ratio and asynchronous execution parameters in the test parameters, the parallel scheduling module is called to generate the test case; Among them, the parallel scheduling module realizes the generation of the test case through the following configuration: based on the asynchronous execution parameters, the created computing task queue and memory operation queue are associated with the asynchronous execution mechanism of the processor, so that the processor executes the tasks in the computing task queue and the memory operation queue according to the task execution ratio.

7. The method according to claim 2, characterized in that The method further comprises: When it is determined that the multiple load states in the load state sequence have been tested and the cumulative test duration has not reached the preset duration configured in the initialization load parameters, dynamically generating an updated state sequence through the load generation model; The updated state sequence is added to the end of the load state sequence in the form of a queue, and the test is continued until the accumulated test duration reaches the preset duration, and the test result is output.

8. The method according to claim 1, characterized in that The method further comprises: During the execution of the test case, a disturbance factor for causing disturbance to the load state is added to the load running environment of the corresponding logical partition.

9. The method according to claim 1, characterized in that Determining the test result of the processor under the load state by analyzing the test data generated during the execution process includes: During the process of testing the processor, performing multi-dimensional detection on the generated performance data to obtain the test data, wherein the multi-dimensional detection includes at least two of operating temperature detection, average power consumption detection, and calculation error rate detection; The test data is compared and analyzed with the corresponding standard threshold value in the preset threshold value set to generate the test result.

10. The method according to claim 9, characterized in that The performance data includes temperature data, power consumption data and error code data; wherein, the temperature data is obtained through a temperature sensor built into the processor, the power consumption data is obtained through a communication bus of a power management integrated circuit in the processor, and the error code data is obtained through a video memory error correction counter of the processor.

11. The method according to claim 1, wherein The method further comprises: Determining coverage of the test case for a dynamic load scenario in the processor; Input the coverage rate and the execution time of the test case in the logical partition into a target reward function and output a reward value; Based on the reward value, model parameters of the parameter configuration model are dynamically optimized.

12. The method according to claim 11, characterized in that The method further comprises: According to the core indicators in the test results, as well as the coverage and execution time of the test cases, a weighted scoring algorithm is used to screen out test parameters that meet preset conditions from the multiple test parameters as recommended configuration parameters.

13. An electronic device comprising: one or more processors; a memory for storing one or more computer programs, It is characterized in that the one or more processors execute the one or more computer programs to implement the steps of the method according to any one of claims 1 to 12.

14. A computer-readable storage medium having a computer program or instruction stored thereon, characterized in that: When the computer program or instructions are executed by a processor, the steps of the method according to any one of claims 1 to 12 are implemented.

15. A computer program product, characterized in that The invention comprises a computer program, which implements the method according to any one of claims 1 to 12 when being executed by a processor.

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