Processor testing methods, apparatus, media, and program products

Abstract

The application provides a processor testing method, device, medium and program product, which can be applied to the technical field of computers. The processor testing method comprises the following steps: in response to a testing instruction for a processor, a plurality of load states for simulating load fluctuation of the processor are generated; for each load state, performance data of the processor and a load state input parameter are input into a parameter configuration model, and testing parameters adapted to the load state are output; according to a task processing type of the testing parameters, a test case constructed based on the testing parameters is distributed to a matching logical partition in the processor for execution; and by analyzing testing data generated in the execution process, a testing result of the processor under the load state is determined.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and more specifically to a processor testing method, apparatus, medium, and program product. Background Technology

[0002] As a core component of electronic devices, processors require comprehensive and accurate performance testing during research, development, production, and application. Related technologies typically employ fixed test cases to evaluate processor performance, that is, standardized testing using pre-defined configuration parameters.

[0003] The relevant technologies have at least the following problems: relying on fixed test cases makes it difficult to adapt to the complex and ever-changing load fluctuations of the processor in actual operation, resulting in low testing efficiency and low accuracy of test results. Summary of the Invention

[0004] In view of the above problems, the present invention provides a processor testing method, apparatus, device, medium and program product.

[0005] According to a first aspect of the present invention, a processor testing method is provided, comprising: generating multiple load states for simulating processor load fluctuations in response to a test instruction for the processor; configuring a model of acquired processor performance data and load state input parameters for each load state, and outputting test parameters adapted to the load state; distributing test cases constructed based on the test parameters to matching logical partitions in the processor for execution according to the task processing type of the test parameters; and determining the test results of the processor under the load states by analyzing the test data generated during the execution process.

[0006] A second aspect of the present invention provides a processor testing apparatus, comprising: a state generation module, configured to generate multiple load states simulating processor load fluctuations in response to a test instruction for the processor; a parameter output module, configured to, for each of the load states, output test parameters adapted to the load states by configuring the acquired performance data of the processor and the load state input parameter model; a test case distribution module, configured to distribute test cases constructed based on the test parameters to matching logical partitions in the processor for execution according to the task processing type of the test parameters; and a result determination module, configured to determine the test results of the processor under the load states by analyzing the test data generated during execution.

[0007] A third aspect of the present invention provides an electronic device comprising: one or more processors; and a memory for storing one or more computer programs, wherein the one or more processors execute the one or more computer programs to implement the steps of the method described above.

[0008] A fourth aspect of the present invention also provides a computer-readable storage medium having a computer program or instructions stored thereon, wherein the computer program or instructions, when executed by a processor, implement the steps of the above-described method.

[0009] A fifth aspect of the present invention also provides a computer program product, including a computer program or instructions that, when executed by a processor, implement the steps of the above-described method.

[0010] According to embodiments of the present invention, by simulating multiple load states of the processor during actual operation and configuring performance data and load state input parameters in the model, test parameters adapted to the load states are output, improving the accuracy of the adaptation between test parameters and load states. Based on the task processing type of the test parameters, the constructed test cases are distributed to the corresponding logical partitions in the processor for execution, effectively enhancing the targeting of the test. During execution, the generated test data is analyzed to evaluate the processor's performance under different load states, thereby obtaining targeted test results. By simulating load fluctuations, the realism and coverage of the test scenario are effectively improved. Simultaneously, by utilizing test parameters adapted to the load states to implement a targeted execution mechanism for logical partitions, the efficiency of the test and the accuracy of the results are further improved. Attached Figure Description

[0011] The above-mentioned contents, as well as other objects, features and advantages of the present invention, will become clearer from the following description of embodiments of the present invention with reference to the accompanying drawings.

[0012] Figure 1 The diagram illustrates application scenarios of the processor testing method, apparatus, device, medium, and program product according to embodiments of the present invention.

[0013] Figure 2 A flowchart of a processor testing method according to an embodiment of the present invention is shown.

[0014] Figure 3 A schematic diagram of test case distribution in a processor testing method according to an embodiment of the present invention is shown.

[0015] Figure 4 A flowchart of a processor testing method according to an embodiment of the present invention is shown.

[0016] Figure 5 A schematic diagram of module interaction of a processor testing method according to an embodiment of the present invention is shown.

[0017] Figure 6 A structural block diagram of a processor testing apparatus according to an embodiment of the present invention is shown.

[0018] Figure 7 A block diagram of an electronic device suitable for implementing a processor testing method according to an embodiment of the present invention is shown. Detailed Implementation

[0019] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the invention. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the invention for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concept of the invention.

[0020] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0021] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0022] When using expressions such as "at least one of A, B and C", they should generally be interpreted in accordance with the meaning that is commonly understood by those skilled in the art (e.g., "a system having at least one of A, B and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B and C, etc.).

[0023] In the technical solution of this invention, the data involved (including but not limited to data used for analysis, data stored, data displayed, etc.) are all information and data authorized by the user or fully authorized by all parties. The collection, storage, use, processing, transmission, provision, disclosure and application of related data all comply with relevant laws, regulations and standards, necessary confidentiality measures have been taken, and they do not violate public order and good morals. Corresponding operation entry points are provided for users to choose to authorize or refuse.

[0024] Embodiments of the present invention provide a processor testing method, comprising: generating multiple load states for simulating processor load fluctuations in response to test instructions for the processor; configuring a model with acquired processor performance data and load state input parameters for each load state, and outputting test parameters adapted to the load state; distributing test cases constructed based on the test parameters to matching logical partitions in the processor for execution according to the task processing type of the test parameters; and determining the test results of the processor under the load state by analyzing the test data generated during the execution process.

[0025] Figure 1 The diagram illustrates application scenarios of the processor testing method, apparatus, device, medium, and program product according to embodiments of the present invention.

[0026] like Figure 1 As shown, application scenario 100 according to this embodiment may include a first terminal device 101, a second terminal device 102, a third terminal device 103, and a server 105. Network 104 serves as a medium for providing a communication link between the first terminal device 101, the second terminal device 102, the third terminal device 103, and the server 105. Network 104 may include various connection types, such as wired or wireless communication links, or fiber optic cables, etc.

[0027] Users can use the first terminal device 101, the second terminal device 102, and the third terminal device 103 to interact with the server 105 via the network 104 to receive or send messages, etc. Various communication client applications can be installed on the first terminal device 101, the second terminal device 102, and the third terminal device 103, such as web browser applications, search applications, instant messaging tools, email clients, social media platform software, etc. (for example only).

[0028] The first terminal device 101, the second terminal device 102, and the third terminal device 103 can be various electronic devices with displays and support web browsing, including but not limited to smartphones, tablets, laptops, and desktop computers.

[0029] Server 105 can be a server that provides various services, such as a backend management server that supports websites browsed by users using the first terminal device 101, the second terminal device 102, and the third terminal device 103 (this is just an example). The backend management server can analyze and process data such as received user requests, and feed back the processing results (such as web pages, information, or data obtained or generated according to user requests) to the terminal devices.

[0030] It should be noted that the processor testing method provided in this embodiment of the invention can generally be executed by server 105. Correspondingly, the processor testing device provided in this embodiment of the invention can generally be located in server 105. The processor testing method provided in this embodiment of the invention can also be executed by a server or server cluster that is different from server 105 and capable of communicating with the first terminal device 101, the second terminal device 102, the third terminal device 103, and / or server 105. Correspondingly, the processor testing device provided in this embodiment of the invention can also be located in a server or server cluster that is different from server 105 and capable of communicating with the first terminal device 101, the second terminal device 102, the third terminal device 103, and / or server 105.

[0031] It should be understood that Figure 1 The number of first terminal devices, second terminal devices, third terminal devices, networks, and servers in the system is only a certain number. Depending on the implementation needs, it can have any number of first terminal devices, second terminal devices, third terminal devices, networks, and servers.

[0032] The following will be based on Figure 1 The described scene, through Figures 2-5 The processor testing method of the embodiments of the invention will be described in detail.

[0033] Figure 2 A flowchart of a processor testing method according to an embodiment of the present invention is shown.

[0034] like Figure 2 As shown, this embodiment includes operations S210 to S240.

[0035] In operation S210, in response to test instructions for the processor, multiple load states are generated to simulate processor load fluctuations.

[0036] When operating the S220, for each load state, the acquired processor performance data and load state input parameter configuration model are used to output test parameters adapted to the load state.

[0037] In operation S230, test cases built based on test parameters are distributed to the matching logical partitions in the processor for execution, according to the task processing type of the test parameters.

[0038] By operating S240, the test results of the processor under load are determined by analyzing the test data generated during the execution process.

[0039] According to embodiments of the present invention, the processor, as a core component of electronic devices, directly affects the operating efficiency and stability of the entire system. Among them, the Graphics Processing Unit (GPU) plays a crucial role in parallel computing and graphics rendering. Comprehensive and accurate performance testing is essential during the research, development, production, and application of processors, and simulating load fluctuations in real-world operating environments is a key step in evaluating the overall capabilities of the processor.

[0040] Upon receiving test commands for the processor, multiple load states with different characteristics are generated. These load states cover various scenarios that the processor may encounter in actual operation, such as idle state, intermediate state, peak state, and load surge, accurately simulating the load changes of the processor under different workloads.

[0041] For each generated load state, the processor's performance data under that load state is collected in real time. For graph processors, the performance data includes key indicators such as core utilization, memory bandwidth, texture fill rate, and power consumption. This performance data, along with the corresponding load state parameters, is then input into a pre-trained parameter configuration model. This parameter configuration model, based on machine learning algorithms, learns from a large amount of historical test data and can automatically output test parameters highly adapted to the current load state, such as test duration, data throughput, and number of concurrent tasks, ensuring that the test parameters can fully stimulate the processor's performance under specific loads.

[0042] After obtaining the appropriate test parameters, the tests are categorized according to the task processing type corresponding to those parameters. The processor is pre-divided into different logical partitions, each specifically responsible for handling tasks of a particular type. For example, a graph processor might have logical partitions for processing computational tasks and storage-type tasks. By matching the task processing type with the functionality of the logical partitions, the constructed test cases are accurately distributed to the corresponding logical partitions for execution, ensuring the efficiency and relevance of the testing process.

[0043] During test case execution, various test data are continuously collected, including task response time, resource utilization, and error rate. After the test, these test data are analyzed and mined in depth using data analysis tools to compare the processor's performance under different load conditions, evaluate its stability, efficiency, and reliability under various load scenarios, and finally determine the processor's comprehensive test results under load conditions.

[0044] By simulating multiple load states of the processor during actual operation and configuring performance data and load state input parameters into the model, test parameters adapted to the load states are output, improving the accuracy of the adaptation between test parameters and load states. Based on the task processing type of the test parameters, the constructed test cases are distributed to the corresponding logical partitions in the processor for execution, effectively enhancing the targeting of the tests. During execution, the generated test data is analyzed to evaluate the processor's performance under different load states, thereby obtaining targeted test results. By simulating load fluctuations, the realism and coverage of the test scenarios are effectively improved. At the same time, the use of test parameters adapted to the load states to implement a targeted execution mechanism for logical partitions further improves the efficiency of testing and the accuracy of results.

[0045] According to an embodiment of the present invention, multiple load states include an idle state, an intermediate state, and a peak state; generating multiple load states for simulating processor load fluctuations includes: configuring initialization load parameters according to the processor's hardware specifications; using a load generation model, under the constraints of the initialization load parameters, generating a load state sequence for simulating state switching between idle, intermediate, and peak states to simulate processor load fluctuations; wherein, during processor testing, tests are executed sequentially according to the order of load state changes in the load state sequence.

[0046] Before conducting processor testing, it is necessary to obtain the processor's hardware specifications, including but not limited to key parameters such as the number of cores, clock speed range, cache size, video memory capacity, and maximum power consumption limit. Based on these hardware specifications, initial load parameters are automatically configured. These initial load parameters cover the base load intensity, load change step size, and state transition interval, ensuring that the initial parameters match the processor's hardware capabilities and providing a reasonable constraint range for subsequent load generation.

[0047] For example, the target load power is calculated by reading the rated power consumption of the graph processor, and a power limit is set using the hardware management interface. Simultaneously, a timer is used to precisely control the preset duration of the test, and the environment is initialized before the test, including terminating irrelevant background processes and locking the graph processor frequency to its highest performance mode, to ensure the stability and accuracy of the test.

[0048] Based on the configured initial load parameters, a preset load generation model is invoked. This model, combining the processor's hardware characteristics and the load variation patterns that may occur in real-world application scenarios, generates a load state sequence including idle, intermediate, and peak states, under the constraints of the initial load parameters. During the generation process, the load generation model appropriately sets the duration of each load state, the switching threshold between load states, and the transition method, enabling the load state sequence to realistically simulate the dynamic changes of the processor during actual operation, from low load to high load, and from stable operation to sudden peaks. For example, it transitions from an almost unattended idle state to an intermediate state of moderate computation, then suddenly switches to a peak state of full load operation, and subsequently falls back to the intermediate state, forming a complete load fluctuation cycle.

[0049] Furthermore, during the generation of load state sequences, the load generation model can also refer to the processor's work logs to simulate load states under different scenarios such as cloud computing and artificial intelligence computing, generating load state sequences that are closer to real-world applications. For example, for cloud computing scenarios, it can simulate load fluctuations during multi-user task concurrency. For artificial intelligence computing scenarios, it can simulate the large-scale matrix operation load during model training and the input-output intensive load during the data preprocessing stage.

[0050] This method of generating load state sequences based on real-world application data makes performance test results more valuable, helping developers more accurately assess the processor's actual performance in target application scenarios. Furthermore, this scenario-based testing approach can expose potential performance bottlenecks in specific operating modes, providing data support for subsequent architecture optimization.

[0051] When testing the processor, the test procedure is executed according to the changing order of the load states in the generated load state sequence. When the load state sequence indicates the entry into a specific load state, the intensity and type of the test task are immediately adjusted to place the processor at the load level corresponding to that load state, and various performance data are stably collected during the duration of that load state. When the load state sequence indicates a load state transition, the test task is smoothly transitioned to ensure that the load change conforms to the rhythm set in the sequence, while the processor's response during the state transition is recorded, thereby comprehensively capturing the processor's performance under different load fluctuation scenarios.

[0052] By configuring and initializing load parameters according to the processor hardware specifications, and then generating a load state sequence simulating idle, intermediate, and peak state switching under the constraints of the initial load parameters through a load generation model, the hardware characteristics can be accurately matched, the real load state switching scenario can be reproduced, the relevance and realism of the load simulation can be improved, and reliable scenario support can be provided for comprehensive testing of processor performance.

[0053] According to an embodiment of the present invention, there are multiple test cases; according to the task processing type of the test parameters, the test cases constructed based on the test parameters are distributed to the corresponding logical partitions in the processor for execution, including: sending multiple test cases to the task scheduler, so as to distribute each test case to the corresponding logical partition in the processor for execution according to the preset mapping relationship between the task processing type and the logical partition stored in the task scheduler, wherein the task processing type includes computing type and storage type.

[0054] After constructing multiple test cases, these test cases are sent to the task scheduler. The task scheduler pre-stores a complete set of preset mapping relationships, which clearly define the correspondence between different task processing types and the logical partitions within the processor. The task processing types are mainly divided into computational types and storage types. Computational types cover various tasks that require a large amount of computation, while storage types involve data reading and writing, caching operations, and other storage-related tasks.

[0055] Upon receiving test cases, the task scheduler first parses the task processing type of each test case to determine whether it belongs to the computation or storage type. Then, based on a preset mapping relationship, it finds the logical partition that matches the task processing type. For example, computation-type tasks are assigned to a logical partition specifically responsible for computation, while storage-type tasks are distributed to a logical partition focused on data storage and access.

[0056] After matching is complete, the task scheduler accurately distributes each test case to its corresponding logical partition, ensuring that each test case can be executed in a region of the processor suitable for its type. This type-based precise distribution mechanism not only fully leverages the specialized processing capabilities of different logical partitions but also avoids resource waste caused by chaotic task allocation, thereby improving the efficiency and accuracy of the entire testing process.

[0057] Figure 3 A schematic diagram of test case distribution in a processor testing method according to an embodiment of the present invention is shown.

[0058] like Figure 3 As shown, the task scheduler first parses the received test cases, identifies the task processing type, and determines whether it is a computational task (such as matrix multiplication, ray tracing, etc.) or a storage task (such as memory bandwidth testing, data persistence, etc.). Subsequently, the task scheduler, according to a preset mapping relationship, assigns computational tasks to dedicated partition 1 and storage tasks to partition 2 for execution.

[0059] The entire scheduling process utilizes a lightweight task processing type identification mechanism and a logical partition matching mechanism to ensure that tasks can quickly locate the appropriate processing area. Each partition, based on its own hardware optimization characteristics, focuses on processing the corresponding type of task.

[0060] By strategically matching task processing types with logical partitions, resource contention between different task types is effectively reduced, allowing for efficient utilization of computing and storage resources, thereby improving overall task processing efficiency. Furthermore, the partitioned, focused processing mode reduces system overhead from switching between task types and minimizes redundant operations in resource scheduling. Simultaneously, targeted task allocation better matches hardware resource characteristics with task requirements, further optimizing system performance and stability.

[0061] According to an embodiment of the present invention, when the test cases are used to test the performance of mixed-precision matrix multiplication, the method further includes: calling the mixed-precision computing kernel module to generate test cases based on the dynamic matrix size parameter in the test parameters; wherein, the mixed-precision computing kernel module generates test cases through the following configuration: constructing a parallel matrix multiplication kernel according to the rule of alternating execution of half-precision calculation and single-precision calculation, so that the processor executes the parallel matrix multiplication kernel, and adaptively adjusting the thread grid dimension of the parallel matrix multiplication kernel during execution to match the dynamic matrix size parameter.

[0062] When test cases are used to test the performance of mixed-precision matrix multiplication, the dynamic matrix size parameter included in the test parameters is read. This dynamic matrix size parameter determines the dimensional range and variation rules of the matrix during the test. Based on the dynamic matrix size parameter, a pre-built mixed-precision calculation kernel module is invoked, which is responsible for generating the corresponding test cases.

[0063] The core configuration of the mixed-precision computing kernel module revolves around the construction and dynamic adjustment of the parallel matrix multiplication kernel. The mixed-precision computing kernel module first follows the rule of alternating between half-precision and single-precision computations, designing parallel computing logic in the underlying architecture. Specifically, for different computation stages or different sub-matrix blocks in the matrix multiplication process, half-precision (e.g., FP16) and single-precision (e.g., FP32) modes are used alternately for computation. This leverages the efficiency of half-precision computation to improve processing speed while ensuring the computational accuracy of critical parts through single-precision computation.

[0064] After generating the parallel matrix multiplication kernel, the mixed-precision computing kernel module monitors changes in the dynamic matrix size parameter in real time. When the dynamic matrix size parameter indicates an increase or decrease in matrix size, the mixed-precision computing kernel module adaptively adjusts the kernel's thread grid dimension. Specifically, it changes the number of thread blocks, the number of threads per thread block, and the collaboration method between threads to match the parallel processing capability of the thread grid with the current matrix size. For example, when the dynamic matrix size parameter indicates an increase in matrix dimension, the number of thread blocks is appropriately increased to improve parallelism; when the dynamic matrix size parameter indicates a decrease in matrix dimension, thread allocation is optimized to reduce resource idleness. Through this configuration, the mixed-precision computing kernel module can generate test cases adapted to the dynamic matrix size parameter, accurately testing the processor's performance in mixed-precision matrix multiplication scenarios.

[0065] According to an embodiment of the present invention, when the test cases are used to test video memory pressure, the method further includes: calling the video memory load module to generate test cases according to the video memory access parameters in the test parameters; wherein, the video memory load module generates test cases through the following configuration: allocating an unaligned video memory buffer corresponding to the video memory access parameters, and constructing a multi-threaded cyclic read-write operation sequence so that the processor concurrently accesses the unaligned video memory buffer according to the multi-threaded cyclic read-write operation sequence.

[0066] When test cases are used to test memory stress, the memory access parameters in the test parameters are parsed. These memory access parameters include key indicators such as target memory utilization, data transfer bandwidth, access frequency, and read / write ratio. Based on these memory access parameters, the memory load module is invoked, which is responsible for generating corresponding test cases to simulate memory access scenarios of different intensities and modes.

[0067] The core configuration of the memory load module focuses on the allocation of unaligned memory buffers and the construction of multi-threaded access sequences. The memory load module first allocates unaligned memory buffers in the video memory according to the memory size and distribution characteristics specified in the memory access parameters. The starting address and size of these unaligned memory buffers do not match the natural alignment boundaries of the video memory, thus simulating irregular memory allocation patterns in real-world applications and increasing the processing load on the memory controller.

[0068] After allocating the unaligned memory buffer, the memory load module constructs a multi-threaded cyclic read / write operation sequence. Based on the set number of threads and concurrency level, a specific memory access range and operation type (read or write) are allocated to each thread, and the cyclic execution access logic is designed. When the processor executes these test cases, multiple threads will concurrently access the unaligned memory buffer according to the multi-threaded cyclic read / write operation sequence. By continuously consuming memory bandwidth and triggering memory page swapping through read / write operations, the processing capability of the memory controller under high concurrency and irregular access scenarios is tested, thus comprehensively testing the processor's performance under different memory pressures and effectively improving the depth of memory performance evaluation.

[0069] According to an embodiment of the present invention, when the test cases are used to test the performance of mixed load control, the method further includes: calling the parallel scheduling module to generate test cases based on the task execution ratio and asynchronous execution parameters in the test parameters; wherein, the parallel scheduling module generates test cases through the following configuration: based on the asynchronous execution parameters, associating the created computing task queue and video memory operation queue with the asynchronous execution mechanism of the processor, so that the processor executes the tasks in the computing task queue and video memory operation queue according to the task execution ratio.

[0070] When test cases are used to test the performance of mixed load control, the task execution ratio and asynchronous execution parameters are extracted from the test parameters. The task execution ratio specifies the quantity or time allocation ratio of computation tasks to memory operation tasks. The asynchronous execution parameters include task scheduling interval, concurrency limit, synchronization point settings, etc. Based on the test parameters, the parallel scheduling module is invoked, which is responsible for generating corresponding test cases to simulate a mixed load scenario where computation and memory operations are intertwined.

[0071] The core configuration of the parallel scheduling module revolves around the relationship between the task queue and the processor's asynchronous mechanism. First, the parallel scheduling module creates independent computation task queues and memory operation queues based on testing requirements. The computation task queues contain computationally intensive tasks such as various arithmetic operations and matrix processing, while the memory operation queues cover tasks that interact with memory, such as data loading, storage, and copying. Then, based on asynchronous execution parameters, the parallel scheduling module establishes a connection between the computation task queues and the memory operation queues and the processor's asynchronous execution mechanism. Specifically, by configuring the processor's asynchronous engine interface, computation tasks and memory operation tasks can be initiated independently and executed in parallel, allowing subsequent tasks to start without waiting for the completion of preceding tasks.

[0072] During the task execution phase, the parallel scheduling module dynamically adjusts the dequeueing pace and execution priority of tasks in the two queues based on a preset task execution ratio. For example, when the task execution ratio is set to 60% computation tasks and 40% memory operation tasks, the parallel scheduling module will adjust the task distribution frequency to ensure that the two types of tasks executed by the processor within a unit of time conform to this ratio. Simultaneously, leveraging the characteristics of asynchronous execution, the processor can perform memory operations in parallel in the background while executing computation tasks. This tests the processor's resource coordination capabilities, task switching efficiency, and overall performance under mixed load scenarios, generating test cases that accurately reflect the performance of mixed load control and achieving precise adaptation between test cases and processor parameters.

[0073] According to an embodiment of the present invention, the processor testing method further includes: when it is determined that multiple load states in the load state sequence have been tested and the cumulative test duration has not reached the preset duration configured in the initial load parameters, dynamically generating an updated state sequence through a load generation model; adding the updated state sequence to the end of the load state sequence in the form of a queue, continuing to execute the test until the cumulative test duration reaches the preset duration, and outputting the test result.

[0074] During testing, the completion status of each load state in the load state sequence is monitored in real time, and the cumulative test duration is recorded. When it is confirmed that all load states in the load state sequence have completed testing, and the cumulative test duration has not yet reached the preset duration configured in the initial load parameters, the load generation model is triggered to run again.

[0075] At this point, the load generation model dynamically generates a new updated state sequence based on the characteristics of the completed load states, processor performance data feedback, and remaining test time. This updated state sequence will continue the previous load fluctuation pattern and may introduce new combinations of load features to ensure the comprehensiveness and continuity of the test.

[0076] The generated updated state sequence will be added to the end of the original load state sequence in the form of a queue, forming an extended load state sequence. Then, the test will continue to be executed according to the new sequence, repeating the process of load state switching, data collection and analysis.

[0077] This dynamic scaling process will continue until the cumulative test duration reaches the preset duration. At this point, the test process will terminate, and all test data and results collected in all test phases will be integrated to finally output complete processor test results. This ensures that the test results reflect the long-term operating performance of the processor, effectively improving the completeness and continuity of the test.

[0078] Figure 4A flowchart of a processor testing method according to an embodiment of the present invention is shown.

[0079] like Figure 4 As shown, this embodiment includes operations S411 to S417.

[0080] In operation S411, configure and initialize load parameters. In operation S412, generate a load state sequence. In operation S413, execute tests sequentially according to the order of load state changes in the load state sequence.

[0081] In operation S414, determine whether the test is complete. If complete, proceed to operation S415. If not complete, return to operation S413.

[0082] In operation S415, determine whether the cumulative test duration has reached the preset duration. If it has, proceed to operation S417. If it has not, proceed to operation S416.

[0083] In operation S416, update the load state sequence. In operation S417, output the test results.

[0084] According to an embodiment of the present invention, before performing processor testing, it is necessary to configure initialization load parameters. Based on the initialization load parameters, a load state sequence is generated through a load generation model, and the duration and state switching rules of each load state are defined. During the testing process, the corresponding tests are executed sequentially according to the order of the load states in the load state sequence, and performance data is recorded in real time.

[0085] After testing all load states in the current load state sequence, it is necessary to confirm whether the test is complete. If the test is not yet complete, continue execution according to the original sequence. If the test is complete, check whether the cumulative test duration has reached the preset duration. If the preset duration has been reached, integrate all data and output the final test results. If the preset duration has not been reached, call the load generation model to generate a new load state sequence, append it to the end of the original sequence, and then continue the test process.

[0086] By dynamically generating and updating the load state sequence, the test can cover a sufficient number of load scenarios, while strictly controlling the cumulative test duration within the preset duration, thus balancing the comprehensiveness of the test with the time cost.

[0087] According to an embodiment of the present invention, the processor testing method further includes: adding a disturbance factor to the load operating environment of the corresponding logical partition to cause disturbance to the load state during the execution of test cases.

[0088] During test case execution, the current state of the load environment of the logical partitions running test tasks on the processor is monitored in real time, including task execution progress, resource usage levels, and data flow efficiency. Based on these real-time states, various disturbance factors are dynamically generated. These disturbance factors cover types such as sudden increases in computing tasks, fluctuations in data transmission latency, temporary resource preemption, and random adjustments to instruction execution priorities. The strength and mode of action of each disturbance factor are adapted to the characteristics of the current load state.

[0089] Subsequently, these perturbation factors are added in an orderly manner to the load operating environment of the corresponding logical partition. For example, when the logical partition is in a high-load peak state, a small-scale resource preemption perturbation may be introduced to simulate the temporary occupation of resources by other processes. In intermediate states, incremental perturbations of computing tasks may be added to test the processor's ability to adjust when the load suddenly increases. The process of adding perturbation factors is coordinated with the execution rhythm of the current test cases, so as not to interrupt the normal test process, but to realistically simulate the environmental fluctuations that may occur in actual operation, thereby more comprehensively testing the processor's stability and fault tolerance under complex load conditions.

[0090] According to an embodiment of the present invention, the test results of the processor under load are determined by analyzing the test data generated during the execution process, including: performing multi-dimensional detection on the generated performance data during the processor testing process to obtain test data, wherein the multi-dimensional detection includes at least two of the following: operating temperature detection, average power consumption detection, and calculation error rate detection; and comparing and analyzing the test data with the corresponding standard thresholds in a preset threshold set to generate test results.

[0091] During processor testing, a multi-dimensional data acquisition mechanism is simultaneously activated to monitor and record performance data generated during the test in real time, forming complete test data. This multi-dimensional monitoring includes at least the following two aspects: Operating temperature monitoring: Temperature sensors deployed on the processor core and surrounding circuitry continuously collect real-time temperature values ​​from different areas, generating temperature change curves. Average power consumption monitoring: A power consumption monitoring module records energy consumption data per unit time, calculating the average power consumption during the test period. Error rate monitoring: For the computational tasks executed by the processor, the output results are compared with preset standard answers, and the number of computational errors is counted and the error rate is calculated.

[0092] After acquiring multi-dimensional test data, a preset threshold set is invoked. This set includes standard thresholds corresponding to various test indicators, such as the upper limit of the processor's safe operating temperature (e.g., 85℃), normal power consumption range, and acceptable calculation error rate threshold (e.g., 0.01%). Subsequently, the test data is compared and analyzed one by one with the corresponding standard thresholds in the preset threshold set. If a test data point does not exceed its corresponding standard threshold, the indicator is considered to be performing normally. If it exceeds the standard threshold, it is marked as abnormal, and the degree of deviation is recorded.

[0093] By comparing the results of various indicators, a comprehensive test result is generated, which not only includes the specific values ​​and compliance status of each detection indicator, but also analyzes the possible impact of abnormal indicators and the correlation between indicators of different dimensions, thereby providing a basis for evaluating the overall performance of the processor under test load.

[0094] According to an embodiment of the present invention, the performance data includes temperature data, power consumption data, and error data; wherein, the temperature data is obtained through a temperature sensor built into the processor, the power consumption data is obtained through the communication bus of the power management integrated circuit in the processor, and the error data is obtained through the processor's memory error correction counter.

[0095] The performance data collected during processor testing covers three core metrics: temperature data, power consumption data, and error data. Each type of data is acquired through targeted collection methods. Temperature data originates from the processor's built-in temperature sensors, which are distributed across key areas such as the core computing unit and memory controller. These sensors can detect temperature changes in various components in real time, converting analog signals into digital data, which is then transmitted to the testing system via the processor's internal monitoring interface to form a complete record of temperature changes.

[0096] The acquisition of power consumption data relies on the power management integrated circuit (IC) in the processor, which is responsible for dynamically regulating the processor's power supply. The test system establishes data interaction through a communication bus connected to the power management IC, reads parameters such as power supply voltage and current in real time, and then calculates the energy consumption value per unit time, i.e., power consumption data, using the power calculation formula.

[0097] Error data is primarily acquired through the processor's memory error correction counter. During memory read / write operations, if data errors occur, the processor's error correction mechanism automatically corrects them and records the number, type, and location of the errors via a counter. The testing system reads the real-time data from this counter and organizes it into error data, thereby reflecting the stability of memory data transfer and storage. These three types of data together constitute the key basis for evaluating processor performance and stability, providing comprehensive raw information for subsequent testing and analysis.

[0098] According to an embodiment of the present invention, the processor testing method further includes: determining the coverage of test cases to dynamic load scenarios in the processor; inputting the coverage and the execution time of test cases in logical partitions into a target reward function and outputting a reward value; and dynamically optimizing the model parameters of the parameter configuration model based on the reward value.

[0099] When evaluating the effectiveness of test cases, it is necessary to determine their coverage of dynamic processor load scenarios. Specifically, the load states covered by the test cases are compared with a preset set of dynamic load scenarios to determine the coverage. The comparison process covers multiple dimensions such as load intensity range, state switching frequency, and concurrent task types. Finally, the coverage is quantified as a percentage, reflecting the degree to which the test cases cover actual dynamic load scenarios.

[0100] Subsequently, the calculated coverage rate and the actual execution time of the test cases in the corresponding logical partitions are input into the target reward function. The target reward function sets weight parameters according to testing requirements and performs a comprehensive calculation on coverage and execution time. Specifically, high coverage usually corresponds to a higher reward value, while excessively long execution times will proportionally reduce the reward value, thus balancing the comprehensiveness and efficiency of the test. After calculation, the target reward function outputs a specific reward value as a quantitative indicator to measure the quality of the current test cases and their corresponding parameter configurations.

[0101] Based on the output reward value, the model parameters of the parameter configuration model are dynamically optimized. If the reward value is high, it indicates that the test cases generated by the current parameter configuration perform well, and the parameter configuration model will retain the core parameters and fine-tune the details to enhance the effect. If the reward value is low, the weight coefficients, threshold parameters, etc. in the parameter configuration model are adjusted through the backpropagation algorithm to optimize the parameter mapping relationship. This allows the parameter configuration model to more accurately balance coverage and execution efficiency when generating test parameters in subsequent tests, thereby improving the testing effect on dynamic load scenarios.

[0102] Figure 5 A schematic diagram of module interaction of a processor testing method according to an embodiment of the present invention is shown.

[0103] like Figure 5 As shown, when testing the processor 503, the main control module 501 is responsible for the overall process control, including receiving the load status output by the load generation model, managing the test execution process, and outputting the final test results. The main control module 501 passes the completed test cases to the task scheduler 502, which accurately allocates the test cases to the corresponding computing units of the processor 503 for execution according to the matching rules of task processing type and logical partition.

[0104] During the execution of the test task, the processor 503 works in concert with the core group 504, the memory controller 505, and the serial bus interface 506 to collect key performance data such as temperature, power consumption, and error rate in real time, and transmits the raw data to the data acquisition module 507. After the data acquisition module 507 performs structured processing on the data, it stores it in the test database 508 for persistent storage.

[0105] After testing, based on historical data in test database 508, a visual test report containing key indicators such as performance curves and power consumption trends can be automatically generated using visualization tools. Simultaneously, the test system possesses anomaly handling capabilities. For example, when the processor 503's temperature exceeds a safe threshold, the main control module 501 immediately triggers a dynamic frequency reduction protection mechanism, adjusting the clock frequency through the underlying driver interface to ensure system safety, and recording detailed information about the anomaly event in the system log for subsequent analysis.

[0106] During the testing process, the unified scheduling of the main control module 501 enabled automated collaborative work in task allocation, data acquisition, and exception handling, ensuring the efficiency and reliability of the testing process and providing complete technical support for the performance evaluation of the processor 503.

[0107] According to an embodiment of the present invention, the processor testing method further includes: selecting test parameters that meet preset conditions from multiple test parameters using a weighted scoring algorithm based on the core indicators in the test results, as well as the coverage and execution time of the test cases, and using these parameters as recommended configuration parameters.

[0108] When selecting recommended configuration parameters, core metrics are extracted from the test results. These core metrics include key performance data such as peak temperature, average power consumption, and calculation error rate of the processor under different load conditions. At the same time, the coverage and execution time of each test case are summarized to form a multi-dimensional evaluation dataset.

[0109] Subsequently, a weighted scoring algorithm is invoked to assign corresponding weights to each evaluation metric. Core metrics typically receive higher weights to ensure that the recommended parameters prioritize meeting the processor's basic performance requirements. Coverage and execution time are assigned appropriate weights based on the emphasis of the testing objective, balancing the comprehensiveness and efficiency of the test. The weighted scoring algorithm standardizes the actual values ​​of each metric, multiplies them by their corresponding weights, and then sums them to obtain a comprehensive score for each test parameter.

[0110] Finally, based on preset conditions (such as comprehensive scoring thresholds, core indicator compliance requirements, or the top 10% of test parameters with the highest energy efficiency ratio), the comprehensive scores of all test parameters are filtered, and the test parameters that meet the preset conditions are determined as recommended configuration parameters. These recommended configuration parameters not only ensure the stable operation of the processor under load scenarios, but also take into account the comprehensiveness of test coverage and execution efficiency, providing a reference for subsequent processor testing or practical applications.

[0111] Based on the above-described processor testing method, this invention also provides a processor testing apparatus. The following will be combined with... Figure 6 The device is described in detail.

[0112] Figure 6 A structural block diagram of a processor testing apparatus according to an embodiment of the present invention is shown.

[0113] like Figure 6 As shown, the processor testing device 600 of this embodiment includes a state generation module 610, a parameter output module 620, a test case distribution module 630, and a result determination module 640.

[0114] The state generation module 610 is used to generate multiple load states to simulate the aforementioned processor load fluctuations in response to test instructions for the processor. In one embodiment, the state generation module 610 may be used to perform the operation S210 described above, which will not be repeated here.

[0115] The parameter output module 620 is used to take the acquired processor performance data and the load state input parameter configuration model for each of the above-mentioned load states, and output test parameters adapted to the load states. In one embodiment, the parameter output module 620 can be used to perform the operation S220 described above, which will not be repeated here.

[0116] The test case distribution module 630 is used to distribute test cases constructed based on the test parameters to the matching logical partitions in the processor for execution, according to the task processing type of the test parameters. In one embodiment, the test case distribution module 630 can be used to perform the operation S230 described above, which will not be repeated here.

[0117] The result determination module 640 is used to determine the test results of the processor under the aforementioned load state by analyzing the test data generated during the execution process. In one embodiment, the result determination module 640 can be used to perform the operation S240 described above, which will not be repeated here.

[0118] According to embodiments of the present invention, any plurality of modules among the state generation module 610, parameter output module 620, test case distribution module 630, and result determination module 640 may be combined into one module, or any one of these modules may be split into multiple modules. Alternatively, at least part of the functionality of one or more of these modules may be combined with at least part of the functionality of other modules and implemented in one module. According to embodiments of the present invention, at least one of the state generation module 610, parameter output module 620, test case distribution module 630, and result determination module 640 may be at least partially implemented as hardware circuitry, such as a field-programmable gate array (FPGA), a programmable logic array (PLA), a system-on-a-chip, a system-on-a-substrate, a system-on-package, an application-specific integrated circuit (ASIC), or any other reasonable means of integrating or packaging circuitry, or implemented in hardware or firmware, or in any one of software, hardware, and firmware implementations, or in a suitable combination of any of these. Alternatively, at least one of the state generation module 610, parameter output module 620, test case distribution module 630, and result determination module 640 may be implemented at least partially as a computer program module that can perform corresponding functions when the computer program module is run.

[0119] Figure 7 A block diagram of an electronic device suitable for implementing a processor testing method according to an embodiment of the present invention is shown.

[0120] like Figure 7 As shown, an electronic device 700 according to an embodiment of the present invention includes a processor 701, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 702 or a program loaded from a storage portion 708 into a random access memory (RAM) 703. The processor 701 may include, for example, a general-purpose microprocessor (e.g., a CPU), an instruction set processor and / or an associated chipset and / or a special-purpose microprocessor (e.g., an application-specific integrated circuit (ASIC)), etc. The processor 701 may also include onboard memory for caching purposes. The processor 701 may include a single processing unit or multiple processing units for performing different actions of the method flow according to an embodiment of the present invention.

[0121] RAM 703 stores various programs and data required for the operation of electronic device 700. Processor 701, ROM 702, and RAM 703 are interconnected via bus 704. Processor 701 executes various operations of the method flow according to embodiments of the present invention by executing programs in ROM 702 and / or RAM 703. It should be noted that programs may also be stored in one or more memories other than ROM 702 and RAM 703. Processor 701 may also execute various operations of the method flow according to embodiments of the present invention by executing programs stored in one or more memories.

[0122] According to an embodiment of the present invention, the electronic device 700 may further include an input / output (I / O) interface 705, which is also connected to a bus 704. The electronic device 700 may also include one or more of the following components connected to the input / output (I / O) interface 705: an input section 706 including a keyboard, mouse, etc.; an output section 707 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 708 including a hard disk, etc.; and a communication section 709 including a network interface card such as a LAN card, modem, etc. The communication section 709 performs communication processing via a network such as the Internet. A drive 710 is also connected to the input / output (I / O) interface 705 as needed. A removable medium 711, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on the drive 710 as needed so that computer programs read from it can be installed into the storage section 708 as needed.

[0123] The present invention also provides a computer-readable storage medium, which may be included in the device / apparatus / system described in the above embodiments; or it may exist independently and not assembled into the device / apparatus / system. The computer-readable storage medium carries one or more programs, which, when executed, implement the method according to the embodiments of the present invention.

[0124] According to embodiments of the present invention, a computer-readable storage medium may be a non-volatile computer-readable storage medium, such as including, but not limited to: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In the present invention, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. For example, according to embodiments of the present invention, a computer-readable storage medium may include ROM 702 and / or RAM 703 and / or one or more memories other than ROM 702 and RAM 703 described above.

[0125] Embodiments of the present invention also include a computer program product comprising a computer program containing program code for performing the methods shown in the flowchart. When the computer program product is run on a computer system, the program code is used to cause the computer system to implement the processor testing method provided in the embodiments of the present invention.

[0126] When the computer program is executed by the processor 701, it performs the functions defined in the system / apparatus of this invention. According to embodiments of the invention, the systems, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0127] In one embodiment, the computer program may rely on a tangible storage medium such as an optical storage device or a magnetic storage device. In another embodiment, the computer program may also be transmitted and distributed in the form of signals over a network medium, and may be downloaded and installed via the communication section 709, and / or installed from a removable medium 711. The program code contained in the computer program can be transmitted using any suitable network medium, including but not limited to: wireless, wired, etc., or any suitable combination thereof.

[0128] In such an embodiment, the computer program can be downloaded and installed from a network via the communication section 709, and / or installed from the removable medium 711. When the computer program is executed by the processor 701, it performs the functions defined in the system of this embodiment of the invention. According to embodiments of the invention, the systems, devices, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0129] According to embodiments of the present invention, program code for executing the computer programs provided in the embodiments of the present invention can be written in any combination of one or more programming languages. Specifically, these computational programs can be implemented using high-level procedural and / or object-oriented programming languages, and / or assembly / machine languages. Programming languages ​​include, but are not limited to, languages ​​such as Java, C++, Python, "C", or similar programming languages. The program code can be executed entirely on the user's computing device, partially on the user's device, partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0130] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0131] Those skilled in the art will understand that the features described in the various embodiments of the present invention can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in the present invention. In particular, the features described in the various embodiments of the present invention can be combined and / or combined in various ways without departing from the spirit and teachings of the present invention. All such combinations and / or combinations fall within the scope of the present invention.

[0132] The embodiments of the present invention have been described above. However, these embodiments are merely illustrative and not intended to limit the scope of the invention. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the invention, and all such substitutions and modifications should fall within the scope of the invention.

Claims

1. A processor testing method, characterized in that, The method includes: In response to test commands for the processor, multiple load states are generated to simulate load fluctuations of the processor; For each load state, the acquired processor performance data and the load state input parameter configuration model are used to output test parameters adapted to the load state. Based on the task processing type of the test parameters, the test cases constructed based on the test parameters are distributed to the matching logical partitions in the processor for execution; By analyzing the test data generated during execution, the test results of the processor under the load condition are determined; The method further includes: When the test case is used to test the performance of mixed-precision matrix multiplication, the test case is generated based on the dynamic matrix size parameter in the test parameters; When the test case is used to test video memory pressure, the test case is generated based on the video memory access parameters in the test parameters; When the test case is used to test the performance of mixed load control, the test case is generated based on the task execution ratio and asynchronous execution parameters in the test parameters.

2. The method according to claim 1, characterized in that, The multiple load states include an idle state, an intermediate state, and a peak state; the generation of multiple load states for simulating processor load fluctuations includes: Configure the initial load parameters according to the processor's hardware specifications; Using a load generation model, under the constraints of the initial load parameters, a load state sequence is generated to simulate the state switching between the idle state, the intermediate state, and the peak state, so as to simulate the load fluctuation of the processor. During the testing of the processor, the tests are performed sequentially according to the order of changes in the load states in the load state sequence.

3. The method according to claim 1, characterized in that, The test cases are multiple; the step of distributing the test cases constructed based on the test parameters to the matching logical partitions in the processor for execution according to the task processing type of the test parameters includes: Multiple test cases are sent to the task scheduler to distribute each test case to a matching logical partition in the processor for execution, based on a preset mapping relationship between the task processing type and the logical partition stored in the task scheduler. The task processing type includes computation type and storage type.

4. The method according to claim 3, characterized in that, When the test case is used to test the performance of mixed-precision matrix multiplication, the method further includes: Based on the dynamic matrix size parameter in the test parameters, the mixed precision calculation kernel module is invoked to generate the test cases; The mixed-precision computing kernel module generates the test cases through the following configuration: it constructs a parallel matrix multiplication kernel according to the rule of alternating execution of half-precision and single-precision calculations, so that the processor executes the parallel matrix multiplication kernel, and adaptively adjusts the thread grid dimension of the parallel matrix multiplication kernel during execution to match the dynamic matrix size parameter.

5. The method according to claim 3, characterized in that, When the test case is used to test video memory stress, the method further includes: Based on the video memory access parameters in the test parameters, the video memory load module is invoked to generate the test cases; The video memory load module generates the test cases through the following configuration: allocating an unaligned video memory buffer corresponding to the video memory access parameters, and constructing a multi-threaded cyclic read / write operation sequence so that the processor concurrently accesses the unaligned video memory buffer according to the multi-threaded cyclic read / write operation sequence.

6. The method according to claim 3, characterized in that, When the test case is used to test the performance of mixed load control, the method further includes: Based on the task execution ratio and asynchronous execution parameters in the test parameters, the parallel scheduling module is invoked to generate the test cases; The parallel scheduling module generates the test cases through the following configuration: based on the asynchronous execution parameters, it associates the created computing task queue and video memory operation queue with the asynchronous execution mechanism of the processor, so that the processor executes the tasks in the computing task queue and the video memory operation queue according to the task execution ratio.

7. The method according to claim 2, characterized in that, The method further includes: If it is determined that multiple load states in the load state sequence have been tested and the cumulative test duration has not reached the preset duration configured in the initial load parameters, the load generation model is used to dynamically generate and update the state sequence. The updated state sequence is added to the end of the load state sequence in the form of a queue, and the test continues to be executed until the cumulative test duration reaches the preset duration, and the test result is output.

8. The method according to claim 1, characterized in that, The method further includes: During the execution of the test cases, a disturbance factor is added to the load operating environment of the corresponding logical partition to cause disturbance to the load state.

9. The method according to claim 1, characterized in that, The step of determining the test results of the processor under the load state by analyzing the test data generated during execution includes: During the processor testing process, the generated performance data is subjected to multi-dimensional detection to obtain the test data. The multi-dimensional detection includes at least two of the following: operating temperature detection, average power consumption detection, and calculation error rate detection. The test data is compared and analyzed with the corresponding standard thresholds in the preset threshold set to generate the test results.

10. The method according to claim 9, characterized in that, The performance data includes temperature data, power consumption data, and error data; wherein, the temperature data is obtained through the temperature sensor built into the processor, the power consumption data is obtained through the communication bus of the power management integrated circuit in the processor, and the error data is obtained through the memory error correction counter of the processor.

11. The method according to claim 1, characterized in that, The method further includes: Determine the coverage of the test cases for dynamic load scenarios in the processor; Input the coverage rate and the execution time of the test cases in the logical partition into the target reward function, and output the reward value; Based on the reward value, the model parameters of the parameter configuration model are dynamically optimized.

12. The method according to claim 11, characterized in that, The method further includes: Based on the core metrics in the test results, as well as the coverage and execution time of the test cases, a weighted scoring algorithm is used to select test parameters that meet preset conditions from multiple test parameters, which are then used as recommended configuration parameters.

13. An electronic device, comprising: One or more processors; Memory, used to store one or more computer programs. The characteristic feature is that the one or more processors execute the one or more computer programs to implement the steps of the method according to any one of claims 1 to 12.

14. A computer-readable storage medium having a computer program or instructions stored thereon, characterized in that, When the computer program or instructions are executed by a processor, they implement the steps of the method according to any one of claims 1 to 12.

15. A computer program product, characterized in that, It includes a computer program that, when executed by a processor, implements the method according to any one of claims 1 to 12.

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