Memory management method and electronic device

Abstract

The application discloses a memory management method and an electronic device. The method is executed by the electronic device. In the method, a hardware accelerator detects a first event. The first event indicates that a probability of a first DMA memory used by a first application appearing a page fault exception is greater than a first threshold. In response to the first event, the hardware accelerator performs one or more operations: killing a first process of the first application; writing first data of the first application in a disk to the first DMA memory, and updating a first memory page table. The first memory page table includes a mapping from a virtual address on the hardware accelerator side to a physical address on the first DMA memory side. In the application, the hardware accelerator can handle the page fault exception that may occur in the DMA memory, and the memory management efficiency is improved.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and more particularly to a memory management method and an electronic device. Background Technology

[0002] Central processing units (CPUs) in electronic devices and hardware accelerators (such as graphics processing units (GPUs) within system-on-chips (SoCs) can share memory (e.g., direct memory access (DMA) memory) to enable high-speed data transfer between the CPU and the hardware accelerators. Specifically, the hardware accelerators utilize a system memory management unit (SMMU) to map virtual addresses on the hardware accelerator side to physical addresses on the DMA memory side.

[0003] When the CPU or hardware accelerator accesses data in DMA memory, a page fault will occur if the data is not already in that DMA memory. Since the SMMU (Memory Management Unit) lacks the capability for automated hardware handling of page faults, it does not reclaim data from DMA memory managed by the SMMU to prevent page faults from occurring when the hardware accelerator accesses it. This means the data remains in the DMA memory, resulting in a high load on that memory. Therefore, SMMU-managed DMA memory has relatively low memory management efficiency. Summary of the Invention

[0004] This application provides a memory management method and an electronic device to improve memory management efficiency.

[0005] In a first aspect, embodiments of this application provide a memory management method applicable to electronic devices or components (e.g., units / modules, circuits, or chips) within said electronic devices. Taking an electronic device as an example, the method includes: a hardware accelerator of said electronic device detecting a first event; wherein the first event indicates that the probability of a page fault occurring in a first DMA memory used by a first application is greater than a first threshold; in response to the first event, said hardware accelerator performing a first operation; wherein the first operation includes one or more of the following: killing a first process of said first application; writing first data of said first application from the disk to said first DMA memory, and updating a first memory page table according to said first data in said first DMA memory, said first memory page table including a mapping from virtual addresses on the hardware accelerator side to physical addresses on the first DMA memory side.

[0006] In this embodiment, if the hardware accelerator determines that the probability of a page fault occurring in the DMA memory used by the application is greater than a first threshold, where the first threshold is greater than or equal to zero (the first threshold can be pre-configured or standard-defined), meaning that a page fault may occur in the DMA memory used by the application, the hardware accelerator can handle the potential page fault by instructing the CPU to kill the application's process; alternatively, the hardware accelerator can preemptively swap the application's data from the DMA memory to the disk, and then rewrite all or part of the application's data from the disk back into the DMA memory (e.g., full page write or single page write) and update the SMMU page table to handle the potential page fault. In other words, the hardware accelerator can handle potential page faults in the DMA memory, thus allowing it to reclaim the application's data from the DMA memory when the DMA memory is heavily loaded, thereby improving memory management efficiency.

[0007] In one possible implementation, the first event includes the first application's running state switching from a frozen state to a non-frozen state; and / or, the first event includes the data corresponding to the first virtual address to be accessed by the central processing unit (CPU) of the electronic device not being stored in the first DMA memory.

[0008] This implementation provides multiple ways for the hardware accelerator to determine if a page fault might occur in the DMA memory used by an application. For example, if the application's running state changes from frozen to unfrozen, it indicates a high probability that the user will operate the application within a short period. Similarly, the CPU and hardware accelerator are likely to access some or all of the application's data in the DMA memory within that short period. If the data accessed by the CPU and hardware accelerator is not in the DMA memory, a page fault will occur. Another example is monitoring a virtual address that the CPU wants to access; if the data corresponding to that virtual address is not in the DMA memory, a page fault will occur. This makes the hardware accelerator's methods for determining if a page fault might occur in the DMA memory more flexible.

[0009] In one possible implementation, the first data is either the second data or the third data, the second data includes the third data, the second data is all the data of the first application stored in the disk, the third data is part of the data of the first application stored in the disk, and the part of the data is the data corresponding to the first virtual address that the CPU of the electronic device needs to access.

[0010] In this implementation, the hardware accelerator handles page faults that may occur in the DMA memory used by the application in various ways. For example, it can rewrite all the application's data from the disk into the DMA memory. Or, it can rewrite a portion of the application's data from the disk (i.e., the data of the application that the CPU needs to access) into the DMA memory, making the hardware accelerator's handling of page faults in the DMA memory more flexible.

[0011] In one possible implementation, before the hardware accelerator detects the first event, the method further includes: the hardware accelerator detecting a second event; wherein the second event includes the first application's running state switching from a non-frozen state to a frozen state; in response to the second event, the hardware accelerator swaps the second data in the first DMA memory to the disk, and updates the first memory page table according to the second data in the disk.

[0012] In this implementation, the hardware accelerator can manage the DMA memory used by the application based on its running state to ensure the application's performance in the corresponding running state as much as possible. For example, if the application's running state changes from a non-frozen state to a frozen state, it indicates that the probability of the user operating the application in a short period of time is low, and the probability of the CPU and hardware accelerator accessing some or all of the application's data in the DMA memory in a short period of time is also low. Therefore, the hardware accelerator can perform a swap-out operation on some or all of the application's data in the DMA memory, for example, swapping it out to disk and updating the SMMU page table, thereby reducing the load on the DMA memory.

[0013] In one possible implementation, the first DMA memory includes a first buffer queue, and the second data is stored in the first buffer queue; the hardware accelerator swaps the second data in the first DMA memory to the disk, including: the hardware accelerator detecting a third event; wherein the third event indicates that the data in the first DMA memory is no longer being updated, and / or, the identifier of each buffer area in the first buffer queue is a first identifier, the first identifier being used to indicate that the data in the corresponding buffer area can be swapped out to the disk by the hardware accelerator; in response to the third event, the hardware accelerator swaps out the data in each buffer area of ​​the first buffer queue to the disk.

[0014] In this implementation, when the hardware accelerator swaps out some or all of the application's data from the DMA memory used by the application to the disk, it can determine whether the data is safe data—that is, data that the CPU and hardware accelerator will not access in the short term. Only if the data is safe will it be swapped out to the disk, thus avoiding interference with normal access by the CPU and hardware accelerator. For example, if the data in the DMA memory is no longer being updated, it indicates that the data in the DMA memory is in a stable state and will not be accessed by the CPU and hardware accelerator in the short term. Another example is that if each buffer area in the buffer queue storing the data is identified by a first identifier, it indicates that the data in each buffer area of ​​the buffer queue is in a stable state and will not be accessed by the CPU and hardware accelerator in the short term.

[0015] In one possible implementation, the hardware accelerator updates the first memory page table based on the second data in the disk, including: the hardware accelerator deleting the mapping from the second virtual address to the first physical address in the first memory page table; wherein the second virtual address is the virtual address corresponding to the second data on the hardware accelerator side, and the first physical address is the physical address corresponding to the second data on the first DMA memory side.

[0016] In this implementation, after the hardware accelerator swaps out some or all of the application's data from the DMA memory used by the application to the disk, it can delete the mapping associated with that data in the SMMU page table (i.e., unmap it). Since the hardware accelerator accesses the DMA memory through the SMMU page table, this avoids affecting the normal access of the hardware accelerator.

[0017] In one possible implementation, the first data is the second data, and the hardware accelerator writes the first data from the disk to the first DMA memory, including: the hardware accelerator writes the second data from the disk to a second buffer queue in the first DMA memory.

[0018] In this implementation, a method is provided for a hardware accelerator to rewrite application data from disk into the DMA memory used by the application. For example, the data can be rewritten into a buffer queue of the DMA memory.

[0019] In one possible implementation, the method further includes: the hardware accelerator detecting a fourth event; wherein the fourth event indicates that the data in the first buffer region of the first buffer queue is different from the data in the first buffer region of the second buffer queue, and / or that the data in the last buffer region of the first buffer queue is different from the data in the last buffer region of the second buffer queue, the first buffer queue being the buffer queue in which the second data was stored before being swapped out from the first DMA memory to the disk; in response to the fourth event, the hardware accelerator kills the first process of the first application.

[0020] In this implementation, before the hardware accelerator swaps some or all of the application's data from the DMA memory used by the application to the disk, this data is stored in buffer queue 1 of the DMA memory. After the hardware accelerator rewrites some or all of the application's data from the disk back into the DMA memory, this data is stored in buffer queue 2 of the DMA memory. Therefore, the hardware accelerator determines whether the data read from the disk is correct by comparing the data in buffer queue 1 with the data in buffer queue 2. If they are different, it indicates that the data read from the disk is incorrect, and the hardware accelerator can instruct the CPU to terminate the application process to handle potential page faults. Furthermore, the hardware accelerator can improve its judgment efficiency by comparing only the data in the first and last buffer regions.

[0021] In one possible implementation, the method further includes: the hardware accelerator detecting a fifth event; wherein the fifth event indicates that data in a first buffer region of a first buffer queue is the same as data in a first buffer region of a second buffer queue, and that data in a last buffer region of the first buffer queue is the same as data in a last buffer region of the second buffer queue, the first buffer queue being the buffer queue in which the second data was previously swapped out from the first DMA memory to the disk; in response to the fifth event, the hardware accelerator updates the first memory page table based on the second data in the first DMA memory.

[0022] In this implementation, before the hardware accelerator swaps out some or all of the application's data from the DMA memory used by the application to the disk, this data is stored in buffer queue 1 within the DMA memory. After the hardware accelerator rewrites the application's data from the disk back into the DMA memory, this data is stored in buffer queue 2 within the DMA memory. Therefore, the hardware accelerator determines whether the data read from the disk is correct by comparing the data in buffer queue 1 with the data in buffer queue 2. If they are the same, it indicates that the data read from the disk is correct, and the hardware accelerator can update the SMMU page table, thereby avoiding affecting the normal access of the hardware accelerator. Furthermore, the hardware accelerator can compare the data in only the first and last buffer regions, thereby improving the efficiency of the hardware accelerator's judgment.

[0023] In one possible implementation, the hardware accelerator updates the first memory page table based on the first data in the first DMA memory, including: the hardware accelerator adding a mapping from a second virtual address to a first physical address to the first memory page table; wherein the second virtual address is the virtual address corresponding to the second data on the hardware accelerator side, and the first physical address is the physical address corresponding to the second data on the first DMA memory side.

[0024] In this implementation, after the hardware accelerator rewrites some or all of the application's data from the disk into the DMA memory used by the application, it can add a mapping (i.e., remapping) related to that part or all of the data in the SMMU page table. Since the hardware accelerator accesses the DMA memory through the SMMU page table, this avoids affecting the normal access of the hardware accelerator.

[0025] In one possible implementation, the first data is the third data, and the hardware accelerator writes the first data from the disk to the first DMA memory, including: the hardware accelerator queries a second memory page table based on the first virtual address to obtain a third virtual address; wherein, the second memory page table includes a mapping from virtual addresses on the CPU side to virtual addresses on the hardware accelerator side, and the third virtual address is the virtual address corresponding to the third data on the hardware accelerator side; the hardware accelerator accesses the third data from the disk based on the third virtual address and writes the third data from the disk to the first DMA memory.

[0026] In this embodiment, a method is provided for a hardware accelerator to rewrite data of an application accessed by the CPU from the disk into the DMA memory used by the application. For example, the hardware accelerator determines the virtual address of the data on the hardware accelerator side based on a memory page table that includes a mapping from virtual addresses on the CPU side to virtual addresses on the hardware accelerator side, and determines the storage area of ​​the data on the disk based on the virtual address of the data on the hardware accelerator side, so as to realize the rewriting of the data from the disk into the DMA memory.

[0027] In one possible implementation, the hardware accelerator updates the first memory page table based on the first data in the first DMA memory, including: the hardware accelerator adding a mapping from a third virtual address to a second physical address in the first memory page table; wherein the third virtual address is the virtual address corresponding to the third data on the hardware accelerator side, and the second physical address is the physical address corresponding to the third data on the first DMA memory side.

[0028] In this implementation, after the hardware accelerator rewrites the data of the application that the CPU needs to access from the disk into the DMA memory used by the application, it can add a mapping related to the data in the SMMU page table (i.e., remapping). Since the hardware accelerator accesses the DMA memory through the SMMU page table, this avoids affecting the normal access of the hardware accelerator.

[0029] In one possible implementation, the method further includes: when the first application switches from foreground to background operation and the first application is not running a background task, the hardware accelerator determines that the running state of the first application switches from a non-frozen state to a frozen state; or, when the first application switches from background to foreground operation or the first application is running a background task, the hardware accelerator determines that the running state of the first application switches from a frozen state to a non-frozen state.

[0030] This implementation provides multiple ways for the hardware accelerator to determine the running state of an application. For example, if the application switches from foreground to background and no longer runs tasks, it indicates that the application's running state has switched from a non-frozen state to a frozen state. Alternatively, if the application switches from background to foreground, or switches from foreground to background but is still running tasks, it indicates that the application's running state has switched from a frozen state to a non-frozen state. This makes the way the hardware accelerator determines the running state of an application more flexible.

[0031] Secondly, embodiments of this application also provide an electronic device, the electronic device including a processor, a memory, and one or more programs; wherein the one or more programs are stored in the memory, and the one or more programs include instructions that, when executed by the processor, cause the electronic device to perform the method described in the first aspect or any possible design of the first aspect.

[0032] Thirdly, embodiments of this application also provide a computer-readable storage medium for storing a computer program that, when run on a computer, causes the computer to perform the method described in the first aspect or any possible design of the first aspect.

[0033] Fourthly, embodiments of this application also provide a computer program product, including a computer program that, when run on a computer, causes the computer to perform the method described in the first aspect or any possible design of the first aspect.

[0034] Fifthly, embodiments of this application also provide a chip system including a processor and an interface, the processor being configured to call and execute instructions from the interface to cause the chip system to perform the methods described in the first aspect or any possible design of the first aspect.

[0035] The beneficial effects of the second to fifth aspects and their possible designs can be referred to the description of the beneficial effects of the methods described in the first aspect and any possible design. Attached Figure Description

[0036] Figure 1 A schematic diagram of the hardware structure of an electronic device provided in an embodiment of this application;

[0037] Figure 2 A schematic diagram of the software structure of an electronic device provided in an embodiment of this application;

[0038] Figure 3 This is a schematic diagram illustrating a data transfer from the CPU to a hardware accelerator via DMA memory, provided as an embodiment of this application.

[0039] Figure 4 A schematic diagram of a first DMA memory provided in an embodiment of this application;

[0040] Figure 5 A schematic diagram illustrating a page fault in a first DMA memory according to an embodiment of this application;

[0041] Figure 6 A flowchart illustrating a memory management method provided in an embodiment of this application;

[0042] Figure 7 A schematic diagram of a first buffer queue provided in an embodiment of this application;

[0043] Figure 8 This is a schematic diagram illustrating the swapping of some or all of the data of a first application in a first DMA memory to a disk, as provided in an embodiment of this application.

[0044] Figure 9 This application provides a schematic diagram of a first DMA memory page table;

[0045] Figure 10 A schematic diagram illustrating a hardware accelerator managing a first DMA memory, provided as an embodiment of this application;

[0046] Figure 11 This application provides a schematic diagram for comparing data in a first buffer queue and a second buffer queue;

[0047] Figure 12 A schematic diagram illustrating another hardware accelerator managing the first DMA memory, provided as an embodiment of this application;

[0048] Figure 13 A schematic diagram illustrating yet another hardware accelerator managing a first DMA memory, provided as an embodiment of this application;

[0049] Figure 14 This is a schematic diagram illustrating the writing of some or all of the data of a first application in a disk to a first DMA memory, as provided in an embodiment of this application.

[0050] Figure 15 This is a schematic diagram of the hardware structure of another electronic device provided in an embodiment of this application. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the embodiments of this application will be further described in detail below with reference to the accompanying drawings.

[0052] The technical solutions provided in the embodiments of this application can be applied to electronic devices. Electronic devices can be mobile phones, tablets, desktop computers, laptop computers, handheld computers, notebook computers, ultra-mobile personal computers (UMPCs), netbooks, as well as cellular phones, personal digital assistants (PDAs), augmented reality (AR) devices, virtual reality (VR) devices, artificial intelligence (AI) devices, wearable devices, in-vehicle devices, smart home devices, and / or smart city devices. The embodiments of this application do not impose any special limitations on the specific type of electronic device.

[0053] For example, Figure 1 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of this application.

[0054] like Figure 1 As shown, the electronic device may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, a headphone jack 170D, a sensor module 180, buttons 190, a motor 191, an indicator 192, a camera 193, a display screen 194, and a subscriber identification module (SIM) card interface 195, etc. The sensor module 180 may include a pressure sensor 180A, a gyroscope sensor 180B, a barometric pressure sensor 180C, a magnetic sensor 180D, an accelerometer sensor 180E, a distance sensor 180F, a proximity sensor 180G, a fingerprint sensor 180H, a temperature sensor 180I, a touch sensor 180J, an ambient light sensor 180K, a bone conduction sensor 180L, etc.

[0055] It is understood that the structures illustrated in the embodiments of the present invention do not constitute a specific limitation on the electronic device. In other embodiments of this application, the electronic device may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0056] Processor 110 may include one or more processing units, such as application processors (APs), modem processors, graphics processing units (GPUs), image signal processors (ISPs), controllers, video codecs, digital signal processors (DSPs), baseband processors, and / or neural network processing units (NPUs). These different processing units may be independent devices or integrated into one or more processors.

[0057] The controller can generate operation control signals based on the instruction opcode and timing signals to complete the control of instruction fetching and execution.

[0058] The processor 110 may also include a memory for storing instructions and data. In some embodiments, the memory in the processor 110 is a cache memory. This memory can store instructions or data that the processor 110 has just used or that are used repeatedly. If the processor 110 needs to use the instruction or data again, it can retrieve it directly from the memory. This avoids repeated accesses, reduces the waiting time of the processor 110, and thus improves the efficiency of the system.

[0059] In some embodiments, the processor 110 may include one or more interfaces. Interfaces may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a subscriber identity module (SIM) interface, and / or a universal serial bus (USB) interface, etc.

[0060] The I2C interface is a bidirectional synchronous serial bus, including a serial data line (SDA) and a serial clock line (SCL). In some embodiments, the processor 110 may include multiple I2C buses. The processor 110 can couple to the touch sensor 180J, charger, flash, camera 193, etc., through different I2C bus interfaces. For example, the processor 110 can couple to the touch sensor 180J through the I2C interface, enabling the processor 110 and the touch sensor 180J to communicate through the I2C bus interface, thereby realizing the touch function of the electronic device.

[0061] The I2S interface can be used for audio communication. In some embodiments, the processor 110 may include multiple I2S buses. The processor 110 can be coupled to the audio module 170 via the I2S bus to enable communication between the processor 110 and the audio module 170. In some embodiments, the audio module 170 can transmit audio signals to the wireless communication module 160 via the I2S interface to enable the function of answering phone calls through a Bluetooth headset.

[0062] The PCM interface can also be used for audio communication, sampling, quantizing, and encoding analog signals. In some embodiments, the audio module 170 and the wireless communication module 160 can be coupled via the PCM bus interface. In some embodiments, the audio module 170 can also transmit audio signals to the wireless communication module 160 via the PCM interface, enabling the function of answering phone calls through a Bluetooth headset. Both the I2S interface and the PCM interface can be used for audio communication.

[0063] The UART interface is a universal serial data bus used for asynchronous communication. This bus can be a bidirectional communication bus. It converts the data to be transmitted between serial and parallel communication. In some embodiments, the UART interface is typically used to connect the processor 110 and the wireless communication module 160. For example, the processor 110 communicates with the Bluetooth module in the wireless communication module 160 via the UART interface to implement Bluetooth functionality. In some embodiments, the audio module 170 can transmit audio signals to the wireless communication module 160 via the UART interface to enable music playback through Bluetooth headphones.

[0064] The MIPI interface can be used to connect the processor 110 to peripheral devices such as the display screen 194 and the camera 193. The MIPI interface includes a camera serial interface (CSI) and a display serial interface (DSI). In some embodiments, the processor 110 and the camera 193 communicate via the CSI interface to enable the electronic device to capture images. The processor 110 and the display screen 194 communicate via the DSI interface to enable the electronic device to display images.

[0065] The GPIO interface is configurable via software. It can be configured as a control signal or a data signal. In some embodiments, the GPIO interface can be used to connect the processor 110 to a camera 193, a display screen 194, a wireless communication module 160, an audio module 170, a sensor module 180, etc. The GPIO interface can also be configured as an I2C interface, an I2S interface, a UART interface, a MIPI interface, etc.

[0066] USB port 130 is a USB standard compliant interface, which can be a Mini USB port, Micro USB port, USB Type-C port, etc. USB port 130 can be used to connect a charger to charge electronic devices, and can also be used for data transfer between electronic devices and peripheral devices. It can also be used to connect headphones for audio playback. This interface can also be used to connect other electronic devices, such as AR devices.

[0067] It is understood that the interface connection relationships between the modules illustrated in the embodiments of the present invention are merely illustrative and do not constitute a limitation on the structure of the electronic device. In other embodiments of this application, the electronic device may also employ different interface connection methods or combinations of multiple interface connection methods as described in the above embodiments.

[0068] The charging management module 140 receives charging input from a charger. The charger can be a wireless charger or a wired charger. In some wired charging embodiments, the charging management module 140 receives charging input from the wired charger via a USB interface 130. In some wireless charging embodiments, the charging management module 140 receives wireless charging input via the wireless charging coil of the electronic device. While charging the battery 142, the charging management module 140 can also supply power to the electronic device via the power management module 141.

[0069] The power management module 141 connects the battery 142, the charging management module 140, and the processor 110. The power management module 141 receives input from the battery 142 and / or the charging management module 140, providing power to the processor 110, internal memory 121, display screen 194, camera 193, and wireless communication module 160, etc. The power management module 141 can also monitor parameters such as battery capacity, battery cycle count, and battery health status (leakage current, impedance). In some other embodiments, the power management module 141 may also be located within the processor 110. In other embodiments, the power management module 141 and the charging management module 140 may be located in the same device.

[0070] The wireless communication function of electronic devices can be realized through antenna 1, antenna 2, mobile communication module 150, wireless communication module 160, modem processor and baseband processor, etc.

[0071] Antenna 1 and antenna 2 are used to transmit and receive electromagnetic wave signals. Each antenna in the electronic device can be used to cover one or more communication frequency bands. Different antennas can also be reused to improve antenna utilization. For example, antenna 1 can be reused as a diversity antenna for a wireless local area network. In some other embodiments, the antennas can be used in conjunction with a tuning switch.

[0072] The mobile communication module 150 can provide solutions for wireless communication applications including 2G / 3G / 4G / 5G in electronic devices. The mobile communication module 150 may include at least one filter, switch, power amplifier, low noise amplifier (LNA), etc. The mobile communication module 150 can receive electromagnetic waves via antenna 1, and perform filtering, amplification, and other processing on the received electromagnetic waves before transmitting them to a modem processor for demodulation. The mobile communication module 150 can also amplify the signal modulated by the modem processor and convert it into electromagnetic waves for radiation via antenna 1. In some embodiments, at least some functional modules of the mobile communication module 150 may be housed in processor 110. In some embodiments, at least some functional modules of the mobile communication module 150 and at least some modules of the processor 110 may be housed in the same device.

[0073] The modem processor may include a modulator and a demodulator. The modulator modulates the low-frequency baseband signal to be transmitted into a mid-to-high frequency signal. The demodulator demodulates the received electromagnetic wave signal into a low-frequency baseband signal. The demodulator then transmits the demodulated low-frequency baseband signal to the baseband processor for processing. After processing by the baseband processor, the low-frequency baseband signal is transmitted to the application processor. The application processor outputs sound signals through an audio device (not limited to speaker 170A, receiver 170B, etc.) or displays images or videos through the display screen 194. In some embodiments, the modem processor may be a separate device. In other embodiments, the modem processor may be independent of the processor 110 and may be housed in the same device as the mobile communication module 150 or other functional modules.

[0074] The wireless communication module 160 can provide solutions for wireless communication applications in electronic devices, including wireless local area networks (WLANs) (such as wireless fidelity (Wi-Fi) networks), Bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), and infrared (IR) technologies. The wireless communication module 160 can be one or more devices integrating at least one communication processing module. The wireless communication module 160 receives electromagnetic waves via antenna 2, performs frequency modulation and filtering of the electromagnetic wave signals, and sends the processed signal to processor 110. The wireless communication module 160 can also receive signals to be transmitted from processor 110, perform frequency modulation and amplification, and convert them into electromagnetic waves for radiation via antenna 2.

[0075] In some embodiments, antenna 1 of the electronic device is coupled to mobile communication module 150, and antenna 2 is coupled to wireless communication module 160, enabling the electronic device to communicate with networks and other devices via wireless communication technology. The wireless communication technology may include Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Wideband Code Division Multiple Access (WCDMA), Time-Division Code Division Multiple Access (TD-SCDMA), Long Term Evolution (LTE), BT, GNSS, WLAN, NFC, FM, and / or IR technologies. The GNSS may include Global Positioning System (GPS), Global Navigation Satellite System (GLONASS), BeiDou Navigation Satellite System (BDS), Quasi-Zenith Satellite System (QZSS), and / or Satellite Based Augmentation Systems (SBAS).

[0076] Electronic devices implement display functions through a GPU, a display screen 194, and an application processor. The GPU is a microprocessor for image processing, connecting the display screen 194 and the application processor. The GPU is used to perform mathematical and geometric calculations and for graphics rendering. The processor 110 may include one or more GPUs, which execute program instructions to generate or modify display information.

[0077] Display screen 194 is used to display images, videos, etc. Display screen 194 includes a display panel. The display panel can be a liquid crystal display (LCD). The display panel can also be manufactured using organic light-emitting diodes (OLEDs), active-matrix organic light-emitting diodes (AMOLEDs), flexible light-emitting diodes (FLEDs), miniled, microled, micro-OLEDs, quantum dot light-emitting diodes (QLEDs), etc. In some embodiments, the electronic device may include one or N displays 194, where N is a positive integer greater than 1.

[0078] Electronic devices can achieve shooting functions through ISP, camera 193, video codec, GPU, display 194 and application processor.

[0079] The ISP (Image Signal Processor) is used to process data fed back from the camera 193. For example, when taking a picture, the shutter is opened, and light is transmitted through the lens to the camera's photosensitive element. The light signal is converted into an electrical signal, and the camera's photosensitive element transmits the electrical signal to the ISP for processing, transforming it into an image visible to the naked eye. The ISP can also perform algorithmic optimization of image noise, brightness, and color. The ISP can also optimize parameters such as exposure and color temperature of the shooting scene. In some embodiments, the ISP can be set in the camera 193.

[0080] Camera 193 is used to capture still images or videos. An object is projected onto a photosensitive element by generating an optical image through the lens. The photosensitive element can be a charge-coupled device (CCD) or a complementary metal-oxide-semiconductor (CMOS) phototransistor. The photosensitive element converts the light signal into an electrical signal, which is then passed to an ISP for conversion into a digital image signal. The ISP outputs the digital image signal to a DSP for processing. The DSP converts the digital image signal into image signals in standard RGB, YUV, or other formats. In some embodiments, the electronic device may include one or N cameras 193, where N is a positive integer greater than 1.

[0081] Digital signal processors (DSPs) are used to process digital signals. Besides digital image signals, they can also process other digital signals. For example, when an electronic device is selecting a frequency, a DSP can perform a Fourier transform on the frequency energy.

[0082] Video codecs are used to compress or decompress digital video. Electronic devices can support one or more video codecs. This allows the electronic device to play or record video in various encoded formats, such as Moving Picture Experts Group (MPEG) 1, MPEG2, MPEG3, MPEG4, etc.

[0083] An NPU (Neural Processing Unit) is a computational processor for neural networks (NNs). By borrowing the structure of biological neural networks, such as the transmission patterns between neurons in the human brain, it can rapidly process input information and continuously learn on its own. NPUs enable intelligent cognitive applications in electronic devices, such as image recognition, facial recognition, speech recognition, and text understanding.

[0084] Internal memory 121 may include one or more random access memory (RAM) and one or more non-volatile memory (NVM).

[0085] Random access memory can include static random-access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM, for example, fifth generation DDR SDRAM is generally called DDR5 SDRAM), etc.

[0086] Non-volatile memory can include disk storage devices and flash memory.

[0087] Flash memory can be classified according to its operating principle, including NOR FLASH, NAND FLASH, 3D NAND FLASH, etc.; according to the level of the storage cell, including single-level cell (SLC), multi-level cell (MLC), triple-level cell (TLC), quad-level cell (QLC), etc.; and according to the storage specification, including universal flash storage (UFS) and embedded multimedia card (eMMC), etc.

[0088] The random access memory can be directly read and written by the processor 110. It can be used to store executable programs (such as machine instructions) of the operating system or other running programs, as well as user and application data.

[0089] Non-volatile memory can also store executable programs and user and application data, and can be pre-loaded into random access memory for direct reading and writing by the processor 110.

[0090] The external memory interface 120 can be used to connect to external non-volatile memory, thereby expanding the storage capacity of the electronic device. The external non-volatile memory communicates with the processor 110 through the external memory interface 120 to perform data storage functions. For example, music, video, and other files can be stored in the external non-volatile memory.

[0091] Electronic devices can implement audio functions such as music playback and recording through audio modules 170, speakers 170A, receivers 170B, microphones 170C, headphone jacks 170D, and application processors.

[0092] The audio module 170 is used to convert digital audio information into analog audio signals for output, and also to convert analog audio input into digital audio signals. The audio module 170 can also be used for encoding and decoding audio signals. In some embodiments, the audio module 170 may be located in the processor 110, or some functional modules of the audio module 170 may be located in the processor 110.

[0093] The speaker 170A, also known as a "loudspeaker," is used to convert audio electrical signals into sound signals. Electronic devices can listen to music or make hands-free calls through the speaker 170A.

[0094] The receiver 170B, also known as the "earpiece," is used to convert audio electrical signals into sound signals. When an electronic device answers a phone call or voice message, the receiver 170B can be brought close to the ear to hear the voice.

[0095] Microphone 170C, also known as a "microphone" or "voice transducer," is used to convert sound signals into electrical signals. When making a phone call or sending a voice message, the user can speak by bringing their mouth close to microphone 170C, inputting the sound signal into microphone 170C. Electronic devices can have at least one microphone 170C. In some embodiments, electronic devices can have two microphones 170C, which, in addition to collecting sound signals, can also perform noise reduction. In other embodiments, electronic devices can have three, four, or more microphones 170C, enabling sound signal collection, noise reduction, sound source identification, and directional recording, among other functions.

[0096] The 170D headphone jack is used to connect wired headphones. The 170D headphone jack can be a USB 130 interface or a 3.5mm Open Mobile Terminal Platform (OMTP) standard interface, a CTIA (Cellular Telecommunications Industry Association of the USA) standard interface.

[0097] The pressure sensor 180A is used to sense pressure signals and can convert pressure signals into electrical signals.

[0098] The gyroscope sensor 180B can be used to determine the motion posture of electronic devices.

[0099] The barometric pressure sensor 180C is used to measure air pressure. In some embodiments, the electronic device calculates altitude using the air pressure value measured by the barometric pressure sensor 180C to assist in positioning and navigation.

[0100] The magnetic sensor 180D includes a Hall effect sensor. Electronic devices can use the magnetic sensor 180D to detect the opening and closing of a flip cover.

[0101] The 180E accelerometer can detect the magnitude of acceleration in various directions (typically three axes) of an electronic device. When the electronic device is stationary, it can detect the magnitude and direction of gravity. It can also be used to identify the posture of electronic devices, and is applicable to screen orientation switching, pedometers, and other applications.

[0102] A distance sensor 180F is used to measure distance. Electronic devices can measure distance using infrared or laser. In some embodiments, during a shooting scene, the electronic device can utilize the distance sensor 180F to measure distance for rapid focusing.

[0103] The proximity light sensor 180G may include, for example, a light-emitting diode (LED) and a light detector, such as a photodiode.

[0104] The Ambient Light Sensor 180K is used to detect ambient light levels. Electronic devices can adaptively adjust the brightness of their displays based on the detected ambient light. The Ambient Light Sensor 180K can also be used to automatically adjust white balance when taking photos. Furthermore, the Ambient Light Sensor 180K can be used in conjunction with the Proximity Sensor 180G to detect whether an electronic device is in a pocket, preventing accidental touches.

[0105] The fingerprint sensor 180H is used to collect fingerprints. Electronic devices can utilize the characteristics of the collected fingerprints to achieve fingerprint unlocking, app access locks, fingerprint photography, fingerprint answering of calls, etc.

[0106] The temperature sensor 180I is used to detect temperature.

[0107] Touch sensor 180J, also known as a "touch device," can be located on display screen 194. The touch sensor 180J and display screen 194 together form a touchscreen, also known as a "touchscreen." Touch sensor 180J detects touch operations applied to or near it. The touch sensor can transmit the detected touch operation to the application processor to determine the type of touch event. Visual output related to the touch operation can be provided through display screen 194.

[0108] The 180L bone conduction sensor can acquire vibration signals.

[0109] Buttons 190 include a power button, volume buttons, etc. Buttons 190 can be mechanical buttons or touch-sensitive buttons. The electronic device can receive button input and generate key signal inputs related to user settings and function control of the electronic device.

[0110] Motor 191 can generate vibration alerts. Motor 191 can be used for incoming call vibration alerts or for touch vibration feedback. For example, different vibration feedback effects can correspond to touch operations performed on different applications (such as taking photos, playing audio, etc.). Motor 191 can also correspond to different vibration feedback effects for touch operations performed on different areas of the display screen 194. Different application scenarios (such as time reminders, receiving messages, alarm clocks, games, etc.) can also correspond to different vibration feedback effects. The touch vibration feedback effect can also be customized.

[0111] Indicator 192 can be an indicator light, used to indicate charging status, power changes, or to indicate messages, missed calls, notifications, etc.

[0112] The SIM card interface 195 is used to connect a SIM card. The SIM card can be inserted into or removed from the SIM card interface 195 to achieve contact and separation with the electronic device. The electronic device can support one or N SIM card interfaces, where N is a positive integer greater than 1. The SIM card interface 195 can support Nano SIM cards, Micro SIM cards, SIM cards, etc. Multiple cards can be inserted into the same SIM card interface 195 simultaneously. The multiple cards can be of the same or different types. The SIM card interface 195 is also compatible with different types of SIM cards. The SIM card interface 195 is also compatible with external memory cards. The electronic device interacts with the network through the SIM card to achieve functions such as calls and data communication. In some embodiments, the electronic device uses an eSIM, i.e., an embedded SIM card. The eSIM card can be embedded in the electronic device and cannot be separated from it.

[0113] For example, Figure 2 This is a schematic diagram of the software structure of an electronic device provided in an embodiment of this application.

[0114] like Figure 2 As shown, the software architecture of an electronic device can be a layered architecture. For example, the software can be divided into several layers, each with a clear role and division of labor. Layers communicate with each other through software interfaces. In some embodiments, the operating system is divided into four layers, from top to bottom: the application layer, the application framework layer (framework, FWK), the runtime and system libraries, and the kernel layer.

[0115] The application layer can include a series of application packages. For example... Figure 2 As shown, the application layer can include camera, settings, skin modules, user interface (UI), third-party applications, etc. Third-party applications can include gallery, calendar, call, map, navigation, WLAN, Bluetooth, music, video, SMS, etc.

[0116] The application framework layer provides an application programming interface (API) and programming framework for applications in the application layer. The application framework layer can include some predefined functions. For example... Figure 2 As shown, the application framework layer may include a window manager, content provider, view system, phone manager, resource manager, and notification manager.

[0117] The window manager is used to manage windowed applications. It can obtain the screen size, determine if a status bar is present, lock the screen, and capture screenshots. The content provider stores and retrieves data, making this data accessible to applications. This data may include videos, images, audio, made and received phone calls, browsing history and bookmarks, phone books, etc.

[0118] A view system includes visual controls, such as controls for displaying text and controls for displaying images. View systems can be used to build applications. A display interface can consist of one or more views. For example, a display interface including a text notification icon could include views for displaying text and views for displaying images.

[0119] A phone manager is used to provide communication functions for electronic devices. For example, it manages call status (including connection and disconnection).

[0120] The file explorer provides applications with various resources, such as localized strings, icons, images, layout files, video files, and more.

[0121] The notification manager allows applications to display notifications in the status bar. These notifications can be used to deliver informational messages and can disappear automatically after a short pause, requiring no user interaction. For example, the notification manager can be used to notify users of completed downloads or message alerts. The notification manager can also display notifications as icons or scrolling text in the top status bar, such as notifications from background applications, or as dialog boxes on the screen. Examples include displaying text messages in the status bar, emitting sounds, vibrating electronic devices, and flashing indicator lights.

[0122] The runtime includes the core libraries and the virtual machine. The runtime is responsible for the scheduling and management of the operating system.

[0123] The core library consists of two parts: one part contains the functionalities that the Java language needs to call, and the other part contains the core libraries of the operating system. The application layer and application framework layer run in the virtual machine. The virtual machine executes the Java files of the application layer and application framework layer as binary files. The virtual machine is used to perform functions such as object lifecycle management, stack management, thread management, security and exception management, and garbage collection.

[0124] System libraries can include multiple functional modules. For example: surface manager, media libraries, 3D graphics processing libraries (e.g., OpenGLES), 2D graphics engines (e.g., SGL), etc.

[0125] The Surface Manager is used to manage the display subsystem and provides the blending of 2D and 3D layers for multiple applications.

[0126] The media library supports playback and recording of various common audio and video formats, as well as still image files. It supports multiple audio and video encoding formats, such as MPEG4, H.264, MP3, AAC, AMR, JPG, and PNG.

[0127] The 3D graphics processing library is used to implement 3D graphics drawing, image rendering, compositing, and layer processing.

[0128] A 2D graphics engine is a graphics engine for 2D drawing.

[0129] The kernel layer is the layer between hardware and software. The kernel layer contains at least the display driver, camera driver, audio driver, and sensor driver.

[0130] The hardware layer can include various types of sensors, such as accelerometers, gravity sensors, and touch sensors.

[0131] The above describes the electronic devices to which the embodiments of this application are applicable. The following describes the relevant technical solutions involved in the embodiments of this application.

[0132] 1) The central processing unit (CPU) of electronic devices and the hardware accelerators (such as GPU, NPU, codec, display subsystem, DSS, etc.) in system-on-chip (SoC) of electronic devices can share memory (such as direct memory access (DMA) memory) to enable high-speed data transfer between the CPU and hardware accelerators.

[0133] The hardware accelerator in the system-on-a-chip is also known as the master internet protocol (master IP) or hardware IP. The CPU uses a memory management unit (MMU) to map virtual addresses on the CPU side to physical addresses on the DMA side; that is, the MMU provides address translation functionality based on the MMU page table.

[0134] The hardware accelerator uses a system memory management unit (SMMU) (also known as an input output memory management unit (IOMMU)) to implement the mapping of virtual addresses on the hardware accelerator side to physical addresses on the DMA memory side. In other words, the SMMU is used to provide address translation function based on the SMMU page table.

[0135] For example, Figure 3 This is a schematic diagram illustrating a data flow from the CPU to a hardware accelerator via DMA memory, provided as an embodiment of this application. Figure 3 As shown, the CPU (e.g., image component, player component, codec interface, surface component, webview component) acts as a producer, using the MMU for address translation to write data into DMA memory, while the hardware accelerator (e.g., picture decoder, codec, GPU, DSS) acts as a consumer, using the SMMU for address translation to read data from DMA memory.

[0136] To improve the efficiency of asynchronous collaboration between the CPU and hardware accelerators, DMA memory often adopts a buffer queue structure. A buffer queue is a queue structure that contains multiple buffer areas, and one buffer area in the buffer queue represents one DMA memory. Therefore, the buffer queue contains multiple DMA memory areas.

[0137] Taking the CPU and DSS as an example, after the CPU and GPU jointly complete the rendering of the screen content, the CPU writes the data to a buffer area (i.e., a DMA memory) in the buffer queue by calling the surface component to display it. At this time, the DSS continuously retrieves the buffer areas with written data from the buffer queue and refreshes them to the corresponding screen. Thus, the CPU and DSS complete one data transfer cycle through a buffer area (i.e., a DMA memory).

[0138] 2) When the CPU or hardware accelerator accesses data in DMA memory, a page fault will occur if the data is not present in that DMA memory. For example, when the CPU accesses data stored in DMA memory, the CPU, through the MMU, uses the virtual address of the data on the CPU side to look up the corresponding physical address in the mapping relationship between the virtual address on the CPU side and the physical address on the DMA side (i.e., the MMU page table). If the corresponding physical address does not exist in this mapping relationship, it means that the data accessed by the CPU is not in the DMA memory, and a page fault occurs in that DMA memory. The MMU has the capability to automatically handle page faults in hardware, while the SMMU does not.

[0139] For DMA memory managed by the SMMU, if the SMMU reclaims data from that DMA memory, a page fault will occur when the hardware accelerator accesses that data again. Since the SMMU lacks the capability for automated hardware handling of page faults, it does not reclaim data from the DMA memory to avoid page faults when the hardware accelerator accesses it. In other words, data resides in that DMA memory, resulting in a high load on it. Therefore, SMMU-managed DMA memory exhibits low memory management efficiency.

[0140] Currently, there are three ways to solve the above problems in the operating system of electronic devices. These will be introduced below.

[0141] One approach for iOS systems is to integrate a memory management unit (MMU) into a chip. This allows for automated hardware handling of page faults on the hardware accelerator side. However, this method only works for chips with integrated MMUs; it is not applicable to chips without integrated MMUs.

[0142] Secondly, the Android system can use the onTrimMemory interface to monitor memory load. When the DMA memory load is high, the application can execute a memory release method to free up some DMA memory. While this method is applicable to all chips, it heavily relies on the cooperation of the application developer, requiring the application to actively connect to the onTrimMemory interface.

[0143] Thirdly, the Android system can use process killing to reclaim the data in the DMA memory used by the process. Although this method does not rely on the cooperation of application developers, it sacrifices the user experience of background caching.

[0144] In view of this, embodiments of this application provide a memory management method that improves memory management efficiency while taking into account chip versatility, seamless compatibility for application developers, and user experience.

[0145] In the embodiments of this application, "when," "if," and "if" all refer to the device taking corresponding actions under certain objective circumstances, and are not time-limited, nor do they require the device to perform a judgment action, nor do they imply any other limitations. Unless otherwise specified, "if" and "if" can be substituted, and "when" and "in the case of" can be substituted. "When" and "if" / "if" can be substituted.

[0146] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0147] In this application embodiment, the number of nouns, unless otherwise specified, refers to "singular nouns or plural nouns," that is, "one or more." "At least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, or B exists alone, where A and B can be singular or plural. The character " / " can indicate that the related objects before and after are in an "or" relationship. For example, A / B means: A or B. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c means: a, b, c, a and b, a and c, b and c, or a and b and c, where a, b, and c can be single or multiple.

[0148] In this application, the ordinal numbers such as "first" and "second" are used to distinguish multiple objects, and are not used to limit the size, content, order, timing, priority, or importance of the multiple objects. For example, "first event" and "second event" refer to two different events, and do not indicate a difference in priority or importance between the two events. For a technical feature, the technical features within that technical feature are distinguished by "A," "B," "C," and "D," and there is no sequential or hierarchical order among the technical features described by "A," "B," "C," and "D." For example, in this document, "case A" and "case B" are only used to distinguish different contents, and do not limit the sequential or hierarchical order, priority, or importance between cases A and B.

[0149] The solution provided by the embodiments of this application will be described in detail below with reference to the accompanying drawings. In the following description, the memory management method provided by the embodiments of this application is applied to... Figures 1-2 Take the electronic device shown as an example.

[0150] To facilitate understanding of the embodiments of this application, the CPU, hardware accelerator, first application, and first DMA memory involved in the embodiments of this application will be introduced below.

[0151] Electronic devices may include a CPU and a hardware accelerator (or hardware acceleration module, or hardware acceleration unit). The CPU may include an image component, a player component, a codec interface, a surface component, a network view component, etc. The hardware accelerator may include a GPU, an NPU, a codec, a DSS, etc. This application does not limit the scope of the embodiments.

[0152] One or more applications can run on a CPU. Each application can correspond to one or more processes, and each process can include one or more threads that execute tasks. The CPU and hardware accelerators can share memory (e.g., DMA memory) to enable high-speed data transfer between the CPU and the hardware accelerator for one or more applications running on the CPU.

[0153] In other words, one or more applications running on the CPU can use DMA memory to store their data. The CPU can access the application's data in the DMA memory through address translation via the MMU (Memory Management Unit). Specifically, the MMU provides address translation functionality based on its page tables, which map virtual addresses on the CPU side to physical addresses on the DMA memory side. Similarly, the hardware accelerator can access the application's data in the DMA memory through the SMMU (Smart Memory Management Unit). This SMMU provides address translation functionality based on its page tables, which map virtual addresses on the hardware accelerator side to physical addresses on the DMA memory side.

[0154] In practice, the first application running on the CPU can use the first DMA memory to store its data. The CPU and the hardware accelerator can share the first DMA memory to enable high-speed data transfer between the CPU and the hardware accelerator. The first DMA memory may include one or more DMA memory modules.

[0155] Figure 4 This is a schematic diagram of a first DMA memory provided in an embodiment of this application. Figure 4 As shown, the first DMA memory can be a buffer queue, which can include N buffer regions, namely buffer region 1, buffer region 2, buffer region 3, buffer region 4, ..., buffer region N. Each buffer region can represent one DMA memory, meaning the first DMA memory can include N DMA memories, where N is a positive integer greater than or equal to 1.

[0156] The CPU can access data of the first application in the first DMA memory based on the first MMU page table. The first MMU page table can include a mapping from virtual addresses on the CPU side to physical addresses on the first DMA memory side. For example, if data 1 of the first application is stored in buffer area 1 of the first DMA memory, and the virtual address corresponding to data 1 on the CPU side is 0x0012321A, and the physical address corresponding to data 1 on the first DMA memory side is 0x04F251BC, then the first MMU page table can include a mapping from the virtual address 0x0012321A on the CPU side to the physical address 0x04F251BC on the first DMA memory side.

[0157] The hardware accelerator can access the data of the first application in the first DMA memory based on the first SMMU page table (or the first memory page table). The first SMMU page table can include a mapping from virtual addresses on the hardware accelerator side to physical addresses on the first DMA memory side. For example, if the data 1 of the first application is stored in buffer area 1 of the first DMA memory, and the virtual address corresponding to the data 1 of the first application on the hardware accelerator side is 0x025412CB, and the physical address corresponding to the data 1 of the first application on the first DMA memory side is 0x04F251BC, then the first SMMU page table can include a mapping from the virtual address 0x025412CB on the hardware accelerator side to the physical address 0x04F251BC on the first DMA memory side.

[0158] Figure 5 This is a schematic diagram illustrating a page fault in a first DMA memory, provided as an embodiment of this application. Figure 5As shown, when the CPU accesses data 1 of the first application in the first DMA memory, the CPU can use the MMU to look up the physical address of the first DMA memory corresponding to the virtual address 0x0012321A on the CPU side of the data 1 in the first MMU page table. If the physical address of the first DMA memory corresponding to the virtual address 0x0012321A on the CPU side does not exist in the first MMU page table, it means that the data 1 of the first application is not stored in the buffer area 1 of the first DMA memory, that is, a page fault has occurred in the first DMA memory.

[0159] When the hardware accelerator accesses data 1 of the first application in the first DMA memory, the hardware accelerator can use the SMMU to look up the corresponding physical address on the first DMA memory side from the first SMMU page table based on the virtual address 0x04F251BC of the first application data 1 on the hardware accelerator side. If the physical address on the first DMA memory side corresponding to the virtual address 0x04F251BC on the hardware accelerator side does not exist in the first SMMU page table, it means that the first application data 1 is not stored in the buffer area 1 of the first DMA memory, that is, a page fault has occurred in the first DMA memory.

[0160] Please see Figure 6 The above is a flowchart of a memory management method provided in an embodiment of this application. The specific process of the memory management method is described below.

[0161] S601, The hardware accelerator detects a first event; wherein, the first event indicates that the probability of a page fault in the first DMA memory used by the first application is greater than a first threshold.

[0162] In this embodiment, when the CPU and hardware accelerator share the first DMA memory, the hardware accelerator can detect a first event. The first event can indicate that the probability of a page fault occurring in the first DMA memory used by the first application is greater than a first threshold. The first threshold is greater than or equal to zero. The first threshold can be pre-configured or standard-defined; this embodiment does not limit this, but for ease of explanation, it is used as an example where the first threshold is zero. That is, the first event can indicate that a page fault may occur in the first DMA memory used by the first application, or the first event can indicate that the probability of a page fault occurring in the first DMA memory used by the first application is greater than zero.

[0163] The first event may include one or more of the following: the running state of the first application changes from a frozen state to a non-frozen state; the data A of the first application corresponding to the first virtual address that the CPU wants to access is not stored in the first DMA memory. This application embodiment does not limit this. The first event will be described in detail below.

[0164] 1) The first event may include the first application's running state changing from a frozen state to a non-frozen state. That is, if the hardware accelerator determines that the first application's running state (or the lifecycle stage of the first application) has changed from a frozen state to a non-frozen state, the hardware accelerator can determine that the probability of a page fault occurring in the first DMA memory used by the first application is greater than zero.

[0165] The non-frozen state includes foreground running state, background running state, etc. The frozen state can include background cache state, shallow frozen state, deep frozen state, etc. This application embodiment does not limit this.

[0166] The foreground running state refers to the application running in the foreground. In this state, the application presents a user interface (UI), through which users can interact with the application.

[0167] Background running state refers to an application switching from the foreground to the background while still running tasks. In this state, the application no longer displays a user interface, but its tasks (or functions) continue to run. For example, a music application runs music playback in the background, and a navigation application runs navigation tasks in the background.

[0168] Background cache state refers to an application switching from foreground to background operation, ceasing to run tasks, and where the user has not interacted with the application for a short period (e.g., the first duration). In this state, the application resides in the background primarily to preserve the user interface previously displayed when the application was running in the foreground, so that the user can continue operating the application when it switches back to the foreground.

[0169] A shallow freeze state refers to an application that, after being moved to the background, ceases to run tasks and is not interacted with by the user for a certain period (e.g., a second duration). In this running state, the application only responds to system behaviors when certain specific system events occur, such as responding to system resolution conversions. The second duration is longer than the first duration.

[0170] A deep freeze state refers to an application that, after being moved to the background, ceases to run tasks and is not interacted with by the user for an extended period (e.g., a third duration). In this state, the application no longer responds to system actions and is completely in a non-running state. The third duration is longer than the second duration.

[0171] It's understandable that in the background cache state, shallow freeze state, and deep freeze state, the application doesn't run any tasks. The difference between these three states lies in the duration the application resides in the background. When the application resides in the background and doesn't run tasks for a short time (e.g., the first duration), the application is in the background cache state. When the application resides in the background and doesn't run tasks for a relatively long time (e.g., the second duration), the application is in the shallow freeze state. When the application resides in the background and doesn't run tasks for a very long time (e.g., the third duration), the application is in the deep freeze state. If an application in the background cache state hasn't been interacted with by the user after the second duration (i.e., no tasks are running), it can switch to the shallow freeze state. If an application in the shallow freeze state hasn't been interacted with by the user after the third duration (i.e., no tasks are running), it can switch to the deep freeze state.

[0172] It's understandable that in non-frozen states such as foreground or background running, the application is running tasks. The CPU, acting as a producer, continuously writes data to the DMA memory used by the application; that is, the producer is constantly producing data. The hardware accelerator, acting as a consumer, continuously reads data from the DMA memory used by the application; that is, the consumer is constantly consuming data. In other words, the data in the DMA memory used by the application is not in a stable state.

[0173] In frozen states such as background caching, shallow freeze, and deep freeze, the application no longer runs tasks. The CPU, acting as the producer, immediately stops writing data to the DMA memory used by the application; that is, the producer immediately stops producing data. However, the hardware accelerator, acting as the consumer, gradually stops reading data from the DMA memory used by the application; that is, the consumer gradually stops consuming data until it no longer accesses the data in the DMA memory used by the application. In other words, the data in the DMA memory used by the application has reached a stable state.

[0174] In other words, if the first application switches from the foreground to the background and no longer runs any tasks, it means that the running state of the first application has switched from a non-frozen state to a frozen state. Therefore, when the first application switches from the foreground to the background and no longer runs any background tasks, the hardware accelerator can determine that the running state of the first application has switched from a non-frozen state to a frozen state.

[0175] If the first application switches from the background to the foreground, or switches from the foreground to the background but is still running a task, it indicates that the running state of the first application has switched from a frozen state to a non-frozen state. Therefore, when the first application switches from the background to the foreground, or when the first application is running a background task, the hardware accelerator can determine that the running state of the first application has switched from a frozen state to a non-frozen state.

[0176] The hardware accelerator can manage the first DMA memory used by the first application based on the running status of the first application, so as to ensure the performance of the first application in the corresponding running status as much as possible.

[0177] For example, if the running state of the first application changes from a non-frozen state to a frozen state, it indicates that the probability of the user operating the first application in a short period of time is low. This can be understood as a low probability that the CPU and hardware accelerator will access some or all of the data of the first application in the first DMA memory in a short period of time. Therefore, in order to save space in the first DMA memory, the hardware accelerator can perform a swap-out operation on some or all of the data of the first application in the first DMA memory, such as swapping it out to disk (or writing it to disk).

[0178] If the running state of the first application changes from frozen to unfrozen, it indicates a high probability that the user will operate the first application within a short period of time. This can be understood as a high probability that the CPU and hardware accelerator will access some or all of the first application's data in the first DMA memory within a short period of time. If some or all of the first application's data in the first DMA memory accessed by the CPU and hardware accelerator has been swapped out to disk, a page fault will occur in the first DMA memory. If some or all of the first application's data in the first DMA memory accessed by the CPU and hardware accelerator has not been swapped out to disk, a page fault will not occur in the first DMA memory. In other words, the probability of a page fault occurring in the first DMA memory used by the first application is greater than zero. Therefore, to avoid potential page faults in the first DMA memory, the hardware accelerator can rewrite some or all of the first application's data from the disk back into the first DMA memory.

[0179] In one possible implementation, before the hardware accelerator detects the first event, the hardware accelerator may swap some or all of the data of the first application in the first DMA memory to the disk by performing the following steps.

[0180] Step a1: The hardware accelerator detects the second event.

[0181] The second event may include the first application switching its running state from a non-frozen state to a frozen state.

[0182] It's understandable that when the first application is in a non-frozen state, it's running tasks. The CPU, acting as a producer, continuously writes data to the first DMA memory used by the first application; that is, the producer continuously produces data. The hardware accelerator, acting as a consumer, continuously reads data from the first DMA memory used by the first application; that is, the consumer continuously consumes data.

[0183] When the first application is in a frozen state, it ceases running tasks. The CPU, acting as the producer, immediately stops writing data to the first DMA memory used by the first application; that is, the producer immediately stops producing data. However, the hardware accelerator, acting as the consumer, gradually stops reading data from the first DMA memory used by the first application; that is, the consumer gradually stops consuming data until it no longer accesses the data in the first DMA memory. It's worth noting that when the first application is in a frozen state, the hardware accelerator gradually migrates its consumption to the DMA memory used by other applications that are not in a frozen state. Therefore, the hardware accelerator does not read all the data from the first DMA memory used by the first application before stopping; when the hardware accelerator stops reading data from the first DMA memory, a portion of data that has not yet been read by the hardware accelerator still remains in the first DMA memory.

[0184] In other words, the prerequisite for writing some or all of the data of the first application in the first DMA memory to disk is that the running state of the first application is frozen.

[0185] Step a2: In response to the second event, the hardware accelerator swaps the data B of the first application in the first DMA memory to the disk and updates the first SMMU page table according to the data B of the first application in the disk.

[0186] The first DMA memory includes a first buffer queue, in which the data B of the first application is stored. That is, the data B of the first application is stored in the first buffer queue in the first DMA memory before being swapped out of the first DMA memory to the disk.

[0187] To ensure that the data B in the first application is as safe as possible—that is, data that the CPU and hardware accelerator will not access in the short term—the hardware accelerator can detect whether each buffer region in the first buffer queue is a safe buffer region, i.e., a buffer region that the CPU and hardware accelerator will not access in the short term. If each buffer region in the first buffer queue is a safe buffer region, the hardware accelerator can swap the data in each buffer region of the first buffer queue to the disk.

[0188] For example, in step a2, the hardware accelerator can swap the data B of the first application in the first DMA memory to the disk by executing steps a21-a22.

[0189] Step a21: The hardware accelerator detected a third event.

[0190] The third event can indicate that the data in the first DMA memory is no longer being updated, and / or that each buffer region in the first buffer queue is identified by the first identifier. The first identifier can be used to indicate that the data in the corresponding buffer region can be swapped out to the disk by the hardware accelerator.

[0191] The data in the first DMA memory is no longer being updated. This can be understood as the CPU, acting as the producer, ceasing to write data to the first DMA memory used by the first application, and the hardware accelerator, acting as the consumer, ceasing to read data from the first DMA memory used by the first application. In other words, the producer has stopped producing data and the consumer has stopped consuming data; the data in the first DMA memory is in a stable state and will not be accessed by the CPU or hardware accelerator in the short term. In other words, all data in the first DMA memory can be swapped out to the disk by the hardware accelerator.

[0192] Each buffer region in the first buffer queue is identified by the first identifier, which can be understood as the data in each buffer region of the first buffer queue being in a stable state and unlikely to be accessed by the CPU and hardware accelerator in the short term. In other words, the data in each buffer region of the first buffer queue can be swapped to disk by the hardware accelerator.

[0193] For example, Figure 7 This is a schematic diagram of a first buffer queue provided in an embodiment of this application. Figure 7 As shown, the first DMA memory can be a buffer queue, which can include N buffer regions, namely buffer region 1, buffer region 2, buffer region 3, buffer region 4, ..., buffer region N. N is a positive integer greater than or equal to 1. After the running state of the first application switches from the unfrozen state to the frozen state, the CPU, as the producer, stops writing data to the first DMA memory used by the first application, but the hardware accelerator, as the consumer, continues to read data from buffer region 2. Therefore, the data in buffer region 1, buffer region 3, buffer region 4, ..., buffer region N can all be swapped out to the disk by the hardware accelerator, that is, the identifiers of buffer region 1, buffer region 3, buffer region 4, ..., buffer region N are all the first identifier. However, the data in buffer region 2 cannot be swapped out to the disk by the hardware accelerator, that is, the identifier of buffer region 2 is the second identifier (or attachment identifier). The second identifier can be used to indicate that the data in the corresponding buffer region cannot be swapped out to the disk by the hardware accelerator. In other words, the first buffer queue in the first DMA memory used to store the data B of the first application includes buffer area 1, buffer area 2, buffer area 3, ..., buffer area N.

[0194] Step a22: In response to the third event, the hardware accelerator swaps the data in each buffer region of the first buffer queue to the disk.

[0195] It's understandable that after the first application's running state switches from unfrozen to frozen, although the CPU, as the producer, will no longer write data to the first DMA memory used by the first application, the hardware accelerator, as the consumer, will continue to read data from the first DMA memory used by the first application. Therefore, to avoid affecting the hardware accelerator's current access, some or all of the first application's data in the first DMA memory needs to be written to disk after the hardware accelerator stops reading data from the first DMA memory. Furthermore, to avoid affecting subsequent access by the CPU and hardware accelerator, the data written to disk needs to be data in the buffer area corresponding to the first identifier; in other words, the data written to disk cannot be data in the buffer area corresponding to the second identifier.

[0196] For example, in step a2, the hardware accelerator can update the first SMMU page table based on the data B of the first application in the disk by executing step a23.

[0197] Step a3: The hardware accelerator deletes the mapping from the second virtual address to the first physical address in the first SMMU page table.

[0198] Wherein, the second virtual address is the virtual address corresponding to the data B of the first application on the hardware accelerator side, and the first physical address is the physical address corresponding to the data B of the first application on the first DMA memory side.

[0199] It is understandable that after the hardware accelerator swaps the data B of the first application from the first DMA memory to the disk, the hardware accelerator can delete the mapping from the virtual address of the data B of the first application on the hardware accelerator side to the physical address of the data B of the first application on the first DMA memory side in the first SMMU page table. Furthermore, the CPU can also delete the mapping from the virtual address of the data B of the first application on the CPU side to the physical address of the data B of the first application on the first DMA memory side in the first MMU page table. In other words, the hardware accelerator can unmap the data B of the first application from the first SMMU page table, and the CPU can unmap the data B of the first application from the first MMU page table.

[0200] For example, regarding the above Figure 4As shown in the first SMMU page table and the first MMU page table, after the hardware accelerator swaps out the data 1 of the first application from the buffer area 1 of the first DMA memory to the disk, the hardware accelerator can delete the mapping from the virtual address 0x025412CB on the hardware accelerator side to the physical address 0x04F251BC on the first DMA memory side in the first SMMU page table, and the CPU can delete the mapping from the virtual address 0x0012321A on the CPU side to the physical address 0x04F251BC on the first DMA memory side in the first MMU page table, thereby obtaining the above-described... Figure 5 The first SMMU page table and the first MMU page table are shown.

[0201] For example, Figure 8 This is a schematic diagram illustrating the swapping of some or all data of a first application from a first DMA memory to a disk, as provided in an embodiment of this application. Figure 8 As shown, the process of placing the plate can be divided into four steps, which will be introduced below.

[0202] Step 1: The first application is in a frozen state. That is, the first application no longer runs tasks, and the CPU, acting as the producer, immediately stops writing data to the first DMA memory used by the first application; in other words, the producer immediately stops producing data. However, the hardware accelerator, acting as the consumer, gradually stops reading data from the first DMA memory used by the first application; in other words, the consumer gradually stops consuming data.

[0203] Step 2: The data in buffer area N of the first DMA memory is in a stable state. That is, the hardware accelerator, acting as the consumer, has stopped reading data from buffer area N of the first DMA memory used by the first application. In other words, the producer has stopped producing data and the consumer has stopped consuming data; the data in the first DMA memory is in a stable state, and the data in buffer area N of the first DMA memory will not be accessed by the CPU and hardware accelerator for a short period of time, and can be swapped out to disk by the hardware accelerator.

[0204] Step 3: The hardware accelerator swaps the data of the first application from the buffer area N in the first DMA memory to the disk, i.e., writes it to the disk.

[0205] Step 4: The hardware accelerator removes the mapping from the virtual address 0x013412AF on the hardware accelerator side to the physical address 0x04F261BC on the first DMA memory side in the first SMMU page table, i.e., demapping.

[0206] 2) The first event may include the fact that the data A of the first application corresponding to the first virtual address that the CPU wants to access is not stored in the first DMA memory. That is, if the hardware accelerator determines that the data A of the first application corresponding to the first virtual address that the CPU wants to access is not stored in the first DMA memory, the hardware accelerator can determine that the probability of a page fault in the first DMA memory used by the first application is greater than zero.

[0207] In this context, data A of the first application belongs to data B of the first application; that is, data B of the first application includes data A of the first application. This can be understood as follows: data B of the first application is all the data of the first application stored on the disk, and data A of the first application is a portion of the data of the first application stored on the disk. The first virtual address is the virtual address corresponding to data A of the first application on the CPU side.

[0208] It is understandable that the hardware accelerator can monitor the first virtual address that the CPU wants to access and determine whether the data A of the first application corresponding to the first virtual address is stored in the first DMA memory. If the data A of the first application is stored in the first DMA memory, the hardware accelerator can determine that the first DMA memory used by the first application has not experienced a page fault, that is, the probability of a page fault in the first DMA memory used by the first application is zero; if the data A of the first application is not stored in the first DMA memory, the hardware accelerator can determine that the first DMA memory used by the first application has experienced a page fault, that is, the probability of a page fault in the first DMA memory used by the first application is greater than zero.

[0209] In one possible implementation, the hardware accelerator can determine whether the data A of the first application corresponding to the first virtual address to be accessed by the CPU is stored in the first DMA memory by performing the following steps.

[0210] Step b1: The hardware accelerator searches for the third virtual address corresponding to the first virtual address from the first DMA memory page table (or the second memory page table).

[0211] The first DMA memory page table may include a mapping from virtual addresses on the CPU side to virtual addresses on the hardware accelerator side. The third virtual address is the virtual address corresponding to data A of the first application on the hardware accelerator side.

[0212] Step b2: The hardware accelerator looks up the second physical address corresponding to the third virtual address from the first SMMU page table based on the third virtual address.

[0213] The second physical address is the physical address of the data A of the first application on the first DMA memory side.

[0214] Step b3: If the second physical address exists in the first SMMU page table, the hardware accelerator determines that the data A of the first application is stored in the first DMA memory; if the second physical address does not exist in the first SMMU page table, the hardware accelerator determines that the data A of the first application is not stored in the first DMA memory.

[0215] For example, Figure 9 This application provides a schematic diagram of a first DMA memory page table. For example... Figure 9 As shown, when the CPU accesses data 1 of the first application in the first DMA memory, the CPU can send the virtual address 0x0012321A of data 1 on the CPU side to the hardware accelerator. Based on the virtual address 0x0012321A of data 1 on the CPU side, the hardware accelerator looks up the virtual address 0x04F251BC of data 1 on the hardware accelerator side in the first DMA memory page table. Based on the virtual address 0x04F251BC of data 1 on the hardware accelerator side, the hardware accelerator looks up the corresponding physical address on the first DMA memory side in the first SMMU page table. If the physical address on the first DMA memory side corresponding to the virtual address 0x04F251BC on the hardware accelerator side does not exist in the first SMMU page table, it means that data 1 of the first application is not stored in the first DMA memory; that is, a page fault has occurred in the first DMA memory.

[0216] S602. In response to the first event, the hardware accelerator performs a first operation; wherein the first operation includes one or more of the following: killing the first process of the first application; writing the first data of the first application in the disk to the first DMA memory, and updating the first SMMU page table according to the first data in the first DMA memory, wherein the first SMMU page table includes a mapping from the virtual address on the hardware accelerator side to the physical address on the first DMA memory side.

[0217] In this embodiment, the first data of the first application can be data B (or second data) of the first application, or it can be data A (or third data) of the first application. Since data B of the first application is all the data of the first application stored on the disk, and data A of the first application is a portion of the data of the first application stored on the disk (i.e., the data corresponding to the first virtual address that the CPU needs to access), writing data B of the first application from the disk to the first DMA memory can be called a full-page write, while writing data A of the first application from the disk to the first DMA memory can be called a single-page write.

[0218] In other words, after the hardware accelerator detects the first event, that is, after the hardware accelerator determines that the probability of a page fault in the first DMA memory used by the first application is greater than zero, the hardware accelerator can perform the first operation to handle the possible page fault in the first DMA memory, thereby improving memory management efficiency.

[0219] In practice, the hardware accelerator can determine the first operation to be performed based on the storage space already occupied by the data of the first application on the disk. The first operation is described in detail below, depending on the specific circumstances.

[0220] In scenario A, if the storage space occupied by the data of the first application on the disk is greater than or equal to the second threshold, the first operation may include terminating the first process of the first application. That is, when the hardware accelerator determines that a page fault may occur in the first DMA memory, the hardware accelerator can terminate the first process of the first application. For example, the hardware accelerator can send termination information to the CPU instructing the termination of the first process of the first application. The second threshold is greater than zero and can be pre-configured or standard-defined; this embodiment does not limit this.

[0221] It's understandable that if the data from the first application occupies a large amount of storage space on the disk (e.g., greater than or equal to the second threshold), it indicates that the data from the first application is increasing the disk load significantly. Therefore, to improve disk management efficiency, after the hardware accelerator determines that the first DMA memory used by the first application may experience a page fault, the hardware accelerator can directly terminate the first application to handle the potential page fault in the first DMA memory, thereby improving both memory management and disk management efficiency.

[0222] For example, Figure 10 This is a schematic diagram of a hardware accelerator managing a first DMA memory, provided as an embodiment of this application.

[0223] like Figure 10As shown, when the first application switches from foreground to background, the hardware accelerator determines whether the first application is running a background task. If the first application is running a background task, the hardware accelerator determines that the first application's running state is non-frozen. If the first application is not running a background task, the hardware accelerator determines that the first application's running state is frozen. The hardware accelerator determines that the data of the first application in the first DMA memory is no longer being updated, that is, the data of the first application in the first DMA memory is in a stable state and will not be accessed by the CPU and hardware accelerator in the short term. The hardware accelerator swaps out the data B of the first application in the first DMA memory to the disk. The hardware accelerator listens to the first virtual address that the CPU wants to access and determines whether the data A of the first application corresponding to the first virtual address that the CPU wants to access is stored in the first DMA memory. If the data A of the first application corresponding to the first virtual address that the CPU wants to access is stored in the first DMA memory, it is determined that no page fault has occurred in the first DMA memory. If the data A of the first application corresponding to the first virtual address that the CPU wants to access is not stored in the first DMA memory, the hardware accelerator determines the storage space occupied by the data B of the first application on the disk. If the storage space occupied by the data B of the first application on the disk is greater than or equal to the second threshold, the first process of the first application is killed.

[0224] In scenario B, where the storage space occupied by the data of the first application on the disk is less than the second threshold and greater than the third threshold (i.e., the second threshold is greater than the third threshold), the first operation may include writing the data B of the first application on the disk to the first DMA memory, and updating the first SMMU page table based on the data B of the first application in the first DMA memory. In other words, when the hardware accelerator determines that a page fault may occur in the first DMA memory, the hardware accelerator can write the data B of the first application on the disk to the first DMA memory and update the first SMMU page table based on the data B of the first application in the first DMA memory. The third threshold is greater than or equal to zero, and can be pre-configured or standard-defined; this embodiment does not limit this.

[0225] It's understandable that if the data from the first application occupies a large amount of storage space on the disk (e.g., less than the second threshold and greater than the third threshold), it means that the data from the first application will increase the disk load, but the increased load is generally significant. Therefore, to improve disk management efficiency and without affecting the user experience of the background cache, after the hardware accelerator determines that the first DMA memory used by the first application may experience a page fault, the hardware accelerator can write the data B of the first application from the disk to the first DMA memory (i.e., write the entire page). This improves memory management efficiency and disk management efficiency without affecting the user experience of the background cache.

[0226] In one possible implementation, after the hardware accelerator detects the first event, in response to the first event, the hardware accelerator may perform the following steps to write the data B of the first application in the disk to the first DMA memory, and update the first SMMU page table according to the data B of the first application in the first DMA memory.

[0227] Step c1: The hardware accelerator writes the data B of the first application in the disk to the second buffer queue in the first DMA memory.

[0228] It can be understood that in step a2 above, the hardware accelerator swaps out the data B of the first application from the first buffer queue in the first DMA memory to the disk. In step c1, the hardware accelerator rewrites the data B of the first application from the disk to the second buffer queue in the first DMA memory. That is, before the data B of the first application is written to disk, it is stored in the first buffer queue of the first DMA memory. After the data B is written to disk and rewritten back to the first DMA memory, it is stored in the second buffer queue of the first DMA memory. In other words, the first buffer queue is the buffer queue where the data B of the first application was located before it was swapped out from the first DMA memory to the disk, and the second buffer queue is the buffer queue where the data B of the first application is located after it is rewritten back to the first DMA memory from the disk.

[0229] To ensure the accuracy of the data B for the first application read from the disk by the hardware accelerator, after writing the data B to the second buffer queue in the first DMA memory, the hardware accelerator can determine whether the data B for the first application in the first buffer queue is the same as the data B for the first application in the second buffer queue. If the data B for the first application in the first buffer queue is different from the data B for the first application in the second buffer queue, it means that the data B for the first application read from the disk by the hardware accelerator after being written to disk is incorrect; if the data B for the first application in the first buffer queue is the same as the data B for the first application in the second buffer queue, it means that the data B for the first application read from the disk by the hardware accelerator after being written to disk is correct.

[0230] Furthermore, in order to improve the judgment efficiency of the hardware accelerator, the hardware accelerator can only compare whether the data in the first buffer region of the first buffer queue is the same as the data in the first buffer region of the second buffer queue, and whether the data in the last buffer region of the first buffer queue is the same as the data in the last buffer region of the second buffer queue.

[0231] For example, after the hardware accelerator performs step c1 above, the hardware accelerator can also perform the following steps d1-d2.

[0232] Step d1: The hardware accelerator detected the fourth event.

[0233] The fourth event indicates that the data in the first buffer region of the first buffer queue is different from the data in the first buffer region of the second buffer queue, and / or, the data in the last buffer region of the first buffer queue is different from the data in the last buffer region of the second buffer queue.

[0234] Step d2: In response to the fourth event, the hardware accelerator kills the first process of the first application.

[0235] For example, after the hardware accelerator performs step c1 above, it can also perform the following steps e1-e2.

[0236] Step e1: The hardware accelerator detected the fifth event.

[0237] The fifth event indicates that the data in the first buffer region of the first buffer queue is the same as the data in the first buffer region of the second buffer queue, and that the data in the last buffer region of the first buffer queue is the same as the data in the last buffer region of the second buffer queue.

[0238] Step e2: In response to the fifth event, the hardware accelerator updates the first SMMU page table based on the data B of the first application in the first DMA memory.

[0239] Figure 11 This application provides a schematic diagram for comparing data in a first buffer queue and a second buffer queue. For example... Figure 11As shown, the first DMA memory can be a buffer queue, which can include N buffer areas, namely buffer area 1, buffer area 2, buffer area 3, buffer area 4, ..., buffer area N. N is a positive integer greater than or equal to 1. Before the data B of the first application is written to disk in the first DMA memory, the data B of the first application is stored in the first buffer queue (including buffer area 1, buffer area 3, buffer area 4, ..., buffer area N) in the first DMA memory. At this time, the data B of the first application in the first buffer queue are data 11, data 13, data 14, ..., data 1N. After the data B of the first application is written to disk and re-stored in the first DMA memory, the data B of the first application is re-stored in the second buffer queue (including buffer area 1, buffer area 3, buffer area 4, ..., buffer area N) in the first DMA memory. At this time, the data B of the first application in the second buffer queue are data 21, data 23, data 24, ..., buffer area 2N. The hardware accelerator can compare whether data 11 in buffer area 1 of the first buffer queue is the same as data 21 in buffer area 1 of the second buffer queue, and whether data 1N in buffer area N of the first buffer queue is the same as data 2N in buffer area N of the second buffer queue. If they are different, it means that the data B of the first application read from the disk by the hardware accelerator after being written to disk is incorrect. To prevent the CPU and hardware accelerator from accessing the incorrect data B of the first application, the hardware accelerator can instruct the CPU to kill the first process of the first application. If they are the same, it means that the data B of the first application read from the disk by the hardware accelerator after being written to disk is correct, and the hardware accelerator can re-establish the mapping related to the data B of the first application in the first SMMU page table.

[0240] Optionally, if the first application is currently running in a frozen state, the hardware accelerator can also send a first instruction message to the CPU, wherein the first instruction message is used to instruct the CPU to switch the running state of the first application from the frozen state to the unfrozen state.

[0241] Step c2: The hardware accelerator adds a mapping from the second virtual address to the first physical address to the first SMMU page table.

[0242] It is understandable that after the hardware accelerator writes the data B of the first application from the disk to the first DMA memory, the hardware accelerator can update the virtual address of the data B of the first application on the hardware accelerator side to the physical address of the data B of the first application on the first DMA memory side in the first SMMU page table. Furthermore, the CPU can also update the virtual address of the data B of the first application on the CPU side to the physical address of the data B of the first application on the first DMA memory side in the first MMU page table. In other words, the hardware accelerator can rebuild the mapping related to the data B of the first application in the first SMMU page table, and the CPU can rebuild the mapping related to the data B of the first application in the first MMU page table.

[0243] For example, regarding the above Figure 5 As shown in the first SMMU page table and the first MMU page table, after the hardware accelerator writes the data 1 of the first application from the disk to the buffer area 1 of the first DMA memory, the hardware accelerator can add a mapping from the virtual address 0x025412CB on the hardware accelerator side to the physical address 0x04F251BC on the first DMA memory side in the first SMMU page table, and the CPU can add a mapping from the virtual address 0x0012321A on the CPU side to the physical address 0x04F251BC on the first DMA memory side in the first MMU page table, thereby obtaining the above-described... Figure 4 The first SMMU page table and the first MMU page table are shown.

[0244] For example, Figure 12 This is a schematic diagram of another hardware accelerator managing a first DMA memory, provided as an embodiment of this application.

[0245] like Figure 12As shown, when the first application switches from foreground to background, the hardware accelerator determines whether the first application is running a background task. If the first application is running a background task, the hardware accelerator determines that the first application's running state is in a non-frozen state. If the first application is not running a background task, the hardware accelerator determines that the first application's running state is in a frozen state. The hardware accelerator determines that the data of the first application in the first DMA memory is no longer being updated, that is, the data of the first application in the first DMA memory is in a stable state and will not be accessed by the CPU and hardware accelerator in the short term. The hardware accelerator swaps out the data B of the first application in the first DMA memory to the disk. The hardware accelerator listens to the first virtual address that the CPU wants to access and determines whether the data A of the first application corresponding to the first virtual address that the CPU wants to access is stored in the first DMA memory. If the data A of the first application corresponding to the first virtual address that the CPU wants to access is stored in the first DMA memory, it is determined that there is no page fault in the first DMA memory. If the data A of the first application corresponding to the first virtual address that the CPU wants to access is not stored in the first DMA memory, the hardware accelerator determines the storage space occupied by the data B of the first application on the disk. If the storage space occupied by the data B of the first application on the disk is less than the second threshold or greater than the third threshold, the hardware accelerator writes the data B of the first application on the disk to the first DMA memory, and updates the first SMMU page table according to the data B of the first application in the first DMA memory, that is, the hardware accelerator triggers a full page write.

[0246] In scenario C, if the storage space occupied by the data of the first application on the disk is less than or equal to the third threshold, the first operation may include writing the data A of the first application from the disk to the first DMA memory, and updating the first SMMU page table based on the data A of the first application in the first DMA memory. In other words, when the hardware accelerator determines that a page fault may occur in the first DMA memory, the hardware accelerator can write the data A of the first application from the disk to the first DMA memory and update the first SMMU page table based on the data A of the first application in the first DMA memory.

[0247] It's understandable that if the data from the first application occupies a small amount of storage space on the disk (e.g., less than or equal to the third threshold), it means that the data from the first application will not increase the disk load, or although it will increase the disk load, the increase will be small. Therefore, after the hardware accelerator determines that the first DMA memory used by the first application may experience a page fault, the hardware accelerator can write the data A of the first application from the disk to the first DMA memory (i.e., single-page write), thereby improving memory management efficiency.

[0248] In one possible implementation, after the hardware accelerator detects the first event, in response to the first event, the hardware accelerator may perform the following steps to write data A from the disk to the first DMA memory, and update the first SMMU page table according to the data A of the first application in the first DMA memory.

[0249] Step d1: The hardware accelerator searches for the third virtual address corresponding to the first virtual address in the first DMA memory page table based on the first virtual address.

[0250] Step d2: The hardware accelerator accesses the data A of the first application in the disk according to the third virtual address and writes the data A of the first application in the disk to the first DMA memory.

[0251] Step d3: The hardware accelerator adds a mapping from the third virtual address to the second physical address to the first SMMU page table.

[0252] It is understandable that after the hardware accelerator writes the data A of the first application from the disk to the first DMA memory, the hardware accelerator can add a virtual address of the data A of the first application on the hardware accelerator side to the physical address of the data B of the first application on the first DMA memory side in the first SMMU page table. Furthermore, the CPU can also add a virtual address of the data A of the first application on the CPU side to the physical address of the data A of the first application on the first DMA memory side in the first MMU page table. In other words, the hardware accelerator can rebuild the mapping associated with the data A of the first application in the first SMMU page table, and the CPU can rebuild the mapping associated with the data A of the first application in the first MMU page table.

[0253] For example, Figure 13 This is a schematic diagram of another hardware accelerator managing a first DMA memory, provided as an embodiment of this application.

[0254] like Figure 13As shown, when the first application switches from foreground to background, the hardware accelerator determines whether the first application is running a background task. If the first application is running a background task, the hardware accelerator determines that the first application's running state is in a non-frozen state. If the first application is not running a background task, the hardware accelerator determines that the first application's running state is in a frozen state. The hardware accelerator determines that the data of the first application in the first DMA memory is no longer being updated, that is, the data of the first application in the first DMA memory is in a stable state and will not be accessed by the CPU and hardware accelerator in the short term. The hardware accelerator swaps out the data B of the first application in the first DMA memory to the disk. The hardware accelerator listens to the first virtual address that the CPU wants to access and determines whether the data A of the first application corresponding to the first virtual address that the CPU wants to access is stored in the first DMA memory. If the data A of the first application corresponding to the first virtual address that the CPU wants to access is stored in the first DMA memory, it is determined that there is no page fault in the first DMA memory. If the data A of the first application corresponding to the first virtual address that the CPU wants to access is not stored in the first DMA memory, the hardware accelerator determines the storage space occupied by the data B of the first application on the disk. If the storage space occupied by the data B of the first application on the disk is less than or equal to the third threshold, the hardware accelerator writes the data A of the first application on the disk to the first DMA memory, and updates the first SMMU page table according to the data A of the first application in the first DMA memory, that is, the hardware accelerator triggers a single page write.

[0255] For example, Figure 14 This is a schematic diagram illustrating the writing of some or all of the data of a first application on a disk to a first DMA memory, as provided in an embodiment of this application. Figure 14 As shown, rewriting after disk write can be divided into three steps, which will be introduced below.

[0256] Step 1: The hardware accelerator writes the data of the first application in the buffer area N of the disk to the first DMA memory, i.e., rewrites it.

[0257] Step 4: The hardware accelerator adds a mapping from the virtual address 0x013412AF on the hardware accelerator side to the physical address 0x04F261BC on the first SMMU page table, i.e., remapping.

[0258] Step 3: The first application is in an unfrozen state. This means the first application is running tasks, and the CPU, acting as the producer, continuously writes data to the first DMA memory used by the first application; that is, the producer is continuously producing data. The hardware accelerator, acting as the consumer, continuously reads data from the first DMA memory used by the first application; that is, the consumer is continuously consuming data.

[0259] Based on the above scheme, the hardware accelerator can handle the possible page faults of the first DMA memory by performing the first operation after determining that the probability of a page fault in the first DMA memory used by the first application is greater than zero, thereby improving memory management efficiency.

[0260] Based on the above embodiments and the same concept, this application also provides an electronic device for implementing the memory management method provided in this application.

[0261] like Figure 15 As shown, the electronic device 1500 may include: a memory 1501, one or more processors 1502, and one or more computer programs (not shown in the figure). These devices can be coupled via one or more communication buses 1503. Optionally, when the electronic device 1500 is used to implement the memory management method provided in the embodiments of this application, the electronic device 1500 may further include a display screen 1504.

[0262] The memory 1501 stores one or more computer programs (code), each including computer instructions; one or more processors 1502 call the computer instructions stored in the memory 1501, causing the electronic device 1500 to execute the memory management method provided in this embodiment. The display screen 1504 is used to display images, videos, application interfaces, and other related user interfaces.

[0263] In a specific implementation, memory 1501 may include high-speed random access memory and may also include non-volatile memory, such as one or more disk storage devices, flash memory devices, or other non-volatile solid-state storage devices. Memory 1501 may store an operating system (hereinafter referred to as the system), such as embedded operating systems like Android, iOS, Windows, or Linux. Memory 1501 can be used to store implementation programs of the embodiments of this application. Memory 1501 may also store network communication programs, which can be used to communicate with one or more additional devices, one or more user devices, or one or more electronic devices. One or more processors 1502 may be a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits used to control the execution of programs in the scheme of this application.

[0264] It should be noted that, Figure 15 This is merely one implementation of the electronic device 1500 provided in this application embodiment. In actual applications, the electronic device 1500 may include more or fewer components, which is not limited here.

[0265] Based on the above embodiments and the same concept, this application also provides a computer-readable storage medium storing a computer program that, when run on a computer, causes the computer to execute the memory management method provided in the above embodiments.

[0266] Based on the above embodiments and the same concept, this application also provides a computer program product, which includes a computer program or instructions. When the computer program or instructions are run on a computer, the computer executes the memory management method provided in the above embodiments.

[0267] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0268] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0269] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0270] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0271] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A memory management method, characterized in that, Applied to electronic devices, the method includes: The hardware accelerator of the electronic device detects a first event; wherein the first event indicates that the probability of a page fault occurs in the first direct memory access DMA memory used by the first application is greater than a first threshold, the first event includes the first application's running state switching from a frozen state to a non-frozen state, and / or, the first event includes the data corresponding to the first virtual address to be accessed by the central processing unit (CPU) of the electronic device not being stored in the first DMA memory. In response to the first event, the hardware accelerator performs a first operation; wherein the first operation includes one or more of the following: Kill the first process of the first application; Write the first data of the first application in the disk to the first DMA memory, and update the first memory page table according to the first data in the first DMA memory. The first memory page table includes a mapping from the virtual address on the hardware accelerator side to the physical address on the first DMA memory side.

2. The method as described in claim 1, characterized in that, The first data is either the second data or the third data. The second data includes the third data. The second data is all the data of the first application stored in the disk. The third data is part of the data of the first application stored in the disk. The part of the data is the data corresponding to the first virtual address that the CPU of the electronic device needs to access.

3. The method as described in claim 2, characterized in that, Before the hardware accelerator detects the first event, the method further includes: The hardware accelerator detects a second event; wherein the second event includes the first application switching its running state from a non-frozen state to a frozen state; In response to the second event, the hardware accelerator swaps the second data in the first DMA memory to the disk and updates the first memory page table based on the second data in the disk.

4. The method as described in claim 3, characterized in that, The first DMA memory includes a first buffer queue, and the second data is stored in the first buffer queue; The hardware accelerator swaps the second data from the first DMA memory to the disk, including: The hardware accelerator detects a third event; wherein the third event indicates that the data in the first DMA memory is no longer being updated, and / or, the identifier of each buffer area in the first buffer queue is a first identifier, the first identifier being used to indicate that the data in the corresponding buffer area can be swapped out to the disk by the hardware accelerator; In response to the third event, the hardware accelerator swaps out the data in each buffer region of the first buffer queue to the disk.

5. The method as described in claim 3 or 4, characterized in that, The hardware accelerator updates the first memory page table based on the second data in the disk, including: The hardware accelerator deletes the mapping from the second virtual address to the first physical address in the first memory page table; wherein the second virtual address is the virtual address corresponding to the second data on the hardware accelerator side, and the first physical address is the physical address corresponding to the second data on the first DMA memory side.

6. The method as described in any one of claims 2-5, characterized in that, The first data is the second data, and the hardware accelerator writes the first data from the disk to the first DMA memory, including: The hardware accelerator writes the second data from the disk to the second buffer queue in the first DMA memory.

7. The method as described in claim 6, characterized in that, The method further includes: The hardware accelerator detects a fourth event; wherein the fourth event indicates that the data in the first buffer region of the first buffer queue is different from the data in the first buffer region of the second buffer queue, and / or, the data in the last buffer region of the first buffer queue is different from the data in the last buffer region of the second buffer queue, the first buffer queue being the buffer queue in which the second data was stored before it was swapped out from the first DMA memory to the disk; In response to the fourth event, the hardware accelerator kills the first process of the first application.

8. The method as described in claim 6, characterized in that, The method further includes: The hardware accelerator detects a fifth event; wherein the fifth event indicates that the data in the first buffer region of the first buffer queue is the same as the data in the first buffer region of the second buffer queue, and that the data in the last buffer region of the first buffer queue is the same as the data in the last buffer region of the second buffer queue, wherein the first buffer queue is the buffer queue in which the second data was stored before it was swapped out from the first DMA memory to the disk; In response to the fifth event, the hardware accelerator updates the first memory page table based on the second data in the first DMA memory.

9. The method as described in any one of claims 6-8, characterized in that, The hardware accelerator updates the first memory page table based on the first data in the first DMA memory, including: The hardware accelerator adds a mapping from a second virtual address to a first physical address to the first memory page table; wherein the second virtual address is the virtual address corresponding to the second data on the hardware accelerator side, and the first physical address is the physical address corresponding to the second data on the first DMA memory side.

10. The method according to any one of claims 2-5, characterized in that, The first data is the third data, and the hardware accelerator writes the first data from the disk to the first DMA memory, including: The hardware accelerator obtains a third virtual address by querying a second memory page table based on the first virtual address; wherein, the second memory page table includes a mapping from the virtual address on the CPU side to the virtual address on the hardware accelerator side, and the third virtual address is the virtual address corresponding to the third data on the hardware accelerator side. The hardware accelerator accesses the third data in the disk according to the third virtual address and writes the third data in the disk to the first DMA memory.

11. The method as described in claim 10, characterized in that, The hardware accelerator updates the first memory page table based on the first data in the first DMA memory, including: The hardware accelerator adds a mapping from a third virtual address to a second physical address to the first memory page table; wherein the third virtual address is the virtual address corresponding to the third data on the hardware accelerator side, and the second physical address is the physical address corresponding to the third data on the first DMA memory side.

12. The method according to any one of claims 1-11, characterized in that, The method further includes: When the first application switches from foreground to background operation, and the first application is not running background tasks, the hardware accelerator determines that the running state of the first application switches from an unfrozen state to a frozen state; or, When the first application switches from background to foreground or runs a background task, the hardware accelerator determines that the running state of the first application switches from frozen to unfrozen.

13. An electronic device, characterized in that, The electronic device includes: one or more processors and memory; The memory is coupled to the one or more processors, the memory being used to store computer program code, the computer program code including computer instructions, the one or more processors invoking the computer instructions to cause the electronic device to perform the method as described in any one of claims 1-12.

14. A chip system, characterized in that, The chip system is applied to an electronic device, the chip system including one or more processors, the processors being configured to invoke computer instructions to cause the electronic device to perform the method as described in any one of claims 1-12.

15. A computer-readable storage medium comprising instructions, characterized in that, When the instructions are executed on an electronic device, the electronic device causes the electronic device to perform the method as described in any one of claims 1-12.

16. A computer program product, characterized in that, Includes computer-readable instructions that, when executed by one or more processors, implement the method as described in any one of claims 1-12.

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