Chip functional safety design automation verification method, device, equipment and medium

Abstract

The application discloses a kind of chip function safety design automation verification method, device, equipment and medium, it is related to chip design technical field, the method includes reading wrong insertion simulation requirement table to obtain simulation test case and running, the incentive needed for producing FIT simulation, and based on simulation test case running situation, abnormal simulation test case is eliminated;FIT simulation environment file is detected, and the generation of FIT simulation verification environment, the formulation of FIT simulation process and the required incentive according to FIT simulation type are matched;FIT simulation is executed, FIT simulation result report is generated based on FIT simulation result or FIT simulation process is adjusted to execute FIT simulation again.The present application can effectively reduce artificial workload, improve work efficiency, avoid error occurrence by formulating standardized, quantifiable, statistical, efficient positioning wrong insertion simulation process.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip design, in particular to a chip function safety design automatic verification method, device, equipment and medium. BACKGROUND

[0002] When performing FIT (fault injection) simulation on each IP (Intellectual Property, a design with independent intellectual property in an integrated circuit), a FUSA (Function Safety) verification environment needs to be manually built, and a diagnostic rate report is obtained after the verification environment is run by manually using tool commands. A plurality of excitation generation files evcd (a file format used to record signal changes in digital circuit simulation) required for simulation are matched by each IP independently.

[0003] The excitation generation file evcd is obtained during function simulation and manually transplanted to the testbench (a verification means) verification environment of FUSA, and can be used only after that. Each IP independently maintains an observation environment file strobe.sv, which is used for analyzing the coverage of the function safety logic by the FIT simulation tool. When Dump (download storage simulation result information) waveforms are needed, each IP independently maintains a waveform generation script Dump.sh, as well as the error insertion information, observation information and diagnostic information list required for FIT simulation.

[0004] For the existing simulation method, the following problems exist:

[0005] (1) When performing FIT simulation, each IP needs to be manually written and debugged to build the FUSA verification environment, and the tool commands need to be manually run to complete the FIT simulation and obtain the results, and the results need to be manually judged. When the number of IPs is large, the human resources are consumed greatly, and the verification efficiency is low;

[0006] (2) When the error insertion information, observation information and diagnostic information list required for FIT simulation of each IP are large, manual operation using each set of error insertion information, observation information and diagnostic information for FIT simulation is prone to miss some set of error insertion information, observation information and diagnostic information;

[0007] (3) A large amount of manual work is prone to cause differences in the execution of the FIT simulation verification process, the workload is difficult to quantify, and the simulation process cannot be finely managed;

[0008] (4) The FIT simulation verification environment and verification process need to be manually modified according to the differences in the function safety design of a large SOC (System On Chip, system on chip). SUMMARY

[0009] The application provides a chip functional safety design automated verification method, device, equipment and medium. By formulating a standardized, quantifiable, statistical and efficient positioning error insertion simulation process, the application can effectively reduce the manual workload, improve the work efficiency and avoid errors.

[0010] In a first aspect, the application provides a chip functional safety design automated verification method, which comprises the following steps:

[0011] reading an error insertion simulation requirement table to obtain a simulation test case and running the simulation test case to generate an excitation required for FIT simulation, and eliminating an abnormal simulation test case based on a running condition of the simulation test case;

[0012] detecting a FIT simulation environment file, generating a FIT simulation verification environment, formulating a FIT simulation process, and matching a required excitation according to a FIT simulation type;

[0013] performing FIT simulation, generating a FIT simulation result report based on a FIT simulation result, or adjusting a FIT simulation process to perform FIT simulation again.

[0014] In combination with the first aspect, in an implementation mode, the reading of the error insertion simulation requirement table to obtain the simulation test case and the running of the simulation test case to generate the excitation required for the FIT simulation specifically comprises the following steps:

[0015] reading the error insertion simulation requirement table through fit_regression, and identifying each member information in the error insertion simulation requirement table;

[0016] automatically matching the simulation test case and running the simulation test case based on the simulation excitation information in the error insertion simulation requirement table, and generating the excitation required for the FIT simulation in the simulation test case running.

[0017] In combination with the first aspect, in an implementation mode, the eliminating of the abnormal simulation test case based on the running condition of the simulation test case specifically comprises the following steps:

[0018] checking the running condition of each simulation test case through sitimulus check, if the current simulation test case is abnormal, reporting through report and eliminating the current simulation test case from the FIT simulation, otherwise, the current simulation test case is retained.

[0019] In combination with the first aspect, in an implementation mode, the performing of the FIT simulation, the generating of the FIT simulation result report based on the FIT simulation result, or the adjusting of the FIT simulation process to perform the FIT simulation again specifically comprises the following steps:

[0020] performing the FIT simulation, and generating the FIT simulation result report based on the FIT simulation result.

[0021] If the FIT simulation result meets the preset simulation requirement, a FIT simulation result report is generated and published.

[0022] If the FIT simulation result does not meet the preset simulation requirement, the FIT simulation process is adjusted, and then the FIT simulation is executed again.

[0023] In combination with the first aspect, in an implementation mode, the adjustment of the FIT simulation process specifically includes:

[0024] According to the FIT simulation result, it is analyzed whether the formulated FIT simulation flow is correct:

[0025] If not, the FIT simulation flow is adjusted;

[0026] If yes, it is analyzed whether the configuration of the FIT simulation verification environment is correct:

[0027] If not, the FIT simulation verification environment is generated again;

[0028] If correct, it is analyzed whether the stimuli required for the FIT simulation are sufficient, if not, the stimuli required for the FIT simulation are continuously generated, and if yes, the mis-inserted simulation requirement in the mis-inserted simulation requirement table is adjusted.

[0029] In combination with the first aspect, in an implementation mode,

[0030] In the execution of the FIT simulation according to the formulated FIT simulation flow, isolation technology is adopted for stimulus isolation, simulation object top layer limitation and compilation isolation operation, so as to adapt the FIT simulation to the IP level, the subsystem level and the SOC level.

[0031] In combination with the first aspect, in an implementation mode,

[0032] The stimulus isolation includes configuring the hierarchical compilation information of the stimulus collection interface layer to isolate the interface stimulus collection, configuring the hierarchy of the Dump stimulus file to isolate the high-level interface stimulus, and ensuring the single naming of the stimulus file without duplication;

[0033] The compilation isolation includes defining the compilation module setting compilation command to specify the compilation options, the compilation tool and the environment variable, and the compilation macro specification to compile the top layer specification.

[0034] The simulation object top layer limitation includes specifying the interface information of the top layer, setting the monitoring interface of the observation point and the diagnosis point.

[0035] The second aspect, the embodiment of the application provides a chip functional safety design automation verification device, the chip functional safety design automation verification device includes:

[0036] a reading module configured to read the mis-insertion simulation requirement table to obtain a simulation test case and run the simulation test case to generate a stimulus required for FIT simulation and eliminate abnormal simulation test cases based on a running condition of the simulation test case;

[0037] a generating module configured to detect a FIT simulation environment file and generate a FIT simulation verification environment, formulate a FIT simulation flow, and match a required stimulus according to a FIT simulation type;

[0038] an executing module configured to execute the FIT simulation, generate a FIT simulation result report based on a FIT simulation result, or adjust the FIT simulation process to execute the FIT simulation again.

[0039] In a third aspect, an embodiment of the present application provides a chip functional safety design automated verification device, which comprises a processor, a memory, and a chip functional safety design automated verification program stored in the memory and executable by the processor, wherein when the chip functional safety design automated verification program is executed by the processor, the steps of the chip functional safety design automated verification method described above are implemented.

[0040] In a fourth aspect, an embodiment of the present application provides a computer readable storage medium, which stores a chip functional safety design automated verification program, wherein when the chip functional safety design automated verification program is executed by a processor, the steps of the chip functional safety design automated verification method described above are implemented.

[0041] The technical scheme provided by the embodiment of the present application has the following beneficial effects:

[0042] (1) By formulating a standardized, quantifiable, statistical, and efficient mis-insertion simulation flow, the manual workload can be effectively reduced, the work efficiency can be improved, and errors can be avoided;

[0043] (2) The embodiment of the present application can solve the problems of difficult maintenance and high independent development cost of FIT verification environments of different levels in large SOC projects by providing a mis-insertion simulation flow architecture that can simultaneously adapt to IP level, subsystem level, and SOC level;

[0044] (3) The embodiment of the present application can standardize the statistics and publication of mis-insertion simulation results by designing a verification environment and running related instructions for automatically generating mis-insertion simulation, thereby timely and comprehensively feeding back the running results, reducing the labor cost of collecting results, and reducing the possibility of making mistakes in the process of collecting results. BRIEF DESCRIPTION OF DRAWINGS

[0045] Figure 1 FIG. 1 is a flowchart of a chip functional safety design automated verification method according to an embodiment of the present application;

[0046] Figure 2 Adapt isolation map for each level of FIT;

[0047] Figure 3 Functional module schematic diagram of the chip functional safety design automation verification device of the present application;

[0048] Figure 4 Hardware structure schematic diagram of the chip functional safety design automation verification device of the present application. DETAILED DESCRIPTION

[0049] In order for those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0050] In order to make the purpose, technical solutions and advantages of the present application clearer, the embodiments of the present application will be described in further detail below with reference to the drawings.

[0051] In a first aspect, the embodiments of the present application provide a chip functional safety design automation verification method. In combination with actual applications, by formulating a standardized, quantifiable, statistical and efficient positioning error insertion simulation process, the process execution difference problem in the FIT simulation process is reduced. The embodiments of the present application provide an error insertion simulation process architecture that can simultaneously adapt to IP level, subsystem level and SOC level, unify the FIT simulation environment building of various levels, and design a verification environment and related instructions that can automatically generate error insertion simulation, and can perform standardized statistics and publish error insertion simulation results.

[0052] In an embodiment, reference is made to Figure 1 , Figure 1 The flowchart of the chip functional safety design automation verification method of the present application is shown in FIG. 1. As shown in FIG. 1, the chip functional safety design automation verification method comprises the following steps. Figure 1

[0053] S1: read the error insertion simulation requirement table to obtain simulation test cases and run, generate the excitation required by FIT simulation, and eliminate abnormal simulation test cases based on the simulation test case running situation;

[0054] S2: detect the FIT simulation environment file, and generate the FIT simulation verification environment, formulate the FIT simulation process, and match the required excitation according to the FIT simulation type;

[0055] ​S3: performing FIT simulation, generating FIT simulation result report based on FIT simulation result or adjusting FIT simulation process to perform FIT simulation again.

[0056] Specifically, in actual application, fit_regression is taken as the entrance to read the fault insertion simulation requirement table first, and the above process is completed by identifying the members in the simulation requirement table. The identification of the members in the simulation requirement table includes setting macro definition, file list of simulation, generating directory structure prefix information, subsystem path information, generating directory structure suffix information, excitation name list, simulation command option generated by excitation, and excitation file download automation script name. Among them, the program or device is started by running the fitregression command, and fit_regression represents fault injection batch regression.

[0057] Further, in an embodiment, the fault insertion simulation requirement table is read to obtain simulation test cases and run, and the excitation required by FIT simulation is generated, specifically including:

[0058] S101: reading the fault insertion simulation requirement table by fit_regression, and identifying the information of each member in the fault insertion simulation requirement table;

[0059] S102: function regression (functional simulation batch regression) automatically matches simulation test cases and runs based on the simulation excitation information in the fault insertion simulation requirement table, and the excitation required by FIT simulation is generated during the running of the simulation test cases.

[0060] Specifically, function regression automatically matches simulation test cases and runs the simulation test cases by the simulation excitation information in the fault insertion simulation requirement table, and the excitation required by FIT simulation is generated during the running of the simulation test cases. For the simulation excitation information, the full name of the directory generated by the simulation excitation and the test.evcd file are included.

[0061] Further, in an embodiment, abnormal simulation test cases are removed based on the running of the simulation test cases, specifically including:

[0062] sitimulus check (stimulus check) checks the running of each simulation test case, if the current simulation test case is abnormal, it reports and removes the current simulation test case from FIT simulation, otherwise, it retains the current simulation test case.

[0063] Specifically, the sitimulus check checks the running situation of the simulation test case of the FIT simulation, and if the simulation test case fails in the checking process, a report is generated and the current simulation test case is excluded from the FIT simulation. In the running of the simulation test case, if the simulation result does not have the PASS word or the ERROR word appears in the simulation, it indicates that the current simulation test case has an exception.

[0064] Further, in an embodiment, for detecting the FIT simulation environment file and generating the FIT simulation verification environment, formulating the FIT simulation process and matching the required excitation according to the FIT simulation type, specifically, the FIT simulation environment file is checked to confirm whether the FIT simulation environment file is sufficient for FIT simulation. For fit simulation (fault injection simulation), it includes three sub-steps, which are FIT simulation verification environment generation, error insertion simulation requirement table analysis and FIT simulation automatic execution.

[0065] Further, in an embodiment, FIT simulation is performed, FIT simulation result report is generated based on the FIT simulation result or FIT simulation process is adjusted to perform FIT simulation again, specifically including:

[0066] FIT simulation is performed, and based on the FIT simulation result:

[0067] If the FIT simulation result meets the preset simulation requirement, a FIT simulation result report is generated and published;

[0068] If the FIT simulation result does not meet the preset simulation requirement, the FIT simulation process is adjusted, and then the FIT simulation is performed again.

[0069] Specifically, after performing the FIT simulation and waiting for the FIT simulation to end, whether the FIT simulation result meets the requirement (the actual value of the diagnostic coverage rate is greater than or equal to the ideal input value, which indicates that it meets the requirement) is counted one by one. If it meets the requirement, a FIT simulation result report is generated and published; if it does not meet the requirement, a backtracking process is performed, the FIT simulation process is adjusted, and the FIT simulation is restarted.

[0070] Further, in an embodiment, for adjusting the FIT simulation process, specifically including:

[0071] According to the FIT simulation result, whether the formulated FIT simulation process is correct is analyzed:

[0072] If not, the FIT simulation process is adjusted;

[0073] If yes, whether the configuration of the FIT simulation verification environment is correct is analyzed:

[0074] - if not, then re-generate the FIT simulation verification environment;

[0075] - if yes, then analyze if the stimuli required for the FIT simulation is sufficient, if not, then continue to generate the stimuli required for the FIT simulation, if yes, then adjust the FIT simulation requirements in the FIT simulation requirements table.

[0076] The chip functional safety design automation verification method of the present application is described in detail as follows.

[0077] a: read the FIT simulation requirements table, go to b;

[0078] b: generate the stimuli required for the FIT simulation according to the requirements, go to c;

[0079] c: check if the FIT simulation environment file has the FIT simulation conditions, go to d;

[0080] d: generate one or more FIT simulation verification environments, go to e;

[0081] e: match the required stimuli according to the FIT simulation type, go to f;

[0082] f: customize the FIT simulation process, go to g;

[0083] g: run the FIT simulation, go to h;

[0084] h: judge if the FIT simulation result meets the expectation, if yes, go to i, if not, go to j;

[0085] i: generate the FIT simulation result report and publish, end;

[0086] j: analyze if the FIT simulation process is correct, if not, go to f, if yes, go to k;

[0087] k: analyze if the configuration of the FIT simulation verification environment is correct, if not, go to d, if yes, go to l;

[0088] l: analyze if the stimuli required for the FIT simulation is sufficient, if not, go to b, if yes, go to m;

[0089] m: adjust the FIT simulation requirements in the FIT simulation requirements table, go to a.

[0090] Further, referring to Figure 2As shown, when performing FIT simulation according to the formulated FIT simulation process, excitation isolation, simulation object top layer limitation and compilation isolation operation are performed by using isolation technology to adapt FIT simulation to IP level, subsystem level and SOC level. That is, by using isolation technology, the same FIT simulation is adapted to IP level, subsystem level and SOC level through simulation isolation mode.

[0091] In the present application, the excitation isolation includes configuring excitation collection interface layer compilation information to isolate interface excitation collection, configuring the layer of Dump excitation file to isolate high-level interface excitation, and ensuring that the excitation file has a single name without duplication; the compilation isolation includes defining compilation module setting compilation command to specify compilation options, specifying compilation tools and environment variables, and compiling macro specification to compile top layer specification; the simulation object top layer limitation includes specifying interface information of the top layer, setting monitoring interface of observation points and diagnosis points.

[0092] That is, by placing the structure of FIT simulation environment file isolation, the isolation of directory retrieval can produce reasonable FIT simulation environment in different levels of circuit design.

[0093] The chip functional safety design automation verification method of the present application can effectively reduce the manual workload, improve the work efficiency and avoid errors by formulating a standardized, quantifiable, statistical and efficient positioning error insertion simulation process. The present application can solve the problems of difficult maintenance and high independent development cost of FIT verification environment of different levels in large SOC projects by providing an error insertion simulation process architecture that can adapt to IP level, subsystem level and SOC level. The present application can automatically generate a verification environment and related instructions for error insertion simulation, and can standardize and publish error insertion simulation results, so as to timely and comprehensively feedback the running results, reduce the labor cost of collecting results, and reduce the possibility of making mistakes in the process of collecting results.

[0094] In a second aspect, the present application also provides a chip functional safety design automation verification device.

[0095] In an embodiment, the chip functional safety design automation verification device comprises a reading module, a generating module and an executing module. Figure 3 , Figure 3 FIG. 1 is a schematic diagram of a functional module of the chip functional safety design automation verification device of the present application. As shown in FIG. 1, the chip functional safety design automation verification device comprises a reading module, a generating module and an executing module. Figure 3

[0096] ​The reading module is configured to read the misinsertion simulation requirement table to obtain a simulation test case and run, generate a required excitation for FIT simulation, and eliminate an abnormal simulation test case based on a running condition of the simulation test case; the generating module is configured to detect a FIT simulation environment file, and generate a FIT simulation verification environment, formulate a FIT simulation process, and match a required excitation according to a FIT simulation type; and the executing module is configured to execute the FIT simulation, generate a FIT simulation result report based on a FIT simulation result, or adjust the FIT simulation process to execute the FIT simulation again.

[0097] In a third aspect, embodiments of the present application provide a chip functional safety design automated verification device. The chip functional safety design automated verification device can be a personal computer (PC), a notebook computer, a server, or other device with data processing capabilities.

[0098] Reference Figure 4 , Figure 4 FIG. 1 is a schematic diagram of a hardware structure of a chip functional safety design automated verification device according to an embodiment of the present application. In the embodiment, the chip functional safety design automated verification device can include a processor, a memory, a communication interface, and a communication bus.

[0099] The communication bus can be of any type and is used to interconnect the processor, the memory, and the communication interface.

[0100] The communication interface includes an input / output (I / O) interface, a physical interface, and a logical interface, and other interfaces used to interconnect devices within the chip functional safety design automated verification device, and interfaces used to interconnect the chip functional safety design automated verification device with other devices (e.g., other computing devices or user devices). The physical interface can be an Ethernet interface, a fiber interface, an ATM interface, etc. The user device can be a display (Display), a keyboard (Keyboard), etc.

[0101] The memory can be various types of storage media, such as random access memory (RAM), read-only memory (ROM), non-volatile RAM (NVRAM), flash memory, optical storage, hard disk, programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), etc.

[0102] The processor can be a general-purpose processor, which can invoke a chip functional safety design automation verification program stored in the memory and execute the chip functional safety design automation verification method provided in the embodiments of the present application. For example, the general-purpose processor can be a central processing unit (CPU). The method executed when the chip functional safety design automation verification program is invoked can refer to the embodiments of the chip functional safety design automation verification method of the present application, which will not be described here.

[0103] Those skilled in the art can understand that the hardware structure shown in the foregoing embodiments is not a limitation on the present application, and can include more or fewer components than those shown, or combine certain components, or different component arrangements. Figure 4 Those skilled in the art can understand that the hardware structure shown in the foregoing embodiments is not a limitation on the present application, and can include more or fewer components than those shown, or combine certain components, or different component arrangements.

[0104] In a fourth aspect, the embodiments of the present application further provide a computer readable storage medium.

[0105] The computer readable storage medium of the present application stores a chip functional safety design automation verification program, wherein the chip functional safety design automation verification program, when executed by a processor, implements the steps of the chip functional safety design automation verification method as described above.

[0106] The method implemented when the chip functional safety design automation verification program is executed can refer to the embodiments of the chip functional safety design automation verification method of the present application, which will not be described here.

[0107] The terms "comprising" and "having" and any variations thereof in the specification and claims of the present application and the above-described drawings are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units is not limited to the listed steps or units, but can optionally further include steps or units not listed, or can optionally further include other steps or units inherent to the process, method, product or device. The terms "first", "second" and "third" and the like descriptions are used to distinguish different objects, and do not represent the order or limit the types of "first", "second" and "third".

[0108] In the description of the embodiments of the present application, "exemplary", "for example", "for instance" or "such as" are used to represent an example, illustration or description. Any embodiment or design scheme described as "exemplary", "for example", "for instance" or "such as" in the embodiments of the present application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes. Rather, the words "exemplary", "for example", "for instance" or "such as" are intended to present the relevant concept in a specific manner.

[0109] ​In the description of the embodiments of the present application, unless otherwise specified, " / " means the meaning of or, for example, A / B can mean A or B; the text "and / or" only describes the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent: A exists alone, A and B exist together, and B exists alone, and in addition, in the description of the embodiments of the present application, "multiple" means two or more than two.

[0110] In some of the processes described in the embodiments of the present application, a plurality of operations or steps are included in a specific order, but it should be understood that these operations or steps can be executed or in parallel without the order in which they appear in the embodiments of the present application, and the serial number of the operation is only used to distinguish different operations, and the serial number itself does not represent any execution order. In addition, these processes can include more or fewer operations, and these operations or steps can be executed in sequence or in parallel, and these operations or steps can be combined.

[0111] From the above description of the embodiments, those skilled in the art can clearly understand that the above-mentioned embodiment method can be realized by means of software and the necessary general hardware platform, of course, it can also be realized by hardware, but in many cases the former is a better embodiment. Based on such understanding, the technical solutions of the present application can be embodied in the form of a software product, which is stored in a storage medium (such as a ROM / RAM, a magnetic disk, an optical disk) as described above, and includes a plurality of instructions for making a terminal device execute the method described in each embodiment of the present application.

[0112] The above is only the preferred embodiment of the present application, and does not limit the patent scope of the present application, and any equivalent structure or equivalent process transformation using the content of the present application specification and drawings, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. An automated verification method for chip functional safety design, characterized in that, The automated verification method for chip functional safety design includes: Read the simulation requirement table to obtain simulation test cases and run them to generate the stimuli required for FIT simulation. Then, based on the running status of the simulation test cases, eliminate abnormal simulation test cases. The FIT simulation environment file is checked, and the FIT simulation verification environment is generated, the FIT simulation process is formulated, and the required stimuli are matched according to the FIT simulation type. Perform a FIT simulation, generate a FIT simulation result report based on the FIT simulation results, or adjust the FIT simulation process and perform the FIT simulation again; Among them, when performing FIT simulation according to the established FIT simulation process, isolation technology is used to perform stimulus isolation, top-level limitation of simulation objects and compilation isolation operations, so as to adapt FIT simulation to IP level, subsystem level and SOC level; The incentive isolation includes configuring incentive collection interface layer compilation information to isolate interface incentive collection, configuring the layer of dump incentive files to isolate high-level interface incentives, and ensuring that incentive files have unique and non-duplicate names. The compilation isolation includes defining compilation module settings, setting compilation commands to specify compilation options, specifying compilation tools and environment variables, and specifying compilation macros to compile the top-level specification. The top-level definition of the simulation object includes specifying the top-level interface information and setting the monitoring interface for observation points and diagnostic points.

2. The automated verification method for chip functional safety design as described in claim 1, characterized in that, The process of reading the insertion error simulation requirement table to obtain simulation test cases and running them generates the stimuli required for FIT simulation, specifically including: The insertion error simulation requirement table is read using fit_regression, and the information of each member in the insertion error simulation requirement table is identified. Function regression automatically matches and runs simulation test cases based on the simulation stimulus information in the simulation requirement table, and generates the stimulus required for FIT simulation during the execution of the simulation test cases.

3. The automated verification method for chip functional safety design as described in claim 1, characterized in that, The process of eliminating abnormal simulation test cases based on the execution status of simulation test cases specifically includes: The sitimulus check checks the running status of each simulation test case. If the current simulation test case has an anomaly, a report is submitted and the current simulation test case is removed from the FIT simulation; otherwise, the current simulation test case is retained.

4. The automated verification method for chip functional safety design as described in claim 1, characterized in that, The process of performing FIT simulation, generating a FIT simulation result report based on the FIT simulation results, or adjusting the FIT simulation process and re-performing the FIT simulation specifically includes: Perform a FIT simulation and analyze the results: If the FIT simulation results meet the preset simulation requirements, a FIT simulation result report will be generated and published. If the FIT simulation results do not meet the preset simulation requirements, adjust the FIT simulation process and then execute the FIT simulation again.

5. The automated verification method for chip functional safety design as described in claim 1, characterized in that, The adjustments to the FIT simulation process specifically include: Based on the FIT simulation results, analyze whether the established FIT simulation process is correct: If not, adjust the FIT simulation process; If so, analyze whether the configuration of the FIT simulation verification environment is correct: - If incorrect, regenerate the FIT simulation verification environment; - If correct, analyze whether the stimulus required for the FIT simulation is sufficient. If not, continue to generate the stimulus required for the FIT simulation. If sufficient, adjust the insertion simulation requirements in the insertion simulation requirement table.

6. An automated verification device for chip functional safety design, characterized in that, The automated verification device for chip functional safety design includes: The reading module is used to read the simulation requirement table to obtain simulation test cases and run them, generate the stimuli required for FIT simulation, and eliminate abnormal simulation test cases based on the running status of the simulation test cases. The generation module is used to detect FIT simulation environment files and generate the FIT simulation verification environment, formulate the FIT simulation process, and match the required stimuli according to the FIT simulation type. The execution module is used to perform FIT simulations, generate FIT simulation result reports based on the FIT simulation results, or adjust the FIT simulation process and perform FIT simulations again. Among them, when performing FIT simulation according to the established FIT simulation process, isolation technology is used to perform stimulus isolation, top-level limitation of simulation objects and compilation isolation operations, so as to adapt FIT simulation to IP level, subsystem level and SOC level; The incentive isolation includes configuring incentive collection interface layer compilation information to isolate interface incentive collection, configuring the layer of dump incentive files to isolate high-level interface incentives, and ensuring that incentive files have unique and non-duplicate names. The compilation isolation includes defining compilation module settings, setting compilation commands to specify compilation options, specifying compilation tools and environment variables, and specifying compilation macros to compile the top-level specification. The top-level definition of the simulation object includes specifying the top-level interface information and setting the monitoring interface for observation points and diagnostic points.

7. An automated verification device for chip functional safety design, characterized in that, The automated verification device for chip functional safety design includes a processor, a memory, and an automated verification program for chip functional safety design stored in the memory and executable by the processor, wherein when the automated verification program for chip functional safety design is executed by the processor, it implements the steps of the automated verification method for chip functional safety design as described in any one of claims 1 to 5.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores an automated verification program for chip functional safety design, wherein when the automated verification program for chip functional safety design is executed by a processor, it implements the steps of the automated verification method for chip functional safety design as described in any one of claims 1 to 5.

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