Optimization method for connection position between parallel lithium ion battery modules

Abstract

The invention discloses a method for optimizing a connection position between parallel lithium ion battery modules, and belongs to the field of performance optimization of battery packs of electric bicycles. Comprising the following steps: calculating all possible connection positions among parallel modules based on mathematical symmetry similarity and permutation and combination to obtain a module current collector position combination list; constructing a parallel module simulation model based on the module current collector position combination list, the electrical parameters of the battery units, the values of the connection resistors and different working conditions; performing simulation test on each current collector based on the parallel module simulation model to obtain non-uniform current quantification results and SoC quantification results under different working conditions; and determining an optimal current collector position based on the non-uniform current quantification result and the SoC quantification result under different working conditions. According to the method, the optimal current collector positions of different numbers of battery parallel modules can be rapidly obtained, and a scientific basis is provided for connection design and optimization between parallel lithium ion battery modules.

Description

Technical Field

[0001] The present invention belongs to the field of electric bicycle battery pack performance optimization, and in particular relates to a method for optimizing the connection positions between parallel lithium-ion battery modules. Background Art

[0002] To address the severe challenges of global environmental pollution and energy shortages caused by excessive fossil fuel consumption, the development and application of electric vehicles and large-scale energy storage systems are becoming increasingly important for reducing carbon emissions. Lithium-ion batteries have become a core component of both systems due to their cost-effectiveness, high energy density, and low self-discharge rate. To meet the capacity and power requirements of practical applications, hundreds of individual cells are typically connected in parallel and then in series. The performance of battery modules, particularly those connected in parallel, plays a crucial role in the overall functionality of the battery pack. However, the inevitable interconnect resistance between cells leads to uneven current flow and system-on-charge (SoC) within the parallel module, significantly reducing the battery pack's service life and safety. Furthermore, parallel modules can be connected in a variety of different connection positions. This results in varying connection resistance between cells, which in turn affects the uniformity of current flow and system-on-charge within the parallel module. Therefore, systematically quantifying the impact of connection resistance and different module current collector positions on uneven current flow and system-on-charge is crucial for improving module safety and performance.

[0003] While existing technical research has minimized inter-cell connection resistance and extensively studied current nonuniformity and SoC at common module current collector locations, a large number of other module current collector locations still require systematic analysis. Furthermore, previous research has mostly been conducted under constant current conditions, whereas in practice, the module's operating environment is dynamically changing, such as during dynamic stress testing. Consequently, existing technologies lack comprehensiveness and adaptability, failing to provide sufficient guidance for optimizing battery module design and usage strategies.

[0004] Therefore, in parallel-connected lithium-ion battery modules, there is a technical problem that needs to be solved urgently: the uneven current distribution and SoC inside the module caused by the inevitable connection resistance will not only reduce the performance of the battery pack, but also seriously affect its service life and reliability. Summary of the Invention

[0005] In order to solve the above technical problems, the present invention proposes a method for optimizing the connection positions between parallel lithium-ion battery modules to solve the problems existing in the above prior art.

[0006] To achieve the above objectives, the present invention provides a method for optimizing the connection positions between parallel lithium-ion battery modules, comprising:

[0007] Based on mathematical symmetry, similarity and permutation and combination, all possible connection positions between parallel modules are calculated to obtain a list of module current collector position combinations;

[0008] Constructing a parallel module simulation model based on the module current collector position combination list, battery cell electrical parameters, connection resistance values, and different operating conditions;

[0009] Based on the parallel module simulation model, simulation tests are performed on each current collector to obtain uneven current quantification results and SoC quantification results under different working conditions;

[0010] The optimal current collector position is determined based on the non-uniform current quantification results and the SoC quantification results under the different working conditions.

[0011] Optionally, the process of building a parallel module simulation model includes:

[0012] Determining a battery cell connection method corresponding to each current collector position based on the module current collector position combination list;

[0013] constructing an equivalent circuit model of each battery cell based on the electrical parameters of the battery cell;

[0014] The equivalent circuit model is connected according to the battery unit connection mode corresponding to the current collector, and the value of the connection resistance is added at the connection to obtain the parallel module simulation model.

[0015] Optionally, the equivalent circuit model of each battery cell is:

[0016]

[0017] Where U T Indicates terminal voltage, I L Indicates the given current, U oc Indicates the voltage of OCV, R0 indicates the battery ohmic internal resistance, U ts and U tl Represents the voltage of two RC parallel pairs, C ts ,R ts ,C tl , and R tl Represent the resistance and capacitance of each of the two resistor-capacitor pairs, respectively.

[0018] Optionally, the process of obtaining the electrical parameters of the battery cell includes:

[0019] Conducting a mixed pulse power characteristic test experiment on the battery cell to obtain experimental data at different states of charge, the experimental data including: open circuit voltage, ohmic internal resistance, and resistance and capacitance parameters at different states of charge;

[0020] The experimental data are fitted using the least squares method to obtain the electrical parameters of the battery cell.

[0021] Optionally, the different working conditions include: a constant current discharge condition and a dynamic stress test condition.

[0022] Optionally, the process of obtaining the non-uniform current quantization result and the SoC quantization result includes:

[0023] In the parallel module simulation model, simulation tests are performed on each module current collector position respectively;

[0024] During the simulation test, the difference between the maximum current and the minimum current of different battery cells at the same time is recorded as a quantitative indicator of uneven current;

[0025] The difference between the maximum SoC and the minimum SoC between different battery cells at the same time is recorded as a quantitative indicator of SoC.

[0026] Optionally, the optimal current collector position satisfies the symmetrical distribution of positive and negative current collectors, and the difference in equivalent resistance from the battery to the current collector on each parallel branch is minimized.

[0027] Compared with the prior art, the present invention has the following advantages and technical effects:

[0028] This paper proposes a method for optimizing the connection positions between parallel lithium-ion battery modules. Through systematic mathematical symmetry, similarity, and permutation and combination calculations, all possible connection positions between parallel modules are comprehensively identified, and a list of current collector position combinations for the parallel modules is obtained. A simulation model is used to quantitatively analyze the current and SoC nonuniformity of each current collector position under different operating conditions. The study found that compared with traditional parallel module current collector positions (such as Z-type current collector positions and ladder-type current collector positions), the optimized current collector positions can significantly reduce the current and SoC nonuniformity within the module, especially under high current rate and dynamic conditions. For example, under 1C discharge conditions, the maximum current difference within the parallel module after the optimized position is reduced by 87.5% compared with the traditional position, and the maximum SoC difference is reduced by 85.7%. In addition, the optimized current collector position also shows better adaptability under dynamic stress test conditions, with its SoC dispersion being only 15% of that of the traditional position. By optimizing the connection positions between battery modules, the current and SoC distribution of the module are more uniform, thereby extending the service life of the battery module and improving the safety and reliability of the battery pack. The present invention can quickly obtain the optimal current collector position for parallel modules with different numbers of batteries, provides a scientific basis for the connection design and optimization between parallel lithium-ion battery modules, and has significant technical effects and practical application value. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings, which constitute part of this application, are intended to provide a further understanding of this application. The exemplary embodiments and descriptions of this application are intended to explain this application and do not constitute an improper limitation on this application. In the accompanying drawings:

[0030] Figure 1 Parallel modules constructed for all possible module collector positions of the embodiment of the present invention; wherein, (a) the connection mode of the battery pack of the electric bicycle in actual application; (b) the parallel module of four single cells (P 1-N1 To P 2-N3 ) of all module current collector positions (six types); (c) different operating conditions, including constant current conditions (1C and 2C (1C = 3A)) and dynamic stress test conditions (DST);

[0031] Figure 2 A test device for conducting mixed pulse power characteristics test experiments;

[0032] Figure 3 The components of the experimental and battery models for the embodiments of the present invention were developed in Matlab / Simscape. (a) shows the electrical parameters used to construct the equivalent circuit model; (b) shows the simulation model of a single battery; and (c) shows the current collector positions of a parallel module including connection resistors.

[0033] Figure 4 Figure 1 shows the non-uniform current (SoC) and current (SoC) difference at the three module current collectors when tested under the 1C discharge state according to an embodiment of the present invention (black lines); wherein (a) shows the non-uniform current and current difference at the trapezoidal module current collector position; (b) shows the non-uniform SoC and SoC difference at the trapezoidal module current collector; (c) shows the non-uniform current and current difference at the Z-shaped module current collector and the optimized module current collector; and (d) shows the non-uniform SoC and SoC difference at the Z-shaped module current collector and the optimized module current collector.

[0034] Figure 5 The maximum current difference and maximum SoC difference of all module current collectors under 1C discharge in the embodiment of the present invention are shown; (a) is the maximum current difference of all module current collectors; (b) is the maximum SoC difference of all module current collectors;

[0035] Figure 6 The quantized non-uniform current (quantized current) and the current difference (quantized current difference (black line)) under the typical module current collector (trapezoidal module current collector position) of the embodiment of the present invention under 1C and 2C discharge conditions are shown;

[0036] Figure 7The non-uniform current, non-uniform SoC, and maximum current (SoC) difference (black lines) inside the module under dynamic stress test conditions at three module current collector positions according to the embodiment of the present invention are shown. (a) shows the non-uniform current and current difference under the trapezoidal module current collector; (b) shows the non-uniform SoC and SoC difference under the trapezoidal module current collector; (c) shows the non-uniform current and current difference under the Z-shaped module current collector and the optimal module current collector; (d) shows the non-uniform SoC and SoC difference under the Z-shaped module current collector and the optimal module current collector.

[0037] Figure 8 is a representative module for calculating current in an embodiment of the present invention, wherein Inter R represents interconnect resistance;

[0038] Figure 9 The present invention is a process for obtaining the number of all optional current collector positions between N battery cells in parallel; wherein, (a) is the number of all optional current collector positions between N battery cells in parallel; 1-N(N-1) The module current collector position can lead to other module current collector positions with the same maximum module internal non-uniform performance; (b) is P i Optional N i ; (c) is the number of module collector positions and P i (or N parallel modules); (d) is the mathematical model of the optimal connection position between N parallel modules;

[0039] Figure 10 This is a flow chart of an embodiment of the invention. DETAILED DESCRIPTION

[0040] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in this application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0041] It should be noted that the steps shown in the flowcharts of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and that, although a logical order is shown in the flowcharts, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0042] Example 1

[0043] Quantifying the impact of module current collectors obtained from the connection positions between all parallel modules on uneven current and SoC is very important for ensuring the safe and efficient operation of the module. Based on mathematical similarity, symmetry and permutation and combination calculations, the present invention defines and obtains for the first time a list of all possible module current collector position combinations belonging to parallel modules with different numbers of cells. Then, a typical four-cell parallel module was developed in Matlab / Simscape as an example to quantify the impact of all module current collectors. In addition, the different working conditions experienced by the module were also considered. The results show that the maximum unevenness is caused when the positive and negative current collectors of the module are simultaneously connected to the edge cells of the parallel module. For example, P 2-N2 The module uneven current and SoC at the module collector position are only P 1-N1 50% and 51% of the module current collector position. In addition, the symmetrical distribution of the positive and negative current collectors of the module shows better uniformity. For example, P 2-N3 Module uneven current and SoC ratio P under module collector position 1-N1 The current difference under the module collector position is 87.5% and 85.7% lower. By increasing the discharge rate from 1C to 2C, the maximum current difference can be increased by 101%. Under the dynamic stress test condition, the maximum SoC difference is only 16% of that under 1C. Even if the uneven current and SoC within the module are reduced in actual application environment, the optimal module collector position will still have a positive impact on the uneven performance of the module. For example, P 2-N3 The module under the module collector position is not SoC than P 1-N1 Based on the above results, the present invention can provide valuable guidance for optimizing battery module design and usage strategy, which will greatly improve the current and SoC uniformity of the module, thereby improving the safety and performance of parallel connected battery systems.

[0044] like Figure 1 and Figure 10 As shown, this embodiment provides a method for optimizing the position of current collectors in a parallel lithium-ion battery module, comprising the following steps:

[0045] Parallel module model development: Based on the electrical parameters and equivalent circuit model of the battery, a description of the modeling and verification of parallel modules with connection resistors in Simscape is given.

[0046] (1) Battery cell model

[0047] The equivalent circuit model (ECM) is widely used due to its relative simplicity, convenient parameterization, and real-time feasibility. This paper adopts the most commonly used second-order RC equivalent circuit to describe the single battery in the parallel module. The developed single-cell equivalent circuit consists of several components: open circuit voltage (OCV), ohmic internal resistance RO and two resistor-capacitor (RC) pairs (C ts ,R ts ,C tl , and R tl ), each pair consists of a resistor and a capacitor in parallel. By applying Kirchhoff's law, the equation system (1) can be obtained from the second-order RC equivalent circuit.

[0048]

[0049] Where U T Indicates terminal voltage, I L Indicates the given current, U oc Indicates the voltage of OCV, R0 indicates the battery ohmic internal resistance, U ts and U tl Represents the voltage of two RC parallel pairs, C ts ,R ts ,C tl , and R tl Represent the resistance and capacitance of each of the two resistor-capacitor pairs, respectively.

[0050] (2) Experiment and module model development

[0051] like Figure 2 As shown in the figure, in order to obtain the parameters of battery cell components under different SoC, a battery cell testing device was developed. In the experiment, the battery voltage was detected using the AGILENT 6.5-digit multimeter 34410A, and the battery discharge equipment used the ITECH IT8513C programmable electronic load. All experiments were completed in an indoor laboratory at a constant temperature of 20°C. The multimeter and electronic load were controlled by computer software to realize the discharge system required for the experiment. These parameters are related to the SoC of the battery cell (ignoring the temperature effect), quantified through a standard hybrid pulse power characteristic test (HPPC) experiment, and adjusted using a recursive least squares algorithm in the Matlab program. These values ​​are then input into the equivalent circuit model as a lookup table for the battery electrical parameters, as shown in Figure 2. Figure 3 In the present invention, based on the second-order RC model, a single battery simulation model of NCM / graphite electrode cylindrical battery was established using MATLAB / Simscape, as shown in FIG. Figure 3 As shown in (b). Then, as Figure 3 As shown in (c), a four-cell parallel module was developed in Matlab / Simscape. The connection resistance between each parallel branch is 1.2mΩ.

[0052] (3) Module simulation process

[0053] like Figure 1As shown in (b), from the positive and negative current collectors at the edge of the parallel module to the last module current collector position (P 2-N3 ) were tested in six different module current collector positions in the order of . At the same time, different working conditions that the actual operating environment of the module may experience were considered, such as Figure 1 As shown in (c), the single cells in the parallel module are marked from left to right as cell #1 to cell #N. The configuration in which the positive current collector is connected to cell #m and the negative current collector is connected to cell #i is marked as P. m-Ni The detailed simulation process of each step in the module is shown in Table 1.

[0054] Table 1

[0055]

[0056] Step 1 Under the same connection resistance, according to the module current collector list, obtain the parallel connection of different module current collector positions.

[0057]

[0058] Experimental Results: The effects of module current collector position on non-uniform current and SoC under different operating conditions are summarized.

[0059] (1) Simulation results under constant current conditions

[0060] The above simulation experiments show the impact of all module current collector positions on the uneven current and SoC between cells within the module. This example mainly shows the simulation results for two common and typical module current collector positions and the optimized module current collector position for a parallel module with four battery cells.

[0061]

[0062] Among them, SoC difference (SD(t)) and current difference (CD(t)) are the differences between the maximum (Max) current (SoC) and the minimum (Min) current (SoC) of the four batteries in the parallel battery module at the same time. Max CD(SD) is the maximum value of CD(t)(SD(t)) during the discharge cycle. SoC celln (t) and SoC cellm (t) are the state of charge of batteries numbered n and m at time t respectively.

[0063] The results show that the uneven current and SoC distribution in the module are different at different module current collector positions. Figure 4 (a) and Figure 4As shown in (c), in the initial stage, cells closer to the current collector bear a larger discharge current. As discharge progresses, the current exhibits a wave-like distribution. Furthermore, it is noted that the current distribution exhibits different trends: cells with higher initial currents gradually decrease in current, while cells with lower initial currents gradually increase in current. In the final stage of discharge, the current fluctuations of each cell intensify, presenting a completely different current distribution compared to the initial current. It can also be seen that the uneven current and SoC within the module are affected by the module current collector. Figure 4 (c) and Figure 4 The current and SoC distribution of the two module current collectors shown in (d) are significantly better than Figure 4 (a) and Figure 4 Middle (b).

[0064] Figure 5 The current difference and maximum SoC difference under all module current collectors during the module discharge cycle at 1C discharge are shown. It is important to note that when exploring the impact of module current collector position on the uneven performance within the module, the initial state and all battery operating conditions should be maintained consistent.

[0065] The results show that the Z-shaped and ladder-shaped current collector positions commonly used in the process are not the optimal connection positions between parallel modules. The current collector position where the positive and negative current collectors are connected to the same edge cells of the parallel module will lead to greater unevenness in current and SoC, while the connection method of the middle cell can help reduce this unevenness. For example, P 2-N2 The module uneven current and SoC at the module collector position are only P 1-N1 50% and 51% of the module current collector position. In addition, the symmetrical distribution of the positive and negative current collectors of the module shows better uniformity. For example, P 2-N3 Module uneven current and SoC ratio P under module collector position 1-N1 The module current collector position is as low as 87.5% and 85.7%.

[0066] Figure 6 The uneven currents of the modules under 1C and 2C conditions are compared. These uneven currents are dimensionless after being normalized by the average current shown in formula (3).

[0067]

[0068] Among them, I Qucelln is the normalized current flowing through battery n, I celln is the current flowing through battery n, IModule AV is the average current of each battery in the parallel module, and Qu CD is the quantified current unevenness difference.

[0069] High discharge rates increase the uneven current and SoC within the module. High rates can exacerbate uneven performance among parallel modules. For example, the maximum current difference and SoC difference at 2C are 101% and 23% higher, respectively, than at 1C. Table 2 shows the maximum uneven current and SoC within the module at different discharge rates.

[0070] Table 2

[0071]

[0072] (2) Simulation results under dynamic stress test conditions

[0073] Under the dynamic stress test conditions, the module uneven current and SoC under the three module collector positions are as follows: Figure 7 As shown. Figure 7 (a) and Figure 7 As shown in (c), using P 2-N4 The modules still show lower uneven current and SoC.

[0074] The main factors affecting the uneven current and SoC of the module: In the initial stage, the different equivalent connection resistances of each battery cell to the module current collector cause the initial currents of the battery cells to be different. As the discharge continues, the uneven current causes uneven state of charge and open circuit voltage (OCV) between the batteries. As the discharge process continues, the terminal voltage of the battery gradually decreases, the open circuit voltage of the battery and the internal resistance of the battery begin to compete for the dominant position in the current change, and the uneven current gradually tends to be consistent. Finally, when the battery is discharged to the low SoC stage and the gradient of the OCV-SoC curve is large, the OCV difference becomes the main factor causing the rapid deviation of the current between the cells. In addition, it can be seen from formula (4) that the difference in OCV leads to the difference in current.

[0075] OCV(t1)+U pa (t1)+U pc (t1)+U T (t1)=OCV(t2)+U pa (t2)+U pc (t2)+U T (t2) (4)

[0076] However, the primary cause of uneven current flow is the initial current unevenness caused by connection resistance. This initial uneven current flow directly impacts the unevenness of the SoC between cells, leading to uneven internal electrical parameters such as the open-circuit voltage (OCV) of each cell and, subsequently, uneven internal parameters between cells during discharge. This unevenness in internal battery parameters directly leads to uneven and dynamic current flow between cells during subsequent discharge. Uneven current flow and uneven SoC flow are coupled together. Therefore, the internal performance of parallel modules can be affected by a variety of factors, including the position of the module current collectors, varying current rates, and dynamic stress test conditions. The following sections will explore the relationship between these factors and the uneven internal performance of the modules.

[0077] (1) Impact of module current collector position on uneven current and SoC

[0078] In order to analyze the reasons why the module collector position affects the uneven current and SoC, we can use Figure 8 The topology is calculated by equation (5) by connecting the resistor i th The current I ci .like Figure 8 As shown, the module has two different module current collector positions (P 1-N1 and P 3-N3 ).

[0079]

[0080] I j is the current flowing through battery j. Figure 8 P 3-N3 Position, I ci is the current value calculated by formula (6).

[0081]

[0082] Obviously, the maximum current difference in formula (5) is higher than the maximum current difference in formula (6). Further analysis shows that the influence of the module collector position on the performance of the parallel module is mainly due to the fact that the parallel branch units produce different equivalent resistances to the module collector, thus affecting the uneven performance inside the parallel module.

[0083] In addition, according to Figure 5 The data is available at P 1-N1Modules with the current collector position always have more uneven current than modules with other current collector positions. It was also found that under the same positive electrode position (P1, P2 or P3), the uneven current and SoC gradually decreased when the negative electrode position moved from the same positive electrode position to the other side of the module. In addition, in the study of all module current collector positions for four battery cells in parallel, the symmetrically distributed current collector positions ensured the minimum unevenness of the module. The reason is that the module presents the greatest symmetry around the middle battery, which helps to reduce the uneven current and SoC between batteries.

[0084] (2) Effect of current rate on uneven current and SoC

[0085] As shown in Table 2, high discharge rates exacerbate uneven current and SoC within parallel modules. For example, the maximum current difference and SoC difference at 2C are 101% and 23% higher than those at 1C, respectively. This is because the resistance and inductance effects inside the battery are more pronounced due to the larger current, which causes the uneven current and SoC to mainly affect the nearest battery. At low discharge rates, the current is smaller and the resistance and inductance effects inside the battery are weaker, so the uneven current and SoC can propagate farther to the battery at the other end of the parallel module. Figure 6 It can also be found that although high discharge rate will aggravate the uneven performance inside the parallel module, the current distribution inside the parallel battery module shows a similar dynamic process during the entire discharge process. 1-N1 Within the module, the maximum current difference after quantization at a 1C current rate is essentially the same as that at a 2C current rate. This indicates that the connection resistance and the unevenness of the battery parameters during charge and discharge are the main reasons for the uniform performance within the parallel module, and high rates will only exacerbate this unevenness. In addition, the configuration of the parallel battery modules will alleviate the unevenness within the parallel battery modules caused by the above multiple factors. At a 2C current rate, P 2-N4 The maximum current difference and SoC difference under the module collector position are respectively greater than P 1-N1 The maximum current and SoC differences at different module current collector positions at a current rate of 1C are shown in Table 3.

[0086] Table 3

[0087]

[0088] (3) Impact of dynamic stress test conditions on battery uneven current and SoC

[0089] Under the dynamic stress test (DST) condition, the various parameters of the module did not change much. During the discharge process, the uneven SoC inside the parallel battery module was reduced.1-N1 The maximum SoC difference of the module collector position under DST condition is 18.5% at 1C discharge. Figure 7 As shown, the position of the symmetrical distribution of the current collector (P 2-N3 The module current collector position shows better adaptability to the connection resistance between battery cells. This shows that the module current collector position still affects the uneven current and SoC of the module under actual working conditions. For example, under DST conditions, P 1-N1 Maximum SoC difference ratio P under current collector position 2-N3 The current collector position is 550% higher.

[0090] In order to quantify the influence of all module current collector positions on the non-uniform performance in parallel modules, the present invention first defines and obtains all module current collector positions of different modules based on mathematical symmetry similarity and permutation and combination calculations. A typical four-cell parallel module was developed in Matlab / Simscape for the experimental scheme. It was found that the module current collectors cause the equivalent connection resistance of each parallel branch to be different, which leads to non-uniform current and SoC in the module. The positive and negative current collectors are connected to the same edge battery (P 1-N1 ) leads to the greatest performance non-uniformity within the module, while symmetrical module current collector placement can greatly improve module performance uniformity. The optimal single current collector configuration is one that makes the module most symmetrical with respect to the central cell, that is, it makes the equivalent resistance from the cells in each parallel branch to the current collector of the parallel modules as uniform as possible.

[0091] Furthermore, different operating conditions significantly impact the uneven current and SoC caused by interconnect resistance and internal battery electrical parameters. High discharge rates lead to greater performance unevenness. The maximum current difference and SoC difference at 2C are 101% and 23% higher than at 1C, respectively. Compared to constant current operating conditions, the internal module performance unevenness is reduced under DST operating conditions. 1-N1 The maximum SoC difference of the module collector position under DST condition is 18.5% at 1C discharge. Figure 7 As shown, the position of the symmetrical distribution of the current collector (P 2-N3 The module current collector position shows better adaptability to the connection resistance between battery cells. This shows that the module current collector position still affects the uneven current and SoC of the module under actual working conditions. For example, under DST conditions, P 1-N1 Maximum SoC difference ratio P under current collector position 2-N3 The current collector position is 550% higher.

[0092] Overall, this study provides important insights into the complex relationship between module current collector location and module non-uniform performance. These findings are valuable for optimizing battery module design and operation strategies to improve the overall performance and reliability of parallel-connected battery systems.

[0093] like Figure 9 As shown in (a), in the N parallel modules, due to the collector position, the symmetry characteristics of the parallel modules caused by the connection resistance, P 1-N(N-1) Parallel module configuration mode, P (N-1)-N1 Configuration mode module (similar repetition), P N-N2 Configuration mode module (symmetrical repetition) (P 2-NN Configuration mode module (P N-N2 Similar repetition of configurations) can lead to similar uneven current and SoC within the module. Based on the above analysis, for example, in a parallel module with N cells, with P 2-N1 The two single-collector fluid configurations that lead to uneven performance within similar parallel modules are P 1-N2 (Previously, battery #1 was selected as the positive module current collector, i.e., the positive and negative current collectors were swapped in battery numbers); P (N-1)-NN (Single cell #N is symmetrical with respect to unit 1 relative to the center of the parallel module) and P N-N(N-1) Subsequently, as shown in (b) of FIG9 , when the positive current collector of the parallel module is fixed to battery #i, the negative current collector can be selected in addition to the battery with battery #i as the negative current collector when serving as the positive current collector and the battery with battery #i as the negative current collector when serving as the positive current collector, which is symmetrical about the center of the parallel module. When exploring the number of optional configuration modes of the parallel modules in this embodiment, the battery number selected by the positive current collector is only from battery #1 to battery #(N+1) / 2 (when there are an odd number of single cells in the parallel battery module) or battery #(N) / 2 (when there are an even number of single cells in the parallel battery module). Because of the symmetry of the parallel module caused by the current collector position and connection resistance, the uneven current inside the parallel module caused by the battery number selected by the positive current collector from battery #((N+1) / 2+1) (when there are an odd number of single cells in the parallel battery module) or battery #((N) / 2+1) (when there are an even number of single cells in the parallel battery module) to battery #N is similar to the battery number selected by the positive current collector from battery #1 to battery #(N+1) / 2 (when there are an odd number of single cells in the parallel battery module) or battery #(N) / 2 (when there are an even number of single cells in the parallel battery module).

[0094] So, if Figure 9As shown in (c), the positive module current collector of the N parallel modules first selects battery #1, and the negative module current collector can select any battery of the module, a total of N types; when the positive module current collector of the parallel module selects battery #2, the negative module current collector can select other batteries except battery #1 and battery #N (battery #1 and battery #N are symmetrical with respect to the interior of the parallel module), a total of N-2 types; when the positive module current collector of the parallel module selects battery #3, the negative module current collector can select other batteries except battery #1 and battery #N (battery #1 and battery #N are symmetrical with respect to the interior of the parallel module), a total of N-2 types. For the other batteries other than the parallel module's internal symmetry, Battery #2, and Battery #(N-1) (Battery #2 and Battery #(N-1) are symmetric with respect to the parallel module's interior), there are N-4 possible configurations. Therefore, based on mathematical permutations and symmetry, when the positive module current collector of the parallel module selects Battery #i, the negative module current collector can select all batteries except the battery that previously used Battery #i as the negative module current collector and the battery that previously used Battery #i as the negative module current collector, which are symmetric about the parallel module's center, for a total of N-2(i-1) possible configurations. This induction yields the number of possible parallel module configurations that can be achieved in N parallel configurations.

[0095] Finally, based on the analysis of the module current collector position and the uneven performance inside the module, it can be concluded that the positive and negative current collectors are connected to the same edge battery of the module (P 1-N1 ) leads to the greatest non-uniformity in module performance, while symmetrical module current collector positions can greatly improve module performance uniformity. The best single current collector configuration is the one that makes the module show the most symmetrical configuration with respect to the middle battery, that is, the equivalent resistance from the battery in each parallel branch to the parallel module current collector can be as uniform as possible. Figure 9 In (d), a mathematical model is derived for quickly determining the optimal connection position between parallel modules with different numbers of single cells.

[0096] The above are merely preferred embodiments of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A method for optimizing the connection position between parallel lithium-ion battery modules, characterized in that: The following steps are involved: Based on mathematical symmetry, similarity and permutation and combination, all possible connection positions between parallel modules are calculated to obtain a list of module current collector position combinations; Constructing a parallel module simulation model based on the module current collector position combination list, battery cell electrical parameters, connection resistance values, and different operating conditions; Based on the parallel module simulation model, simulation tests are performed on each current collector to obtain uneven current quantification results and SoC quantification results under different working conditions; The optimal current collector position is determined based on the non-uniform current quantification results and the SoC quantification results under the different working conditions.

2. The method according to claim 1, characterized in that The process of building a parallel module simulation model includes: Determining a battery cell connection method corresponding to each current collector position based on the module current collector position combination list; constructing an equivalent circuit model of each battery cell based on the electrical parameters of the battery cell; The equivalent circuit model is connected according to the battery unit connection mode corresponding to the current collector, and the value of the connection resistance is added at the connection to obtain the parallel module simulation model.

3. The method according to claim 2, characterized in that The equivalent circuit model of each battery cell is: Where U T Indicates terminal voltage, I L Indicates the given current, U oc Indicates the voltage of OCV, R0 indicates the battery ohmic internal resistance, U ts and U tl Represents the voltage of two RC parallel pairs, C ts ,R ts ,C tl , and R tl Represent the resistance and capacitance of each of the two resistor-capacitor pairs, respectively.

4. The method according to claim 2, characterized in that The process of obtaining the electrical parameters of the battery cell includes: Conducting a mixed pulse power characteristic test experiment on the battery cell to obtain experimental data at different states of charge, the experimental data including: open circuit voltage, ohmic internal resistance, and resistance and capacitance parameters at different states of charge; The experimental data are fitted using the least squares method to obtain the electrical parameters of the battery cell.

5. The method according to claim 1, characterized in that The different working conditions include: constant current discharge working condition and dynamic stress test working condition.

6. The method according to claim 1, characterized in that The process of obtaining the uneven current quantification results and the SoC quantification results includes: In the parallel module simulation model, simulation tests are performed on each module current collector position respectively; During the simulation test, the difference between the maximum current and the minimum current of different battery cells at the same time is recorded as a quantitative indicator of uneven current; The difference between the maximum SoC and the minimum SoC between different battery cells at the same time is recorded as a quantitative indicator of SoC.

7. The method according to claim 6, characterized in that The optimal current collector position satisfies the symmetrical distribution of positive and negative current collectors, and the difference in equivalent resistance from the battery to the current collector in each parallel branch is minimized.

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