Method for reconstructing integrated circuit layout file, electronic device and storage medium

Abstract

Embodiments of the present disclosure provide a method for reconstructing an integrated circuit layout file, an electronic device, and a storage medium. The method includes: obtaining a set of repetitive image regions in a layout image of an integrated circuit layout, the repetitive image regions being image regions in the layout image that are identical to at least one other image region after an affine transformation; dividing the set of repetitive image regions into at least one image region group, each repetitive image region in each image region group being identical to each other after an affine transformation; and generating a new layout file with a hierarchical cell structure of the integrated circuit layout based on the at least one image region group.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor integrated circuit technology, and more specifically, to methods for reconstructing layout files of integrated circuit layouts, electronic devices, and computer-readable storage media. Background Technology

[0002] The layout file of a semiconductor integrated circuit is the core data carrier of the physical layout. It contains data such as the geometry of the semiconductor integrated circuit or chip (e.g., involving transistors, interconnects, etc.), hierarchical structure, and layout dimensions. Therefore, the layout file is a key input file for photomask manufacturing.

[0003] Chip manufacturing process refers to the smallest feature size of components such as transistors in semiconductor manufacturing, typically measured in nanometers. As chip manufacturing processes continue to shrink, the number of elements contained in the layout is increasing exponentially. In this context, the efficiency of the element organization in the layout file becomes increasingly important. Inefficient element organization can severely impact the efficiency of various stages in integrated circuit and chip manufacturing. Summary of the Invention

[0004] To at least partially address the above and other potential problems, embodiments of this disclosure provide a scheme for reconstructing layout files of integrated circuit layouts.

[0005] According to one aspect of this disclosure, a method for reconstructing a layout file of an integrated circuit layout is provided. The method includes: obtaining a set of repeating image regions in a layout image of the integrated circuit layout, wherein each repeating image region is an image region in the layout image that, after an affine transformation, is identical to at least one other image region; dividing the set of repeating image regions into at least one group of image regions, wherein the repeating image regions in each group are identical to each other after an affine transformation; and generating a new layout file of the integrated circuit layout with a hierarchical cell structure based on at least one group of image regions.

[0006] In a second aspect of this disclosure, an electronic device is provided, comprising: a processor; and a memory coupled to the processor, the memory having instructions stored therein, the instructions causing the device to perform actions when executed by the processor, the actions including: acquiring a set of repeating image regions in a layout image of an integrated circuit layout, the repeating image regions being image regions in the layout image that are identical to at least one other image region after an affine transformation; dividing the set of repeating image regions into at least one group of image regions, the repeating image regions in each group being identical to each other after an affine transformation; and generating a new layout file of the integrated circuit layout having a hierarchical cell structure based on at least one group of image regions.

[0007] In some embodiments of this disclosure, the actions further include: acquiring information associated with an initial layout file of the integrated circuit layout, the information including graphic information and hierarchical information of the initial layout file; determining scaling settings and coordinate transformation settings based on the size of the integrated circuit layout and a predefined layout image resolution; and generating a layout image by rendering based on the acquired information and the determined scaling settings and coordinate transformation settings, wherein different structural layers in the hierarchical structure of the integrated circuit layout are rendered in different colors.

[0008] In some embodiments of this disclosure, affine transformations include at least one of translation, rotation, and scaling.

[0009] In some embodiments of this disclosure, obtaining a set of repeating image regions in a layout image includes the following steps: a) dividing the layout image into multiple image blocks according to a predetermined block size; b) classifying the multiple image blocks based on the image features and geometric features of each image block; c) generating a matrix based on the position and category of the multiple image blocks; and d) determining the repeating image regions of the layout image based on the generated matrix, and generating a set of repeating image regions.

[0010] In some embodiments of this disclosure, b) classifying multiple image blocks based on the image features and geometric features of each image block in the multiple image blocks includes: for each image block in the multiple image blocks, using an image feature algorithm to obtain the image features of the corresponding image block, obtaining the geometric features of the corresponding image block by determining the physical location of the corresponding image block in the integrated circuit layout, and fusing the image features and geometric features of the corresponding image block; and using a clustering algorithm to classify the multiple image blocks based on the fused features of each image block in the multiple image blocks.

[0011] In some embodiments of this disclosure, obtaining a set of repeating image regions in a layout image further includes: changing a predetermined block size at least once; performing steps a) to d) after each change of the predetermined block size; determining an optimal predetermined block size by evaluating the area and / or number of elements of the repeating image regions corresponding to various predetermined block sizes; and determining a set of repeating image regions based on the optimal predetermined block size.

[0012] In some embodiments of this disclosure, obtaining a set of repeating image regions in a layout image further includes: performing preprocessing on the layout image, including image denoising and texture enhancement, before dividing the layout image into multiple image blocks.

[0013] In some embodiments of this disclosure, dividing a set of repeating image regions into at least one group of image regions includes: clustering the repeating image regions in the set using an image algorithm with scaling and rotation invariance; and determining at least one group of image regions based on the clustering results.

[0014] In some embodiments of this disclosure, generating a new layout file with a hierarchical unit structure for an integrated circuit layout based on at least one group of image regions includes: identifying a repeating image region in each group of image regions as a basic unit; generating a first hierarchical structure based on the basic unit, including at least two layers and a reference relationship between the layers, wherein one of the at least two layers includes the basic unit of each group of image regions, and the reference relationship includes affine transformation information between the basic unit in each group of image regions and other repeating image regions; and generating a new layout file with a hierarchical unit structure for an integrated circuit layout based on the first hierarchical structure.

[0015] In some embodiments of this disclosure, the first hierarchical structure includes a first layer, a second layer, and a reference relationship between the first layer and the second layer, wherein the first layer includes non-repeating image regions, the second layer includes basic units of each image region group, and the affine transformation information in the reference relationship includes at least one of translation position, scaling factor, and rotation angle.

[0016] In some embodiments of this disclosure, generating a new layout file with a hierarchical cell structure for an integrated circuit layout based on a first hierarchical structure includes: selecting at least a portion of basic cells from a second layer; generating a second hierarchical structure by iteratively generating the same hierarchical structure as the first hierarchical structure within each basic cell of the at least a portion of basic cells; and generating a new layout file based on the second hierarchical structure and the initial layout file.

[0017] In some embodiments of this disclosure, generating a new layout file with a hierarchical cell structure for an integrated circuit layout based on at least one group of image regions further includes: before determining the basic cells, for each of the at least one group of image regions: determining the physical location of each repeating image region in the corresponding group of image regions in the integrated circuit layout, obtaining the geometry at the physical location from the initial layout file, and verifying, based on the obtained geometry, whether the repeating image regions in the corresponding group of image regions are identical to each other after at least one of translation, rotation, and scaling operations, and removing different image regions.

[0018] In a third aspect of this disclosure, a computer-readable storage medium is provided, wherein a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, implements the method according to the first aspect of this disclosure.

[0019] It should be understood that the description in the Summary of the Invention is not intended to limit the key or essential features of the embodiments of this disclosure, nor is it intended to restrict the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0020] The above and other objects, features and advantages of this disclosure will become more apparent from the accompanying drawings, in which like reference numerals generally denote like parts.

[0021] Figure 1 A schematic diagram of an example scenario in which embodiments of the present disclosure can be implemented is shown.

[0022] Figure 2 A schematic flowchart of a method for reconstructing a layout file of an integrated circuit layout according to an embodiment of the present disclosure is shown.

[0023] Figure 3A An exemplary schematic diagram is shown illustrating the generation of a layout image by rendering an initial layout file according to an embodiment of the present disclosure.

[0024] Figure 3B A schematic diagram of an exemplary integrated circuit layout according to an embodiment of the present disclosure is shown.

[0025] Figure 3C A schematic diagram of an exemplary integrated circuit layout image according to an embodiment of the present disclosure is shown.

[0026] Figure 4A A schematic diagram illustrating a portion of the process of image processing of a layout image according to an embodiment of the present disclosure is shown.

[0027] Figure 4B A schematic diagram of a preprocessed exemplary layout image according to an embodiment of the present disclosure is shown.

[0028] Figure 5 A schematic diagram illustrating a portion of the process of image processing of a layout image according to an embodiment of the present disclosure is shown.

[0029] Figure 6 A schematic diagram illustrating a portion of the process of image processing of a layout image according to an embodiment of the present disclosure is shown.

[0030] Figure 7 A schematic diagram illustrating a portion of the process of image processing of a layout image according to an embodiment of the present disclosure is shown.

[0031] Figure 8A schematic diagram is shown illustrating the division of a set of repeating image regions into at least one group of image regions according to an embodiment of the present disclosure.

[0032] Figure 9 A schematic diagram illustrating the generation of a new layout file with a hierarchical unit structure according to an embodiment of the present disclosure is shown.

[0033] Figure 10 A schematic diagram illustrating the generation of a new layout file with a hierarchical unit structure according to an embodiment of the present disclosure is shown.

[0034] Figure 11 A schematic flowchart illustrating a process for generating a layout image by rendering a layout file of an integrated circuit according to an embodiment of the present disclosure is shown.

[0035] Figure 12 A schematic flowchart illustrating a process for obtaining a set of repeating image regions in a layout image by performing image processing on the layout image according to an embodiment of the present disclosure is shown.

[0036] Figure 13 A schematic flowchart illustrating a process for dividing a set of repeating image regions into at least one group of image regions according to an embodiment of the present disclosure.

[0037] Figure 14 A schematic flowchart illustrating a process for generating a new layout file of an integrated circuit layout based on at least one group of image regions according to an embodiment of the present disclosure is shown.

[0038] Figure 15 A schematic flowchart illustrating the process of generating a new layout file based on a first hierarchy according to an embodiment of the present disclosure is shown.

[0039] Figure 16 A schematic block diagram of an example device that can be used to implement embodiments of the present disclosure is shown. Detailed Implementation

[0040] Embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. Those skilled in the art can derive alternative technical solutions from the following description without departing from the spirit and scope of the present disclosure.

[0041] The term “comprising” and its variations as used herein signify open inclusion, i.e., “including but not limited to”. Unless otherwise stated, the term “or” means “and / or”. The term “based on” means “at least partially based on”. The terms “an example embodiment” and “an embodiment” mean “at least one example embodiment”. Other explicit and implicit definitions may also be included below.

[0042] As mentioned earlier, the number of elements in integrated circuit layouts is increasing, and the organizational efficiency of the element structure in layout files will affect processes such as mask manufacturing, process rule verification (e.g., Design Rule Check, DRC, and layout and schematic diagrams). Figure 1 The consistency of the layout is affected by manufacturing processes such as Layout Versus Schematic (LVS) and Optical Proximity Correction (OPC). For example, DRC needs to scan all the graphics in the layout to ensure they conform to manufacturing rules, such as whether the minimum linewidth and spacing meet the requirements. OPC, on the other hand, needs to simulate the lithography imaging effect and add correction graphics. Therefore, if the element organization structure of the layout file is not efficient enough, duplicate modules will be calculated repeatedly, resulting in low operating efficiency.

[0043] Currently, there are two main storage structures for geometric data in layout files: flat structure and hierarchical cell structure. In a flat structure, all geometric shapes are tiled in their corresponding positions, resulting in low data compression. A hierarchical cell structure typically includes multiple levels, each containing several basic cells. These cells are connected to each other in a tree structure through references. These references are used to place child cells in different positions within the parent cell through various linear transformations (such as translation, scaling, and rotation). This nested cell referencing in a hierarchical cell structure effectively reduces redundant storage of repetitive geometric data.

[0044] In integrated circuit manufacturing, because the design principles, generation methods, and sources of layout files are uncontrollable, the data organization or element organization structure in these files is often inefficient, and there are many duplicate modules that are not organized according to, or only partially according to, a hierarchical structure. To improve the efficiency of the organization structure, some solutions analyze the characteristics of each level and the geometric properties of each unit based on the current hierarchical structure and basic units of the layout file, thereby finding units with similar characteristics to merge to improve data utilization. Other solutions acquire all geometric shapes in the layout, generate some initial seed regions based on a seed region generation algorithm, and then search for possible duplicate regions throughout the layout file based on the geometric features of the seed regions. They then attempt to add new geometric shapes around the found duplicate regions, thereby searching for possible duplicate regions throughout the layout based on the new regions, iterating multiple times until convergence.

[0045] However, these solutions primarily rely on the original hierarchical structure and basic units of the layout, resulting in poor robustness. Because they require multiple rounds of data extraction and matching of all geometric data within the layout, these solutions are computationally intensive and time-consuming. Furthermore, current solutions mainly rely on geometric feature matching methods and algorithms based on geometric features and properties. This makes them ill-suited for scenarios involving rotation and scaling between different repeating regions. Moreover, most algorithms extract geometric features from local regions, lacking a global perspective and easily getting trapped in local optima without finding a globally optimal reconstruction method.

[0046] This disclosure provides an improved scheme for reconstructing layout files of integrated circuit layouts. In the improved scheme, an initial layout file of the integrated circuit layout is rendered to generate a layout image. Image processing is performed on the layout image to obtain a set of repeating image regions. After grouping the set of repeating image regions, a new layout file with a hierarchical unit structure is reconstructed. This method allows for efficient reconstruction of integrated circuit layout files. The reconstruction process does not depend on the original hierarchical structure of the layout file, thus it is also applicable to layouts with poor hierarchical structures, expanding the application scope and scenarios of layout file reconstruction. Since the layout file is rendered as a layout image, features can be extracted from both global and local perspectives, facilitating the finding of the globally optimal reconstruction method. Furthermore, computational matching on a single layout image avoids extensive geometric data iteration matching, significantly improving computational and processing efficiency. In addition, image features can be easily extracted using the rendered layout image, which is beneficial for handling matching problems of geometric shapes within basic units after scaling and / or rotation, and is more conducive to perceiving graphic distortion caused by OPC. In addition, image features can be advantageously combined with geometric features, thereby compensating for each other's shortcomings in feature matching during the reconstruction process, while ensuring the nanometer-level accuracy of geometric features and the physical perceptibility of image features.

[0047] Figure 1 A schematic diagram of an example scenario 100 in which embodiments of the present disclosure can be implemented is shown. The computing device 110 in example scenario 100 can be any device with computing capabilities. The computing device 110 may include a storage device 111 and a processing device 112. In one example, the computing device 110 can be any type of fixed computing device, mobile computing device, or portable computing device; for example, the computing device 110 includes, but is not limited to, desktop computers, laptop computers, notebook computers, netbook computers, tablet computers, multimedia computers, mobile phones, etc. In another example, all or some components of the computing device 110 may be distributed in the cloud.

[0048] In example scenario 100, computing device 110 can obtain an initial layout file 120 of the integrated circuit layout and reconstruct the initial layout file 120. As a result, computing device 110 generates or outputs a new layout file 130 after reconstruction.

[0049] Figure 2 A schematic flowchart of a method 200 for reconstructing a layout file of an integrated circuit layout according to an embodiment of the present disclosure is shown. Method 200 can be performed in... Figure 1 This is implemented in the exemplary scenario 100 and executed by the computing device 110. For the purposes of discussion, it will be combined with... Figure 1Let's describe method 200.

[0050] In block 201, computing device 110 acquires a set of repeating image regions in a layout image of an integrated circuit layout. A repeating image region is an image region in the layout image that, after an affine transformation, is identical to at least one other image region. Each repeating image region may correspond to a geometric region in the layout. Repeating image regions can be found in the layout image using methods such as image processing, and these repeating image regions can be identified to generate a set of image regions. In other words, any image region that appears repeatedly in the layout image can be included in the set of repeating image regions. In some embodiments, the affine transformation includes at least one of translation, rotation, and scaling. Translation refers to shifting the image region as a whole to change its coordinate position; rotation refers to rotating the image region as a whole to change its orientation; and scaling refers to scaling the image region as a whole to change its size or dimensions. That is, a repeating image region can become an image region identical to at least one other image region after undergoing at least one of the transformation operations of translation, rotation, and scaling.

[0051] In block 202, computing device 110 divides the set of repeating image regions into at least one group of image regions, where the repeating image regions in each group are identical after an affine transformation. Thus, the set of repeating image regions can be divided into at least one group to group substantially different image regions into different groups and substantially identical image regions into the same group. Repeating image regions in the same group can reference or be associated with each other through an affine transformation.

[0052] In block 203, computing device 110 generates a new layout file 130 of the integrated circuit layout with a hierarchical cell structure based on at least one group of image regions. The image regions within each group are repeating image regions and can reference each other through affine transformations. Based on this, a new layout file can be established using at least one group of image regions of the layout image, following a hierarchical cell structure. This new layout file reduces redundant data compared to the initial layout file, is more efficient in terms of storage and organization, and helps improve the processing efficiency of various stages of chip manufacturing.

[0053] Figure 3A An exemplary schematic diagram is shown illustrating the generation of a layout image 20 by rendering an initial layout file 10 according to an embodiment of the present disclosure. Figure 3B A schematic diagram of an exemplary integrated circuit layout according to an embodiment of the present disclosure is shown, and Figure 3C A schematic diagram of an exemplary integrated circuit layout image according to an embodiment of the present disclosure is shown. Figures 3A to 3C As shown, layout file 10 can be Figure 1The initial layout file 120 of the integrated circuit layout shown can be converted into a layout image 20 through rendering. In some embodiments of this disclosure, the computing device 110 can acquire information associated with the initial layout file of the integrated circuit layout, including graphical and hierarchical information of the initial layout file. The computing device 110 also determines scaling settings and coordinate transformation settings based on the size of the integrated circuit layout and a predefined layout image resolution. Thus, the computing device 110 generates the layout image 20 by rendering based on the acquired information and the determined scaling and coordinate transformation settings.

[0054] As an example, computing device 110 can parse layout file 10 to extract relevant information and calculate the required scaling dimensions based on the layout size (typically in nanometers) and a predefined layout image resolution, thereby performing coordinate transformation and scaling to convert the physical dimensions of the geometry in the layout into corresponding pixel values. Then, computing device 110 can construct a canvas and draw the extracted geometry as a layout image on the canvas, for example, using a graphics library in a programming language. In one example, the graphics library in the programming language may include Pillow and Matplotlib for Python, OpenCV for C++, or a custom-developed plotting algorithm. In one embodiment, obtaining information associated with the initial layout file of the integrated circuit layout includes obtaining graphical and hierarchical information of the initial layout file. For example, graphical information includes polygons, rectangles, paths, and circles. If the initial layout file has a hierarchical structure, computing device 110 can obtain hierarchical information. For example, hierarchical information may include basic cells and reference information. Computing device 110 can recursively process references to sub-cells to ensure that all instances are rendered correctly. In one embodiment, different structural layers in the hierarchical structure of an integrated circuit layout can be rendered in different colors. As an example, the hierarchical structure of the layout may include structural layers such as metal layers, diffusion layers, and contact layers, and the computing device 110 can render different structural layers with different colors, thereby preserving the physical separation information of the initial device. This avoids interference between different structural layers that could lead to feature confusion and facilitates subsequent image segmentation and feature extraction based on different colors. It is understood that the generation and acquisition of layout images can be implemented using other existing methods or new methods developed in the future, and is not limited to this. However, the above-described layout image generation method is preferred for reconstructing layout files using layout images because it can obtain layout images that are more conducive to subsequent detection of recurring image regions and can be applied to layout files that already have a certain hierarchical structure, thus helping to achieve efficient and accurate layout file reconstruction in a wider range of applications and scenarios.

[0055] Figure 4A A schematic diagram of an optional process for image processing of a layout image 20 according to an embodiment of the present disclosure is shown, and Figure 4B A schematic diagram of a preprocessed exemplary layout image 20 according to an embodiment of the present disclosure is shown. Figure 4A and Figure 4B As shown, in some embodiments of this disclosure, the computing device 110 can perform preprocessing on the layout image 20, including image denoising and texture enhancement. For example, algorithms such as Gaussian filtering or erosion and dilation operations in image morphology can be used to denoise the image, and Fourier transform or Laplacian transform can be used to enhance the texture details of the image edges. By performing preprocessing, a layout image with better image quality and more favorable for subsequent processing can be obtained.

[0056] Figure 5 A schematic diagram illustrates an optional process for image processing of a layout image 20 according to an embodiment of the present disclosure. For example... Figure 5As shown, in some embodiments of this disclosure, the computing device 110 divides the layout image 20 into multiple image blocks according to a predetermined block size. As an example, as shown by the dotted lines in the figure, the layout image 20 can be divided along the horizontal and vertical directions according to a predetermined block size or predetermined granularity, for example, into 10×6 image blocks or any other number of image blocks. In one example, a layout such as SRAM has obvious edge contour features, so connected contour regions in the image can be obtained based on edge detection algorithms (e.g., Canny edge detection). In some embodiments of this disclosure, the computing device 110 classifies multiple image blocks based on the image features and geometric features of each image block. Specifically, image features refer to features extracted from the image; for example, image features can be image texture features and color features, and can form multiple different categories of features (such as SIFT features, SURF features, Gabor features, neural network features, etc.) depending on the algorithm used to extract the features. Geometric features refer to features extracted from geometric figures. For example, the geometric features of an image patch correspond to the geometric features of layout elements within the region of the image patch (e.g., minimum linewidth, perimeter, area, edge spacing, etc.), and can form different categories of geometric features based on different defined geometric rules. Furthermore, the computing device 110 can cluster all image patches based on their geometric and image features, for example, using common clustering algorithms such as K-means clustering or density-based clustering (DBSCAN), thereby dividing all image patches into several classes. In one example, the classification process can use Euclidean distance as a similarity measure, iteratively optimizing the intra-cluster sum of squares to achieve compact intra-cluster division and separation between clusters. In one example, the number of classes into which an image patch is divided can be predefined. In one embodiment, the computing device 110 can perform the following operations for each of multiple image patches: using an image feature algorithm to obtain the image features of the corresponding image patch; obtaining the geometric features of the corresponding image patch by determining its physical location in the integrated circuit layout; and fusing the image features and geometric features of the corresponding image patch. As an example, image feature operators (such as Gabor filters, gray-level co-occurrence matrices, etc.) can be used to extract image features from image patches. Furthermore, the region corresponding to the image patch in the layout can be calculated based on the patch's position and size and according to a scaling parameter, thereby obtaining the geometry within that region. The geometric features of the geometry can be described by the topological features of the shape or the positional relationship between the vertices and center points of the shape within the region. Image features and geometric features can be normalized and fused separately to obtain the fused features of all image patches. Thus, the computing device 110 can classify multiple image patches using a clustering algorithm based on the fused features of each image patch.In this way, the image features and geometric features of each image patch can be combined to form fused features for subsequent classification processing steps. Considering both image and geometric features offers several advantages over conventional approaches that only consider geometric features. Specifically, image features provide a more comprehensive view of the entire field of view than geometric features, while geometric features compensate for the representational blind spots caused by resolution loss in image features. By combining both, nanometer-level accuracy of geometric data and the physical perceptibility of image features can be simultaneously guaranteed.

[0057] Figure 6 and Figure 7 A schematic diagram illustrates an optional process for image processing of a layout image 20 according to an embodiment of the present disclosure. For example... Figure 6 and Figure 7 As shown, in some embodiments of this disclosure, computing device 110 generates a matrix based on the positions and categories of multiple image blocks, and based on the generated matrix, determines repeating image regions 20A to 20H of the layout image 20, and generates a set 21 of repeating image regions. Repeating image regions refer to image regions that appear repeatedly in the layout image (including regions with different rotation orientations and scaling scales). Repeating image regions can consist of one or more image blocks. By generating the matrix, the process of finding repeating image regions in the layout image is transformed into the process of finding repeating submatrices within a large matrix.

[0058] As an example, a matrix can be formed based on multiple image blocks into which the layout image 20 is divided. For instance, if the layout image 20 is divided into 10×6 image blocks, the corresponding matrix is ​​a 10×6 matrix, and the elements in the matrix are the classification results (e.g., category numbers) determined after classifying each image block. Repeating submatrices can be found and identified in the matrix using matrix algorithms such as brute-force enumeration or hash-based block decomposition. Then, the positions of the repeating submatrices in the layout image can be calculated from their positions, thereby identifying the repeating image regions 20A to 20H in the layout image. The repeating image regions 20A to 20H are identified and form a set 21 of repeating image regions.

[0059] Understandably, other methods can also be used to detect repeating image regions and generate sets. For example, repeating image regions can be identified through image comparison, or neural network models can be used to identify recurring image regions in a layout image. However, using a reference... Figures 5 to 7 The described steps for obtaining repeating image regions and generating a set are preferred because this approach converts the image into a matrix and uses matrix algorithms to determine repeating image regions, thereby achieving more efficient and comprehensive repeating image region detection.

[0060] In some embodiments of this disclosure, computing device 110 may change the size of a predetermined block of layout image 20 at least once, and repeat the process after each change of the predetermined block size. Figures 5 to 7 The corresponding steps. That is, the block division of the layout image 20 can be performed repeatedly at different granularities, so that the layout image 20 can be divided multiple times according to a larger or smaller predetermined block size, and for each division result, the steps of image block classification, matrix generation, and determination of repeating image regions are performed, thereby obtaining a set of multiple different repeating image regions corresponding to multiple different predetermined block sizes. In some embodiments of this disclosure, the computing device 110 can determine the optimal predetermined block size by evaluating the area and / or number of elements of the repeating image regions corresponding to various predetermined block sizes, and determine the set of repeating image regions based on the optimal predetermined block. For example, the ratio of the area of ​​the repeating image region to the total area of ​​the layout or the ratio of the number of elements of the repeating image region to the total number of elements in the layout can be evaluated, which helps to determine the benefit of reconstructing the layout file, thereby selecting the image partitioning method with the best benefit. For example, the computing device 110 can select the predetermined block with the largest area of ​​the repeating image region as the optimal predetermined block, or it can select other predetermined blocks as the optimal predetermined block based on cost or other factors. In this way, repeating image regions generated by various segmentation methods can be compared to obtain the optimal or desired set of repeating image regions.

[0061] Figure 8 A schematic diagram is shown illustrating the division of a set 21 of repeating image regions into at least one group of image regions 22-1, 22-2, and 22-3 according to an embodiment of the present disclosure. Figure 8As shown, in some embodiments of this disclosure, computing device 110 uses an image algorithm with scaling and rotation invariance to cluster the repeating image regions in the set 21 of repeating image regions, and determines at least one image region group 22-1, 22-2, and 22-3 based on the clustering results. As an example, computing device 110 can extract texture features from each image region 20A to 20H in the set of repeating image regions, for example, using an image algorithm with scaling and rotation invariance (e.g., SIFT operator, SUFR operator, or ORB operator). Using an image algorithm with scaling and rotation invariance, repeating regions can be identified even after scaling or rotation. Using the extracted texture features and auxiliary information such as the size of the image regions, computing device 110 can use a clustering algorithm to cluster the set 21 of repeating image regions, thereby obtaining image region groups 22-1, 22-2, and 22-3. For example, set 21, including repeating image regions 20A to 20H, is divided into three image region groups: image region group 22-1 includes repeating image regions 20A, 20E, 20F, and 20G; image region group 22-2 includes repeating image regions 20B and 20C; and image region group 22-3 includes repeating image regions 20D and 20H. Each image region group includes multiple repeating image regions that differ only in location, orientation, and / or scaling. It is understood that the number of repeating image regions and image region groups shown in the figures is merely exemplary and not limiting, and that there may be more or fewer repeating image regions and image region groups, and any other number thereof.

[0062] Figure 9 A schematic diagram illustrating the generation of a new layout file with a hierarchical unit structure according to embodiments of the present disclosure is shown. Figure 9As shown, in some embodiments of this disclosure, computing device 110 identifies a repeating image region in each image region group as a basic unit and generates a first hierarchical structure 23 based on the basic unit, including at least two layers and reference relationships between the layers. One of the at least two layers includes the basic unit of each image region group, and the reference relationships include affine transformation information between the basic unit in each image region group and other repeating image regions. The basic unit or the repeating image region identified as the basic unit may include a set of all image elements of the corresponding region in the layout. Thus, image region groups can be used to establish a hierarchical structure that can reduce repeating modules. In some embodiments, the first hierarchical structure 23 includes a first layer 231, a second layer 232, and reference relationships between the first layer 231 and the second layer 232. The first layer 231 includes non-repeating image regions, the second layer 232 includes the basic unit of each image region group, and the affine transformation information in the reference relationships includes at least one of translation position, scaling factor, and rotation angle. For example, repeating image regions 20A, 20C, and 20D in image region groups 22-1, 22-2, and 22-3 can be identified as basic units and arranged in the second layer 232. Other image regions in the layout image that are not classified as repeating image regions (i.e., non-repeating image regions) are arranged in the first layer 231. Non-repeating image regions can include all geometric shapes within their regions. The first layer 231 is connected to the basic units in the second layer 232 via reference relationships. These reference relationships record transformation information between the basic units and other repeating image regions outside the basic units, such as translation position, scaling factor, and rotation angle. Thus, other repeating image regions outside the basic units can be represented using the reference relationships between the basic units in the first layer 231 and the first layer 231 and the second layer 232, without needing to arrange and store other repeating image regions in the hierarchical structure of the first layer 231 and the second layer 232, thereby reducing repeating modules and units within the layout file. In some embodiments of this disclosure, the computing unit 110 generates a new layout file with a hierarchical unit structure for the integrated circuit layout based on the first hierarchical structure 23. In this way, repeating units in the layout can be identified to the greatest extent possible, and inefficient initial layout files can be reconstructed into a more efficient hierarchical unit structure.

[0063] In some embodiments of this disclosure, before determining the basic unit, for each of at least one image region group 22-1, 22-2, and 22-3, the computing device 110 determines the physical location of each repeating image region in the corresponding image region group within the integrated circuit layout, obtains the geometry at the physical location from an initial layout file, and verifies, based on the obtained geometry, whether the repeating image regions in the corresponding image region group are identical to each other after at least one operation of translation, rotation, and scaling, and removes different image regions. As an example, the physical location of an image region in the layout file can be calculated based on the pixel position and scaling scale of the image region in the layout image, thereby obtaining the geometry at the corresponding physical location. Then, a transformation matrix (e.g., including translation vectors, rotation angles, and scaling factors) of the geometry of different image regions in the same image region group can be calculated, thereby calculating, based on the transformation matrix, whether the geometry of different image regions in the same image region group is consistent after a linear transformation. If all image regions within the same group are consistent, the verification is considered successful. If inconsistent image regions exist, they can be removed, or some or all of the previous steps can be re-executed to regenerate the image region group. In this way, duplicate image regions generated by image processing and their grouping results can be verified to ensure the correctness of the reconstructed layout file.

[0064] Figure 10 A schematic diagram of a new layout file with a hierarchical cell structure for generating an integrated circuit layout according to embodiments of the present disclosure is shown. Figure 10 As shown, in some embodiments of this disclosure, the computing unit 110 selects at least a portion of basic units from the second layer 232 and generates a second hierarchical structure 24 by iteratively generating the same hierarchical structure as the first hierarchical structure 23 within each of the selected basic units. As an example, the computing unit 110 may select larger basic units from the second layer 232, such as image region 20C. The computing unit 110 may iteratively perform operations from the selected basic units... Figures 3A to 9The processing steps are as follows: That is, using a process similar to or the same as that used for the initial layout file of the map, rendering, image processing, grouping, and first-level structure generation are performed on the selected basic units. This further establishes the first-level structure within the selected basic units and obtains reference information for smaller-granularity basic units. The above process can be iteratively executed on the smaller-granularity basic units and subsequently generated basic units. For example, image region 20C, as a basic unit, is further processed to generate a hierarchy 24C and a lower-level hierarchy 241C. Thus, the first-level structure 23 is transformed into a second-level structure 24 with N (greater than 2) layers. It is understood that the number of basic units and the number of layers in the hierarchy selected above are merely exemplary and not restrictive. More basic units can be selected as needed to form more or fewer layers in the hierarchy, as long as the basic units of the second layer 232 and the subsequently obtained smaller-granularity basic units still have repeating units or regions, they can be selected for further iterative processing.

[0065] In some embodiments of this disclosure, computing device 110 generates a new layout file 130 based on a second-level structure 24 and an initial layout file 120 or 10. As an example, information on the basic units and reference relationships (also referred to as vertices and edges in the structure) of each level in the second-level structure 24 can be traversed from bottom to top. Furthermore, the geometry within the basic units can be obtained by querying the initial layout file of the layout using the coordinate positions of the basic units. Based on the obtained information and the geometry of the basic units, a new layout file 130 is generated using the second-level structure according to the storage format information of the layout file.

[0066] Through embodiments of this disclosure, an initial file of an integrated circuit layout can be rendered into a layout image and image processing can be performed to obtain repeating image regions and their groupings for reconstructing the layout file. This allows for feature extraction from both a global and pixel-level local perspective, facilitating the determination of the global optimal solution. Furthermore, since matching is calculated on a single image and does not depend on the initial hierarchical structure of the layout file, processing efficiency is significantly improved, making it suitable for reconstructing layouts with poor hierarchical structures. In addition, the rendered layout image easily incorporates image features, yielding more beneficial effects. Texture features in images are scale- and rotation-invariant, thus helping to address the problem of difficulty in matching geometric shapes within basic units after scaling or rotation. OPC corrects the original shape of the layout, and the corrected shape becomes complex and difficult to describe using geometric features, but can be extracted using image features. Therefore, image features are more helpful in perceiving and correcting graphic distortions caused by optical proximity effects. The combination or fusion of image features and geometric features can compensate for the representational blind spots caused by resolution loss in image features (information loss may occur after the layout is rendered into an image, leading to misidentification), and provide an observation dimension closer to the global view than geometric features, thereby simultaneously ensuring the nanometer-level accuracy of geometric data and the physical perception of image features. Furthermore, some embodiments of this disclosure, by introducing correctness verification and benefit evaluation, can reconstruct layout files with a more efficient and accurate hierarchical structure, thereby maximizing the improvement of the layout file's organizational structure and thus enhancing the processing efficiency of various stages in integrated circuit or chip manufacturing.

[0067] Figure 11 A schematic flowchart of a process 1100 for generating a layout image according to an embodiment of the present disclosure is shown.

[0068] In box 1101, computing device 110 acquires information associated with an initial layout file of the integrated circuit layout, including graphical and hierarchical information of the initial layout file.

[0069] In box 1102, based on the size of the integrated circuit layout and the predefined layout image resolution, computing device 110 determines scaling settings and coordinate transformation settings.

[0070] In box 1103, computing device 110 generates a layout image by rendering based on the acquired information and the determined scaling and coordinate transformation settings, wherein different structural layers in the hierarchical structure of the integrated circuit layout are rendered in different colors.

[0071] Figure 12 A schematic flowchart of a process 1200 for obtaining a set of repeating image regions in a layout image by performing image processing on the layout image according to an embodiment of the present disclosure is shown. Figure 12 The process 1200 shown can be performed in Figure 2 Implemented at box 201.

[0072] In block 1201, computing device 110 divides the layout image into multiple image blocks according to a predetermined block size. In some embodiments of this disclosure, prior to block 1201, computing device 110 performs preprocessing on the layout image, including image denoising and texture enhancement.

[0073] In block 1202, computing device 110 classifies multiple image blocks based on the image features and geometric features of each image block. In some embodiments of this disclosure, for each image block, computing device 110 uses an image feature algorithm to obtain the image features of the corresponding image block, obtains the geometric features of the corresponding image block by determining its physical location in the integrated circuit layout, and fuses the image features and geometric features of the corresponding image block. In some embodiments of this disclosure, based on the fused features of each image block, computing device 110 uses a clustering algorithm to classify the multiple image blocks.

[0074] In box 1203, computing device 110 generates a matrix based on the location and category of multiple image patches.

[0075] In box 1204, computing device 110 determines repeating image regions of the layout image based on the generated matrix and generates a set of repeating image regions.

[0076] In box 1205, computing device 110 determines whether to change the predetermined block size.

[0077] In box 1206, if it is determined that the predetermined block size will be changed, the computing device 110 changes the predetermined block size and returns to box 1201 to re-execute the operations of boxes 1201 to 1204 according to the changed predetermined block size.

[0078] In box 1207, if it is determined that the predetermined block size will not be changed, the computing device 110 determines the optimal predetermined block size by evaluating the area and / or number of elements of the repeating image regions corresponding to various predetermined block sizes, and determines the set of repeating image regions based on the optimal predetermined block.

[0079] Figure 13 A schematic flowchart of a process 1300 for dividing a set of repeating image regions into at least one group of image regions according to an embodiment of the present disclosure is shown. Figure 13 The process 1300 shown can be performed in Figure 2 Implemented at box 202.

[0080] In box 1301, computing device 110 uses an image algorithm with scaling and rotation invariance to cluster repeating image regions in the set.

[0081] In box 1302, computing device 110 determines at least one group of image regions based on clustering results.

[0082] Figure 14 A schematic flowchart of a process 1400 for generating a new layout file of an integrated circuit layout based on at least one group of image regions, according to an embodiment of the present disclosure, is shown. Figure 14 The process 1400 shown can be performed in Figure 2 Implemented at box 203.

[0083] In block 1401, computing device 110 identifies a repeating image region in each image region group as a basic unit. In some embodiments of this disclosure, prior to identifying the basic unit, for each image region group in at least one image region group, computing device 110 determines the physical location of each repeating image region in the corresponding image region group within the integrated circuit layout, obtains the geometry at the physical location from an initial layout file, and, based on the obtained geometry, verifies whether the repeating image regions in the corresponding image region group are identical to each other after at least one operation of translation, rotation, and scaling, and removes dissimilar image regions.

[0084] In block 1402, computing device 110 generates a first hierarchical structure based on basic units. This first hierarchical structure includes at least two layers and a reference relationship between the layers. One of the at least two layers includes basic units for each image region group, and the reference relationship includes affine transformation information between the basic units in each image region group and other repeating image regions. In some embodiments of this disclosure, the first hierarchical structure includes a first layer, a second layer, and a reference relationship between the first and second layers. The first layer includes non-repeating image regions, the second layer includes basic units for each image region group, and the affine transformation information in the reference relationship includes at least one of translation position, scaling factor, and rotation angle.

[0085] Those skilled in the art will understand that a third layer can be generated from a portion of the first or second layer's image, forming a reference relationship between the first, second, and third layers, which can also be used for implementation. Under the guidance of the embodiments of this invention, those skilled in the art can extend the implementation through the relationship between at least two layers; this invention does not impose specific limitations here.

[0086] In box 1403, computing device 110 generates a new layout file with a hierarchical cell structure for the integrated circuit layout based on the first-level structure.

[0087] Figure 15 A schematic flowchart of a process 1500 for generating a new layout file based on a first hierarchy according to an embodiment of the present disclosure is shown. Figure 15 The process shown in step 1500 can be performed in... Figure 14 Implemented at box 1403.

[0088] In box 1501, computing device 110 selects at least a portion of basic units from the second layer of the first hierarchy.

[0089] In box 1502, computing device 110 generates a second hierarchy by iteratively generating the same hierarchy as the first hierarchy within each of at least a portion of the basic units.

[0090] In box 1503, computing device 110 generates a new layout file based on the second-level structure and the initial layout file.

[0091] Figure 16 A schematic block diagram of an example device 1600 that can be used to implement embodiments of the present disclosure is shown. Device 1600 can be implemented as a computing device 110 for performing method 200 and processes 1100 to 1500.

[0092] As shown in the figure, device 1600 includes a central processing unit (CPU) 1601, which can perform various appropriate actions and processes according to computer program instructions stored in read-only memory (ROM) 1602 or loaded from storage unit 1608 into random access memory (RAM) 1603. RAM 1603 can also store various programs and data required for the operation of device 1600, such as the measurement data mentioned above. CPU 1601, ROM 1602, and RAM 1603 are interconnected via bus 1604. Input / output (I / O) interface 1605 is also connected to bus 1604.

[0093] Multiple components in device 1600 are connected to I / O interface 1605, including: input unit 1606, such as keyboard, mouse, etc.; output unit 1607, such as various types of monitors, speakers, etc.; storage unit 1608, such as disk, optical disk, etc.; and communication unit 1609, such as network card, modem, wireless transceiver, etc. Communication unit 1609 allows device 1600 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0094] Processing unit 1601 executes the methods or processes described above, methods 200 and processes 1100 to 1500. For example, in some embodiments, methods 200 and processes 1100 to 1500 may be implemented as computer software programs or computer program products tangibly contained in a machine-readable medium, such as a non-transient computer-readable medium, such as storage unit 1608. In some embodiments, part or all of the computer program may be loaded and / or installed on device 1600 via ROM 1602 and / or communication unit 1609. When the computer program is loaded into RAM 1603 and executed by CPU 1601, one or more steps of methods 200 and processes 1100 to 1500 described above may be performed. Alternatively, in other embodiments, CPU 1601 may be configured to execute methods 200 and processes 1100 to 1500 by any other suitable means (e.g., by means of firmware).

[0095] Those skilled in the art will understand that the various steps of the methods disclosed above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. Optionally, they can be implemented using device-executable program code, which can then be stored in a storage device for execution by the computing device. Alternatively, they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, this disclosure is not limited to any particular combination of hardware and software.

[0096] It should be understood that although several devices or sub-devices of the device have been mentioned in the detailed description above, this division is merely exemplary and not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more devices described above can be embodied in one device. Conversely, the features and functions of one device described above can be further divided and embodied by multiple devices.

[0097] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Various modifications and variations can be made to this disclosure by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method of reconstructing a layout file of an integrated circuit layout, comprising: obtaining a set of repetitive image regions in a layout image of the integrated circuit layout, the repetitive image regions being image regions in the layout image that are identical to at least one other image region after an affine transformation; dividing the set of repetitive image regions into at least one group of image regions, each repetitive image region in each group of image regions being identical to each other after an affine transformation; and generating a new layout file of the integrated circuit layout with a hierarchical cell structure based on the at least one group of image regions and a hierarchy. 2.The method of claim 1, further comprising: obtaining information associated with an initial layout file of the integrated circuit layout, the information comprising graphic information and hierarchy information of the initial layout file; determining a scaling setting and a coordinate conversion setting based on a size of the integrated circuit layout and a predefined layout image resolution; and generating the layout image by rendering based on the obtained information and the determined scaling setting and coordinate conversion setting, wherein different structure layers in a hierarchy of the integrated circuit layout are rendered into different colors. 3.The method of claim 1, wherein the affine transformation comprises at least one of a translation, a rotation and a scaling. 4.The method of claim 1, wherein obtaining the set of repetitive image regions in the layout image comprises the following steps: a) dividing the layout image into a plurality of image blocks according to a predetermined block size; b) classifying the plurality of image blocks based on image features and geometric features of each image block in the plurality of image blocks; c) generating a matrix based on locations and classes of the plurality of image blocks; and d) determining repetitive image regions of the layout image based on the generated matrix, and generating the set of repetitive image regions. 5.The method of claim 4, wherein b) classifying the plurality of image blocks based on image features and geometric features of each image block in the plurality of image blocks comprises: for each image block in the plurality of image blocks, obtaining image features of the corresponding image block by using an image feature algorithm; obtaining geometric features of the corresponding image block by determining a physical location of the corresponding image block in the integrated circuit layout; and fusing the image features and the geometric features of the corresponding image block; and classifying the plurality of image blocks based on the fused features of each image block in the plurality of image blocks by using a clustering algorithm. 6.The method of claim 4, wherein obtaining the set of repetitive image regions in the layout image further comprises: changing the predetermined block size at least once; after each change of the predetermined block size, performing steps a) to d); determining an optimal predetermined block size by evaluating areas and / or element numbers of the repetitive image regions corresponding to various predetermined block sizes; and determining the set of repetitive image regions based on the optimal predetermined block size. ​ ​ ​ 7. The method of claim 4, wherein obtaining the set of repetitive image regions in the layout image further comprises: performing pre-processing on the layout image including image denoising and texture enhancement before dividing the layout image into a plurality of image tiles.

8. The method of claim 1, wherein dividing the set of repetitive image regions into at least one group of image regions comprises: clustering the repetitive image regions in the set with an image algorithm that is invariant to scaling and rotation; and determining the at least one group of image regions based on the clustering result.

9. The method of claim 1, wherein generating a new layout file of the integrated circuit layout with a hierarchical cell structure based on the at least one group of image regions comprises: determining one repetitive image region in each group of image regions as a base cell; generating a first hierarchy including at least two layers and a reference relationship between the layers based on the base cell, wherein one of the at least two layers includes the base cell of each group of image regions, and the reference relationship includes affine transformation information between the base cell in each group of image regions and other repetitive image regions; and generating the new layout file of the integrated circuit layout with the hierarchical cell structure based on the first hierarchy.

10. The method of claim 9, wherein the first hierarchy includes a first layer, a second layer, and a reference relationship between the first layer and the second layer, wherein the first layer includes non-repetitive image regions, the second layer includes the base cell of each group of image regions, and the affine transformation information in the reference relationship includes at least one of a translation position, a scaling factor, and a rotation angle.

11. The method of claim 9, wherein generating the new layout file of the integrated circuit layout with the hierarchical cell structure based on the first hierarchy comprises: selecting at least a portion of base cells from a layer including the base cell in the first hierarchy; generating a second hierarchy by iteratively generating the same hierarchy as the first hierarchy within each base cell in the at least a portion of base cells; and generating the new layout file based on the second hierarchy and an initial layout file of the integrated circuit layout.

12. The method of claim 9, wherein generating the new layout file of the integrated circuit layout with the hierarchical cell structure based on the at least one group of image regions further comprises: before determining the base cell, for each group of image regions in the at least one group of image regions: determining physical locations of respective repetitive image regions in the corresponding group of image regions in the integrated circuit layout, obtaining geometries at the physical locations from an initial layout file of the integrated circuit layout, and verifying whether respective repetitive image regions in the corresponding group of image regions are identical to each other after at least one of translation, rotation, and scaling and removing different image regions based on the obtained geometries.

13. An electronic device, comprising: a processor; and a memory coupled to the processor and configured to store instructions that, when executed by the processor, cause the processor to perform operations comprising: a memory coupled with the processor, the memory having stored therein instructions that, when executed by the processor, cause the electronic device to perform acts comprising: obtaining a set of repetitive image regions in a layout image of an integrated circuit layout, the repetitive image regions being image regions in the layout image that are identical to at least one other image region after an affine transformation; dividing the set of repetitive image regions into at least one image region group, each repetitive image region in each image region group being identical to each other after an affine transformation; and generating a new layout file of the integrated circuit layout having a hierarchical cell structure based on the at least one image region group and a hierarchy.

14. A computer readable storage medium, wherein a computer program is stored on the computer readable storage medium and when the computer program is executed by a processor, implements the method according to any one of claims 1-12.

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