Standard cell library and semiconductor device

Abstract

The invention provides a standard cell library and a semiconductor device capable of suppressing repetition of work in a design process using a design device and the like. A standard cell library according to an embodiment includes: a first standard cell in which a first internal power supply wiring is disposed; and a second standard cell in which a second internal power supply wiring is disposed. When the first standard cell and the second standard cell are arranged adjacent to each other in the second direction, the first internal power supply wiring and the second internal power supply wiring are spaced apart from each other. The first standard cell has: a first wiring region in which a first external power supply wiring can be disposed and which extends in a second direction; and a first connectable position capable of connecting the first external power supply wiring and the first internal power supply wiring. The first standard cell has: a third wiring region in which a second external power supply wiring can be disposed; and a third connectable position capable of connecting the second external power supply wiring and the first internal power supply wiring.

Description

Technical Field

[0001] Embodiments of the present invention relate to a standard cell library and a semiconductor device. Background Art

[0002] In the design of semiconductor integrated circuits, the automation, high performance and high functionality of computers are significant, especially in the layout design of semiconductor integrated circuits, a method using standard cells is used. In this method, a P&R (Placement and Routing) processing method is adopted in which standard cells are configured when generating the layout of the circuit and the configured standard cells are connected and wired to each other. In recent years, with the demand for higher speed or lower power consumption of circuits, the use of multiple power supplies in one P&R area has become more common. In contrast, P&R tools do not have the function of optimizing the position, size, number, etc. of the area of ​​each power supply. Therefore, in order to obtain a layout that is excellent in terms of electricity and area, it is necessary to repeatedly adjust the position, size and shape of the area of ​​each power supply and perform the P&R adjustment operation again, which requires a lot of time and work. Summary of the Invention

[0003] One embodiment provides a standard cell library and a semiconductor device capable of suppressing duplication of work in a design process using a design device (P&R tool or layout design tool) or the like.

[0004] A standard cell library in one embodiment has a first standard cell and a second standard cell having the following characteristics. The first standard cell is internally configured with a first internal power supply wiring, and the second standard cell is internally configured with a second internal power supply wiring. The structure is such that when the first standard cell and the second standard cell are adjacently configured along the second direction, the first internal power supply wiring and the second internal power supply wiring are separated. The first standard cell has: a first wiring area in which a first external power supply wiring can be configured and extends along the second direction; and a first connectable position in which the first external power supply wiring and the first internal power supply wiring can be connected. The second standard cell has: a second wiring area in which a first external power supply wiring can be configured and extends along the second direction; and a second connectable position in which the first external power supply wiring and the second internal power supply wiring can be connected. The first wiring area and the second wiring area can be connected adjacent to each other.

[0005] The first standard cell includes: a third wiring region capable of arranging a second external power supply wiring and extending in a second direction; and a third connectable location capable of connecting the second external power supply wiring to the first internal power supply wiring. The first standard cell includes: a fourth wiring region capable of arranging a third external power supply wiring and extending in the second direction; a third internal power supply wiring; and a fourth connectable location capable of connecting the third external power supply wiring to the third internal power supply wiring. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 This is a diagram showing the configuration of a semiconductor device according to the first embodiment.

[0007] Figure 2 This is a diagram showing the configuration of a standard cell according to the first embodiment.

[0008] Figure 3A It is a cross-sectional structural diagram of the standard cell according to the first embodiment.

[0009] Figure 3B It is a cross-sectional structural diagram of the standard cell according to the first embodiment.

[0010] Figure 4 This is a first configuration diagram in which standard cells and power supply wiring according to the first embodiment are arranged.

[0011] Figure 5A It is a cross-sectional view of a first configuration in which standard cells and power supply wirings according to the first embodiment are arranged.

[0012] Figure 5B It is a cross-sectional view of a first configuration in which standard cells and power supply wirings according to the first embodiment are arranged.

[0013] Figure 6A This is a second configuration diagram in which the standard cells and power supply wiring of the first embodiment are arranged.

[0014] Figure 6B This is a third structural diagram showing the arrangement of the standard cells and power supply wiring according to the first embodiment.

[0015] Figure 7 This is a flowchart of the layout design method of the semiconductor device according to the first embodiment.

[0016] Figure 8 This is a schematic diagram of a layout design system for a semiconductor device according to the first embodiment.

[0017] Figure 9 yes Figure 8 A block diagram of the layout design system.

[0018] Figure 10 It is a diagram showing the structure of a semiconductor device according to the second embodiment.

[0019] Figure 11 This is a diagram showing a configuration in which standard cells and power supply wiring according to the second embodiment are arranged.

[0020] Figure 12 It is a diagram showing the structure of a semiconductor device according to a third embodiment.

[0021] Figure 13A This is a first configuration diagram in which standard cells and power supply wiring according to the third embodiment are arranged.

[0022] Figure 13B This is a second configuration diagram showing the arrangement of standard cells and power supply wiring according to the third embodiment.

[0023] Figure 14A This is a first configuration diagram in which standard cells and power supply wiring according to the fourth embodiment are arranged.

[0024] Figure 14B This is a second configuration diagram showing the arrangement of standard cells and power supply wiring according to the fourth embodiment.

[0025] Figure 15 It is a first structural diagram of a semiconductor device according to a comparative example.

[0026] Figure 16 It is a diagram showing the structure of a standard cell of a comparative example.

[0027] Figure 17A It is a cross-sectional structural diagram of a standard cell of a comparative example.

[0028] Figure 17B It is a cross-sectional structural diagram of a standard cell of a comparative example.

[0029] Figure 18 It is a second structural diagram of a semiconductor device according to a comparative example.

[0030] Figure 19 This is a flowchart of a layout design method for a semiconductor device according to a comparative example. DETAILED DESCRIPTION

[0031] The embodiments will be described with reference to the accompanying drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals and their description will be omitted. The drawings are schematic.

[0032] The embodiments described below are merely examples of devices or methods for embodying the technical concept, and do not specify the material, shape, structure, arrangement, etc. of each component. The embodiments described above can be modified in various ways within the scope of the claims.

[0033] [First embodiment]

[0034] (Structure of Semiconductor Device)

[0035] In the following description, the semiconductor device is designed using a standard cell approach. The direction of the height hu of the standard cell 10, or a first direction, is defined as the Y direction. A second direction perpendicular to the height hu of the standard cell 10 on paper is defined as the X direction. A third direction perpendicular to the XY plane is defined as the Z direction.

[0036] Figure 1This is a diagram illustrating the structure of a semiconductor device according to the first embodiment. Multiple standard cells 10 are arranged two-dimensionally in the X and Y directions, connected by boundaries. Wiring is then established between these multiple standard cells 10, thereby forming a semiconductor device 100 having a larger semiconductor integrated circuit. Semiconductor device 100 includes standard cell rows 20, 21, and 22, main power supply wiring 13a and 13b on the M2 layer, sub-power supply wiring 13c on the M2 layer, power supply wiring 14 on the M3 layer, external cell contacts 15a, 15b, and 15c, and a contact 16. The M1 layer, M2 layer, and M3 layer are the first, second, and third metal wiring layers, respectively.

[0037] Multiple standard cells 10 are arranged along the X-direction in standard cell rows 20, 21, and 22. Main power supply wirings 13a, 13b, and sub-power supply wiring 13c are arranged outside the standard cell 10 along the X-direction relative to the standard cell rows 20, 21, and 22, respectively. Here, "arranged outside the standard cell" means not included in the components of the standard cell. Power supply wiring 14 is arranged along the Y-direction. External cell contacts 15a, 15b, and 15c are arranged outside the standard cell 10 and connect either of the internal cell power supply wirings 12a and 12b on the M1 layer to either of the main power supply wirings 13a and 13b or the sub-power supply wiring 13c on the M2 layer. Contact 16 connects either of the main power supply wirings 13a and 13b or the sub-power supply wiring 13c on the M2 layer to the power supply wiring 14 on the M3 layer.

[0038] A configuration in which a plurality of standard cell arrangement rows are arranged along the Y direction is referred to as a standard cell arrangement group. In the standard cell arrangement group, the standard cells 10 are arranged two-dimensionally in the X and Y directions.

[0039] Standard cells 10 are logic circuits that perform basic logical operations. By grouping the logic operations into individual units, they can be easily reused. Examples of standard cells 10 include inverters, NANDs (Not-AND), NORs (Not-OR), exclusive ORs (Exclusive-OR), buffers, and D-type flip-flops.

[0040] Generally, a logic circuit uses a pair of power supplies: one high-potential power supply and one low-potential power supply. Figure 1 The standard cell 10 uses the first power supply VDD or the third power supply VDD2 separated from the first power supply VDD as a high potential side power supply of the logic circuit, and uses the second power supply VSS as a low potential side power supply of the logic circuit.

[0041] The third power supply VDD2 is, for example, a power supply having a lower potential than the first power supply VDD. It is used in logic circuits with sufficient operating speed to reduce power consumption. In another example, the third power supply VDD2 can be shut off from the logic circuit even while the first power supply VDD is being supplied. This power supply is shut off when the semiconductor device is in standby mode, thereby reducing standby power consumption.

[0042] The main power supply wiring 13a that supplies the first power supply VDD is referred to as the main power supply wiring 13a(VDD), and the main power supply wiring 13a that supplies the third power supply VDD2 is referred to as the main power supply wiring 13a(VDD2). Furthermore, the sub-power supply wiring 13c that supplies the third power supply VDD2 is referred to as the sub-power supply wiring 13c(VDD2).

[0043] The configuration of the standard cell 10 is common regardless of whether it uses the first power supply VDD or the third power supply VDD2. When configuring the standard cell 10, the power supply used by the standard cell 10 is connected externally to the standard cell 10. When the standard cell 10 uses the first power supply VDD as a high-potential power supply, it is referred to as the standard cell 10 (VDD). When the standard cell 10 uses the third power supply VDD2, it is referred to as the standard cell 10 (VDD2).

[0044] Figure 2 This diagram illustrates the structure of a standard cell 10 according to the first embodiment. A two-input NAND circuit is shown as an example. Standard cell 10, defined as a rectangular region, has borders 11 surrounding it, top, bottom, left, and right. The Y-direction dimension is the unit height hu, while the X-direction dimension varies depending on the type of standard cell.

[0045] The standard cell 10 has internal power supply wiring, referred to as intra-cell power supply wiring. The standard cell 10 includes intra-cell power supply wiring 12a and 12b in the M1 layer, a device spacer boundary line 36, gate layers 37a and 37b, contacts 38 connecting the M1 layer to the gate layer or the M1 layer to the diffusion layer, and signal wiring 39 in the M1 layer. Within the region enclosed by the device spacer boundary line 36, the region where the gate layers 37a and 37b do not overlap, as viewed in the Z direction, is a P-type diffusion layer or an N-type diffusion layer. The standard cell 10 also includes a signal line wiring region 42 in the M2 layer, extra-cell wiring regions 43a, 43b, 43c, and 43d in the M2 layer, and power access points 45a, 45b, 45c, and 45d.

[0046] The M2 layer's external cell wiring regions 43a, 43b, 43c, and 43d are areas where external power supply wiring or signal line wiring can be arranged outside the standard cell. The external power supply wiring arranged in the M2 layer's external cell wiring regions 43a and 43b are referred to as main power supply wiring 13a and 13b, while the external power supply wiring arranged in the M2 layer's external cell wiring regions 43c and 43d are referred to as sub-power supply wiring 13c and 13d.

[0047] Power supply access points 45a, 45b, 45c, and 45d represent locations outside the standard cell 10 where the external cell contacts 15a, 15b, 15c, and 15d can be placed. The external cell contacts 15a, 15b, 15c, and 15d connect any one of the M1-layer intra-cell power supply lines 12a and 12b to any one of the M2-layer main power supply lines 13a and 13b or the M2-layer sub-power supply lines 13c and 13d. In other words, the power supply access points 45a, 45b, 45c, and 45d are locations where the M1-layer intra-cell power supply lines 12a and 12b can be connected to the M2-layer main power supply lines 13a and 13b or the M2-layer sub-power supply lines 13c and 13d. The power supply access points 45a, 45b, 45c, and 45d do not physically exist; rather, they represent the standard cell before placement in terms of data.

[0048] The intra-cell power supply lines 12a and 12b of the M1 layer are formed by combining a first portion of the intra-cell power supply line arranged along the Y direction with a second portion of the intra-cell power supply line arranged along the X direction. The first portion of the intra-cell power supply line arranged along the Y direction is connected to the P-type diffusion layer of a PMOS (Positive-channel Metal Oxide Semiconductor) or the N-type diffusion layer of an NMOS (Negative-channel Metal Oxide Semiconductor), and is further connected to either the main power supply lines 13a and 13b or the sub-power supply lines 13c and 13d of the M2 layer. The second portion of the intra-cell power supply line arranged along the X direction is arranged at a position overlapping with the extra-cell wiring region 43a or extra-cell wiring region 43b of the M2 layer, as viewed in the Z direction. The second portion of the intra-cell power supply wiring arranged in the X direction is connected to the main power supply wiring 13a or 13b of the M2 layer, or is not connected to any of the main power supply wirings 13a, 13b and the sub-power supply wirings 13c, 13d.

[0049] In the first portion of the intra-cell power supply wiring 12a of the M1 layer, arranged along the Y direction, the portion that overlaps with the extra-cell wiring region 43a of the M2 layer as viewed from the Z direction, and the second portion of the intra-cell power supply wiring arranged along the X direction, can have power supply access points 45a. Therefore, the number of power supply access points 45a is greater than the number of power supply access points 45b in the first portion of the intra-cell power supply wiring 12a arranged along the Y direction. Similarly, the number of power supply access points 45b is greater than the number of power supply access points 45b in the first portion of the intra-cell power supply wiring 12b arranged along the Y direction.

[0050] When configuring a standard cell 10, either power supply connection points 45a or 45c are exclusively configured with the corresponding cell external contact 15a or 15c. Furthermore, either power supply connection points 45b or 45d are exclusively configured with the corresponding cell external contact 15b or 15d. When any of the cell external contacts 15a, 15b, 15c, or 15d is configured, the power supply connection points 45a, 45b, 45c, or 45d are replaced with any of the cell external contacts 15a, 15b, 15c, or 15d, or with a physical entity having an insulating film disposed thereon.

[0051] The positions of the M2 layer's extra-cell wiring regions 43a, 43b, 43c, and 43d in the Y direction are substantially identical across multiple standard cells. Therefore, when performing P&R processing and arranging multiple standard cells 10 with their boundaries 11 in the X direction, the extra-cell wiring regions 43a, 43b, 43c, and 43d of adjacent standard cells 10 are connected by their contact at the boundaries 11. This allows the main power supply wirings 13a, 13b, and the auxiliary power supply wirings 13c, 13d of the M2 layer in the X direction to be arranged outside the standard cell 10 at substantially predetermined positions in the Y direction that penetrate the standard cell arrangement row.

[0052] Furthermore, the region sandwiched between the M2 layer external cell wiring regions 43 c and 43 d is referred to as the M2 layer signal line wiring region 42 , and can be used to arrange the M2 layer signal line along the X direction outside the standard cell 10 .

[0053] Figure 3A 、 Figure 3B is a cross-sectional view of the standard cell 10 according to the first embodiment. Figure 3A Indicates along Figure 2 The IIIA-IIIA section in Figure 3B It shows the cross section along IIIB-IIIB.

[0054] exist Figure 3AIn the cross-section along line IIIA-IIIA, the standard cell 10 includes a P-type semiconductor substrate 31, an N-type well 32, an element spacer 33, an insulating film 35, gate layers 37a and 37b, intra-cell power supply wiring 12a in the M1 layer, and a power access point 45a. The power access point 45a is not physically present but is included in the cross-section for convenience. The standard cell 10 further includes an extra-cell wiring region 43a in the M2 layer on the upper surface of the insulating film 35 and the power access point 45a.

[0055] exist Figure 3B In the cross-section along line IIIB-IIIB, the standard cell 10 includes a P-type semiconductor substrate 31, an N-type well 32, an element isolator 33, a P-type diffusion layer 34, an insulating film 35, an element isolator boundary 36, and gate layers 37a and 37b. The standard cell 10 also includes an M1-layer intra-cell power supply wiring 12a, an M1-layer signal wiring 39, and a power supply connection point 45c. The power supply connection point 45c is not physically present but is included in the cross-section for convenience. The standard cell 10 further includes an M2-layer extra-cell wiring region 43c on the upper surface of the insulating film 35 and the power supply connection point 45c.

[0056] Will Figure 2 and Figure 3A 、 Figure 3B The standard cells 10 shown in the figure undergo P&R processing and are arranged in multiple locations, connected by boundaries 11 along the X and Y directions. Before arranging the standard cells 10, a high-potential power supply line for the M2 layer is arranged in one or both of the M2 layer's external cell wiring regions 43a and 43c. Furthermore, a low-potential power supply line for the M2 layer is arranged in one or both of the M2 layer's external cell wiring regions 43b and 43d. The standard cells 10 are arranged in the region where the high-potential power supply lines and the low-potential power supply lines are arranged.

[0057] There are multiple combinations of methods for configuring power wiring in the M2 layer's external wiring area and configuring external cell contacts at power access points. Figure 1 The combination used in the semiconductor device 100 of the first embodiment shown.

[0058] Figure 4 This is a first configuration diagram of a standard cell and power supply wiring according to the first embodiment. The first configuration diagram shows a case where a standard cell 10 is configured in an area where power supply wiring is configured as follows. (1) Figure 2The main power supply wirings 13a and 13b are respectively arranged in the cell outer wiring regions 43a and 43b of the M2 layer. The main power supply wiring 13a is either the first power supply VDD or the third power supply VDD2. The main power supply wiring 13b is either the second power supply VSS or the fourth power supply VSS2. (2) Figure 2 No power supply wiring is arranged in the cell outer wiring regions 43c and 43d of the M2 layer.

[0059] The fourth power supply VSS2 is a power supply that can cut off supply to the logic circuit even when the first power supply VDD and the second power supply VSS are being supplied, and is used to reduce standby power by cutting off supply to the logic circuit when the semiconductor device is in standby mode.

[0060] Since no power supply lines are arranged in the M2 layer external cell wiring regions 43c and 43d, they can be used to arrange signal lines of the M2 layer. In addition, the area sandwiched between the M2 layer external cell wiring regions 43c and 43d is the M2 layer signal line wiring region 42.

[0061] The main power supply wiring 13a and the main power supply wiring 13b are used in the standard cell 10. When the standard cell 10 is arranged by P&R, the following processes (a) to (g) are performed.

[0062] (a) The main power supply wirings 13 a and 13 b are selected as a pair of power supply wirings used in the standard cell 10 .

[0063] (b) Figure 2 Of the power supply entry points 45 a and 45 c in FIG. 1 , the power supply entry point 45 a corresponding to the main power supply wiring 13 a used by the standard cell 10 is selected.

[0064] (c) The cell external contact 15a is arranged at the selected power supply input point 45a, and the intra-cell power supply wiring 12a of the M1 layer is connected to the main power supply wiring 13a of the M2 layer.

[0065] (d) An insulating film is disposed at the unselected power supply connection point 45c to separate the intra-cell power supply wiring 12a disposed in the M1 layer from the signal line in the extra-cell wiring region 43c in the M2 layer.

[0066] (e) Figure 2 Of the power supply entry points 45 b and 45 d in FIG, the power supply entry point 45 b corresponding to the main power supply wiring 13 b used by the standard cell 10 is selected.

[0067] (f) The cell external contact 15b is arranged at the selected power supply input point 45b, and the intra-cell power supply wiring 12b of the M1 layer is connected to the main power supply wiring 13b of the M2 layer.

[0068] (g) An insulating film is disposed at the unselected power supply entry point 45d to isolate the intra-cell power supply wiring 12b disposed in the M1 layer from the signal line in the extra-cell wiring region 43d in the M2 layer.

[0069] In this manner, either the main power supply wiring 13a or the sub-power supply wiring 13c is selected as the high-potential power supply wiring, and connected to the intra-cell power supply wiring 12a of the M1 layer at either the corresponding power supply access points 45a or 45c. Furthermore, either the main power supply wiring 13b or the sub-power supply wiring 13d is selected as the low-potential power supply wiring, and connected to the intra-cell power supply wiring 12b of the M1 layer at either the corresponding power supply access points 45b or 45d.

[0070] The power supply input points 45a, 45b, 45c, and 45d are replaced with physical entities by disposing any one of the cell external contacts 15a, 15b, 15c, and 15d or an insulating film, and therefore are not shown in the drawings after the standard cell is disposed.

[0071] Figure 5A 、 Figure 5B is with Figure 4 The cross-sectional view corresponding to the first configuration of the standard cell and power supply wiring of the first embodiment is shown. Figure 5A Indicates along Figure 4 The VA-VA section in Figure 5B Represents the cross section along VB-VB.

[0072] Figure 5A The cross-sectional view along VA-VA is shown in FIG. Figure 3A Compared to the cross-sectional structure diagram of the standard cell 10 of the first embodiment shown in FIG, the following points are different. (1) The main power supply wiring 13a of the M2 layer is arranged in the cell external wiring area 43a of the M2 layer. (2) The cell external contact 15a is arranged at the position of the power supply access point 45a, connecting the cell internal power supply wiring 12a of the M1 layer to the main power supply wiring 13a of the M2 layer. The other structures are the same as those of FIG. Figure 3A The cross-sectional structure of the standard cell 10 shown is the same, and therefore its description is omitted.

[0073] exist Figure 5B In the cross section along VB-VB shown, the standard cell 10 after configuration is connected to the Figure 3B Compared with the cross-sectional view of the standard cell 10 of the first embodiment shown in FIG, the following points are different. (1) An insulating film is arranged at the position of the power supply input point 45c. The other structures are the same as those of FIG. Figure 3B The cross-sectional structure of the standard cell 10 shown is the same, and therefore its description is omitted.

[0074] Figure 6AThis is a second configuration diagram in which the standard cell and power supply wiring of the first embodiment are arranged. The second configuration diagram shows a case where the standard cell 10 is arranged in the area where the power supply wiring is arranged as follows. (1) Figure 2 The main power supply wirings 13a and 13b are respectively arranged in the cell outer wiring regions 43a and 43b of the M2 layer. The main power supply wiring 13a is either the first power supply VDD or the third power supply VDD2, and the main power supply wiring 13b is either the second power supply VSS or the fourth power supply VSS2. (2) Figure 2 The sub-power supply wiring 13c is configured in the cell outer wiring region 43c of the M2 layer. The sub-power supply wiring 13c is a power supply wiring that supplies a power source different from the power source supplied by the main power supply wiring 13a in the first power source VDD or the third power source VDD2. (3) Figure 2 No power supply wiring is arranged in the cell outer wiring region 43d of the M2 layer.

[0075] Since no power supply wiring is arranged in the M2 layer external cell wiring region 43d, it can be used to arrange the M2 layer signal line. In addition, the area between the secondary power supply wiring 13c and the M2 layer external cell wiring region 43d is the M2 layer signal line wiring region 42.

[0076] The standard cell 10 uses the main power supply wiring 13 a and the main power supply wiring 13 b . Figure 6A The second structure diagram shown is the same as Figure 4 Compared with the first configuration diagram shown in FIG, the difference is that not only the main power supply wiring 13a but also the sub-power supply wiring 13c is configured as the power supply wiring on the high potential side. Figure 4 The process (d) performed when the standard cell 10 is arranged in the first configuration diagram shown in FIG. Figure 6A In the second configuration diagram shown, the power supply wiring 12a in the cell of the M1 layer is separated from the auxiliary power supply wiring 13c. Figure 4 The same is true for the first configuration diagram shown, and the description thereof will be omitted.

[0077] Figure 6B This is a third configuration diagram in which the standard cell and power supply wiring of the first embodiment are arranged. In the third configuration diagram, the configuration of the power supply wiring in the area where the standard cell 10 is arranged is shown in FIG. Figure 6A The same is true for the second configuration diagram shown.

[0078] Figure 6B The third structure shown in Figure 3 is the same as Figure 6A Compared to the second configuration diagram shown, the difference is that the standard cell 10 does not use the main power supply line 13a but uses the secondary power supply line 13c as the high-potential power supply line. In connection with this difference, the processes (a) to (d) performed when configuring the standard cell 10 in the first configuration diagram are as follows.

[0079] (a) The sub-power supply wiring 13 c and the main power supply wiring 13 b are selected as a pair of power supply wirings used in the standard cell 10 .

[0080] (b) Figure 2 Of the power supply entry points 45 a and 45 c in FIG, the power supply entry point 45 c corresponding to the sub-power supply wiring 13 c used in the standard cell 10 is selected.

[0081] (c) The cell external contact 15c is arranged at the selected power supply input point 45c, and the intra-cell power supply wiring 12a of the M1 layer is connected to the sub-power supply wiring 13c of the M2 layer.

[0082] (d) An insulating film is disposed at the unselected power supply input point 45a to isolate the intra-cell power supply line 12a of the M1 layer from the main power supply line 13a.

[0083] The above descriptions have been made of the structural diagram and cross-sectional diagram of the standard cell 10, and the structural diagram and cross-sectional diagram in which the standard cell 10 and the power supply wiring are arranged. Figure 1 The configuration diagram of the semiconductor device 100 according to the first embodiment shown in FIG. 1 is described in detail.

[0084] exist Figure 1 In the standard cell configuration rows 20 and 21, the standard cell 10 is arranged relative to Figure 2 Arranged in an inverted state along the Y direction. This is usually done to reduce the layout area by making the wells at the boundaries of standard cell rows arranged adjacent to each other along the Y direction common, but they can also be arranged without inversion.

[0085] exist Figure 1 In the standard cell configuration line 20, use Figure 4 The first structure of the standard cell and power supply wiring is shown. The main power supply wiring 13a (VDD), 13b of the M2 layer is arranged outside the standard cell 10. Figure 2 Since the standard cell 10 uses the first power supply VDD, it is expressed as a standard cell 10 (VDD). The standard cell arrangement row 20 includes a third standard cell 10 (VDD).

[0086] In the standard cell 10 in the standard cell arrangement row 20, the main power supply wiring 13a (VDD) on the high potential side is connected to the intra-cell power supply wiring 12a of the M1 layer. Therefore, outside the standard cell 10, Figure 2 The cell external contact 15a is configured at the position of the power supply access point 45a in the M1 layer. In addition, the main power supply wiring 13b on the low potential side is connected to the cell internal power supply wiring 12b of the M1 layer. Therefore, outside the standard cell 10, Figure 2The cell external contact 15b is arranged at the position of the power supply input point 45b in the M2 layer. The contact 16 is arranged at the intersection of the main power supply wiring 13a (VDD), 13b of the M2 layer and the power supply wiring 14 of the M3 layer arranged along the Y direction.

[0087] exist Figure 1 In the standard cell configuration line 21, use Figure 4 The first configuration shown is a configuration in which standard cells and power supply wiring are arranged. Since the standard cell 10 uses the main power supply wiring 13a (VDD2) that supplies the third power supply VDD2, it is the same as the standard cell arrangement row 20 except for being expressed as the standard cell 10 (VDD2).

[0088] exist Figure 1 In the standard cell configuration lines 20 and 21, use Figure 4 In the first configuration shown, in which standard cells and power supply wiring are arranged, a pair of power supply wirings, including a main power supply wiring 13a on the high potential side and a main power supply wiring 13b on the low potential side, are arranged as power supply wirings. The area where the pair of power supply wirings are arranged as power supply wirings is referred to as a first block. Figure 1 The standard cell configuration rows 20, 21 belong to the first block.

[0089] exist Figure 1 In the standard cell configuration line 22, use Figure 6A The second structure shown is configured with standard cells and power supply wiring, and Figure 6B The third configuration of the standard cell and power supply wiring is shown. The main power supply wiring 13a (VDD), 13b and the sub-power supply wiring 13c (VDD2) of the M2 layer are arranged outside the standard cell 10. Figure 2 The cell outer wiring regions 43a, 43b, and 43c of the M2 layer.

[0090] Among the four standard cells 10 arranged in the standard cell arrangement row 22, the standard cells 10(VDD)_1 and 10(VDD)_4 use Figure 6A The second configuration of the standard cell and power supply wiring is shown. In the standard cells 10(VDD)_1 and 10(VDD)_4, the main power supply wiring 13a (VDD) on the high potential side is connected to the power supply wiring 12a in the cell of the M1 layer. Therefore, outside the standard cell 10, Figure 2 The position of the power access point 45a in the configuration unit external contact point 15a.

[0091] In the first standard cell 10(VDD2)_2 and the second standard cell 10(VDD2)_3, use Figure 6BThe third structure of the standard cell and the power supply wiring is shown. The first standard cell 10 (VDD)_2 has a first internal power supply wiring, that is, the first cell power supply wiring 12a, and a third internal power supply wiring, that is, the third cell power supply wiring 12b. In the first standard cell 10 (VDD2)_2, the auxiliary power supply wiring 13c (VDD2) arranged on the high potential side of the first wiring area extending in the X direction, that is, the cell external wiring area 43c, is connected to the first cell power supply wiring 12a of the M1 layer. Therefore, outside the first standard cell 10 (VDD)_2, at the first connectable position, that is, Figure 2 The first contact, i.e., the cell external contact 15c, is located at the power supply access point 45c in the first standard cell 10(VDD)_2. In the first standard cell 10(VDD)_2, the second external power supply wiring, i.e., the main power supply wiring 13a(VDD) on the high potential side, is located in the third wiring area, i.e., the cell external wiring area 43a. Outside the first standard cell 10(VDD)_2, at the third connectable position, i.e., Figure 2 An insulating film is arranged at the position of the power supply connection point 45a in the first standard cell 10(VDD)_2. In the first standard cell 10(VDD)_2, the third external power supply wiring, i.e., the main power supply wiring 13b on the low potential side, arranged in the fourth wiring area, i.e., the cell external wiring area 43b, is connected to the third internal power supply wiring 12b of the M1 layer. Therefore, outside the first standard cell 10(VDD)_2, at the fourth connectable position, i.e., Figure 2 The third contact, namely the unit external contact 15b, is configured at the position of the power supply access point 45b.

[0092] The second standard cell 10(VDD2)_3 has a second internal power supply wiring, namely, a second internal power supply wiring 12a. In the second standard cell 10(VDD2)_3, the secondary power supply wiring 13c(VDD2) arranged on the high potential side of the second wiring region extending in the X direction, namely, the external wiring region 43c, is connected to the second internal power supply wiring 12a of the M1 layer. Therefore, outside the second standard cell 10(VDD2)_3, at the second connectable position, namely, Figure 2 The second contact, namely the unit external contact 15c, is configured at the position of the power supply access point 45c.

[0093] exist Figure 1In the standard cell arrangement row 22, a pair of power supply wiring is arranged as power supply wiring, comprising a second external power supply wiring, i.e., a high-potential main power supply wiring 13a, and a third external power supply wiring, i.e., a low-potential main power supply wiring 13b. Also arranged in the standard cell arrangement row 22 is a first external power supply wiring, i.e., a high-potential secondary power supply wiring 13c. The area where the pair of power supply wirings and one or more power supply wirings are arranged as power supply wiring is referred to as the second block, and the standard cell arrangement row 22 belongs to the second block.

[0094] Generally, each area divided by the type of power used is called a power domain. Figure 1 In the semiconductor device 100, the standard cell arrangement row 20 is a region of the VDD-VSS power domain, in which the power supply wiring of the first power supply VDD is arranged as the high-potential main power supply wiring 13a, and the power supply wiring of the second power supply VSS is arranged as the low-potential main power supply wiring 13b. The standard cell arrangement row 21 is a region of the VDD2-VSS power domain, in which the power supply wiring of the third power supply VDD2 is arranged as the high-potential main power supply wiring 13a, and the power supply wiring of the second power supply VSS is arranged as the low-potential main power supply wiring 13b.

[0095] In the standard cell arrangement row 22 located at the boundary between the standard cell arrangement row 20 and the standard cell arrangement row 21 in different power domains, the power supply wiring of the first power supply VDD is arranged as the main power supply wiring 13a, and the power supply wiring of the third power supply VDD2 is arranged as the sub-power supply wiring 13c. Moreover, in the standard cell arrangement row 22, either the main power supply wiring 13a or the sub-power supply wiring 13c is selected as the power supply wiring for each standard cell 10. Figure 2 Among the power supply access points 45a and 45c, a power supply access point corresponding to either the main power supply wiring 13a or the sub-power supply wiring 13c used in the standard cell 10 is selected. By arranging either the corresponding cell external contact point 15a or 15c at the selected power supply access point 45a or 45c, either the main power supply wiring 13a or the sub-power supply wiring 13c is connected to the internal cell power supply wiring 12a.

[0096] Standard cells using either the first power supply VDD or the third power supply VDD2 can be arranged in the standard cell arrangement row 22. The region where standard cells using any of the multiple power supplies can be arranged is called a buffer region of the power domain.

[0097] By configuring the standard cell arrangement row 22 as a buffer region for the power domain, standard cells 10 (VDD) using the first power supply VDD can be arranged in the combined region of the standard cell arrangement row 20 and the standard cell arrangement row 22 in the VDD-VSS power domain. Furthermore, standard cells 10 (VDD2) using the third power supply VDD2 can be arranged in the combined region of the standard cell arrangement row 21 and the standard cell arrangement row 22 in the VDD2-VSS power domain. This increases the degree of freedom in P&R within each power domain, reducing the frequency with which designers must re-adjust the position, size, and shape of each power domain, reconfigure power supply wiring, and perform P&R again.

[0098] [Layout design method]

[0099] A layout design method for the semiconductor device 100 according to the first embodiment will be described.

[0100] Figure 7 This is a flowchart of the layout design method of the semiconductor device 100 according to the first embodiment.

[0101] Before starting layout design, a logic circuit composed of standard cells is logically synthesized by a logic synthesis tool and converted into circuit diagram information composed of elements such as NMOS or PMOS. The circuit diagram information is input when layout design starts.

[0102] Layout design is performed in the following steps. First, in step S11, the designer determines the size and shape of the area to be laid out using P&R. Next, in step S12, the designer provisionally determines the location, size, and shape of each power domain and the area where the secondary power wiring will be located. Next, in step S13, the designer places power wiring in the area where each power domain and the secondary power wiring will be located.

[0103] Next, in step S14, automatic layout is performed through P&R processing. The P&R processing can be decomposed as follows.

[0104] First, in step S141, standard cells are arranged in an area that combines the area of ​​the power domain to which the standard cells belong and the area where the secondary power wiring is arranged. Next, in step S142, the primary power wiring or secondary power wiring used by each standard cell is selected, and the power access point corresponding to the selected primary power wiring or secondary power wiring is selected. Then, by configuring cell external contacts at the selected power access points, the internal power wiring of the cell is connected to the primary power wiring or secondary power wiring. Next, in step S143, wiring is performed between the standard cells.

[0105] Next, in step S144, it is determined whether the quantity and quality of the wirings routed between the power supply wiring and the standard cells satisfy an evaluation criterion. The evaluation criterion includes the degree of congestion of the wirings, and the like.

[0106] In step S144, if the quantity and quality of wiring meet the evaluation criteria, the P&R process of step S14 is terminated and the process proceeds to step S15. In step S15, the designer outputs the layout information of the P&R area, and the layout design is terminated.

[0107] On the other hand, in step S144 , if the quantity or quality of the wiring does not satisfy the evaluation criteria, the process proceeds to step S145 , where it is determined whether there is room for improvement in the arrangement of the standard cells.

[0108] In step S145, if the quantity and quality of wiring, the number of P&R cycles, etc., do not exceed the specified criteria, it is determined that the standard cell layout can be improved. The P&R process then returns to step S141, and the standard cell layout and wiring are re-performed to improve the quantity and quality of wiring.

[0109] On the other hand, in step S145, if the quantity or quality of wiring, the number of P&R cycles, and other factors exceed the specified criteria, even if P&R is repeated, the probability of the wiring quantity and quality meeting the evaluation criteria is low, and the standard cell layout is determined to be unimprovable. The process then returns to step S12, where the designer reconfigures the location, size, and shape of the areas where each power domain and sub-power wiring is located to improve the quantity and quality of wiring based on the evaluation results in step S144. Furthermore, the power wiring is reconfigured in step S13, and the P&R process in step S14 is repeated.

[0110] exist Figure 7 In the flow of the layout design method for the semiconductor device 100 according to the first embodiment shown, in step S141, standard cells are arranged in an area that combines the area of ​​the power domain to which the standard cells belong and the area where the secondary power wiring is located. Then, in step S142, the main power wiring or secondary power wiring used by each standard cell is selected and connected to the intra-cell power wiring. Standard cells using any of multiple power supplies can be arranged in the area where the secondary power wiring is located. This improves the flexibility of P&R.

[0111] By increasing the degree of freedom in P&R, the frequency of determining in step S145 that the standard cell layout has no room for improvement can be reduced. This can also reduce the frequency of returning to S12 to re-adjust the position, size, and shape of each power domain and re-arrange the power wiring.

[0112] [Layout design system]

[0113] A layout design system for the semiconductor device 100 according to the first embodiment will be described.

[0114] Figure 8 1 is a schematic diagram of a layout design system 200 for the semiconductor device 100 according to the first embodiment. Figure 9 yes Figure 8 FIG. 2 is a block diagram of a layout design system 200 .

[0115] like Figure 8 As shown, the layout design system 200 includes a central processing unit (CPU) server 61, a storage medium 62, a computer device 63, and a network 64. In the following description, the central processing unit server 61 is also referred to as a CPU server 61.

[0116] The layout design system 200 is connected via a network 64 to a CPU server 61, a storage medium 62, and a computer device 63 operated by a user. The CPU server 61 stores computer programs used in the layout design system 200. The storage medium 62 stores input information and output information required to execute the computer programs used in the layout design system 200. The computer device 63 is operated by the user.

[0117] The CPU server 61 may be, for example, an engineering workstation (EWS), a mainframe computer, or a supercomputer. The storage medium 62 may be, for example, an external storage device such as a hard disk, a semiconductor storage device such as a memory, or a storage medium (media). The computer device 63 may be, for example, a personal computer (PC), a thin client terminal, a mobile terminal, or a PDA (Personal Digital Assistant). The network 64 may be, for example, the Internet, an intranet, a LAN (Local Area Network), a telephone communication network, or a dedicated line. However, the present invention is not limited to these examples.

[0118] like Figure 9 As shown, the CPU server 61 includes a logic synthesis unit 81 and a layout design tool unit 82 for executing a computer program used in the layout design system 200 .

[0119] The logic synthesis unit 81 and the layout design tool unit 82 may be processing devices such as a CPU or a microprocessor, but are not limited to these examples.

[0120] The logic synthesis unit 81 performs logic synthesis on the standard cell connection information 73 (gate netlist) based on the circuit description information 71 and the information of the standard cell library 72 , and outputs the standard cell connection information 73 after logic synthesis to the storage medium 62 .

[0121] The layout design tool section 82 includes a standard cell placement section 821 , an inter-standard cell wiring section 822 , a wiring evaluation section 823 , and a chip layout output section 824 .

[0122] Storage medium 62 contains circuit description information 71, a standard cell library 72, and standard cell connection information 73. Storage medium 62 also contains power wiring configuration information 74, standard cell configuration information 75, power access point connection information 76, signal line configuration information 77, and chip layout information 78. Standard cell library 72 contains a plurality of standard cells.

[0123] The designer temporarily determines the size and shape of the P&R area, and the position, size, and shape of the area where each power domain and sub-power wiring are arranged, arranges the power wiring, and outputs the power wiring arrangement information 74 to the storage medium 62 .

[0124] The standard cell configuration unit 821 configures standard cells based on the standard cell library 72 , the standard cell connection information 73 , and the power wiring configuration information 74 , and outputs the standard cell configuration information 75 and the power connection point connection information 76 to the storage medium 62 .

[0125] The inter-standard cell wiring section 822 connects wiring between standard cells based on the standard cell connection information 73 , the power supply wiring arrangement information 74 , and the standard cell arrangement information 75 , and outputs the signal line arrangement information 77 to the storage medium 62 .

[0126] The wiring evaluation unit 823 evaluates the quantity and quality of the wiring based on the power supply wiring configuration information 74 and the signal line configuration information 77. If the quantity and quality of the wiring meet the evaluation criteria, the wiring evaluation unit 823 outputs a determination that the evaluation criteria are met to the computer device 63. If the quantity or quality of the wiring does not meet the evaluation criteria, or if it is determined that the standard cell configuration has room for improvement, the wiring evaluation unit 823 transmits a rework command to the standard cell configuration unit. If it is determined that the standard cell configuration has no room for improvement, an error determination result is output to the computer device 63.

[0127] The chip layout output unit 824 outputs chip layout information 78 to the storage medium 62 based on a command from the computer device 63 , the power wiring configuration information 74 , the standard cell configuration information 75 , the power connection point connection information 76 , and the signal line configuration information 77 .

[0128] (Effects of the First Embodiment)

[0129] According to the first embodiment, during layout design, in addition to the area for arranging a pair of main power supply wirings, a partial area for arranging a pair of main power supply wirings and one or more high-potential-side secondary power supply wirings is also partially provided. By partially providing the area for arranging the secondary power supply wirings, an increase in the wiring area can be suppressed. Standard cells that use any of the multiple power supplies can also be arranged in this partially provided area. This increases the degree of freedom in P&R (Planning and Redesign), reduces the frequency with which designers need to re-adjust the position, size, and shape of each power domain, re-arrange the power supply wiring, and then re-perform P&R, and thus reduces duplication of work in the design process.

[0130] Here, in order to facilitate understanding of the features of the present invention, a semiconductor device according to a comparative example will be described.

[0131] In the following description, similar to the first embodiment of the present invention, the direction of the height hu of the standard cell 90, that is, the first direction, is defined as the Y direction, the second direction perpendicular to the direction of the height hu of the standard cell 90 on the paper is defined as the X direction, and the third direction perpendicular to the XY plane is defined as the Z direction.

[0132] Figure 15 This is a first structural diagram of a semiconductor device according to a comparative example. Semiconductor device 300 includes standard cell rows 110, 111, and 112, M3-layer power supply wiring 14, and contacts 96 connecting M2-layer intra-cell power supply wiring 93a and 93b to power supply wiring 14. Standard cells 90 are arranged along the X direction in standard cell rows 110, 111, and 112. M2-layer intra-cell power supply wiring 93a and 93b are arranged along the X direction within the standard cells. Here, "arranged within the standard cells" means included in the components of the standard cells.

[0133] Figure 16 1 is a diagram illustrating the structure of a standard cell 90 of a comparative example. A two-input NAND circuit is shown as an example. The standard cell 90, defined as a rectangular area, has boundary lines 91 surrounding the top, bottom, left, and right sides.

[0134] Standard cell 90 includes intra-cell power supply wiring 92a, 92b in the M1 layer, intra-cell power supply wiring 93a, 93b in the M2 layer, intra-cell contacts 95a, 95b, and a signal line wiring region 94 in the M2 layer. Intra-cell contacts 95a, 95b are located within standard cell 90 and connect intra-cell power supply wiring 92a, 92b in the M1 layer to intra-cell power supply wiring 93a, 93b in the M2 layer. Standard cell 90 also includes device isolation boundary line 36, gate layers 37a, 37b, contacts 38 connecting the M1 layer to the gate layer or the M1 layer to the diffusion layer, and signal wiring 39 in the M1 layer. Within the region enclosed by device isolation boundary line 36, the region where gate layers 37a, 37b do not overlap is a P-type diffusion layer or an N-type diffusion layer, as viewed in the Z direction.

[0135] The positions of the intra-cell power supply lines 93a and 93b in the M2 layer in the Y direction are substantially the same in multiple standard cells. Therefore, when performing P&R processing and arranging multiple standard cells 90 with their boundaries 91 in the X direction, the intra-cell power supply lines 93a and 93b in the M2 layer of adjacent standard cells 90 are connected by the boundaries 91.

[0136] Figure 17A 、 Figure 17B is a cross-sectional view of a standard cell 90 of a comparative example. Figure 17A Indicates along Figure 16 The section XVIIA-XVIIA in Figure 17B It shows the cross section along XVIIB-XVIIB.

[0137] exist Figure 17A In the cross section along line XVIIA-XVIIA, standard cell 90 includes a P-type semiconductor substrate 31, an N-type well 32, an element spacer 33, an insulating film 35, and gate layers 37a and 37b. Standard cell 90 also includes an intra-cell power supply wiring 92a in the M1 layer, an intra-cell power supply wiring 93a in the M2 layer, and an intra-cell contact 95a connecting intra-cell power supply wiring 92a in the M1 layer to intra-cell power supply wiring 93a in the M2 layer.

[0138] exist Figure 17B In the cross section along line XVIIB-XVIIB, standard cell 90 includes a P-type semiconductor substrate 31, an N-type well 32, an element separator 33, a P-type diffusion layer 34, an insulating film 35, an element separator boundary 36, and gate layers 37a and 37b. Standard cell 90 also includes an intra-cell power supply wiring 92a in the M1 layer, a signal wiring 39 in the M1 layer, and a signal line wiring region 94 in the M2 layer.

[0139] exist Figure 15In standard cell rows 110 and 112, standard cells 90 (VDD) using the first power supply VDD are arranged adjacent to each other in the X direction. Consequently, intra-cell power supply wiring 93a (VDD) of the M2 layer is connected to intra-cell power supply wiring 93b of the second power supply VSS throughout the entire row. Furthermore, in standard cell row 111, standard cells 90 (VDD2) using the third power supply VDD2 are arranged adjacent to each other in the X direction. Consequently, intra-cell power supply wiring 93a (VDD2) of the M2 layer is connected to intra-cell power supply wiring 93b of the second power supply VSS throughout the entire row.

[0140] Figure 18 This is a second structural diagram of a semiconductor device according to a comparative example. Semiconductor device 301 includes standard cell rows 110, 111, and 113, power supply wiring 14 in the M3 layer, and contacts 96 connecting intra-cell power supply wirings 93a and 93b in the M2 layer to power supply wiring 14. In standard cell row 113, standard cell 90 (VDD) and standard cell 90 (VDD2) are arranged in the same standard cell row. When standard cell 90 (VDD) and standard cell 90 (VDD2) are arranged adjacent to each other in the X direction, intra-cell power supply wiring 93a (VDD) and intra-cell power supply wiring 93a (VDD2) in the M2 layer connect, short-circuiting the first power supply VDD and the third power supply VDD2. Therefore, standard cell 90 (VDD) and standard cell 90 (VDD2) are arranged with a gap in the X direction.

[0141] Standard cells 90(VDD)_1 and 90(VDD)_4 in standard cell rows 110 and 113 form a VDD-VSS power domain. Standard cells 90(VDD2)_2 and 90(VDD2)_3 in standard cell rows 113 and standard cell rows 111 form a VDD2-VSS power domain.

[0142] Compared to the standard cell 90 of the comparative example described above, the standard cell 10 of the first embodiment of the present invention differs in the following respects. (1) The standard cell 10 of the first embodiment of the present invention does not include the intra-cell power supply wirings 93a, 93b and the intra-cell contacts 95a, 95b of the M2 layer. (2) The standard cell 10 of the first embodiment of the present invention includes power supply access points 45a, 45b, 45c, and 45d. (3) The standard cell 10 of the present invention includes a portion in which the intra-cell power supply wirings 12a, 12b of the M1 layer are arranged in the X direction so as to overlap with the extra-cell wiring regions 43a, 43b of the M2 layer when viewed from the Z direction.

[0143] Figure 19This is a flowchart of a layout design method for the semiconductor devices 300 and 301 of the comparative example. This flowchart is common to the first and second configuration diagrams of the semiconductor device of the comparative example.

[0144] Layout design is performed in the following steps. First, in step S91, the designer determines the size and shape of the area to be laid out using P&R. Next, in step S92, the designer provisionally determines the location, size, and shape of each power domain. Finally, in step S93, the designer configures power routing for each power domain.

[0145] Next, in step S94, automatic layout is performed through P&R processing.

[0146] The P&R process can be broken down as follows: First, in step S941, standard cells are placed in each power domain. Then, in step S942, wiring is performed between the standard cells.

[0147] Next, in step S943, it is determined whether the quantity and quality of the wirings routed between the power supply wiring and the standard cells satisfy an evaluation criterion. The evaluation criterion includes the degree of congestion of the wirings, and the like.

[0148] In step S943, if the quantity and quality of wiring meet the evaluation criteria, the P&R process of step S94 ends and the process proceeds to step S95. In step S95, the designer outputs the layout information of the P&R area, and the layout design ends.

[0149] On the other hand, in step S943 , if the quantity or quality of the wiring does not satisfy the evaluation criteria, the process proceeds to step S944 , where it is determined whether there is room for improvement in the arrangement of the standard cells.

[0150] In step S944, if the amount and quality of wiring, the number of P&R cycles, etc. do not exceed the specified criteria, it is determined that the standard cell layout can be improved. The P&R process then returns to step S941, and the standard cell layout and routing are re-performed to improve the amount and quality of wiring.

[0151] On the other hand, in step S944, if the quantity or quality of wiring, the number of P&R cycles, and other factors exceed the specified criteria, even if P&R is repeated, the probability that the quantity and quality of wiring will meet the evaluation criteria is low, and the standard cell layout is determined to be unimprovable. The process then returns to step S92, and the designer reconfigures the position, size, and shape of each power domain to improve the quantity and quality of wiring based on the evaluation results in step S943. Furthermore, the power wiring is reconfigured in step S93, and P&R in step S94 is repeated.

[0152] The flow of the layout design method of the semiconductor devices 300 and 301 according to the above comparative example returns to Figure 15 1st structural diagram of the semiconductor device of the comparative example, and Figure 18 FIG2 shows the second configuration diagram of the semiconductor device of the comparative example. In the first and second configuration diagrams of the comparative example, P&R is performed after the power domains for the first power supply VDD and the third power supply VDD2 are determined in the pre-P&R stage, so the degree of freedom of P&R is limited.

[0153] For example, in Figure 15 In the first configuration diagram, the locations where standard cells 90 using VDD2 can be placed are limited to the VDD2-VSS power domain, namely, standard cell row 111. Therefore, during a post-P&R evaluation, if the quantity or quality of wiring for standard cells 90 placed in standard cell row 111 does not meet the evaluation criteria, the freedom to reconfigure the standard cells 90 is limited, and it is easy to determine that there is no room for improvement. If it is determined that there is no room for improvement in the configuration of standard cells 90, the designer must adjust the size and shape of the power domain and reconfigure the power wiring to expand the VDD2-VSS power domain.

[0154] As an example of adjusting the size and shape of power domains, Figure 18 As shown in the standard cell arrangement row 113 of the second configuration diagram of FIG, a case where a part of the VDD-VSS power domain is replaced with the VDD2-VSS power domain is considered.

[0155] To separate the intra-cell power supply wiring 93a(VDD) for the first power supply VDD and the intra-cell power supply wiring 93a(VDD2) for the third power supply VDD2 in the M2 layer along the X direction, the designers shifted the power domains to which standard cells 90(VDD)_1 and 90(VDD)_4 belong outward in the X direction. Furthermore, gaps were inserted between standard cells 90(VDD)_1 and 90(VDD2)_2, and between standard cells 90(VDD2)_3 and 90(VDD)_4. The designers adjusted the layout of the power supply wiring 14 in the M3 layer in the Y direction to ensure sufficient power supply capacity for the separated intra-cell power supply wiring 93a(VDD) and 93a(VDD2) in the M2 layer.

[0156] When the layout area increases due to these adjustments made by the designer, the position and shape of the power domain and the layout of the power wiring must be adjusted to fit within the specified area and shape. Furthermore, P&R needs to be re-performed.

[0157] Repeating the adjustment of the position, size, and shape of the power domain, the layout of the power wiring, and P&R in this way requires a lot of time and effort.

[0158] Compared with the semiconductor devices 300 and 301 of the comparative examples described above, the semiconductor device 100 according to the first embodiment of the present invention improves the degree of freedom of P&R and can suppress the duplication of the work of re-performing P&R by adjusting the arrangement of power domains and power wirings.

[0159] Specifically, in addition to the area for arranging a pair of main power supply wires, a partial area is also provided for arranging a pair of main power supply wires and one or more high-potential secondary power supply wires. Furthermore, for each standard cell, either the main power supply wire or the secondary power supply wire is selected. Furthermore, from among multiple power supply access points, a power supply access point corresponding to either the main power supply wire or the secondary power supply wire used by the standard cell is selected. Then, by configuring a corresponding external cell contact at the selected power supply access point, either the main power supply wire or the secondary power supply wire is connected to the internal power supply wire of the cell. This allows standard cells using any of the multiple power supplies to be arranged even in the partially provided area, increasing the flexibility of P&R.

[0160] [Second embodiment]

[0161] (Structure of Semiconductor Device)

[0162] Figure 10 This is a diagram showing the structure of a semiconductor device according to Embodiment 2. The semiconductor device 101 includes standard cell rows 20, 21, and 23, M2-layer main power supply wirings 13a and 13b, M2-layer sub-power supply wiring 13c, M3-layer power supply wiring 14, cell external contacts 15a, 15b, and 15c, and a contact 16.

[0163] Multiple standard cells 10 are arranged along the X direction in standard cell rows 20, 21, and 23. Main power supply lines 13a, 13b, and sub-power supply lines 13c are arranged outside the standard cells along the X direction, respectively, relative to standard cell rows 20, 21, and 23. Power supply lines 14 are arranged along the Y direction. External cell contacts 15a, 15b, and 15c are arranged outside the standard cells and connect either of the internal cell power supply lines 12a and 12b on the M1 layer to either of the main power supply lines 13a and 13b or the sub-power supply line 13c on the M2 layer. Contact 16 connects either of the main power supply lines 13a and 13b or the sub-power supply line 13c on the M2 layer to the power supply line 14 on the M3 layer.

[0164] Figure 11 This is a diagram showing the configuration of the standard cell and power supply wiring of the second embodiment. As an example, a two-input NAND circuit is shown. The configuration diagram of the standard cell used is the same as Figure 2 The configuration diagram of the standard cell of the first embodiment shown is the same. Figure 11The configuration diagram shows a case where the standard cell 10 is arranged in the area where the power supply wiring is arranged as follows. (1) Figure 2 The auxiliary power supply wiring 13c is arranged in the cell outer wiring region 43c of the M2 layer. The auxiliary power supply wiring 13c is either the first power supply VDD or the third power supply VDD2. (2) Figure 2 The main power supply wiring 13b is arranged in the cell outer wiring area 43b of the M2 layer. The main power supply wiring 13b is either the second power supply VSS or the fourth power supply VSS2. (3) Figure 2 No power supply wiring is arranged in the cell outer wiring regions 43a and 43d of the M2 layer.

[0165] Figure 11 The configuration diagram of the second embodiment shown in FIG. Figure 4 Compared to the first configuration diagram of the first embodiment shown in FIG. 1 , the following points are different: (1) No power supply wiring is arranged in the M2 layer external cell wiring region 43a, and no external cell contact 15a is arranged at the power supply access point 45a. (2) Sub-power supply wiring 13c is arranged in the M2 layer external cell wiring region 43c, and external cell contact 15c is arranged at the power supply access point 45c.

[0166] In this manner, the sub-power supply wiring 13c can also be used as a power supply wiring on the high potential side in the standard cell 10. Similarly, the sub-power supply wiring 13d can also be used as a power supply wiring on the low potential side.

[0167] Figure 10 The configuration diagram of the semiconductor device of the second embodiment shown in FIG. Figure 1 Compared to the semiconductor device configuration diagram of the first embodiment shown in FIG. 1 , the following differences exist. (1) In the standard cells 10(VDD2)_2 in a portion of the standard cell arrangement row 23, the main power supply wiring 13a(VDD) is not provided, but remains as the M2 layer external cell wiring area 43a. (2) The secondary power supply wiring 13c(VDD2) is provided in the standard cells 10(VDD2)_2 and 10(VDD2)_3 in a portion of the standard cell arrangement row 23. The area of ​​the standard cell arrangement row 23 not provided with the secondary power supply wiring 13c(VDD2) remains as the M2 layer external cell wiring area 43c.

[0168] exist Figure 10 In the standard cell arrangement rows 20 and 21, a pair of power supply wirings including a high-potential side main power supply wiring 13a and a low-potential side main power supply wiring 13b are arranged as power supply wirings, and belong to the first block.

[0169] Standard cells 10(VDD)_1 and 10(VDD)_4 in standard cell row 23 are equipped with a pair of power supply lines consisting of a high-potential main power supply line 13a and a low-potential main power supply line 13b, and belong to the first block. Standard cell 10(VDD2)_2 in standard cell row 23 is equipped with a pair of power supply lines consisting of a high-potential secondary power supply line 13c and a low-potential main power supply line 13b, and belongs to the first block. Standard cell 10(VDD2)_3 in standard cell row 23 is equipped with a pair of power supply lines consisting of a high-potential main power supply line 13a and a low-potential main power supply line 13b, and a high-potential secondary power supply line 13c, as power supply lines. Standard cell 10(VDD2)_3 in standard cell row 23 belongs to the second block.

[0170] So, in Figure 10 In the configuration diagram of the semiconductor device 101 according to the second embodiment shown, the main power supply wiring 13a (VDD) or the sub-power supply wiring 13c (VDD2) is not arranged throughout the entire standard cell arrangement row 23. In the area where the main power supply wiring 13a (VDD) or the sub-power supply wiring 13c (VDD2) is not arranged, the M2 layer signal line wiring can be arranged in the M2 layer external cell wiring areas 43a and 43c, thereby ensuring more area for the M2 layer signal line wiring.

[0171] Figure 10 The flow of the layout design method of the semiconductor device 101 according to the second embodiment is shown in FIG. Figure 7 The flow of the layout design method of the semiconductor device 100 of the first embodiment shown is the same. Figure 10 The layout design system of the semiconductor device 101 according to the second embodiment shown in FIG. Figure 8 、 Figure 9 The same is true for the layout design system 200 of the semiconductor device 100 according to the first embodiment shown.

[0172] (Effects of the Second Embodiment)

[0173] According to the second embodiment, in addition to the area for configuring a pair of main power supply wiring, a partial area for configuring a pair of main power supply wiring and one or more secondary power supply wiring on the high-potential side is also partially provided during layout design. By partially providing the area for configuring the secondary power supply wiring, the increase in wiring area can be suppressed. Furthermore, in some standard cells, the main power supply wiring is not configured in the cell-outside wiring area of ​​the M2 layer, but the secondary power supply wiring is configured. Alternatively, in a standard cell configuration row, the secondary power supply wiring is configured in the cell-outside wiring area of ​​some standard cells, while the secondary power supply wiring is not configured in the cell-outside wiring area of ​​the remaining standard cells. By not configuring the main power supply wiring or the secondary power supply wiring, more area for configuring the signal line wiring of the M2 layer can be ensured. This increases the freedom of P&R wiring between standard cells, reduces the frequency with which designers have to re-adjust the position, size, and shape of each power domain, reconfigure the power supply wiring, and re-perform P&R, and suppresses duplication of work in the design process. In addition, from another perspective, the layout area required for configuring the signal line wiring can be reduced.

[0174] In addition, with Figure 18 Compared to the second structural diagram of the semiconductor device of the comparative example shown in FIG. , the second embodiment of the present invention can reduce the need to re-do the P&R process by adjusting the layout of power domains and power wiring. Specifically, the case of arranging standard cells using the first power supply VDD and standard cells using the third power supply VDD2 adjacent to each other in the X direction was considered. By configuring the power wiring of the power domain to which either standard cell belongs as a secondary power wiring, the need to insert a gap in the X direction to separate the power wiring of the first power supply VDD and the third power supply VDD2 of the M2 layer can be eliminated. This reduces the frequency with which designers need to adjust the position, size, and shape of the power domains.

[0175] [Third embodiment]

[0176] (Structure of Semiconductor Device)

[0177] Figure 12 This is a diagram showing the structure of a semiconductor device according to Embodiment 3. The semiconductor device 102 includes standard cell rows 20, 21, and 24, M2-layer main power supply wirings 13a and 13b, M2-layer sub-power supply wiring 13d, M3-layer power supply wiring 14, cell external contacts 15a, 15b, and 15d, and a contact 16.

[0178] Multiple standard cells 10 are arranged along the X direction in standard cell rows 20, 21, and 24. Main power supply lines 13a, 13b, and sub-power supply line 13d are arranged outside the standard cells along the X direction, respectively, relative to standard cell rows 20, 21, and 24. Power supply line 14 is arranged along the Y direction. External cell contacts 15a, 15b, and 15d are arranged outside the standard cells and connect either of the internal cell power supply lines 12a and 12b on the M1 layer to either of the main power supply lines 13a and 13b or the sub-power supply line 13d on the M2 layer. Contact 16 connects either of the main power supply lines 13a and 13b or the sub-power supply line 13d on the M2 layer to the power supply line 14 on the M3 layer.

[0179] The main power supply wiring 13b that supplies the second power supply VSS is referred to as the main power supply wiring 13b(VSS), and the main power supply wiring 13b that supplies the fourth power supply VSS2 is referred to as the main power supply wiring 13b(VSS2). Furthermore, the sub-power supply wiring 13d that supplies the fourth power supply VSS2 is referred to as the sub-power supply wiring 13d(VSS2).

[0180] The configuration of the standard cell 10 is the same whether using either the second power supply VSS or the fourth power supply VSS2. When configuring the standard cell 10, the power supply used by the standard cell 10 is connected externally to the standard cell 10. When the standard cell 10 uses the second power supply VSS as the low-potential power supply, it is expressed as "standard cell 10 (VSS);" and when using the fourth power supply VSS2, it is expressed as "standard cell 10 (VSS2).

[0181] Figure 13A This is a first configuration diagram of a standard cell and power supply wiring according to the third embodiment. The first configuration diagram shows a case where a standard cell 10 is configured in an area where power supply wiring is configured as follows. (1) Figure 2 The main power supply wirings 13a and 13b are respectively arranged in the cell outer wiring regions 43a and 43b of the M2 layer. The main power supply wiring 13a is either the first power supply VDD or the third power supply VDD2, and the main power supply wiring 13b is either the second power supply VSS or the fourth power supply VSS2. (2) Figure 2 The sub-power supply wiring 13d is configured in the cell outer wiring region 43d of the M2 layer. The sub-power supply wiring 13d is a power supply wiring that supplies a power different from the power supplied by the main power supply wiring 13b in the second power supply VSS or the fourth power supply VSS2. (3) Figure 2 No power supply wiring is arranged in the cell outer wiring region 43c of the M2 layer.

[0182] The standard cell 10 uses the main power supply wiring 13 a and the main power supply wiring 13 b . Figure 13A The first configuration diagram of the third embodiment shown in FIG. Figure 4 Compared with the first configuration diagram of the first embodiment shown in FIG, the difference is that not only the main power supply wiring 13b but also the sub-power supply wiring 13d is configured as the power supply wiring on the low potential side. Figure 4 The processing (g) performed when the standard cell 10 is configured in the first configuration diagram of the first embodiment is Figure 13A In the first configuration diagram of the third embodiment, the power supply wiring 12b in the unit is separated from the auxiliary power supply wiring 13d. Figure 4 Again, description is omitted.

[0183] Figure 13B This is a second configuration diagram of a standard cell and power supply wiring according to the third embodiment. In the second configuration diagram, the configuration of the power supply wiring in the area where the standard cell 10 is configured is as follows: Figure 13A The same is true for the first configuration diagram shown.

[0184] Figure 13B The second structure diagram shown is the same as Figure 13A Compared with the first structure shown in FIG, the difference is that the standard cell 10 does not use the main power supply wiring 13b but uses the auxiliary power supply wiring 13d as the power supply wiring on the low potential side. Figure 4 The process (a) and the processes (e) to (g) performed when the standard cell 10 is arranged in the first configuration diagram of the first embodiment are as follows.

[0185] (a) The main power supply wiring 13 a and the sub-power supply wiring 13 d are selected as a pair of power supply wirings used in the standard cell 10 .

[0186] (e) Figure 2 Of the power supply entry points 45b and 45d in FIG, the power supply entry point 45d corresponding to the sub-power supply wiring 13d used in the standard cell 10 is selected.

[0187] (f) The cell external contact 15d is arranged at the selected power supply input point 45d, and the intra-cell power supply wiring 12b of the M1 layer is connected to the sub-power supply wiring 13d.

[0188] (g) An insulating film is disposed at the unselected power supply input point 45b to isolate the intra-cell power supply line 12b of the M1 layer from the main power supply line 13b.

[0189] exist Figure 12 In the standard cell configuration lines 20 and 21, use Figure 4 The first configuration shown is one in which the standard cells and power supply wiring of the first embodiment are arranged.

[0190] exist Figure 12 In the standard cell configuration line 24, use Figure 13AThe first configuration of the standard cell and power supply wiring of the third embodiment is shown, and Figure 13B The second configuration of the standard cell and power supply wiring of the third embodiment is shown. Outside the standard cell 10, the main power supply wiring 13a, 13b (VSS) and the sub-power supply wiring 13d (VSS2) of the M2 layer are arranged at Figure 2 The cell outer wiring regions 43a, 43b, and 43d of the M2 layer.

[0191] Among the four standard cells 10 arranged in the standard cell arrangement row 24, the standard cells 10(VSS)_1 and 10(VSS)_4 use Figure 13A In the standard cells 10(VSS)_1 and 10(VSS)_4, the main power supply wiring 13b (VSS) on the low potential side is connected to the power supply wiring 12b in the cell of the M1 layer. Therefore, outside the standard cell 10, Figure 2 The position of the power access point 45b in the configuration unit is the external contact point 15b.

[0192] In standard cells 10(VSS2)_2 and 10(VSS2)_3, use Figure 13B In the standard cells 10(VSS2)_2 and 10(VSS2)_3, the auxiliary power supply wiring 13d (VSS2) on the low potential side is connected to the power supply wiring 12b in the cell of the M1 layer. Therefore, outside the standard cell 10, Figure 2 The location of the power access point 45d in the configuration unit is the external contact point 15d.

[0193] Figure 12 The standard cell arrangement rows 20 and 21 are arranged with a pair of power supply wirings including a main power supply wiring 13a on a high potential side and a main power supply wiring 13b on a low potential side as power supply wirings, and belong to the first block. Figure 12 The standard cell arrangement row 24 is arranged with a pair of power supply wirings including a high potential side main power supply wiring 13a and a low potential side main power supply wiring 13b, and a low potential side sub-power supply wiring 13d as power supply wirings, and belongs to the second block.

[0194] Figure 12 The flow of the layout design method of the semiconductor device 102 according to the third embodiment is shown in FIG. Figure 7 The layout design method of the semiconductor device 100 of the first embodiment shown in FIG. Figure 8 、 Figure 9 The same is true for the layout design system 200 of the semiconductor device 100 according to the first embodiment shown.

[0195] In addition, Figure 12 In the semiconductor device 102 of the third embodiment shown in FIG. Figure 10 Similar to the semiconductor device 101 of the second embodiment, the main power supply wiring 13b may be disposed in the extra-cell wiring regions 43b and 43d of some standard cells 10, but the sub-power supply wiring 13d may be disposed instead. Alternatively, in the standard cell arrangement row 24, the sub-power supply wiring 13d may be disposed in the extra-cell wiring regions 43d of some standard cells 10, while the sub-power supply wiring 13d may not be disposed in the extra-cell wiring regions 43d of the remaining standard cells 10. Signal line wiring for the M2 layer can be disposed in the extra-cell wiring regions 43d of the M2 layer where the sub-power supply wiring 13d is not disposed.

[0196] (Effects of the Third Embodiment)

[0197] According to the third embodiment, in addition to the area for arranging a pair of main power supply wirings, a partial area for arranging a pair of main power supply wirings and one or more low-potential secondary power supply wirings is also partially provided during layout design. By partially providing the area for arranging the secondary power supply wirings, an increase in the wiring area can be suppressed. Standard cells that use any of the multiple power supplies can also be arranged in this partially provided area. This increases the degree of freedom in P&R (Planning and Redesign), reduces the frequency with which designers have to readjust the position, size, and shape of each power domain, reconfigure the power supply wiring, and then re-perform P&R, and thus reduces duplication of work in the design process.

[0198] [Fourth embodiment]

[0199] (Structure of Semiconductor Device)

[0200] Figure 14A This is a first configuration diagram of a standard cell and power supply wiring according to the fourth embodiment. The first configuration diagram shows a case where a standard cell 10 is configured in an area where power supply wiring is configured as follows. (1) Figure 2 The main power supply wirings 13a and 13b are respectively arranged in the cell outer wiring regions 43a and 43b of the M2 layer. (2) Figure 2 Subsidiary power supply lines 13c and 13d are arranged in the cell outer wiring regions 43c and 43d of the M2 layer, respectively.

[0201] The standard cell 10 uses the main power supply wiring 13 a and the main power supply wiring 13 b . Figure 14A The first configuration diagram of the fourth embodiment shown in FIG. Figure 4 Compared with the first configuration diagram of the first embodiment shown in FIG, the difference is that the auxiliary power supply wiring 13c is also configured as the power supply wiring on the high potential side, and the auxiliary power supply wiring 13d is also configured as the power supply wiring on the low potential side. Figure 4The processes (d) and (g) performed when the standard cell 10 is arranged in the first configuration diagram of the first embodiment shown in FIG. Figure 14A The first configuration diagram of the fourth embodiment shown is as follows.

[0202] (d) An insulating film is disposed at the unselected power supply input point 45c to isolate the intra-cell power supply line 12a and the sub-power supply line 13c of the M1 layer.

[0203] (g) An insulating film is disposed at the unselected power supply input point 45d to isolate the intra-cell power supply line 12b and the sub-power supply line 13d of the M1 layer.

[0204] Figure 14B This is a second configuration diagram of a standard cell and power supply wiring according to the fourth embodiment. In the second configuration diagram, the configuration of the power supply wiring in the region where the standard cell 10 is configured is as follows: Figure 14A The same is true for the first configuration diagram shown.

[0205] Figure 14B The second structure diagram shown is the same as Figure 14A Compared with the first structure shown in FIG, the difference is that the standard cell 10 uses the auxiliary power supply wiring 13c as the power supply wiring on the high potential side and uses the auxiliary power supply wiring 13d as the power supply wiring on the low potential side. Figure 4 The processes (a) to (g) performed when the standard cell 10 is arranged in the first configuration diagram of the first embodiment shown in FIG. Figure 14B The second configuration diagram of the fourth embodiment shown is as follows.

[0206] (a) The sub-power supply wirings 13 c and 13 d are selected as a pair of power supply wirings used in the standard cell 10 .

[0207] (b) Figure 2 Of the power supply entry points 45 a and 45 c in FIG, the power supply entry point 45 c corresponding to the sub-power supply wiring 13 c used in the standard cell 10 is selected.

[0208] (c) The cell external contact 15c is arranged at the selected power supply input point 45c, and the intra-cell power supply line 12a of the M1 layer is connected to the sub-power supply line 13c.

[0209] (d) An insulating film is disposed at the unselected power supply input point 45a to isolate the intra-cell power supply line 12a of the M1 layer from the main power supply line 13a.

[0210] (e) Figure 2 Of the power supply entry points 45b and 45d in FIG, the power supply entry point 45d corresponding to the sub-power supply wiring 13d used in the standard cell 10 is selected.

[0211] (f) The cell external contact 15d is arranged at the selected power supply input point 45d, and the intra-cell power supply wiring 12b of the M1 layer is connected to the sub-power supply wiring 13d.

[0212] (g) An insulating film is disposed at the unselected power supply input point 45b to isolate the intra-cell power supply line 12b of the M1 layer from the main power supply line 13b.

[0213] In addition, Figure 14A In the first configuration diagram, it is shown that both the high potential side power supply wiring and the low potential side power supply wiring use the main power supply wiring. Figure 14B In the second configuration diagram, the case where both the high-potential side power wiring and the low-potential side power wiring use the secondary power wiring is shown. As another combination, there is a case where the high-potential side power wiring uses the main power wiring and the low-potential side power wiring uses the secondary power wiring. This is equivalent to Figure 13B The cell outer wiring area 43c, such as Figure 6A As shown in the figure, a secondary power supply wiring 13c on the high potential side is additionally configured. Figure 13B and Figure 6A Since the structure is derived, the description is omitted.

[0214] In addition, as another combination, there is also a case where the power supply wiring on the high potential side uses the secondary power supply wiring and the power supply wiring on the low potential side uses the main power supply wiring. Figure 6B The cell outer wiring area 43d, such as Figure 13A As shown in the figure, a low potential side auxiliary power supply wiring 13d is additionally configured. Figure 6B and Figure 13A Since the structure is derived, the description is omitted.

[0215] By Figure 14A 、 Figure 14B The structure is such that a plurality of standard cell configuration rows are arranged in contact with each other at the boundary lines 11 in the X direction. In the standard cell configuration row, for each standard cell 10, either the main power supply wiring 13a or the auxiliary power supply wiring 13c used by the standard cell 10 is selected as the power supply wiring on the high potential side, and connected to the power supply wiring 12a in the cell. In addition, for each standard cell 10, either the main power supply wiring 13b or the auxiliary power supply wiring 13d used by the standard cell 10 is selected as the power supply wiring on the low potential side, and connected to the power supply wiring 12b in the cell. The structure of the standard cell configuration row can be achieved by Figure 1 The configuration diagram of the semiconductor device 100 according to the first embodiment shown in FIG. Figure 12 The configuration diagrams of the semiconductor device 102 according to the third embodiment are derived by combining the above diagrams, and therefore their description is omitted.

[0216] (Effects of the Fourth Embodiment)

[0217] According to the fourth embodiment, in addition to the area for arranging a pair of main power supply wirings, a partial area for arranging a pair of main power supply wirings, one or more high-potential-side secondary power supply wirings, and one or more low-potential-side secondary power supply wirings is also partially provided during layout design. By partially providing the area for arranging the secondary power supply wirings, an increase in wiring area can be suppressed. Standard cells that use any of the multiple power supplies can also be arranged in this partially provided area. This increases the degree of freedom in P&R (Planning and Redesign), reduces the frequency with which designers have to re-adjust the position, size, and shape of each power domain, re-arrange the power supply wiring, and then re-perform P&R, and thus reduces duplication of work in the design process.

[0218] [Other embodiments]

[0219] Although several embodiments of the present invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the scope of the invention. These embodiments or their variations are included within the scope and spirit of the invention and are included within the scope of the invention described in the claims and their equivalents.

[0220] For example, the configurations of standard cells and semiconductor devices in several embodiments of the present invention have been described as logic circuits, particularly NAND circuits, using a pair of power supplies. However, the logic circuit may also be a level shifter using a pair of power supplies and one or more stepped-up or stepped-down power supplies. Furthermore, the logic circuit may be a flip-flop that uses a pair of power supplies and one or more power supplies that are shut off during standby mode, retaining its value even when the power is turned off.

[0221] In addition, for example, in the configuration of the standard cells and semiconductor devices of several embodiments of the present invention, the case where the size of the standard cell in the Y direction is the unit height hu is described. However, it can also be a multi-height cell (multi height cell) included in multiple types of standard cells and whose size in the Y direction is an integer multiple of the unit height hu. The multi-height cell also uses a pair of power supplies, and the position of each power supply wiring in the Y direction is common to the standard cell whose size in the Y direction is the unit height hu, and is therefore included in the scope or gist of the present invention. For example, a first standard cell whose size in the Y direction is a natural number m times the unit height hu, and a second standard cell whose size in the Y direction is a natural number n times different from the natural number m times the unit height hu can be configured.

[0222] Furthermore, for example, in the configurations of standard cells and semiconductor devices according to several embodiments of the present invention, the main power supply wiring is arranged in the M2 layer external cell wiring regions 43a and 43b, and the secondary power supply wiring is arranged in the M2 layer external cell wiring regions 43c and 43d. However, the main power supply wiring may be arranged in the M2 layer external cell wiring regions 43c and 43d, and the secondary power supply wiring may be arranged in the M2 layer external cell wiring regions 43a and 43b.

[0223] [Explanation of Symbols]

[0224] 10 standard units

[0225] 11 Boundary Line

[0226] 12a, 12b Intra-unit power supply wiring

[0227] 13a,13b Main power wiring

[0228] 13c, 13d Auxiliary power supply wiring

[0229] 14 Power Wiring

[0230] 15a, 15b, 15c, 15d Unit external contacts

[0231] 16 contacts

[0232] 20,21,22,23,24 Standard cell configuration rows

[0233] 31 P-type semiconductor substrate

[0234] 32 N-type well

[0235] 33 Component Isolators

[0236] 34 P-type diffusion layer

[0237] 35 Insulation film

[0238] 36 Boundary Line

[0239] 37a, 37b Gate layer

[0240] 38 contacts

[0241] 39 Signal Wiring

[0242] 42 Signal line routing area

[0243] 43a, 43b, 43c, 43d: External wiring area of ​​the unit

[0244] 45a,45b,45c,45d Power access points

[0245] 100,101,102 Semiconductor devices

[0246] VDD 1st power supply

[0247] VDD2 3rd power supply

[0248] VSS Second power supply

[0249] VSS2 4th power supply.

Claims

1. A standard cell library, comprising a design for configuring standard cells to form a standard cell method for a semiconductor integrated circuit, comprising at least a first standard cell and a second standard cell, and The size of the first standard cell in the first direction is a natural number m times the unit height, and a first internal power supply wiring is configured inside the first standard cell; The size of the second standard cell in the first direction is a natural number n times the unit height, and a second internal power supply wiring is configured inside the second standard cell; The first standard cell and the second standard cell are configured such that when the first standard cell and the second standard cell are adjacently arranged in a second direction orthogonal to the first direction, the first internal power supply wiring and the second internal power supply wiring are separated from each other; The first standard cell includes: a first wiring region capable of arranging a first external power supply wiring and extending along the second direction; and a first connectable position capable of connecting the first external power supply wiring to the first internal power supply wiring; The second standard cell includes: a second wiring region capable of arranging the first external power supply wiring and extending along the second direction; and a second connectable position capable of connecting the first external power wiring to the second internal power wiring; The first wiring region and the second wiring region can be adjacently connected.

2. The standard cell library according to claim 1, wherein The first wiring region of the first standard cell and the second wiring region of the second standard cell are located at substantially the same position in the first direction.

3. The standard cell library according to claim 1, comprising: The third standard cell can be arranged adjacent to the first standard cell in the first direction. The standard cell library according to claim 1 , wherein the natural number m and the natural number n are different natural numbers.

5. The standard cell library according to claim 1, wherein The first standard cell has: a third internal power supply wiring, separated from the first internal power supply wiring; a third wiring region capable of arranging a second external power supply wiring and extending along the second direction; a third connectable position capable of connecting the second external power supply wiring to the third internal power supply wiring; a fourth wiring region capable of arranging a third external power supply wiring and extending along the second direction; and The fourth connectable position is capable of connecting the third external power supply wiring and the third internal power supply wiring. The standard cell library according to claim 5 , wherein When configuring the first standard cell, selecting, among the first external power wiring and the second external power wiring, the first connectable position or the second connectable position corresponding to the external power wiring used by the first standard cell; connecting the first external power supply wiring to the first internal power supply wiring at the selected first connectable position, or connecting the second external power supply wiring to the first internal power supply wiring at the selected second connectable position; At the fourth connectable position, the third external power supply wiring is connected to the third internal power supply wiring.

7. The standard cell library according to claim 1, wherein The first internal power supply wiring includes: a first portion arranged along the first direction; and a second portion arranged along the second direction; and The number of the first connectable positions is greater than the number of the first parts.

8. A semiconductor device comprising: The first standard cell has a size in the first direction that is a natural number m times the unit height, and a first internal power supply wiring is arranged inside. a second standard cell having a size in the first direction that is a natural number n times the unit height, a second internal power supply wiring disposed therein that is separated from the first internal power supply wiring, and being adjacent to the first standard cell in a second direction orthogonal to the first direction; a first external power supply wiring extending along the second direction; a first contact connecting the first internal power supply wiring and the first external power supply wiring at a first connectable position; and The second contact connects the second internal power supply wiring to the first external power supply wiring at a second connectable position.

9. The semiconductor device according to claim 8, wherein The first connectable position and the second connectable position are located at substantially the same position in the first direction.

10. The semiconductor device according to claim 8, comprising: The third standard cell can be arranged adjacent to the first standard cell in the first direction. The semiconductor device according to claim 8 , wherein the natural number m and the natural number n are different natural numbers.

12. The semiconductor device according to claim 8, wherein The first standard cell internally comprises: a third internal power supply wiring, separated from the first internal power supply wiring and the second internal power supply wiring; and Externally it has: a second external power supply wiring extending along the second direction; a third external power supply wiring extending along the second direction; and The third contact connects the third internal power supply wiring and the third external power supply wiring at a fourth connectable position.

13. The semiconductor device according to claim 8, wherein The first internal power supply wiring includes: a first portion arranged along the first direction; and a second portion arranged along the second direction; and The number of the first contacts is greater than the number of the first parts.

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