Circuit board wiring optimization method

Abstract

The invention discloses a circuit board wiring optimization method, and relates to the technical field of circuit board wiring, and the method comprises the steps: obtaining wiring data based on a monitoring weight; outputting a corresponding wiring quality value by using a pre-constructed wiring quality evaluation model; detecting whether the wiring quality value is less than a certain quality threshold, if so, counting the duration when the wiring quality value is less than a preset quality threshold, and judging whether the duration is greater than a certain duration; if yes, triggering an abortion instruction, and generating abortion data in response to the abortion instruction; and optimizing the initial wiring instruction by using the pre-constructed graph neural network model to obtain the final wiring instruction, and wiring the circuit board according to the final wiring instruction to obtain the wiring result of the circuit board, thereby solving the technical problems of incapability of stopping in time, easy occurrence of repeated work, consumption of a large amount of manpower and time cost and the like, and improving the wiring efficiency of the circuit board. The technical effects of improving the wiring efficiency, actively stopping the low-efficiency path and reducing the wiring cost are achieved.

Description

Technical Field

[0001] The present application relates to the technical field of circuit board wiring, and in particular to a method for optimizing circuit board wiring. Background Art

[0002] In related technologies, automatic wiring of circuit boards can be achieved through automatic wiring software; the wiring density can be increased by optimizing the blind hole process, thereby improving the wiring results; and the wiring space utilization rate can be improved and the time cost can be reduced by designing an arc-shaped fan-out signal line between two adjacent vias.

[0003] However, in related technologies, the wiring process of wiring software is not transparent, and the wiring path and intermediate status cannot be monitored in real time, resulting in the system being unable to actively terminate invalid processes, causing the wiring system to enter an infinite loop system, wasting a lot of manpower and time costs; improving wiring density does not involve dynamic monitoring and termination mechanisms of the wiring process; the use of arc fan-out signal line effects relies on static rules and lacks real-time quality evaluation, which urgently needs improvement. Summary of the Invention

[0004] The present application provides a method for optimizing circuit board wiring to at least solve the problems in related technologies, such as the inability to terminate wiring software in a timely manner, prone to repetitive work, resulting in low wiring efficiency and a large amount of manpower and time costs; improving wiring density without involving a dynamic monitoring and termination mechanism for the wiring process; and the use of arc fan-out signal line efficiency relying on static rules and lacking real-time quality evaluation.

[0005] The present application provides a method for optimizing circuit board wiring, comprising the following steps: based on the monitoring weight of at least one circuit board layer in the circuit board, obtaining wiring data corresponding to the monitoring weight; inputting the wiring data into a pre-constructed wiring quality assessment model to output a wiring quality value in response to the initial wiring instruction; detecting whether the wiring quality value is less than a preset quality threshold, and when detecting that the wiring quality value is less than the preset quality threshold, counting the duration of the wiring quality value less than the preset quality threshold based on the circuit board, and judging whether the duration is greater than a preset duration; if the duration is greater than the preset duration, triggering the abort instruction of the circuit board to generate abort data of the circuit board in response to the abort instruction; inputting the abort data into a pre-constructed graph neural network model to optimize the initial wiring instruction using the pre-constructed graph neural network model to obtain the final wiring instruction of the circuit board, and wiring the circuit board according to the final wiring instruction to obtain the wiring result of the circuit board.

[0006] The present application also provides a circuit board wiring optimization device, comprising: a first acquisition module, for acquiring wiring data corresponding to the monitoring weight of at least one circuit board layer in the circuit board; a first output module, for inputting the wiring data into a pre-built wiring quality assessment model to output a wiring quality value in response to the initial wiring instruction; a detection module, for detecting whether the wiring quality value is less than a preset quality threshold, and when detecting that the wiring quality value is less than the preset quality threshold, counting the duration of the wiring quality value less than the preset quality threshold based on the circuit board, and determining whether the duration is greater than a preset duration; a generation module, for triggering a suspension instruction of the circuit board when the duration is greater than the preset duration, and generating suspension data of the circuit board in response to the suspension instruction; a second output module, for inputting the suspension data into a pre-built graph neural network model, so as to optimize the initial wiring instruction using the pre-built graph neural network model to obtain the final wiring instruction of the circuit board, and wiring the circuit board according to the final wiring instruction to obtain the wiring result of the circuit board.

[0007] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any of the above-mentioned circuit board wiring optimization methods when executing the computer program.

[0008] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned circuit board wiring optimization methods are implemented.

[0009] The present application also provides a computer program product, including a computer program, which implements the steps of any of the above-mentioned circuit board wiring optimization methods when executed by a processor.

[0010] Through this application, corresponding wiring data can be obtained based on different monitoring weights, and a pre-built wiring quality assessment model can be used to obtain a wiring quality value in response to the initial wiring instruction, and detect whether the wiring quality value is less than a certain quality threshold. When the wiring quality value is less than a certain quality threshold and the duration is greater than a certain time, a termination instruction is triggered to generate termination data, and then the pre-built graph neural network model is used to optimize the initial wiring instruction to obtain the final wiring instruction, and wiring is performed according to the final wiring instruction to obtain the wiring result. Therefore, it can solve the problems in related technologies that the wiring software cannot be terminated in time, repetitive work is prone to occur, resulting in low wiring efficiency and consuming a lot of manpower and time costs; improving wiring density does not involve dynamic monitoring and termination mechanism of the wiring process; using arc fan-out signal line effect depends on static rules and lacks real-time quality assessment and other technical problems, so as to achieve the technical effects of improving wiring efficiency, shortening wiring cycle, actively terminating inefficient paths, avoiding resource waste, reducing invalid calculations, improving wiring paths, reducing wiring costs, and optimizing resource allocation. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0012] Figure 1 A block diagram of a system for optimizing circuit board wiring suspension according to one embodiment of the present application is provided; Figure 2 A flowchart of a circuit board wiring optimization method provided in an embodiment of the present application; Figure 3 A flowchart of a circuit board wiring optimization method provided according to another embodiment of the present application; Figure 4 A flowchart of a specific process of a circuit board wiring optimization method provided according to another embodiment of the present application; Figure 5 A block diagram of a circuit board wiring optimization device provided according to an embodiment of the present application.

[0013] Reference numerals: Among them, 10-circuit board wiring termination optimization system; 101-monitoring module, 102-decision module, 103-execution module, 104-restore module; 20-circuit board wiring optimization device; 100-first acquisition module, 200-first output module, 300-detection module, 400-generation module, 500-second output module. DETAILED DESCRIPTION

[0014] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0015] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0016] Before introducing the circuit board wiring optimization method proposed in the embodiment of the present application, an optimization system for circuit board wiring termination involved in the embodiment of the present application is first introduced.

[0017] Specifically, Figure 1 The present invention is a block diagram of a system for optimizing circuit board wiring termination according to one embodiment of the present application.

[0018] like Figure 1 As shown, the circuit board wiring suspension optimization system 10 includes: a monitoring module 101 , a decision module 102 , an execution module 103 and a restoration module 104 .

[0019] The monitoring module 101 is used to determine the monitoring weight and obtain the wiring data.

[0020] The decision module 102 is used to process the wiring data until certain data conditions are met, and input the wiring data that meets the certain data conditions into a pre-built wiring quality assessment model, calculate the corresponding wiring quality value, and detect whether the wiring quality value is less than a certain quality threshold. If it is less than, count the duration of the wiring quality value being less than the certain quality threshold, and determine whether the duration is greater than a certain time length. If it is greater than, trigger an abort instruction.

[0021] The execution module 103 is configured to generate suspension data in response to the suspension instruction.

[0022] The restoration module 104 is used to optimize the initial wiring instructions using a pre-built graph neural network model, and then obtain the final wiring instructions of the circuit board, thereby obtaining the corresponding wiring results.

[0023] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0024] An embodiment of the present application provides a circuit board wiring optimization method, and the method is described in detail in conjunction with the execution flow of the circuit board wiring optimization method.

[0025] Specifically, Figure 2 This is a flowchart of a circuit board wiring optimization method provided according to an embodiment of the present application.

[0026] like Figure 2 As shown, the circuit board wiring optimization method includes the following steps: In step S201 , based on the monitoring weight of at least one circuit board layer in the circuit board, wiring data corresponding to the monitoring weight is acquired.

[0027] It is understandable that in the embodiments of the present application, the wiring data may include but is not limited to network routing rate, critical path delay, inter-layer via density and number of design rule violations, etc., and the present application does not impose specific restrictions.

[0028] The network routing rate can be understood as the ratio of the number of successfully routed networks to the total number of routes, which can reflect the current routing progress and identify unrouted networks. Furthermore, in the embodiment of the present application, if the routing rate of the high monitoring weight layer is low, the routing strategy can be prioritized or adjusted, and this application does not impose specific limitations.

[0029] Critical path delay can be understood as the transmission delay of the signal path with the strictest timing requirements, ensuring that critical signals meet timing constraints and guarantee signal integrity. Furthermore, in the embodiments of this application, if the critical path delay of the high monitoring weight layer exceeds the standard, the routing length or layer allocation can be optimized, which is not specifically limited by this application.

[0030] The interlayer via density can be understood as the number of vias per unit area, which can reflect the frequency of interlayer switching. Furthermore, in the embodiments of the present application, if the via density of the high monitoring weight layer exceeds the standard, the wiring strategy can be adjusted, such as reducing layer switching or using blind vias, which is not specifically limited in this application.

[0031] The number of design rule violations can be understood as the total number of design rule violations (such as line width, spacing, via size, etc., which are not specifically limited in this application). It can be used to identify potential manufacturing or performance issues and ensure the manufacturability of the design. Furthermore, in the embodiment of this application, violations in high monitoring weight layers need to be fixed first to avoid affecting the overall design quality.

[0032] In some embodiments, the embodiments of the present application can obtain wiring data corresponding to the monitoring weight based on the monitoring weight of each circuit board layer in a circuit board including at least one circuit board layer.

[0033] Exemplarily, the embodiments of the present application can obtain wiring data based on the monitoring weight of each circuit board layer through an EDA (Electronic Design Automation) software API (Application Programming Interface) interface (such as Cadence SKILL API (Cadence SKILL Application Programming Interface, Cadence SKILL application programming interface), Altium Scripting API (Altium Scripting Application Programming Interface, Altium scripting application programming interface)), where the wiring data may include but is not limited to network routing rate, critical path delay, inter-layer via density and number of design rule violations, etc., and this application does not impose specific restrictions.

[0034] Optionally, in one embodiment of the present application, based on the monitoring weight of at least one circuit board layer in the circuit board, wiring data corresponding to the monitoring weight is obtained, including: determining the actual complexity of the circuit board and the target complexity of the target circuit board based on the number of networks, number of layers and component density of the circuit board; based on the circuit board, obtaining the high-speed signal ratio of the circuit board; and calculating the monitoring weight based on the actual complexity, target complexity and high-speed signal ratio.

[0035] It can be understood that in the embodiments of the present application, the complexity of different circuit boards can be determined by the number of networks, number of layers and component density of the circuit boards, which can be specifically set by technicians in this field according to actual conditions, and this application does not impose any specific restrictions.

[0036] In some embodiments, the embodiments of the present application can determine the complexity of the circuit board based on the number of networks, number of layers and component density of the circuit board.

[0037] For example, the embodiment of the present application can express the number of networks on the circuit board as , the number of layers of the circuit board is expressed as , the component density of the circuit board is expressed as , and then the actual complexity of the corresponding circuit board is obtained. The calculation process can be expressed as but not limited to: , Furthermore, the embodiment of the present application can obtain the target circuit board, that is, the target complexity of the reference circuit board , such as 8-layer HDI board (High Density Interconnector) .

[0038] In addition, it should be noted that in the embodiment of the present application, the high-speed signal ratio can be understood as the ratio of the number of high-speed signals on each circuit board layer to the total number of traces.

[0039] In some embodiments, the embodiment of the present application can calculate the monitoring weight based on the actual complexity, target complexity and high-speed signal ratio. The expression of the monitoring weight can be, but is not limited to: , in, is the actual complexity of the circuit board, is the target complexity of the target board, is the adjustment coefficient (range 0.1~0.5, default 0.2), For the The proportion of high-speed signals corresponding to the wiring of the circuit board layer.

[0040] The embodiments of the present application can determine the actual complexity of the circuit board and the target complexity of the target circuit board based on the number of networks, number of layers and component density of the circuit board, and then combine the high-speed signal ratio to calculate the monitoring weight using the monitoring weight calculation formula. The actual complexity is comprehensively calculated by the number of networks, number of layers and component density, and compared with the target complexity, and a higher monitoring weight is allocated as needed, wiring is optimized first, computing resources are adjusted, dynamic resource scheduling is achieved, wiring efficiency and success rate are improved, the design cycle is shortened, intelligent and adaptive design is supported, and diversified needs are adapted.

[0041] Optionally, in one embodiment of the present application, based on the monitoring weight of at least one circuit board layer in the circuit board, wiring data corresponding to the monitoring weight is obtained, including: determining the size of the wiring data based on the size of the monitoring weight, wherein the size of the monitoring weight is positively correlated with the size of the data volume; and obtaining wiring data including at least one of the network routing rate, critical path delay, interlayer via density, and number of design rule violations based on the data volume.

[0042] It is understandable that the monitoring weights in the embodiments of the present application can be used to reflect the importance or complexity of different circuit board layers in the circuit system, and thus when obtaining wiring data, more computing resources can be allocated to circuit board layers with large monitoring weights to process and generate more detailed wiring data. The positive correlation between the size of the monitoring weight and the amount of data can be understood as follows: the larger the monitoring weight, the larger the amount of data corresponding to the wiring data; the smaller the monitoring weight, the smaller the amount of data corresponding to the wiring data.

[0043] In some embodiments, the embodiments of the present application can obtain corresponding wiring data based on the amount of data that is positively correlated with the monitoring weight.

[0044] For example, the monitoring weight of circuit board layer 1 is 0.3, and the monitoring weight of circuit board layer 2 is 0.4, then the amount of wiring data of circuit board layer 1 is less than the amount of wiring data of circuit board layer 2.

[0045] The embodiments of the present application can achieve reasonable optimization of resource allocation according to the size of the monitoring weight, avoid wiring errors or unreasonableness due to insufficient computing resources, improve the overall wiring quality, and improve the stability and reliability of the circuit.

[0046] Optionally, in one embodiment of the present application, obtaining wiring data corresponding to the monitoring weight includes: obtaining wiring indicators of the wiring data based on the circuit board; determining the update time of the wiring data based on the board layer information of the circuit board; and updating the wiring data based on the wiring indicators and the update time.

[0047] It can be understood that in the embodiments of the present application, the wiring indicators may include but are not limited to line width, spacing, via parameters, pad diameter and mounting hole diameter, etc., and the present application does not impose specific restrictions.

[0048] In addition, in an embodiment of the present application, the update time of the wiring data can be determined by the board layer information of the circuit board. For example, if the structure of the circuit board layer 3 is relatively complex, the corresponding update time can be set to 5 seconds; if the structure of the circuit board layer 4 is relatively simple, the corresponding update time can be set to 10 seconds. This application does not impose any specific restrictions.

[0049] Among them, the board layer information can include but is not limited to the structural information, functional information and physical property information of the circuit board, etc., which can be specifically set by technicians in this field according to actual conditions, and this application does not impose any specific restrictions.

[0050] In some embodiments, the embodiments of the present application may update the wiring data after obtaining the wiring index and the update time, thereby obtaining updated wiring data.

[0051] Illustratively, the embodiment of the present application can start the wiring software, load the circuit board design file, parse the design wiring indicators through regular expressions, generate a line width / spacing matrix and a three-dimensional model of the stacked structure, adopt a distributed sampling strategy, update the wiring data every 10 seconds, reduce the system load, and obtain the wiring data according to the board layering and send it to the monitoring device, and multiple monitoring devices jointly perform data monitoring.

[0052] The embodiments of the present application can update the wiring data according to the wiring indicators and update time of the wiring data, dynamically adapt to the design stage requirements, improve wiring efficiency, accelerate wiring convergence by accurately updating key layer data, enhance signal integrity and reliability, reduce later risks, and support flexible response to complex design scenarios.

[0053] Optionally, in one embodiment of the present application, before inputting the wiring data into a pre-built wiring quality assessment model, it also includes: determining whether the wiring data meets the preset data conditions; if the wiring data does not meet the preset data conditions, processing the wiring data until the wiring data that meets the preset data conditions is obtained, and allowing the wiring data that meets the preset data conditions to be input into the pre-built wiring quality assessment model; if the wiring data meets the preset data conditions, allowing the wiring data to be input into the pre-built wiring quality assessment model.

[0054] During the actual execution process, the embodiment of the present application can determine whether the wiring data meets certain data conditions before inputting the wiring data into a pre-built wiring quality assessment model, and if it does not meet the conditions, process the wiring data until the certain data conditions are met, and allow the wiring data that meets the certain data conditions to be input into the pre-built wiring quality assessment model; and if it meets the conditions, allow the wiring data to be input into the pre-built wiring quality assessment model.

[0055] Among them, certain data conditions can be set by technicians in this field according to actual conditions, and this application does not impose specific restrictions.

[0056] Illustratively, in an embodiment of the present application, when the wiring data does not meet certain data conditions, a distributed computing framework can be used to process the wiring data that does not meet certain data conditions, and the wiring data that meets certain data conditions can be obtained by cleaning, classifying, regressing, clustering, etc. the data.

[0057] Before inputting the wiring data into a pre-built wiring quality assessment model, the embodiment of the present application determines whether the wiring data meets certain data conditions. If not, the wiring data is processed until wiring data that meets the certain data conditions is obtained, invalid data is filtered out, model misjudgment is avoided, model assessment quality is improved, the assessment process is accelerated, and design risks are reduced.

[0058] Optionally, in one embodiment of the present application, before inputting the wiring data into a pre-built wiring quality assessment model, it also includes: determining the target network routing rate, target average winding length and target via density of the circuit board based on the target wiring data; determining the first weight coefficient corresponding to the target network routing rate, the second weight coefficient corresponding to the target average winding length, and the third weight coefficient corresponding to the target via density based on the target network routing rate, the target average winding length and the target via density; constructing a wiring quality assessment model based on the target network routing rate, the target average winding length, the target via density, the first weight coefficient, the second weight coefficient and the third weight coefficient.

[0059] In some embodiments, the embodiments of the present application can determine the target network routing rate, target average winding length, and target via density of the circuit board based on the target wiring data, and then determine the first weight coefficient corresponding to the target network routing rate, the second weight coefficient corresponding to the target average winding length, and the third weight coefficient corresponding to the target via density, thereby constructing a wiring quality assessment model. The expression of the pre-constructed wiring quality assessment model can be, but is not limited to,: , in, is the first weight coefficient, is the second weight coefficient, is the third weight coefficient, , is the number of networks that have been deployed, is the total number of wirings, is the average winding length, reflecting the wiring efficiency, The larger the value, the worse the wiring quality.

[0060] For example, in the embodiment of the present application, for an 8-layer HDI board, , , .

[0061] The embodiment of the present application can determine the target network routing rate, target average winding length and target via density of the circuit board based on the target wiring data, and then determine the corresponding weight coefficients, so as to construct a wiring quality evaluation model, dynamically adapt to different design requirements, avoid "one-size-fits-all" evaluation, and clearly include target indicators and corresponding weight coefficients. It can intuitively understand the contribution of each indicator to the evaluation results, quickly locate the optimization direction, improve the interpretability of the evaluation, accelerate design iteration and model deployment, support incremental model updates, and reduce maintenance costs.

[0062] Optionally, in one embodiment of the present application, before inputting the termination data into a pre-built graph neural network model, it also includes: obtaining historical termination data of the circuit board; determining the structural information and training information of the graph neural network model based on the historical termination data; based on the structural information and training information, using the historical termination data to train the graph neural network model to construct a graph neural network model that meets preset training conditions.

[0063] It can be understood that in the embodiment of the present application, the historical suspension data can be understood as the suspension data of the past three months, six months or one year, which can be specifically set by technicians in this field according to actual conditions, and this application does not impose any specific restrictions.

[0064] In addition, in the embodiment of the present application, when there is no historical termination data for a circuit board, the termination data of a similar or similar circuit board layer can be used as the termination data of the circuit board layer; similar termination data can also be randomly generated; or it can be obtained through other means, which is not specifically limited in this application.

[0065] In some embodiments, embodiments of the present application can first obtain historical suspension data of a circuit board, and then determine the structural information and training information of the graph neural network model. The graph neural network model can then be trained using the historical suspension data to construct a graph neural network model that meets certain training conditions. The training conditions can be set by those skilled in the art based on actual circumstances and are not specifically limited by this application.

[0066] It should be noted that, in an embodiment of the present application, the structural information may include but is not limited to node embedding dimensions. For example, an embodiment of the present application may select a 32-dimensional or 64-dimensional vector to represent each circuit board layer, and the present application does not impose any specific restrictions; the number of graph convolution layers, for example, an embodiment of the present application may select a 2-layer or 3-layer graph convolution network, and the present application does not impose any specific restrictions; the type of aggregation function, for example, an embodiment of the present application may select a sum, average or maximum aggregation function, and the present application does not impose any specific restrictions.

[0067] The training information may include, but is not limited to, a loss function. For example, in an embodiment of the present application, the cross entropy loss function may be selected for classification tasks, and the present application does not impose any specific restrictions; an optimizer. For example, in an embodiment of the present application, the Adam optimizer may be selected, and the present application does not impose any specific restrictions; a learning rate. For example, in an embodiment of the present application, a learning rate such as 0.001 or 0.01 may be selected, and the present application does not impose any specific restrictions; the number of training rounds. For example, in an embodiment of the present application, 100 or 200 rounds of training may be selected, and the present application does not impose any specific restrictions.

[0068] The embodiment of the present application can obtain historical suspension data of the circuit board before inputting the suspension data into a pre-built graph neural network model, and then determine the structural information and training information of the graph neural network model, so as to use the historical suspension data to train the graph neural network model, and then construct a graph neural network model that meets certain training conditions. By statistically analyzing the distribution of suspension causes in various scenarios, the graph neural network model structure and training parameters are dynamically adjusted, so that the model can capture the suspension risk characteristics in different scenarios in a targeted manner, avoid the missed judgment of the fixed structure model in specific scenarios, improve the prediction accuracy, pre-train based on historical data, reduce real-time training costs, accelerate model training and deployment, balance accuracy and efficiency, identify potential suspension risks in advance, and enhance reliability.

[0069] In step S202 , the wiring data is input into a pre-built wiring quality assessment model to output a wiring quality value in response to an initial wiring instruction.

[0070] In some embodiments, the embodiments of the present application may input routing data into a pre-built routing quality assessment model, thereby obtaining a routing quality value in response to an initial routing instruction.

[0071] Illustratively, the embodiment of the present application may first initialize parameters of a pre-built wiring quality assessment model, and then input wiring data into the pre-built wiring quality assessment model, thereby obtaining a wiring quality value in response to the initial wiring instruction.

[0072] In step S203, it is detected whether the wiring quality value is less than the preset quality threshold, and when it is detected that the wiring quality value is less than the preset quality threshold, the duration of the wiring quality value being less than the preset quality threshold is counted based on the circuit board, and it is determined whether the duration is greater than the preset duration.

[0073] It is understandable that in the embodiment of the present application, the certain quality threshold can be dynamically adjusted according to the type of circuit board. For example, in the embodiment of the present application, the certain quality threshold of the ordinary board can be set to 0.6, and the certain quality threshold of the HDI board can be set to 0.7. The specific setting can be made by technicians in this field according to actual conditions, and this application does not impose any specific restrictions.

[0074] In addition, in an embodiment of the present application, the certain time length is negatively correlated with the complexity of the circuit board. For example, in an embodiment of the present application, the certain time length of the HDI board can be set to 10 minutes, and the certain time length of the backplane can be set to 5 minutes. The specific setting can be made by technicians in this field according to actual conditions. This application does not impose specific restrictions. Dynamic quality detection avoids the accumulation of design defects, enhances data value, and supports accurate analysis and automated decision-making.

[0075] In some embodiments, the embodiments of the present application can detect whether the wiring quality value is less than a certain quality threshold, and when it is detected that the wiring quality value is less than a certain quality threshold, count the duration of the wiring quality value being less than the certain quality threshold, and determine whether the duration is greater than a certain duration.

[0076] For example, the embodiment of the present application may express a certain quality threshold as , a certain duration is expressed as , HDI board For 10 minutes, the back For 5 minutes, and detect the wiring quality value of the HDI board circuit board, and when In the case of , and judge Is it greater than .

[0077] In step S204 , if the duration is greater than a preset time length, a circuit board suspension instruction is triggered, so as to generate circuit board suspension data in response to the suspension instruction.

[0078] In some embodiments, the embodiments of the present application may trigger a circuit board suspension instruction when the duration is greater than a certain time, so as to generate circuit board suspension data in response to the suspension instruction.

[0079] For example, the embodiments of the present application In the case of abort, abort instruction is triggered, and corresponding abort data is generated in response to the abort instruction.

[0080] In step S205, the terminated data is input into a pre-built graph neural network model to optimize the initial routing instructions using the pre-built graph neural network model to obtain the final routing instructions of the circuit board, and the circuit board is routed according to the final routing instructions to obtain the routing results of the circuit board.

[0081] In some embodiments, the embodiments of the present application can input the suspension data into a pre-built graph neural network model, and then use the pre-built graph neural network model to optimize the initial wiring instructions to obtain the final wiring instructions of the circuit board, and then wire the circuit board according to the final wiring instructions to obtain the wiring results of the circuit board.

[0082] Exemplarily, the embodiment of the present application can input the suspended data into a pre-built graph neural network model to analyze the unfinished network topology, and then optimize the initial wiring instructions to obtain the final wiring instructions of the circuit board, and automatically call the EDA interface, and again import the final wiring instructions into the wiring software through the API interface of the wiring software, restart the wiring software, and continue the subsequent wiring to obtain the wiring results of the circuit board.

[0083] It should be noted that in addition to using a pre-built graph neural network model to optimize the initial wiring instructions, the embodiments of the present application can also use other intelligent auxiliary systems and intelligent analysis modules for optimization and analysis. The specific settings can be made by technical personnel in this field according to actual conditions, and this application does not impose any specific restrictions.

[0084] Optionally, in one embodiment of the present application, in response to a suspension instruction, suspension data of the circuit board is generated, including: determining the suspension stage of the initial wiring instruction based on the instruction information of the suspension instruction; and generating suspension data under different stage characteristics based on multiple stage characteristics of the suspension stage.

[0085] It can be understood that in the embodiment of the present application, the instruction information may include, but is not limited to, specific parameters and identifiers corresponding to the suspension stage, and the present application does not impose any specific limitations.

[0086] In some embodiments, embodiments of the present application can determine the corresponding abort stage based on the instruction information of the abort instruction, and then use the stage characteristics of different abort stages to generate corresponding abort data. The stage characteristics can be first-stage characteristics, such as priority; second-stage characteristics, such as valid wiring tasks and invalid wiring tasks; and third-stage characteristics, such as heat maps and resource consumption statistics. Specific configurations can be made by those skilled in the art based on actual conditions and are not specifically limited by this application.

[0087] The embodiment of the present application can determine the suspension stage of the initial wiring instruction by parsing the instruction information of the suspension instruction, thereby achieving fast and accurate determination, generating suspension data based on the suspension stage, and processing data at different stages to enhance system flexibility.

[0088] Optionally, in one embodiment of the present application, based on multiple stage characteristics of the suspension stage, suspension data under different stage characteristics is generated, including: based on the first stage characteristics among the multiple stage characteristics, determining that when the suspension stage is the first stage, the task level of at least one wiring task of the initial wiring instruction is reduced to a preset level to obtain the suspension data under the first stage characteristics; based on the second stage characteristics among the multiple stage characteristics, determining that when the suspension stage is the second stage, based on the wiring quality values ​​of different wiring tasks, the wiring tasks that meet the preset invalid conditions are frozen, and the wiring tasks that meet the preset valid conditions are released to form the final tasks, so as to obtain the suspension data under the second stage characteristics; based on the third stage characteristics of the multiple stage characteristics, determining that when the suspension stage is the third stage, at least one of a spatial distribution heat map, an unfinished network priority list, and a resource consumption statistics table is generated to obtain the suspension data under the third stage characteristics.

[0089] In some embodiments, the embodiments of the present application may adopt a progressive abort method in response to an abort instruction, and generate abort data corresponding to the characteristics of different stages based on the characteristics of different stages. The process can be divided into three stages: Phase 1: Reduce the task level of the wiring task to a certain level.

[0090] Among them, a certain level can be set by technicians in this field according to actual conditions, and this application does not impose any specific restrictions.

[0091] Illustratively, the embodiment of the present application is based on the first-stage characteristics and determines that when the termination stage is the first stage, the task level of the wiring task numbered 001 in the initial wiring instruction is reduced to a low priority. For example, if the wiring task 001 has a high priority before responding to the termination instruction, then after responding to the termination instruction, the high priority can be reduced to a low priority. The specific setting can be made by a technician in this field according to the actual situation, and this application does not impose specific restrictions, thereby obtaining the termination data under the corresponding characteristics.

[0092] The second stage: freeze invalid routing tasks and release valid routing tasks.

[0093] Among them, the embodiment of the present application can determine, based on the characteristics of the second stage, that when the termination stage is the second stage, based on the wiring quality values ​​of different wiring tasks, freeze the wiring tasks that meet certain invalid conditions, and release the wiring tasks that meet certain valid conditions to form the final task, and then obtain the termination data under the corresponding characteristics. Among them, the certain invalid conditions and certain valid conditions can be set by technical personnel in this field according to actual conditions, and this application does not impose specific restrictions.

[0094] For example, in an embodiment of the present application, if the routing quality value of routing task 002 is less than a certain threshold, routing task 002 may be determined to be an invalid routing task and may be frozen; if the routing quality value of routing task 003 is greater than a certain threshold, routing task 003 may be determined to be a valid routing task and may be released. The certain threshold value may be set by a person skilled in the art based on actual conditions and is not specifically limited in this application.

[0095] Phase 3: Generate a spatial distribution heat map, a priority list of unfinished networks, and a resource consumption statistics table.

[0096] It can be understood that the spatial distribution heat map in the embodiment of the present application can highlight the design rule check violation areas, and the present application does not impose specific restrictions; the unfinished network priority list can be sorted according to the signal integrity requirements, and the present application does not impose specific restrictions; the resource consumption statistics table can include processor occupancy, memory usage, wiring time, etc., and the present application does not impose specific restrictions. Other data can also be generated, which can be specifically set by technical personnel in this field according to actual conditions, and the present application does not impose specific restrictions.

[0097] Among them, the embodiment of the present application can determine based on the characteristics of the third stage that when the termination stage is the third stage, generate a spatial distribution heat map, an unfinished network priority list and a resource consumption statistics table, and then obtain the termination data under the corresponding characteristics.

[0098] The embodiment of the present application can adopt a progressive three-stage suspension method to generate corresponding suspension data, optimize resource allocation, improve the quality of suspension data, and support accurate analysis and design recovery.

[0099] The following describes the circuit board wiring optimization method proposed in the embodiments of the present application in combination with multiple embodiments.

[0100] Figure 3 The present invention is a flowchart of a method for optimizing circuit board wiring according to another embodiment of the present application.

[0101] Figure 4 The present invention is a flowchart of a specific process of a circuit board wiring optimization method provided according to another embodiment of the present application.

[0102] Step S301: Based on the monitoring weight of at least one circuit board layer, wiring data is obtained using EDA software.

[0103] Among them, combined Figure 4 As shown, the embodiment of the present application includes: Step S401: Loading a circuit board design file.

[0104] Step S402: Analyze the design rules to generate a constraint matrix.

[0105] Step S403: Initialize a pre-built wiring quality assessment model.

[0106] Step S404: configure the threshold.

[0107] In this embodiment of the present application, the threshold value may include and .

[0108] Step S405: Start monitoring.

[0109] Step S406: API obtains wiring data.

[0110] Step S302: Start the wiring software and perform suspension analysis.

[0111] Among them, combined Figure 4 As shown, the embodiment of the present application includes: Step S407: Calculate the actual complexity of the circuit board.

[0112] Step S408: Dynamically adjust the weight coefficient.

[0113] In the embodiment of the present application, the weight coefficient may include, but is not limited to, a first weight coefficient, a second weight coefficient, and a third weight coefficient, etc., and the present application does not impose any specific restrictions.

[0114] Step S409: Calculate the wiring quality value.

[0115] Step S410: Determine whether the wiring quality value is less than a certain quality threshold.

[0116] In this embodiment of the present application, if is less than, step S411 is executed; otherwise, step S406 is executed.

[0117] Step S411: Count the duration.

[0118] Step S412: Determine whether the duration is greater than a certain time period.

[0119] In this embodiment of the present application, if the value is greater than , step S413 is executed; otherwise, step S406 is executed.

[0120] Step S413: triggering a stop instruction.

[0121] In summary, the embodiment of the present application can start the wiring software, and then use the pre-built wiring quality assessment model to calculate the corresponding wiring quality value, and detect whether the wiring quality value is less than a certain quality threshold. If it is less than, the duration of the wiring quality value being less than the certain quality threshold is counted, and it is determined whether the duration is greater than a certain time length, and if it is greater than, a termination instruction is triggered.

[0122] Step S303: suspend the wiring software and generate suspension data.

[0123] Among them, combined Figure 4 As shown, the embodiment of the present application includes: Step S414: The third stage is terminated.

[0124] Step S415: Lower the task level.

[0125] Step S416: Freeze invalid tasks.

[0126] Step S417: Generate suspension data.

[0127] In summary, the embodiment of the present application can trigger a stop instruction, stop the wiring software, and generate stop data.

[0128] Step S304: Optimize the initial routing instructions.

[0129] Among them, combined Figure 4 As shown, the embodiment of the present application includes: Step S418: Generate routing suggestions using a pre-built graph neural network model.

[0130] It can be understood that the embodiment of the present application can use a pre-built graph neural network model to optimize the initial wiring instructions, and then obtain the final wiring instructions of the circuit board.

[0131] Step S305: re-import the EDA software and start the wiring software.

[0132] Among them, combined Figure 4 As shown, the embodiment of the present application includes: Step S419: Automatically restart the wiring software.

[0133] Step S420: Determine whether to continue.

[0134] In this embodiment of the present application, if continuing, execute step S401; otherwise, execute step S421.

[0135] Step S421: Complete the wiring and generate the wiring results.

[0136] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0137] According to the circuit board wiring optimization method proposed in the embodiment of the present application, the corresponding wiring data can be obtained based on different monitoring weights, and the pre-built wiring quality evaluation model can be used to obtain the wiring quality value in response to the initial wiring instruction, and detect whether the wiring quality value is less than a certain quality threshold. When the wiring quality value is less than a certain quality threshold and the duration is greater than a certain time, the termination instruction is triggered to generate termination data, and then the pre-built graph neural network model is used to optimize the initial wiring instruction to obtain the final wiring instruction, and wiring is performed according to the final wiring instruction to obtain the wiring result. Therefore, it can solve the problems in the related technology that the wiring software cannot be terminated in time, repetitive work is prone to occur, resulting in low wiring efficiency and consuming a lot of manpower and time costs; improving the wiring density does not involve the dynamic monitoring and termination mechanism of the wiring process; the arc fan-out signal line effect relies on static rules and lacks real-time quality evaluation and other technical problems, so as to achieve the technical effects of improving wiring efficiency, shortening the wiring cycle, actively terminating inefficient paths, avoiding resource waste, reducing invalid calculations, improving wiring paths, reducing wiring costs, and optimizing resource allocation.

[0138] An embodiment of the present application also provides a circuit board wiring optimization device.

[0139] Figure 5 A block diagram of a circuit board wiring optimization device provided according to an embodiment of the present application.

[0140] like Figure 5 As shown, the circuit board wiring optimization device 20, the circuit board includes at least one circuit board layer, wherein the circuit board wiring optimization device 20 includes: a first acquisition module 100, a first output module 200, a detection module 300, a generation module 400 and a second output module 500.

[0141] The first acquisition module 100 is configured to acquire wiring data corresponding to a monitoring weight based on a monitoring weight of at least one circuit board layer in the circuit board.

[0142] The first output module 200 is configured to input the wiring data into a pre-built wiring quality evaluation model to output a wiring quality value in response to an initial wiring instruction.

[0143] The detection module 300 is used to detect whether the wiring quality value is less than the preset quality threshold, and when it is detected that the wiring quality value is less than the preset quality threshold, the circuit board statistics the duration of the wiring quality value being less than the preset quality threshold, and determine whether the duration is greater than the preset duration.

[0144] The generating module 400 is configured to trigger a circuit board suspension instruction when the duration is greater than a preset duration, and generate circuit board suspension data in response to the suspension instruction.

[0145] The second output module 500 is used to input the terminated data into a pre-built graph neural network model, so as to optimize the initial wiring instructions using the pre-built graph neural network model to obtain the final wiring instructions of the circuit board, and to wire the circuit board according to the final wiring instructions to obtain the wiring results of the circuit board.

[0146] Optionally, in one embodiment of the present application, it further includes: a first determination module, a second determination module and a first construction module.

[0147] Among them, the first determination module is used to determine the target network routing rate, target average winding length and target via density of the circuit board based on the target routing data before inputting the routing data into the pre-built routing quality assessment model.

[0148] The second determination module is used to determine a first weight coefficient corresponding to the target network routing rate, a second weight coefficient corresponding to the target average winding length, and a third weight coefficient corresponding to the target via density based on the target network routing rate, the target average winding length, and the target via density.

[0149] The first construction module is used to construct a wiring quality evaluation model based on a target network routing rate, a target average winding length, a target via density, a first weight coefficient, a second weight coefficient, and a third weight coefficient.

[0150] Optionally, in one embodiment of the present application, the first acquisition module 100 includes: a first determination unit and a first acquisition unit.

[0151] The first determining unit is configured to determine the amount of the wiring data based on the monitoring weight, wherein the monitoring weight is positively correlated with the amount of data.

[0152] The first acquisition unit is used to obtain routing data including at least one of network routing rate, critical path delay, inter-layer via density and design rule violation number according to the data volume.

[0153] Optionally, in one embodiment of the present application, the first acquisition module 100 includes: a second determination unit, a second acquisition unit, and a calculation unit.

[0154] The second determining unit is configured to determine the actual complexity of the circuit board and the target complexity of the target circuit board based on the number of networks, the number of layers, and the component density of the circuit board.

[0155] The second acquiring unit is configured to acquire a high-speed signal ratio of the circuit board based on the circuit board.

[0156] The calculation unit is used to calculate the monitoring weight based on the actual complexity, the target complexity and the high-speed signal ratio.

[0157] Optionally, in one embodiment of the present application, it further includes: a judgment module, a first input module and a second input module.

[0158] The judgment module is used to judge whether the wiring data meets the preset data conditions before inputting the wiring data into the pre-built wiring quality assessment model.

[0159] The first input module is used to process the wiring data when the wiring data does not meet the preset data conditions until the wiring data meeting the preset data conditions is obtained, and allow the wiring data meeting the preset data conditions to be input into the pre-built wiring quality evaluation model.

[0160] The second input module is used to allow the wiring data to be input into a pre-built wiring quality evaluation model when the wiring data meets a preset data condition.

[0161] Optionally, in one embodiment of the present application, the generation module 400 includes: a third determination unit and a generation unit.

[0162] The third determining unit is configured to determine the suspending stage of the initial routing instruction based on instruction information of the suspending instruction.

[0163] The generating unit is used to generate the suspension data under different stage characteristics based on the multiple stage characteristics of the suspension stage.

[0164] Optionally, in one embodiment of the present application, the generating unit includes: a reducing subunit, a first generating subunit and a second generating subunit.

[0165] Among them, the lowering subunit is used to determine, based on the first stage characteristics among multiple stage characteristics, that when the termination stage is the first stage, the task level of at least one wiring task of the initial wiring instruction is lowered to a preset level to obtain termination data under the first stage characteristics.

[0166] The first generating subunit is used to determine, based on the second stage characteristics among the multiple stage characteristics, when the termination stage is the second stage, based on the wiring quality values ​​of different wiring tasks, to freeze the wiring tasks that meet the preset invalid conditions and release the wiring tasks that meet the preset valid conditions to form a final task, so as to obtain the termination data under the second stage characteristics.

[0167] The second generation unit is used to determine, based on the third stage characteristics of multiple stage characteristics, when the termination stage is the third stage, to generate at least one of a spatial distribution heat map, an unfinished network priority list, and a resource consumption statistics table to obtain termination data under the third stage characteristics.

[0168] Optionally, in one embodiment of the present application, it further includes: a second acquisition module, a second determination module and a second construction module.

[0169] Among them, the second acquisition module is used to obtain the historical suspension data of the circuit board before inputting the suspension data into the pre-built graph neural network model.

[0170] The second determination module is used to determine the structural information and training information of the graph neural network model based on historical suspension data.

[0171] The second construction module is used to train the graph neural network model based on structural information and training information using historical interruption data to construct a graph neural network model that meets preset training conditions.

[0172] Optionally, in one embodiment of the present application, the first acquisition module 100 includes: a third acquisition unit, a fourth determination unit and a fourth acquisition unit.

[0173] The third acquisition unit is used to acquire the wiring index of the wiring data based on the circuit board.

[0174] The fourth determining unit is configured to determine an update time of the wiring data based on the layer information of the circuit board.

[0175] The fourth acquiring unit is configured to update the wiring data based on the wiring index and the update time.

[0176] The description of the features in the embodiment corresponding to the circuit board wiring optimization device can be found in the relevant description of the embodiment corresponding to the circuit board wiring optimization method, and will not be repeated here.

[0177] According to the circuit board wiring optimization device proposed in the embodiment of the present application, the corresponding wiring data can be obtained based on different monitoring weights, and a pre-built wiring quality assessment model can be used to obtain a wiring quality value in response to the initial wiring instruction, and detect whether the wiring quality value is less than a certain quality threshold. When the wiring quality value is less than a certain quality threshold and the duration is greater than a certain time, a termination instruction is triggered to generate termination data, and then the pre-built graph neural network model is used to optimize the initial wiring instruction to obtain the final wiring instruction, and wiring is performed according to the final wiring instruction to obtain the wiring result. Therefore, it can solve the problems in the related technology that the wiring software cannot be terminated in time, repetitive work is prone to occur, resulting in low wiring efficiency and consuming a lot of manpower and time costs; improving the wiring density without involving a dynamic monitoring and termination mechanism of the wiring process; using arc fan-out signal line effects that rely on static rules and lack real-time quality assessment and other technical problems, so as to achieve the technical effects of improving wiring efficiency, shortening the wiring cycle, actively terminating inefficient paths, avoiding resource waste, reducing invalid calculations, improving wiring paths, reducing wiring costs, and optimizing resource allocation.

[0178] An embodiment of the present application further provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any of the above-mentioned circuit board wiring optimization method embodiments.

[0179] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above-mentioned circuit board wiring optimization method embodiments when run.

[0180] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0181] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any of the above-mentioned circuit board wiring optimization method embodiments are implemented.

[0182] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, it implements the steps in any of the above-mentioned circuit board wiring optimization method embodiments.

[0183] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0184] The above is a detailed introduction to a circuit board wiring optimization method provided by the present application. This article uses specific examples to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core ideas of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A method for optimizing circuit board wiring, characterized in that: The following steps are involved: Based on a monitoring weight of at least one circuit board layer in the circuit board, obtaining wiring data corresponding to the monitoring weight; Inputting the wiring data into a pre-built wiring quality assessment model to output a wiring quality value responsive to an initial wiring instruction; detecting whether the wiring quality value is less than a preset quality threshold, and if it is detected that the wiring quality value is less than the preset quality threshold, counting a duration during which the wiring quality value is less than the preset quality threshold, and determining whether the duration is greater than a preset duration; If the duration is greater than the preset time length, triggering a suspension instruction of the circuit board, and generating suspension data of the circuit board in response to the suspension instruction; The suspension data is input into a pre-built graph neural network model to optimize the initial wiring instructions using the pre-built graph neural network model to obtain the final wiring instructions of the circuit board, and the circuit board is wired according to the final wiring instructions to obtain the wiring result of the circuit board.

2. The method according to claim 1, characterized in that Before inputting the wiring data into a pre-built wiring quality assessment model, the method further includes: Determining a target network routing rate, a target average winding length, and a target via density of the circuit board based on the target routing data; Based on the target network routing rate, the target average winding length, and the target via density, determining a first weight coefficient corresponding to the target network routing rate, a second weight coefficient corresponding to the target average winding length, and a third weight coefficient corresponding to the target via density; The wiring quality assessment model is constructed based on the target network routing rate, the target average winding length, the target via density, the first weight coefficient, the second weight coefficient, and the third weight coefficient.

3. The method according to claim 1, characterized in that The acquiring, based on the monitoring weight of at least one circuit board layer in the circuit board, wiring data corresponding to the monitoring weight includes: Determining the amount of the wiring data based on the monitoring weight, wherein the monitoring weight is positively correlated with the amount of data; Routing data including at least one of a net routing rate, a critical path delay, an inter-layer via density, and a number of design rule violations is obtained according to the data amount.

4. The method according to claim 1, wherein The acquiring, based on the monitoring weight of at least one circuit board layer in the circuit board, wiring data corresponding to the monitoring weight includes: Determining an actual complexity of the circuit board and a target complexity of a target circuit board based on the number of nets, the number of layers, and the component density of the circuit board; Based on the circuit board, obtaining a high-speed signal ratio of the circuit board; The monitoring weight is calculated based on the actual complexity, the target complexity, and the high-speed signal ratio.

5. The method according to claim 1, wherein Before inputting the wiring data into a pre-built wiring quality assessment model, the method further includes: Determining whether the wiring data meets a preset data condition; If the wiring data does not satisfy the preset data condition, processing the wiring data until wiring data satisfying the preset data condition is obtained, and allowing the wiring data satisfying the preset data condition to be input into the pre-built wiring quality assessment model; If the wiring data satisfies the preset data condition, the wiring data is allowed to be input into the pre-built wiring quality assessment model.

6. The method according to claim 1, characterized in that The step of generating the suspension data of the circuit board in response to the suspension instruction comprises: determining a suspension stage of the initial routing instruction based on instruction information of the suspension instruction; Based on the multiple stage features of the suspension stage, suspension data under different stage features are generated.

7. The method according to claim 6, characterized in that The generating of the suspension data under different stage characteristics based on the multiple stage characteristics of the suspension stage includes: Based on a first stage feature among the multiple stage features, determining that, if the suspension stage is the first stage, the task level of at least one routing task of the initial routing instruction is reduced to a preset level, so as to obtain suspension data under the first stage feature; Based on a second stage feature among the multiple stage features, determining that, if the suspension stage is the second stage, based on routing quality values ​​of different routing tasks, routing tasks that meet a preset invalidation condition are frozen, and routing tasks that meet a preset validation condition are released to form a final task, so as to obtain suspension data under the second stage feature; Based on the third stage characteristics of the multiple stage characteristics, it is determined that when the termination stage is the third stage, at least one of a spatial distribution heat map, an unfinished network priority list and a resource consumption statistics table is generated to obtain the termination data under the third stage characteristics.

8. The method according to claim 1, characterized in that Before inputting the suspension data into the pre-built graph neural network model, the method further includes: Acquiring historical suspension data of the circuit board; Determining structural information and training information of the graph neural network model based on the historical suspension data; Based on the structural information and the training information, the graph neural network model is trained using the historical suspension data to construct a graph neural network model that meets preset training conditions.

9. The method according to claim 1, characterized in that The acquiring of the wiring data corresponding to the monitoring weight includes: Based on the circuit board, obtaining a wiring index of the wiring data; Determining an update time of the wiring data based on the board layer information of the circuit board; The wiring data is updated based on the wiring index and the update time.

10. An electronic device, characterized in that: include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the circuit board wiring optimization method according to any one of claims 1 to 9.

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