Low voltage column select driver for high density memory devices

Abstract

The invention relates to a low voltage column select driver for a high density memory device. A memory device includes a column decoder configured to decode a column address. The column decoder includes a column selection driver configured to modulate a column selection signal based on the column address to activate or deactivate a plurality of column selection circuits coupled to a column selection line. The column selection signal includes an activation pulse for activating the plurality of column selection circuits during an activation interval. The activation pulse includes a first portion having a positive boost signal level and a second portion having an activation signal level less than the positive boost signal level. The column selection driver is configured to generate the first portion of the activation pulse for a first duration of the activation interval and, after the first duration, generate the second portion of the activation pulse for a second duration of the activation interval.

Description

[0001] Cross-reference to related applications

[0002] This patent application claims priority to U.S. Provisional Patent Application No. 63 / 567,118, filed on March 19, 2024, entitled “LOW-VOLTAGE COLUMN SELECT DRIVER FOR HIGH-DENSITY MEMORY DEVICE,” and assigned to the assignee thereof. The disclosure of the prior application is considered part of and incorporated by reference into this patent application. Technical Field

[0003] The present disclosure relates generally to memory devices, memory device operations, and, for example, to low voltage column select drivers for high density memory devices. Background Art

[0004] Memory devices are widely used to store information in various electronic devices. Memory devices include memory cells. A memory cell is an electronic circuit that can be programmed into one of two or more data states. For example, a memory cell can be programmed into a data state representing a single binary value (typically represented by a binary "1" or a binary "0"). As another example, a memory cell can be programmed into a data state representing a fractional value (e.g., 0.5, 1.5, or the like). To store information, an electronic device can write to or program a group of memory cells. To access the stored information, the electronic device can read or sense the stored state from the group of memory cells.

[0005] There are various types of memory devices, including random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), static RAM (SRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), holographic RAM (HRAM), flash memory (such as NAND memory and NOR memory), and others. Memory devices can be volatile or non-volatile. Non-volatile memory (such as flash memory) can store data for a long time, even without an external power source. Volatile memory (such as DRAM) loses stored data over time unless the volatile memory is refreshed by a power source. Summary of the Invention

[0006] An embodiment of the present disclosure provides a memory device comprising: a memory bank comprising a memory array including data lines and a plurality of memory cells coupled to the data lines; a data input / output (I / O) line for transmitting read data from the data lines or transmitting write data to the data lines; a column select line configured to carry a column select signal across the full height of the memory bank; a plurality of column select circuits coupled to the column select lines, wherein the plurality of column select circuits are arranged along the length of the column select lines, and wherein the plurality of column select circuits are configured to connect or disconnect the data I / O lines and the data lines according to the column select signal; and a column decoder configured to decode a column address, wherein the column decoder comprises a column select driver configured to modulate the column select signal based on the column address so as to activate or deactivate the plurality of column select circuits, wherein the column select signal includes an activation pulse for activating the plurality of column select circuits during an activation interval, wherein the activation pulse includes a first portion having a positive boost signal level and a second portion having an activation signal level less than the positive boost signal level, and wherein the column select driver is configured to generate the first portion of the activation pulse during a first duration of the activation interval and to generate the second portion of the activation pulse during a second duration of the activation interval, the second duration of the activation interval being subsequent to the first duration of the activation interval.

[0007] Another embodiment of the present disclosure provides a memory device comprising: a column decoder configured to decode a column address, wherein the column decoder comprises a column select driver configured to modulate a column select signal based on the column address so as to activate or deactivate a plurality of column select circuits coupled to a column select line, wherein the column select signal comprises an activation pulse for activating the plurality of column select circuits during an activation interval, wherein the activation pulse comprises a first portion having a positive boost signal level and a second portion having an activation signal level less than the positive boost signal level, and wherein the column select driver is configured to generate the first portion of the activation pulse within a first duration of the activation interval and to generate the second portion of the activation pulse within a second duration of the activation interval, the second duration of the activation interval being subsequent to the first duration of the activation interval.

[0008] Yet another embodiment of the present disclosure provides a method for connecting and disconnecting data input / output (I / O) lines and bit lines of a memory device, the method comprising: decoding a column address to generate at least one control signal; and modulating a column select signal based on the at least one control signal so as to activate or deactivate a plurality of column select circuits coupled to the column select lines, wherein the plurality of column select circuits are configured to connect or disconnect the data I / O lines and the bit lines based on the at least one control signal, wherein modulating the column select signal comprises: generating an activation pulse for activating the plurality of column select circuits during an activation interval, wherein the activation pulse comprises a first portion having a positive boost signal level and a second portion having an activation signal level less than the positive boost signal level, and wherein generating the activation pulse comprises: generating the first portion of the activation pulse within a first duration of the activation interval and generating the second portion of the activation pulse within a second duration of the activation interval, the second duration of the activation interval being subsequent to the first duration of the activation interval. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a diagrammatic view of an example memory device.

[0010] Figure 2 Diagram showing memory circuitry.

[0011] Figure 3 A schematic diagram showing a column select (CS) driver according to one or more implementations is shown.

[0012] Figure 4 A timing diagram associated with generating column select signals according to one or more implementations is shown.

[0013] Figure 5 A voltage generator according to one or more implementations is shown.

[0014] Figure 6 A pulse duration adjuster according to one or more implementations is shown.

[0015] Figure 7 A driver circuit according to one or more implementations is shown.

[0016] Figure 8 A CS driver according to one or more implementations is shown.

[0017] Figure 9A A driver circuit according to one or more implementations is shown.

[0018] Figure 9B Signal diagrams are shown according to one or more implementations.

[0019] Figure 10 is a flow chart of an example method associated with a low voltage column select driver of a memory device. DETAILED DESCRIPTION

[0020] A transistor may be referred to as a logic switch or a transistor switch that can be used to complete a circuit connection. A transistor includes a first terminal (e.g., a source or emitter) and a second terminal (e.g., a drain or collector). In addition, the conduction path of the transistor can be controlled by a control electrode (sometimes referred to as a gate) connected to the control terminal of the transistor. The conduction path of the transistor is a gate-controlled conductive channel, the conductivity of which can be controlled by a control voltage applied to the control electrode of the transistor. For example, a transistor can be turned on or off by activating and deactivating its control electrode. For example, applying a positive voltage across the gate and source of a metal oxide semiconductor field effect transistor (MOSFET) will keep the MOSFET in its "on" state, while applying a voltage of approximately 0 or slightly negative across the gate and source of the MOSFET will cause the MOSFET to be "off."

[0021] There are turn-on and turn-off processes for turning the transistor on and off. During the turn-on process of an n-channel transistor, a gate driver can be used to provide (supply) a gate current (e.g., a turn-on current) to the gate of the n-channel transistor to charge the gate voltage to a sufficient voltage to turn the n-channel transistor on. Conversely, during the turn-off process of an n-channel transistor, the gate driver can be used to draw (sink) a gate current (e.g., a turn-off current) from the gate of the n-channel transistor to discharge the gate voltage sufficiently to turn the n-channel transistor off. A voltage pulse can be output from the gate driver as a control signal. Thus, the control signal can switch between a turn-on voltage level and a turn-off voltage level for controlling the n-channel transistor. This, in turn, charges and discharges the gate capacitance to correspondingly modulate the gate voltage to turn the n-channel transistor on and off, respectively.

[0022] The opposite is true for p-channel transistors. A gate driver can be used to draw (sink) a gate current (e.g., a turn-on current) from the gate of the p-channel transistor to discharge the gate voltage to a sufficient voltage to turn the p-channel transistor on. Conversely, during the turn-off process of the p-channel transistor, the gate driver can be used to provide (supply) a gate current (e.g., a turn-off current) to the gate of the p-channel transistor to charge the gate voltage of the p-channel transistor sufficiently to turn the p-channel transistor off. A control signal applied to the gate of the p-channel transistor can be switched between a turn-on voltage level and a turn-off voltage level to control the p-channel transistor. This, in turn, charges and discharges the gate voltage to turn the p-channel transistor on and off, respectively.

[0023] For both n-channel and p-channel transistors, the n-channel and p-channel transistors are turned off when the gate-source voltage Vgs is approximately 0 or below the threshold voltage, and the n-channel and p-channel transistors are turned on when the gate-source voltage Vgs is equal to or greater than the threshold voltage. For this reason, the gate-source voltage Vgs can be referred to as a control voltage.

[0024] The memory device may include a column decoder configured to drive a column select (CS) signal. The column select circuitry may be configured to perform data movement operations with respect to memory cells located in a particular column of the subarray, the complementary digit line associated with the particular column, and the shared input / output (I / O) line under the direction of the controller.

[0025] As DRAM density increases, the bank height of memory banks increases. Column select signals may be transmitted toward the far edge of the bank into the near edge of the bank to activate or deactivate multiple column select circuits coupled along column select lines (CSLs). The column select circuits may include transistors that are switched on and off based on the charging and discharging of gate capacitance, respectively. Due to the increased bank height, the column select driver may be unable to drive the column select signals from one rail potential to another (e.g., rail-to-rail) at the far edge of the bank. Furthermore, the charging and discharging times of the gate capacitance at the far edge of the bank may be slower than those at the near edge of the bank. Due to the signal propagation distance to the far edge of the bank, the increased losses associated with signal propagation distance, and the increased signal propagation time, the signal level (e.g., voltage level) of the column select signal at the far edge of the bank may not be sufficient to properly activate or deactivate one or more column select circuits located at the far edge of the bank. Consequently, data may not be properly written to or read from one or more memory cells located at the far edge of the bank during a column select operation.

[0026] Some embodiments provide a column decoder configured to drive column select signals, wherein all input levels are maintained at low voltage (LV) levels and the output of the CS driver has multiple-step voltage levels for achieving better rise and fall times at each column select circuit of the column select line. For example, the column decoder can drive each column select signal with two or more voltage steps during activation of the column select circuit and / or can drive each column select signal with two or more voltage steps during deactivation of the column select circuit. The column select signals can be generated at boosted voltage levels to shorten rise and fall times during activation and deactivation, respectively. As a result, column select circuits located at the far edge of a memory bank can reach turn-on and turn-off voltage levels more quickly, allowing data to be properly written to or read from one or more memory cells located at the far edge of the memory bank during a column select operation.

[0027] Some implementations provide a column decoder with a latched CS driver architecture for the LV column address (CA) signal.

[0028] Some embodiments provide a column decoder with an LV architecture that does not require a level shifter to be added to the CS pre-decoder.

[0029] Some implementations provide a column decoder with simple transmission gates having a single control bias voltage that can be used for the near-edge segment CS signal and can maintain a uniform CS pulse width in both the near and far edges of a segment of a memory bank.

[0030] Some implementations provide a column decoder with a reduced area compared to column decoders with a CS repeater-style architecture.

[0031] Some embodiments provide a column decoder with a single-sided CS driver that generates rail-to-rail CS pulses across all segments of a DRAM bank, eliminating the need for a double-sided CS driver or CS repeater with an additional edge segment in the center of the DRAM bank. A single-sided CS driver can be a single driver positioned at the near edge of the bank. In contrast, a double-sided CS driver can include one driver positioned at the near edge of the bank and another driver positioned at the far edge of the bank. A CS repeater can include additional repeater components arranged along the CSL. Both double-sided CS drivers and CS repeaters require larger chip area and higher manufacturing costs when compared to a single-sided CS driver without a CS repeater.

[0032] Figure 1is a diagrammatic view of an example memory device 100. Memory device 100 may include a memory array 102 comprising a plurality of memory cells 104. Memory array 102 may form a memory bank or may be part of a memory bank. In some implementations, memory device 100 may include a plurality of memory banks, each formed by a respective memory array 102. Memory cells 104 are programmable or configurable to a data state from a plurality of data states (e.g., two or more data states). For example, memory cell 104 may be set to a particular data state at a particular time, and memory cell 104 may be set to another data state at another time. The data state may correspond to a value stored by memory cell 104. The value may be a binary value (e.g., binary 0 or binary 1) or may be a fractional value (e.g., 0.5, 1.5, or the like). Memory cell 104 may include a capacitor for storing charge representing a data state. For example, a charged and uncharged capacitor may represent a first data state and a second data state, respectively. As another example, a first charge level (eg, fully charged) may represent a first data state, a second charge level (eg, fully discharged) may represent a second data state, a third charge level (eg, partially charged) may represent a third data state, and so on.

[0033] Operations such as reading and writing (i.e., cycling) may be performed on the memory cells 104 by activating or selecting the appropriate access lines 106 (shown as access lines AL-1 through AL-M) and digit lines 108 (shown as digit lines DL-1 through DL-N). Access lines 106 may also be referred to as "row lines" or "word lines," and digit lines 108 may also be referred to as "column lines" or "bit lines." Activating or selecting an access line 106 or a digit line 108 may include applying a voltage to the respective line. Access lines 106 and / or digit lines 108 may comprise, consist of, or consist essentially of a conductive material, such as a metal (e.g., copper, aluminum, gold, titanium, or tungsten) and / or a metal alloy, among other examples. In Figure 1 , each row of memory cells 104 is connected to a single access line 106, and each column of memory cells 104 is connected to a single digit line 108. By activating one access line 106 and one digit line 108 (e.g., applying a voltage to the access line 106 and the digit line 108), a single memory cell 104 can be accessed at (e.g., accessible through) the intersection of the access line 106 and the digit line 108. The intersection of the access line 106 and the digit line 108 can be referred to as the “address” of the memory cell 104.

[0034] In some implementations, the logical storage device (e.g., cell capacitor) of a memory cell 104 can be electrically isolated from the corresponding digit line 108 by a selection component (e.g., a cell transistor). An access line 106 can be connected to the selection component and can control the selection component. For example, the selection component can be a cell transistor, and the access line 106 can be connected to the gate of the cell transistor. Activating the access line 106 results in an electrical connection or closed circuit between the capacitor of the memory cell 104 and the corresponding digit line 108. The digit line 108 can then be accessed (e.g., accessible) to read from or write to the memory cell 104. In some implementations, the memory cell 104 can be a DRAM memory cell.

[0035] The row decoder 110 and the column decoder 112 may control access to the memory cells 104. Therefore, the row decoder 110 and the column decoder 112 may each include control logic for generating control signals based on a received row address or a received column address, respectively. For example, the row decoder 110 may receive a row address RADD from the memory controller 114 and may activate the appropriate access lines 106 based on the received row address RADD. For example, the row decoder 110 may enable one or more access lines 106 (e.g., word lines) based on the result obtained by decoding the row address RADD. The memory controller 114 may be part of a host device. The host device may be an external processor, such as a microprocessor. Similarly, the column decoder 112 may receive a column address CADD from the memory controller 114 and may activate the appropriate digital lines 108 based on the column address CADD. The column decoder 112 may activate one or more column select circuits via one or more column select lines (CSL). Therefore, the column decoder 112 may include a plurality of column select (CS) drivers, each of which is configured to drive a corresponding CSL. The column decoder 112 may be arranged at one side of the memory array 102 (e.g., on one side of a memory bank). The column decoder 112 may decode the column address CADD and may output a column select signal CSS to the memory array 102 based on the decoding result.

[0036] After accessing memory cell 104, memory cell 104 may be read (e.g., sensed) by sensing component 116 to determine the stored data state of memory cell 104. For example, after accessing memory cell 104, the capacitor of memory cell 104 may be discharged onto its corresponding digit line 108. Discharging the capacitor may be based on biasing the capacitor or applying a voltage to the capacitor. The discharge may induce a voltage change on digit line 108, which sensing component 116 may compare to a reference voltage (not shown) to determine the stored data state of memory cell 104. For example, if digit line 108 has a voltage higher than the reference voltage, sensing component 116 may determine that the stored data state of memory cell 104 corresponds to a first value, such as a binary 1. Conversely, if digit line 108 has a voltage lower than the reference voltage, sensing component 116 may determine that the stored data state of memory cell 104 corresponds to a second value, such as a binary 0. The detected data state of the memory cell 104 may then be output to an output component 118 (e.g., a data buffer) (e.g., via a column decoder 112). A memory cell 104 may be written (e.g., set) by activating the appropriate access line 106 and digit line 108. The column decoder 112 may receive data to be written to one or more memory cells 104 (e.g., as input from an input component 120). A memory cell 104 may be written by applying a voltage across its capacitor.

[0037] Output components 118 and input components 120 may form a data input / output (I / O) circuit 122 that may output data DQ from the memory array 102 to an external processor during a read operation or may input data DQ from an external processor to the memory array 102 during a write operation. The data I / O circuit 122 may be arranged adjacent to the column decoder 112 for fast access to the column decoder 112.

[0038] The memory controller 114 may control the operation (e.g., reading, writing, rewriting, refreshing, and / or restoring) of the memory cells 104 via the row decoder 110, the column decoder 112, and / or the sensing component 116. The memory controller 114 may generate row and column address signals to activate the desired access lines 106 and digit lines 108. The memory controller 114 may also generate and control various voltages used during operation of the memory array 102.

[0039] As instructed above, Figure 1 For illustration only. Other examples may vary from the Figure 1 The content of the description.

[0040] Figure 2 FIG2 shows a diagram of a memory circuit 200. The memory circuit 200 may be implemented in conjunction with Figure 1Memory device 100 is depicted. Memory circuit 200 may include a memory bank 202 including memory array 102 and a plurality of column select circuits CSEL1 and CSELM.

[0041] The memory array 102 may include a plurality of access lines AL and a plurality of data lines DL. Figure 2 Two access lines AL1 and ALM and one data line DL are illustrated. Access line AL1 can be located in the lower region of memory array 102, or at the near side CSnr of column select line CSL, and access line ALM can be located in the upper region of memory array 102, or at the far side Csfar of column select line CSL. Column select line CSL can extend from column decoder 112 (e.g., from a column select driver) arranged near the near side of memory bank 202 to the far side of memory bank 202.

[0042] Memory array 102 may include a plurality of memory cells MC1 and MCM arranged at respective intersections between a plurality of access lines AL1 and ALM and a plurality of data lines DL. Memory cell MC1 may be coupled to access line AL1 and data line DL, and memory cell MCM may be coupled to access line ALM and data line DL. Memory cell MC1 may include a first cell transistor and a first cell capacitor. Memory cell MCM may include a second cell transistor and a second cell capacitor. Thus, each memory cell 104 may include a cell transistor (or another type of selection circuit) and a cell capacitor.

[0043] The memory cell 104 can be accessed (e.g., written to, read from, and / or erased) using signals on a combination of lines coupled to the memory cell 104, which are shown as a corresponding access line and a corresponding digit line. A cell transistor (sometimes referred to as an access transistor) can include a gate coupled to a corresponding access line. A cell capacitor includes two electrodes separated by an insulator. In some implementations, the capacitor is a ferroelectric capacitor and the insulator is a ferroelectric insulator comprising, consisting of, or consisting essentially of a ferroelectric material. Alternatively, the capacitor can be a linear dielectric capacitor and the insulator can be a linear dielectric insulator comprising, consisting of, or consisting essentially of a linear dielectric material. Alternatively, the cell capacitor can be a paraelectric capacitor and the insulator can be a paraelectric insulator comprising, consisting of, or consisting essentially of a paraelectric material. When the access line is activated (e.g., when a voltage is applied to the access line), the gate of the cell transistor coupled to the access line can be activated. When the gate of the cell transistor is activated, the cell transistor couples the digit line to the cell capacitor.The state of the memory cell 104 can then be written or read via the digit line.

[0044] To write to (or program) memory cell 104, a corresponding access line may be activated, and a voltage may be applied across the cell capacitor by controlling the voltage applied to the cell capacitor through a corresponding digit line.

[0045] In some implementations, data can be stored using a cell capacitor by controlling a voltage difference and / or polarity difference across the cell capacitor (e.g., an insulator between two electrodes). For a linear dielectric capacitor or a paraelectric capacitor, the electrode insulated from the cell transistor can be grounded, and the cell capacitor can be charged by applying a voltage to the electrode coupled to the cell transistor via a digit line.

[0046] To read a memory cell 104 (e.g., the state stored by the cell capacitor), an access line may be activated and a voltage may be sensed from the data line. The magnitude of the change in stored charge may depend on the storage state of the cell capacitor (e.g., whether the storage state is a logic "1" state or a logic "0" state). This may or may not induce a threshold change in the voltage of the digit line based on the charge stored on the cell capacitor. The voltage change or lack thereof (or the magnitude of the voltage change) on the digit line may be used to determine the storage state of the cell capacitor. For example, if the voltage change meets the threshold, the read operation indicates that a first state is stored in the cell capacitor, while if the voltage change does not meet the threshold, the read operation determines that a second state is stored in the cell capacitor. In some cases, multiple threshold voltages may be used, such as when the capacitor is capable of storing more than two data states (e.g., for multi-level cells, triple-level cells, etc.).

[0047] Column select circuits CSEL1 and CSELM may correspond to memory cells MC1 and MCM, respectively. Depending on the height of memory bank 202, additional column select circuits may be provided. For example, additional column select circuits may be provided between column select circuits CSEL1 and CSELM. In other words, the number of column select circuits may depend on the length of column select line CSL. Thus, column select line CSL may have a length corresponding to the height of memory bank 202. In some implementations, a column select circuit may be provided for each memory cell.

[0048] Column select circuit CSEL1 can transmit data from data line DL to data I / O line LIO in response to a column select signal CSS. The data can correspond to data stored in memory cell MC1. Column select circuit CSEL1 can include a select transistor T1. Select transistor T1 can be coupled between data line DL and data I / O line LIO and can receive the column select signal CSS at its gate terminal.

[0049] Column select circuit CSELM can transfer data from bit line DL to data I / O line LIO in response to column select signal CSS. The data can correspond to data stored in memory cell MCM. Column select circuit CSELM can include select transistor TM. Select transistor TM can be coupled between data line DL and data I / O line LIO and can receive column select signal CSS via a gate terminal. Column select signal CSS can be applied via column select line CSL. Thus, column select line CSL can be coupled to the gate terminal of each select transistor, and select transistors are coupled to data line DL. In some embodiments, when multiple data lines DL are provided, column select line CSL can be coupled to each of the data lines DL via a corresponding column select circuit.

[0050] Column select circuits CSEL1 and CSEL2 can operate simultaneously based on a column select signal CSS transmitted on column select line CSL. In other words, column select signal CSS can be used to activate or deactivate both column select circuits CSEL1 and CSEL2. Thus, multiple column select circuits can be arranged along the length of column select line CSL, and the multiple column select circuits can be configured to connect or disconnect data I / O line LIO and data line DL based on column select signal CSS. For example, when column select circuits CSEL1 and CSEL2 are operated by column select signal CSS, data from memory cells MC1 and MCM can be transmitted to data I / O line LIO via data line DL. Data DQ transmitted to data I / O line LIO can be output via data I / O circuit 122.

[0051] When the data line DL is selected for a read operation by the column decoder 112, the select transistors T1 and TM may be turned on according to the column select signal CSS to transmit the voltage of the data line DL to the data I / O line LIO. The data I / O circuit 122 may output the data DQ applied from the data I / O line LIO to an external processor. Therefore, the CS driver of the column decoder 112 may be a gate driver for activating and deactivating the column select circuits CSEL1 and CSEL2 by turning on or off the select transistors T1 and TM, respectively.

[0052] When the data line DL is selected for a write operation by the column decoder 112, the select transistors T1 and TM can be turned on according to the column select signal CSS to transmit the voltage of the data I / O line LIO to the data line DL. At this time, any cell transistor that is turned on can enable its corresponding cell capacitor to be charged or discharged based on the voltage of the data I / O line LIO.

[0053] As instructed above, Figure 2 For illustration only. Other examples may vary from the Figure 2 The content of the description.

[0054] Figure 3 A schematic diagram of a CS driver 300 according to one or more implementations is shown. The CS driver 300 may include a first inverter 302 and a second inverter 304 coupled in series. The first inverter 302 may be configured to receive a control signal CA4 corresponding to a column address CADD. For example, the column decoder 112 ( Figure 3 The column address CADD may be decoded by a processor (not shown) and one or more control signals (e.g., control signals CA456, CA78, and CA9) may be generated or otherwise obtained based on the decoding of the column address CADD. The control signal CA4 may correspond to a portion of the control signal CA456, such as a specific bit of the control signal CA456.

[0055] The CS driver 300 may also include a NAND gate 306 coupled to the negative power supply terminal of the first inverter 302. The NAND gate 306 may be configured to enable the first inverter 302 when both inputs to the NAND gate 306 are at a logic 1 value. When both inputs to the NAND gate 306 are at a logic 1 value, the output of the NAND gate 306 is a logic 0 value, and the negative power supply terminal of the first inverter 302 is properly grounded at ground potential. When neither input to the NAND gate 306 is at a logic 1 value, the output of the NAND gate 306 is a logic 1 value, and the negative power supply terminal of the first inverter 302 is not properly grounded. Therefore, control signals CA78 and CA9 may be used as inputs to the NAND gate 306 to enable or disable the first inverter 302 and, therefore, the CS driver 300. The first inverter 302 may generate a first inverted signal CA4b based on the control signal CA4.

[0056] The second inverter 304 has a first power supply terminal 308 (e.g., a positive power supply terminal) and a second power supply terminal 310 (e.g., a negative power supply terminal). The second inverter 304 can be coupled to the output of the first inverter 302 and configured to generate a column select signal CS4 (e.g., a second inverted signal) corresponding to the control signal CA4 based on a first supply potential (e.g., V1 or V2) coupled to the first power supply terminal 308 and a second supply potential (e.g., V3 or V4) coupled to the second power supply terminal 310. For example, the first supply potential defines a logic-one value for the output voltage of the second inverter 304, and the second supply potential defines a logic-zero value for the output voltage of the second inverter 304. For example, the logic-one value for the output voltage of the second inverter 304 would be V1 when V1 is connected to the first power supply terminal 308 and would be V2 when V2 is connected to the first power supply terminal 308. The logic-zero value of the output voltage of the second inverter 304 will be V3 when V3 is connected to the second power supply terminal 310 and will be V4 when V4 is connected to the second power supply terminal 310 .

[0057] In the examples described herein, V1 may correspond to an activation signal level, V2 may correspond to a positive boost signal level, V3 may correspond to a negative boost signal level, and V4 may correspond to a deactivation signal level. Activation signal level V1 may be less than positive boost signal level V2. For example, activation signal level V1 may be 1V and positive boost signal level V2 may be 2V. Additionally, deactivation signal level V4 may be greater than negative boost signal level V3. For example, deactivation signal level V4 may be 0V (e.g., ground potential) and negative boost signal level V3 may be a negative voltage (e.g., -1V). Activation signal level V1 may be equal to or greater than the threshold voltage of each column select circuit, and deactivation signal level V4 may be less than the threshold voltage of each column select circuit. For example, for an implementation in which multiple column select circuits CSEL1 and CSEL2 are transistors, activation signal level V1 may be equal to or greater than the threshold voltage of each transistor, and deactivation signal level V4 may be less than the threshold voltage.

[0058] The CS driver 300 may include a first switch VG1 coupled between a first voltage source corresponding to an activation signal level V1 and a first power supply terminal 308; a second switch VG2 coupled between a second voltage source corresponding to a positive boost signal level V2 and the first power supply terminal 308; a third switch VG3 coupled between a third voltage source corresponding to a negative boost signal level V3 and a second power supply terminal 310; and a fourth switch VG4 coupled between a fourth voltage source corresponding to a deactivation signal level V4 and the second power supply terminal 310. The column decoder 112 may include control logic for controlling the first, second, third, and fourth switches VG1, VG2, VG3, and VG4 based on a column address CADD to generate a column select signal CS4 having an activation pulse and / or a deactivation pulse. For example, the column decoder 112 may control the first and second switches VG1 and VG2 based on the column address CA4 to generate an activation pulse. The column decoder 112 may control the third switch VG3 and the fourth switch VG4 to generate a deactivation pulse based on the column address CA4 .

[0059] The CS driver 300, and in particular the second inverter 304, can modulate the column select signal CS4 based on the control signal CA4 derived from the column address CADD to activate or deactivate the plurality of column select circuits CSEL1 and CSEL2. The column select signal CS4 can include an activation pulse for activating the plurality of column select circuits during an activation interval. Furthermore, the activation pulse can include a first portion having a positive boosted signal level V2 and a second portion having an activation signal level V1 that is less than the positive boosted signal level V2. The CS driver 300, and in particular the second inverter 304, can generate the first portion of the activation pulse during a first duration of the activation interval and can generate the second portion of the activation pulse during a second duration of the activation interval. The second duration of the activation interval can be later than the first duration of the activation interval.

[0060] Thus, the activation pulse may initially have a higher voltage level during the first portion of the activation pulse to more quickly charge the gate capacitance of the column select circuits located at the far edge of the memory bank with the positive boost signal level V2. Applying the positive boost signal level V2 during the first portion of the activation pulse may improve the rise time of the activation pulse at the far edge of the memory bank. In other words, the rise time of the gate voltage of the column select circuits located at the far edge of the memory bank may be shortened more than would otherwise be possible without the positive boost signal level V2, such that the gate capacitance charges faster and the gate voltage is able to reach a threshold voltage within an appropriate time frame for activating (turning on) all column select circuits coupled to the column select line CSL. For example, applying the positive boost signal level V2 allows the gate voltage of the column select circuits to reach the activation signal level V1 more quickly.

[0061] The first duration of the positive boost signal level V2 is long enough to allow the gate voltage of the column select circuit to increase sufficiently for turning on (e.g., the gate capacitance is sufficiently charged for turning on). However, if the activation pulse is maintained at the positive boost signal level V2 for the entire duration of the activation pulse, the fall time for deactivating the column select circuit will be reduced and deactivation may not be properly achieved. Therefore, the activation pulse can be reduced to the activation signal level V1 during the second duration of the activation pulse. The activation signal level V1 is sufficient to maintain the column select circuit in an activated state for the remainder of the activation period.

[0062] Additionally or alternatively, the CS driver 300 is configured to deactivate the plurality of column select circuits during a deactivation interval. The column select signal CS4 may include a deactivation pulse for deactivating the plurality of column select circuits during the deactivation interval. For example, the CS driver 300, and in particular the second inverter 304, may generate the deactivation pulse at a negative boosted signal level V3 during a first duration of the deactivation interval and maintain the column select signal CS4 at a deactivation signal level V4 greater than the negative boosted signal level V3 during a second duration of the deactivation interval. The second duration of the deactivation interval may be subsequent to the first duration of the deactivation interval.

[0063] Thus, the deactivation pulse may initially have a lower (negative) voltage level during the first portion of the deactivation pulse to more quickly discharge the gate capacitance of the column selection circuits positioned at the far edge of the memory bank with the negative boost signal level V3. Applying the negative boost signal level V3 during the first portion of the deactivation pulse may improve the fall time of the deactivation pulse at the far edge of the memory bank. In other words, the fall time of the gate voltage of the column selection circuits positioned at the far edge of the memory bank may be shortened more than would otherwise be possible without the negative boost signal level V3, such that the gate capacitance is discharged more quickly and the gate voltage is able to reach the cut-off threshold voltage within an appropriate time frame for deactivating (cutting off) all column selection circuits coupled to the column select line CSL. For example, applying the negative boost signal level V3 allows the gate voltage of the column selection circuit to reach the deactivation signal level V4 more quickly.

[0064] The first duration of the negative boost signal level V3 is long enough to allow the gate voltage of the column select circuit to decrease sufficiently for shutoff (e.g., the gate capacitance is sufficiently discharged for shutoff). However, if the deactivation pulse is maintained at the negative boost signal level V3 for the entire duration of the deactivation pulse, the rise time for activating the column select circuit will be reduced and activation may not be properly achieved. Therefore, the deactivation pulse may be increased to the deactivation signal level V4 for the second duration of the deactivation pulse. The deactivation signal level V4 is sufficient to maintain the column select circuit in the deactivated state for the remainder of the deactivation period.

[0065] In some implementations, the first duration T1 of the activation interval 401 and the first duration T1 ′ of the deactivation interval 402 are variable and can depend on the location of the column select line CSL within the memory bank.

[0066] In some implementations, the first difference between the positive boosting signal level V2 and the activation signal level V1 is variable and may depend on the location of the column select line CSL within the memory bank.

[0067] In some implementations, the second difference between the negative boost signal level V3 and the deactivation signal level V4 is variable and may depend on the location of the column select line CSL within the memory bank.

[0068] As instructed above, Figure 3 For illustration only. Other examples may vary from the Figure 3 The content of the description.

[0069] Figure 4 A timing diagram 400 associated with generating a column select signal is shown according to one or more implementations.

[0070] Timing diagram 400 shows an activation interval 401 during which all column select circuits coupled to column select line CSL are activated, and a deactivation interval during which all column select circuits coupled to column select line CSL are deactivated. Activation interval 401 includes a first duration T1 and a second duration T2. ​​During first duration T1, a positive boosted signal level V2 is applied by column select signal CS4 by closing second switch VG2 and opening first switch VG1. During second duration T2, an activation signal level V1 is applied by column select signal CS4 by closing first switch VG1 and opening second switch VG2.

[0071] The deactivation interval 402 includes a first duration T1′ and a second duration T2′. The second duration T2′ may be the remaining duration of the deactivation interval 402 until the next activation interval is triggered. The negative boost signal level V3 is applied by the column select signal CS4 during the first duration T1′ by closing the third switch VG3 and opening the fourth switch VG4. The deactivation signal level V4 is applied by the column select signal CS4 during the second duration T2′ by closing the fourth switch VG4 and opening the third switch VG3.

[0072] In this example, inverter delays are ignored. The first and second switches VG1 and VG2 can be PMOS switches. Therefore, the second switch VG2 can be turned on when its control signal goes low. Similarly, the first switch VG1 can be turned on when its control signal goes low. The third and fourth switches VG3 and VG4 can be NMOS switches. Therefore, the third switch VG3 can be turned on when its control signal goes high. Similarly, the fourth switch VG4 can be turned on when its control signal goes high. However, the control scheme can be modified based on the doping type of the switches.

[0073] Column select signal CS4 has different pulse patterns at the near edge of the bank and at the far edge of the bank. The pulse pattern at the near edge of the bank has a staircase pattern of rising and falling edges. The pulse pattern at the far edge of the bank has a smoother transition of rising and falling edges. Column select signal CS4 can reach the activation signal level V1 at the far edge of the bank due to the positive boost signal level V2 being applied during the first duration T1 of the activation interval 401. Additionally, column select signal CS4 can reach the deactivation signal level V4 at the far edge of the bank due to the negative boost signal level V3 being applied during the first duration T1′ of the deactivation interval 402.

[0074] As instructed above, Figure 4 For illustration only. Other examples may vary from the Figure 4 The content of the description.

[0075] Figure 5 A voltage generator 500 according to one or more implementations is shown. The voltage generator 500 can be configured to generate a positive boost signal level V2 and a negative boost signal level V3 based on the segment of the memory bank controlled by the column select driver. Thus, because the voltage generator 500 is capable of varying the positive boost signal level V2, the first difference between the positive boost signal level V2 and the activation signal level V1 can be adjusted. Furthermore, because the voltage generator 500 is capable of varying the negative boost signal level V3, the second difference between the negative boost signal level V3 and the deactivation signal level V4 can be adjusted.

[0076] Voltage generator 500 may include a first voltage divider 501 having multiple taps and a multiplexer 502 connected to the multiple taps as a reference input (e.g., a reference voltage). Multiplexer 502 may also have a control input for receiving a segment control signal. The segment control signal may be a row address or a segment control bit (e.g., a portion of a column address). Multiplexer 502 may select one of the reference inputs for output as reference voltage REF.

[0077] The voltage generator 500 may also include a first differential component 503 and a second differential component 504. The first differential component 503 and the second differential component 504 may be differential comparators, such as differential amplifiers. The voltage generator 500 may also include an oscillator 505, a negative charge pump 506, a transistor 507, a second voltage divider 508 having a first variable resistor, and a third voltage divider 509 having a second variable resistor. The resistance values ​​set for the first variable resistor and the second variable resistor may be configured based on a row address. The voltage generator 500 may generate a positive boosted signal level V2 and a negative boosted signal level V3 based on a reference voltage REF selected by the multiplexer 502, based on the segment control signal, and based on the resistance values ​​set for the first variable resistor and the second variable resistor.

[0078] As instructed above, Figure 5 For illustration only. Other examples may vary from the Figure 5 The content of the description.

[0079] Figure 6 A pulse duration adjuster 600 is shown according to one or more implementations. The pulse duration adjuster 600 can be configured to adjust a first duration T1 of an activation interval and a first duration T1 ' of a deactivation interval based on a sector of a memory bank controlled by a column select driver.

[0080] The pulse duration adjuster 600 may include an OR gate 601 that receives a control signal CA456, a first delay element 602 that also receives the control signal CA456, a second delay element 603, a first level shifter 604, and a second level shifter 605. The first and second delay elements 602 and 603 may adjust the variable delay based on a segment control signal. The segment control signal may be a row address or a segment control bit (e.g., a portion of a column address). The first level shifter 604 may generate control signals for the first and second switches VG1 and VG2. Based on the segment control signal, the first duration T1 may be adjusted based on the delay imposed by the second delay element 603. The second level shifter 605 may generate control signals for the third and fourth switches VG3 and VG4. Based on the segment control signal, the first duration T1′ may be adjusted based on the delay imposed by the first delay element 602.

[0081] As instructed above, Figure 6 For illustration only. Other examples may vary from the Figure 6 The content of the description.

[0082] Figure 7A driver circuit 700 according to one or more implementations is shown. The driver circuit 700 includes a plurality of CS drivers 701 coupled to respective column select lines CSL. The plurality of CS drivers 701 may be similar to the CS driver 300, except that the third switch VG3 and the fourth switch VG4 are not provided to improve the fall time of the column select signal. Instead, the driver circuit 700 may include a column select ground line CSfarGnd having a ground potential and a plurality of pull-down transistors 702 coupled to the column select ground line CSfarGnd. Each pull-down transistor 702 is connected to the remote end of a respective column select line CSL. The column decoder 112 may generate a pull-down control signal and apply the pull-down control signal to the column select ground line CSfarGnd to control the on / off state of the pull-down transistor 702. The pull-down transistor 702 can be activated (turned on) to improve the fall time of the column select signal at the remote end of the column select line CSL without using the third switch VG3 (e.g., without using a negative supply voltage). The pull-down transistor 702 can be activated, for example, during a first duration T1′ of the deactivation interval to improve the fall time of the column select signal at the far end of the column select line CSL. The pull-down transistor 702 can be deactivated (turned off), for example, during a second duration T2′ of the deactivation interval and during the entire duration of the activation interval.

[0083] The use of a column select ground line CSfarGnd and multiple pull-down transistors 702 can improve the reliability of the CS driver and save chip area that would otherwise be used to accommodate a negative voltage generator (e.g., a negative charge pump). Furthermore, pull-down control of multiple column select lines CSL can be simplified using a single control signal CSfarGnd, instead of individually controlling the corresponding third switch VG3 and fourth switch VG4 of each CS driver. Therefore, by controlling the timing of the pull-down control signal applied to the column select ground line CSfarGnd, the fall time of all column select signals can be controlled.

[0084] In this example, column decoder 112 may be configured to switch control signals CA456, CA78, and CA9 between a positive boosted signal level V2 (e.g., 2 V) and a ground potential (e.g., 0 V) ​​based on column address CADD. Therefore, a pre-decoder of column decoder 112 may include a level shifter to drive control signals CA456, CA78, and CA9 to the positive boosted signal level V2.

[0085] Additionally, the first inverter of each CS driver 701 may include a first pair of high-voltage transistors capable of handling the activation signal level V2, and the second inverter of each CS driver 701 may include a second pair of high-voltage transistors capable of handling the activation signal level V2.

[0086] Since the CS driver 701 is a latch type, it is connected to the corresponding CA456b <0> The LV PMOS transistor 703 at the node turns the voltage level high. This makes the CS <0> A node (eg, CCS) goes low.

[0087] The NAND gate output GENb0 of the first NAND gate 306 controls a first group of eight CS drivers. The NAND gate output GENb1 of the second NAND gate 306 controls a second group of eight CS drivers. When either GENb0 or GENb1 is high, only one of the CS drivers in this group generates a CS pulse in response to the CA control inputs (CA456<7:0>). bCA456OR is complementary to CA456OR, going high when each of CA456<7:0> goes high. CSnrGnd0 goes low each time bCA456OR goes high, pulling down the CS signal CSS and improving the fall time of the CS signal CSS.

[0088] As instructed above, Figure 7 For illustration only. Other examples may vary from the Figure 7 The content of the description.

[0089] Figure 8 A CS driver 800 is shown according to one or more implementations. The CS driver 800 is configured to Figure 7 Column select lines are driven in a similar manner as described above. However, column decoder 112 can be configured to switch control signals CA456, CA78, and CA9 between an activation signal level V1 (e.g., 1V) and a ground potential (e.g., a deactivation signal level V4 or 0V) based on the column address. In other words, a 1V control input can be provided to the CS driver instead of a 2V control input. Thus, no level shifter is required to drive control signals CA456, CA78, and CA9 because the input control does not exceed the activation signal level V1.

[0090] The first inverter 302 may include a high voltage PMOS transistor 801 and a low voltage NMOS transistor 802. The second inverter 304 may include a pair of low voltage transistors 803 and 804 and an nbias transistor 805. The nbias transistor 805 limits or clamps the voltage from CA456b. <0> The voltage received and this limited voltage is sent from CA456b <0> is passed to the gate of the low voltage transistor 804. Therefore, the nbias transistor 805 can limit the gate voltage of the low voltage transistor 804 and can protect the low voltage transistor 804 from reliability issues.

[0091] Therefore, the three inverter transistors (e.g., transistors 802, 803, and 804) can be designed as low-voltage transistors because the control signal CA456 is a low-voltage signal (e.g., a 1V signal). The control electrode of the high-voltage PMOS transistor 801 can be coupled to the output of the second inverter 304 (e.g., the column select line CSL). Transistor 801 is a high-voltage transistor because the column select signal is coupled to the control electrode of the high-voltage PMOS transistor 801 and is periodically driven to a positive boost signal level V2 (e.g., 2V).

[0092] Control signal CA456OR_1V is provided to a series of inverters 806 and 807 to generate control signal CSnrGnd. Whenever one of CA456<7:0> goes high, control signal CA456OR_1V goes high. CSnrGnd goes low each time CA456OR_1V goes low and pulls down CS signal CSS, improving the fall time of CS signal CSS.

[0093] Only when the control signal CA78 <0> 、CA9 <0> When both become high, the CS driver responds to CA456 <0> Input. When the control signal CA456 <0> When going high, the low voltage NMOS transistor 802 behaves like a strong NMOS transistor compared to the high voltage PMOS transistor 801 because it is a LV transistor.

[0094] Since CS driver 800 is a latch type, it is connected to CA456b <0> The LV PMOS transistor 703 at the node turns the voltage level high. This makes the CS <0> Node goes low. When the control signal CA456 <0> When starting to rise high, the strong LV NMOS 802 of the first stage inverter 302 pulls down quickly first compared to the pull up of the weak HVPMOS transistor 801 .

[0095] CSfarGnd helps improve the fall time of the CS pulse by discharging the far side of the CS line CSL, and CSnrGnd helps improve the fall time of the CS pulse and discharge the near CS line by quickly turning on the NMOS pull-down transistor 804 of the last stage inverter 304. The first and second switches VG1 and VG2 are used to create a boosted voltage level during the first period of the CA high pulse.

[0096] As instructed above, Figure 8 For illustration only. Other examples may vary from the Figure 8 The content of the description.

[0097] Figure 9A A driver circuit 900A according to one or more implementations is shown. The driver circuit 900A may include a column select ground line CSfarGnd and a plurality of pull-down transistors 702, such as in combination with Figure 7Similarly described. In addition, the driver circuit 900A may include a plurality of CS drivers 901 coupled to corresponding column select lines CSL. The CS drivers 901 may have Figure 8 A similar configuration is described for the CS driver 800 .

[0098] Driver circuit 900A may include a column select bias line CSbias and a plurality of bias transistors 902 connected to column select bias line CSbias. Each bias transistor 902 is connected to the proximal end of a corresponding column select line CSL. Column decoder 112 may generate a bias control signal and apply the bias control signal to column select bias line CSbias to control the on / off state of bias transistor 902. Bias transistor 902 may be activated (turned on) to shape the column select signal so that the pulse shape of the column select signal at the proximal end of column select line CSL is similar to the pulse shape of the column select signal at the distal end of column select line CSL. In other words, each bias transistor 902 may be controlled to generate a column select signal that is uniform across the length of column select line CSL.

[0099] As instructed above, Figure 9A For illustration only. Other examples may vary from the Figure 9A The content of the description.

[0100] Figure 9B A signal diagram 900B is shown according to one or more embodiments. Signal diagram 900B shows the bias control signal applied to column select bias line CSbias and column select signal CSS. The pulse shape of column select signal CSS at the near end of column select line CSL is similar to the pulse shape of column select signal CSS at the far end of column select line CSL. Thus, controlling bias transistor 902 achieves uniform CS pulses in both near and far edge segments of the memory bank. Alternatively, a weak driver can be used in the near edge segment to achieve uniform CS pulses in both near and far edge segments of the memory bank.

[0101] As instructed above, Figure 9B For illustration only. Other examples may vary from the Figure 9B The content of the description.

[0102] Figure 101 is a flow chart of an example method 1000 associated with a low-voltage column select driver for a memory device. For example, method 1000 can be a method for connecting and disconnecting data I / O lines and bit lines of a memory device. In some implementations, a column decoder (e.g., column decoder 112) can perform or be configured to perform method 1000. Additionally or alternatively, one or more components of a column decoder (e.g., CS driver 300, CS driver 701, CS driver 800, or CS driver 901) can perform or be configured to perform one or more operations of method 1000. Thus, means for performing method 1000 can include a column decoder and / or one or more components of a column decoder. Additionally or alternatively, a non-transitory computer-readable medium can store one or more instructions that, when executed by a column decoder, cause the column decoder to perform method 1000.

[0103] like Figure 10 As shown in FIG. 1 , method 1000 may include decoding a column address to generate at least one control signal (block 1010). Figure 10 As further shown in FIG1 , method 1000 may include modulating a column select signal based on at least one control signal to activate or deactivate a plurality of column select circuits coupled to the column select lines (block 1020). The plurality of column select circuits may be configured to connect or disconnect data I / O lines and bit lines based on the at least one control signal. Modulating the column select signal may include generating an activation pulse for activating the plurality of column select circuits during an activation interval, wherein the activation pulse includes a first portion having a positive boosted signal level and a second portion having an activation signal level less than the positive boosted signal level, and wherein generating the activation pulse includes generating the first portion of the activation pulse for a first duration of the activation interval and generating the second portion of the activation pulse for a second duration of the activation interval, the second duration of the activation interval being subsequent to the first duration of the activation interval.

[0104] Method 1000 may include additional aspects, such as any single aspect or any combination of aspects described in conjunction with one or more methods or operations described herein.

[0105] although Figure 10 An example block diagram of method 1000 is shown, but in some embodiments, method 1000 may be compared to Figure 10 1000. The method 1000 may include additional blocks, fewer blocks, different blocks, or differently arranged blocks, rather than the blocks depicted in the method 1000. Additionally or alternatively, two or more of the blocks of the method 1000 may be performed in parallel. The method 1000 is an example of a method that may be performed by one or more devices described herein. The one or more devices may perform or be configured to perform one or more other methods based on the operations described herein.

[0106] In some embodiments, a memory device includes: a memory bank including a memory array including data lines and a plurality of memory cells coupled to the data lines; a data input / output (I / O) line for transmitting read data from the data lines or transmitting write data to the data lines; a column select line configured to carry a column select signal across the full height of the memory bank; a plurality of column select circuits coupled to the column select lines, wherein the plurality of column select circuits are arranged along the length of the column select lines, and wherein the plurality of column select circuits are configured to connect or disconnect the data I / O lines and the data lines according to the column select signal; and a column decoder configured to decode a column address, wherein the column decoder includes a A column select driver configured to modulate the column select signal based on the column address so as to activate or deactivate the plurality of column select circuits, wherein the column select signal includes an activation pulse for activating the plurality of column select circuits during an activation interval, wherein the activation pulse includes a first portion having a positive boost signal level and a second portion having an activation signal level less than the positive boost signal level, and wherein the column select driver is configured to generate the first portion of the activation pulse during a first duration of the activation interval and to generate the second portion of the activation pulse during a second duration of the activation interval, the second duration of the activation interval being subsequent to the first duration of the activation interval.

[0107] In some embodiments, a memory device includes: a column decoder configured to decode a column address, wherein the column decoder includes a column select driver configured to modulate a column select signal based on the column address so as to activate or deactivate a plurality of column select circuits coupled to a column select line, wherein the column select signal includes an activation pulse for activating the plurality of column select circuits during an activation interval, wherein the activation pulse includes a first portion having a positive boost signal level and a second portion having an activation signal level less than the positive boost signal level, and wherein the column select driver is configured to generate the first portion of the activation pulse within a first duration of the activation interval and to generate the second portion of the activation pulse within a second duration of the activation interval, the second duration of the activation interval being subsequent to the first duration of the activation interval.

[0108] In some embodiments, a method of connecting and disconnecting data input / output (I / O) lines and bit lines of a memory device includes: decoding a column address to generate at least one control signal; and modulating a column select signal based on the at least one control signal so as to activate or deactivate a plurality of column select circuits coupled to the column select lines, wherein the plurality of column select circuits are configured to connect or disconnect the data I / O lines and the bit lines based on the at least one control signal, wherein modulating the column select signal includes: generating an activation pulse for activating the plurality of column select circuits during an activation interval, wherein the activation pulse includes a first portion having a positive boost signal level and a second portion having an activation signal level less than the positive boost signal level, and wherein generating the activation pulse includes generating the first portion of the activation pulse within a first duration of the activation interval and generating the second portion of the activation pulse within a second duration of the activation interval, the second duration of the activation interval being subsequent to the first duration of the activation interval.

[0109] The above disclosure provides illustration and description, but is not intended to be exhaustive or to limit the embodiments to the precise form disclosed. Modifications and variations are possible in light of the above disclosure or may be acquired from practice of the embodiments described herein.

[0110] As used herein, the terms "substantially" and "approximately" mean "within reasonable manufacturing and measurement tolerances." As used herein, "satisfying a threshold" may refer to a value being greater than a threshold, greater than or equal to a threshold, less than a threshold, less than or equal to a threshold, equal to a threshold, not equal to a threshold, or the like, depending on the context.

[0111] Even if the particular combination of features is narrated in the claims and / or disclosed in the specification, these combinations are not intended to limit the disclosure of the embodiments described herein. Many of these features can be combined in a manner not clearly narrated in the claims and / or not clearly disclosed in the specification. For example, the disclosure includes each dependent claim in the claim group in conjunction with each other individual claim in the claim group and each combination of multiple claims in the claim group. As used herein, the phrase "at least one of" related to the project list refers to any combination of the project, including single members. As an example, "at least one of a, b or c" is intended to encompass a, b, c, a+b, a+c, b+c and a+b+c and any combination of multiple identical elements (such as a+a, a+a+a, a+a+b, a+a+c, a+b+b, a+c+c, b+b, b+b+b, b+b+c, c+c and c+c+c or any other sorting of a, b and c).

[0112] When a "component" or "one or more components" (or another element, such as a "controller" or "one or more controllers") is described or claimed (either within a single claim or across multiple claims) as performing or being configured to perform multiple operations, such language is intended to broadly encompass a variety of architectures and environments. For example, unless otherwise expressly claimed (e.g., through the use of "a first component" and "a second component" or other language that distinguishes components in the claims), such language is intended to encompass a single component performing or being configured to perform all operations, a group of components collectively performing or being configured to perform all operations, a first component performing or being configured to perform a first operation and a second component performing or being configured to perform a second operation, or any combination of components performing or being configured to perform operations. For example, when a claim has the form "one or more components configured to: perform X; perform Y; and perform Z," the claim should be interpreted to mean "one or more components configured to perform X; one or more (possibly different) components configured to perform Y; and one or more (possibly different) components configured to perform Z."

[0113] The elements, actions or instructions used herein should not be interpreted as key or necessary unless clearly described as such. Moreover, as used herein, the article "one" is intended to include one or more projects and can be used interchangeably with "one or more". In addition, as used herein, the article "said" is intended to include one or more projects referenced in conjunction with the article "said" and can be used interchangeably with "said one or more". When only one project is desired, the phrase "only one", "single" or similar language is used. Moreover, as used herein, the term "having" or the like is intended to be an open term that does not limit the elements modified thereto (for example, an element "having" A may also have B). In addition, unless otherwise clearly stated, the phrase "based on" is intended to mean "at least partially based on". As used herein, the term "multiple (multiple)" can be replaced with "a plurality of (a plurality of)", and vice versa. Moreover, as used herein, unless otherwise clearly stated (for example, if used in combination with "... either of the two" or "... only one of the two"), the term "or" is intended to be inclusive and can be used interchangeably with "and / or" when used in a series.

Claims

1. A memory device comprising: a memory bank comprising a memory array including a data line and a plurality of memory cells coupled to the data line; a data input / output I / O line for transmitting read data from the data line or transmitting write data to the data line; a column select line configured to carry a column select signal across the full height of the memory bank; a plurality of column select circuits coupled to the column select lines, wherein the plurality of column select circuits are arranged along a length of the column select lines, and wherein the plurality of column select circuits are configured to connect or disconnect the data I / O lines and the data lines according to the column select signals; and a column decoder configured to decode a column address, wherein the column decoder includes a column select driver configured to modulate the column select signal based on the column address so as to activate or deactivate the plurality of column select circuits, wherein the column selection signal comprises an activation pulse for activating the plurality of column selection circuits during an activation interval, wherein the activation pulse comprises a first portion having a positive boost signal level and a second portion having an activation signal level less than the positive boost signal level, and wherein the column select driver is configured to generate the first portion of the activation pulse during a first duration of the activation interval and to generate the second portion of the activation pulse during a second duration of the activation interval, the second duration of the activation interval being subsequent to the first duration of the activation interval.

2. The memory device of claim 1 , wherein the plurality of column selection circuits are transistors, and The activation signal level is equal to or greater than the threshold voltage of each transistor.

3. The memory device of claim 1 , wherein the column select driver comprises a first inverter and a second inverter coupled in series, wherein the first inverter is configured to receive a control signal corresponding to the column address, The second inverter has a first power supply terminal and a second power supply terminal, and The second inverter is coupled to an output of the first inverter and is configured to generate the column select signal corresponding to the control signal based on a first supply potential coupled to the first power supply terminal and a second supply potential coupled to the second power supply terminal.

4. The memory device of claim 3, wherein the first inverter comprises a first pair of high voltage transistors, and wherein the second inverter comprises a second pair of high voltage transistors.

5. The memory device of claim 3, wherein the column decoder is configured to switch the control signal between the positive boosted signal level and ground potential based on the column address.

6. The memory device of claim 3, wherein the first inverter comprises a high-voltage positive metal oxide semiconductor (PMOS) transistor and a low-voltage negative MOS (NMOS) transistor, and wherein the second inverter comprises a pair of low-voltage transistors.

7. The memory device of claim 6, wherein the column decoder is configured to switch the control signal between the activation signal level and ground potential based on the column address.

8. The memory device of claim 6, wherein a control electrode of the high-voltage PMOS transistor is coupled to an output of the second inverter.

9. The memory device of claim 3 , wherein the column decoder comprises: a first switch coupled between a first voltage source corresponding to the positive boost signal level and the first power supply terminal; and a second switch coupled between a second voltage source corresponding to the activation signal level and the first power supply terminal, Wherein the column decoder is configured to control the first switch and the second switch based on the column address to generate the activation pulse.

10. The memory device of claim 1 , wherein the column select driver is configured to deactivate the plurality of column select circuits during a deactivation interval, wherein the column selection signal includes a deactivation pulse for deactivating the plurality of column selection circuits during the deactivation interval, and wherein the column select driver is configured to generate the deactivation pulse at a negative boost signal level for a first duration of the deactivation interval and to maintain the column select signal at a deactivation signal level greater than the negative boost signal level for a second duration of the deactivation interval, the second duration of the deactivation interval being subsequent to the first duration of the deactivation interval.

11. The memory device of claim 10, wherein the deactivation signal level is less than a threshold voltage of each column selection circuit.

12. The memory device of claim 10 , wherein the column select driver comprises a first inverter and a second inverter coupled in series, wherein the first inverter is configured to receive a control signal corresponding to the column address, The second inverter has a first power supply terminal and a second power supply terminal, wherein the second inverter is coupled to an output of the first inverter and is configured to generate the column select signal corresponding to the control signal based on a first supply potential coupled to the first power supply terminal and a second supply potential coupled to the second power supply terminal, and The column decoder comprises: a first switch coupled between a first voltage source corresponding to the positive boost signal level and the first power supply terminal; a second switch coupled between a second voltage source corresponding to the activation signal level and the first power supply terminal; a third switch coupled between a third voltage source corresponding to the negative boost signal level and the second power supply terminal; and a fourth switch coupled between a fourth voltage source corresponding to the deactivation signal level and the second power supply terminal, and Wherein the column decoder is configured to control the first switch, the second switch, the third switch, and the fourth switch based on the column address to generate the column selection signal having the activation pulse and the deactivation pulse.

13. The memory device of claim 10 , wherein the first duration of the activation interval and the first duration of the deactivation interval are variable, and Wherein the column select driver is configured to receive a segment control signal and adjust the first duration of the activation interval and the first duration of the deactivation interval based on the segment control signal.

14. The memory device of claim 13, wherein the sector control signal is a row address.

15. The memory device of claim 13, wherein the sector control signal is part of the column address.

16. The memory device of claim 10 , wherein a first difference between the positive boosting signal level and the activation signal level is variable, wherein a second difference between the negative boost signal level and the deactivation signal level is variable, and wherein the column select driver is configured to receive a segment control signal and adjust the first difference and the second difference based on the segment control signal.

17. The memory device of claim 1, further comprising: a column select ground line having ground potential; and a pull-down transistor coupled to the column select ground line and a distal end of the column select line, wherein the column select driver is configured to deactivate the plurality of column select circuits during a deactivation interval, wherein the column select driver is configured to maintain the column select signal at a deactivation signal level during the deactivation interval, and wherein the column select driver is configured to turn on the pull-down transistor to sink the column select signal to the column select ground line during a first duration of the deactivation interval and to turn off the pull-down transistor during a second duration of the deactivation interval, the second duration of the deactivation interval being subsequent to the first duration of the deactivation interval.

18. The memory device of claim 1, wherein the column decoder is configured to generate a plurality of control signals based on the column address and provide the plurality of control signals to the column select driver for generating the column select signals.

19. A memory device comprising: a column decoder configured to decode a column address, wherein the column decoder includes a column select driver configured to modulate a column select signal based on the column address so as to activate or deactivate a plurality of column select circuits coupled to column select lines, wherein the column selection signal comprises an activation pulse for activating the plurality of column selection circuits during an activation interval, wherein the activation pulse comprises a first portion having a positive boost signal level and a second portion having an activation signal level less than the positive boost signal level, and wherein the column select driver is configured to generate the first portion of the activation pulse during a first duration of the activation interval and to generate the second portion of the activation pulse during a second duration of the activation interval, the second duration of the activation interval being subsequent to the first duration of the activation interval.

20. A method of connecting and disconnecting data input / output (I / O) lines and bit lines of a memory device, the method comprising: decoding a column address to generate at least one control signal; and modulating a column select signal based on the at least one control signal so as to activate or deactivate a plurality of column select circuits coupled to the column select lines, wherein the plurality of column select circuits are configured to connect or disconnect the data I / O lines and the bit lines based on the at least one control signal, Wherein modulating the column selection signal comprises: generating an activation pulse for activating the plurality of column selection circuits during an activation interval, wherein the activation pulse includes a first portion having a positive boosting signal level and a second portion having an activation signal level less than the positive boosting signal level, and Generating the activation pulse comprises: The first portion of the activation pulse is generated during a first duration of the activation interval and the second portion of the activation pulse is generated during a second duration of the activation interval, the second duration of the activation interval being subsequent to the first duration of the activation interval.

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