Peripheral circuit, operation method of memory, memory and memory system

Abstract

The invention provides a peripheral circuit, an operation method of a memory, the memory and a memory system, and relates to the technical field of memory. The problem that the power consumption of a memory is high is solved. The peripheral circuit comprises a data output end, a plurality of local data buses and a plurality of data driving circuits, each data driving circuit comprises an output end, a first input end and a second input end, the output end of the first data driving circuit in the plurality of data driving circuits is connected with the data output end through the first local data bus, and the output end of the second data driving circuit is connected with the second input end through the second local data bus. The output end of the (i + 1) th data driving circuit is connected with the first input end of the ith data driving circuit through the (i + 1) th local data bus, and the second input end of any data driving circuit is connected with the storage block corresponding to the data driving circuit. And the data driving circuit is used for outputting data input by the first input end or data input by the second input end through the output end.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of storage technology, and in particular to a peripheral circuit, a memory operating method, a memory, and a storage system. Background Art

[0002] With the continuous development of emerging technologies such as cloud computing and big data processing, the demand for memory is increasing. The widespread use of these technologies requires memory to store more data and to provide faster and more efficient data access and processing. Therefore, memory needs to have larger capacity, faster speed, lower power consumption, and higher reliability to meet the data storage and processing needs of modern applications. Summary of the Invention

[0003] Embodiments of the present application provide a peripheral circuit, a memory operating method, a memory, and a storage system, which are used to improve the problem of high power consumption of the memory.

[0004] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0005] In a first aspect, the present application provides a peripheral circuit, which includes: a data output end, multiple local data buses and multiple data driving circuits, the data driving circuit including an output end, a first input end and a second input end, the output end of the first data driving circuit in the multiple data driving circuits is connected to the data output end through the first local data bus, the output end of the i+1th data driving circuit is connected to the first input end of the i-th data driving circuit through the i+1th local data bus, the second input end of any data driving circuit is connected to the storage block corresponding to the data driving circuit, i is an integer greater than or equal to 1, and i is less than n, n is the number of data driving circuits in the peripheral circuit, the data driving circuit is used to operate in a low-resistance state or a high-resistance state, when the data driving circuit operates in the low-resistance state, the data input at the first input end of the data driving circuit or the data at the second input end of the data driving circuit is output through the output end of the data driving circuit.

[0006] The peripheral circuits provided herein utilize a distributed drive approach, enabling each memory block to accommodate only a smaller data driver circuit. Furthermore, when a selected memory block outputs data, only the voltage of the local data bus between the data driver circuit connected to the selected memory block and the data output terminal changes, thereby reducing the memory's dynamic power consumption. Furthermore, in any state, the local data buses corresponding to the data driver circuits connected to unselected memory blocks do not experience data flipping or charging or discharging, thus eliminating additional power consumption and reducing the memory's static power consumption.

[0007] In one possible embodiment, when data stored in a storage block connected to the mth data driving circuit is read through a peripheral circuit, the mth data driving circuit is configured to output data inputted at the second input terminal through the output terminal, the 1st to m-1th data driving circuits are configured to output data inputted at the first input terminal through the output terminal, and the m+1th to nth data driving circuits are configured to output data inputted at the first input terminal through the output terminal.

[0008] In a possible implementation, the data driving circuit further includes a second controlled terminal, the second controlled terminal is used to input a switching signal, and the data driving circuit is configured to be in a high-resistance state or a low-resistance state in response to the switching signal.

[0009] In a possible implementation, the data driving circuit further includes a first controlled terminal, the first controlled terminal being used to input a storage block selection signal, and the data driving circuit selectively outputs data input from the first input terminal or data input from the second input terminal in response to the storage block selection signal.

[0010] In one possible embodiment, the data driving circuit includes a selection circuit and a switching circuit, the switching circuit includes an input end, an output end and a second control end, the selection circuit includes an output end, a first input end, a second input end and a first control end, the second control end of the switching circuit is connected to the first controlled end of the data driving circuit, the output end of the switching circuit is connected to the output end of the data driving circuit, the first input end of the selection circuit is connected to the first input end of the data driving circuit, the second input end of the selection circuit is connected to the second input end of the data driving circuit, the first control end of the selection circuit is connected to the first controlled end of the data driving circuit, and the output end of the selection circuit is connected to the input end of the switching circuit.

[0011] In a possible implementation, the peripheral circuit further includes a holding circuit, and the holding circuit is arranged between the output end of the first data driving circuit and the data output end of the peripheral circuit.

[0012] In a possible implementation, the holding circuit includes any one of a level-triggered latch, an edge-triggered latch, or a positive feedback latch-type holding circuit.

[0013] In a second aspect, the present application provides a method for operating a memory, which is applied to the peripheral circuit of the first aspect, the peripheral circuit comprising: a data output end, multiple local data buses and multiple data driving circuits, the data driving circuit comprising an output end, a first input end and a second input end, the output end of the first data driving circuit among the multiple data driving circuits is connected to the data output end through the first local data bus, the output end of the i+1th data driving circuit is connected to the first input end of the i-th data driving circuit through the i+1th local data bus, the second input end of any data driving circuit is connected to the storage block corresponding to the data driving circuit, i is an integer greater than or equal to 1, and i is less than n, and n is the number of data driving circuits in the peripheral circuit, the method comprising: configuring the m-th data driving circuit to output data of the second input end, configuring the 1st to m-th data driving circuits to a low-resistance state, and configuring the m+1th to n-th data driving circuits to a high-resistance state to read data stored in the storage block connected to the m-th data driving circuit.

[0014] In one possible embodiment, the data driving circuit further includes a second controlled end, the second controlled end is used to input a switching signal, and the data driving circuit is configured to a high-impedance state or a low-impedance state in response to the switching signal. Configuring the 1st to mth data driving circuits to a low-impedance state and configuring the m+1th to nth data driving circuits to a high-impedance state includes: sending a first switching signal to the second controlled ends of the 1st to mth data driving circuits, the data driving circuits are configured to a low-impedance state in response to the first switching signal, and sending a second switching signal to the second controlled ends of the m+1th to nth data driving circuits, the data driving circuits are configured to a high-impedance state in response to the second switching signal.

[0015] In a possible implementation, sending the first switching signal to the second controlled ends of the 1st to mth data driving circuits includes: sending the first switching signal to the second controlled ends of the data driving circuits in order from the mth data driving circuit to the 1st data driving circuit.

[0016] The operating method provided in the present application can ensure that the data stored in the selected storage block is effectively transmitted to the data output end by controlling the sending timing of the switch signal, and no invalid data is transmitted.

[0017] In one possible embodiment, the data driving circuit further includes a first controlled terminal, the first controlled terminal being used to input a storage block selection signal, and the data driving circuit selects to output data input from the first input terminal or data input from the second input terminal in response to the storage block selection signal; configuring the mth data driving circuit to output data from the second input terminal, and configuring the 1st to m-1th, and m+1th to nth data driving circuits to output data from the first input terminal includes: sending a first selection signal to the first controlled terminals of the 1st to m-1th data driving circuits and the m+1th to nth data driving circuits, the data driving circuit being configured to select and output data input from the first input terminal in response to the first selection signal, and sending a second selection signal to the first controlled terminal of the mth data driving circuit, the data driving circuit being configured to output data input from the second input terminal in response to the second selection signal.

[0018] In a third aspect, the present application provides a memory, which includes a peripheral circuit and a storage block and a logic control circuit coupled to the peripheral circuit, wherein the peripheral circuit is the peripheral circuit of the first aspect.

[0019] In a fourth aspect, the present application provides a storage system comprising a memory controller and the memory according to the third aspect, wherein the memory controller is configured to control the memory.

[0020] In a fifth aspect, the present application provides a computer-readable storage medium, which stores computer-executable instructions; after the computer-executable instructions are executed, any method of the second aspect can be implemented.

[0021] In a sixth aspect, the present application provides an electronic device comprising a processor and a readable storage medium coupled to the processor, wherein the readable storage medium stores executable instructions, and when the executable instructions are executed by the processor, any method of the second aspect can be implemented.

[0022] The technical effects of the second to sixth aspects refer to the technical effects of the first aspect and any of its embodiments and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0024] Figure 2 A schematic diagram of a storage system provided in an embodiment of the present application;

[0025] Figure 3 A schematic diagram of a peripheral circuit provided in an embodiment of the present application;

[0026] Figure 4 A schematic diagram of another peripheral circuit provided in an embodiment of the present application;

[0027] Figure 5 A schematic diagram of another peripheral circuit provided in an embodiment of the present application;

[0028] Figure 6 A schematic diagram of another peripheral circuit provided in an embodiment of the present application;

[0029] Figure 7 A circuit diagram of a data driving circuit provided in an embodiment of the present application;

[0030] Figure 8 Another circuit diagram of a data driving circuit provided in an embodiment of the present application;

[0031] Figure 9 A schematic flow chart of an operating method provided in an embodiment of the present application;

[0032] Figure 10 A schematic flow chart of another operating method provided in an embodiment of the present application;

[0033] Figure 11 A logic block diagram of another operating method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0034] The terms used in the following examples are only for the purpose of describing specific embodiments and are not intended to be limiting of the present application. As used in the specification and appended claims of the present application, the singular expressions "one", "a kind of", "above", "the" and "this" are intended to also include the "one or more" forms of expression of examples, unless there is clearly an opposite indication in the context. It should also be understood that in the following embodiments of the present application, "at least one", "one or more" refer to one or more (including two). The character " / " generally represents that the objects before and after the association are a kind of "or" relationship.

[0035] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0036] In the following, the terms "first," "second," etc. are used for convenience of description only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more. For example, "plurality of processing units" refers to two or more processing units.

[0037] In the embodiments of this application, unless otherwise specified or limited, the term "connection" should be understood in a broad sense. For example, "connection" can mean fixed connection, detachable connection, or integration; it can mean direct connection or indirect connection through an intermediate medium. In addition, the term "electrical connection" can mean direct electrical connection or indirect electrical connection through an intermediate medium.

[0038] In the embodiments of the present application, the term "module" generally refers to a functional structure divided according to logic. The "module" can be implemented by pure hardware or a combination of hardware and software. In the embodiments of the present application, "and / or" describes the association relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, B exists alone, and A and B exist at the same time.

[0039] In the embodiments of this application, words such as "exemplary" or "exemplary" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "exemplary" in the embodiments of this application should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "exemplary" is intended to present the relevant concepts in a concrete manner.

[0040] The present application provides an electronic device. The electronic device may include a mobile phone, a tablet computer (pad), a television, a smart wearable product (for example, a smart watch, a smart bracelet), a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, and other electronic products, as well as a mobile base station, WiFi, and other communication equipment. The present application does not impose any particular restrictions on the specific form of the above-mentioned electronic devices.

[0041] The following is a structural diagram of an electronic device used in the implementation of this application, taking a mobile phone as an example. Figure 1 The mobile phone may include: a processor 110, an external memory interface 120, a storage system 121, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, an earphone interface 170D, a sensor module 180, a button 190, a motor 191, an indicator 192, a camera 193, a display screen 194, and a subscriber identification module (SIM) card interface 195, etc.

[0042] It should be understood that the structure illustrated in this embodiment does not constitute a specific limitation on the electronic device. In other embodiments, the electronic device may include more or fewer components than shown, or may combine or separate certain components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0043] The storage system 121 can be used to store computer executable program codes, and the executable program codes include instructions. The processor 110 executes various functional applications and data processing of the mobile phone 200 by running the instructions stored in the storage system 121. For example, in an embodiment of the present application, the processor 110 can execute the instructions stored in the storage system 121, and the storage system 121 may include a program storage area and a data storage area. Among them, the program storage area can store an operating system, an application required for at least one function (such as a sound playback function, an image playback function, etc.), etc. The data storage area can store data created during the use of the mobile phone 200 (such as audio data, a phone book, etc.), etc.

[0044] The storage system 121 may include a static random-access memory (SRAM), a dynamic random access memory (DRAM), a universal flash storage (UFS), and the like.

[0045] See Figure 2 , Figure 2 A schematic diagram of a memory system provided in an embodiment of the present application is provided. The memory system 121 may include a memory controller 1210 and a memory 1211. The memory controller 1210 is coupled to the memory 1211 to control the memory 1211 to store data. The memory may include a memory block and a peripheral circuit coupled to the memory block.

[0046] See Figure 3 , Figure 3 A schematic diagram of a peripheral circuit provided in an embodiment of the present application, wherein the peripheral circuit includes a holding circuit and multiple data driving circuits. The multiple data driving circuits are coupled to a data output bus in a mounted form, and each storage block (BANK) is connected to the data driving circuit through its local data bus. For example, storage block 0 is connected to its corresponding data driving circuit 0 through the local data bus DOB0, and data n is connected to its corresponding data driving circuit n through the local data bus DOBn.

[0047] When the memory receives a data read instruction from the memory controller, it determines the selected memory block by parsing the address signal and transmits the data stored in the selected memory block to the memory's data output terminal. For example, when reading data stored in memory block 2, the data stored in memory block 2 is first transmitted to the data output bus via the local data bus DOB2, and then transmitted to the memory's data output terminal via the data output bus.

[0048] The function of the data driving circuit is to conduct the local data bus and the data output bus of the selected memory block after receiving the memory block selection signal, so that the data stored in the selected memory block can be transmitted to the data output end of the memory.

[0049] In one possible implementation, the data driver circuit may be a tri-state driver circuit. For a selected memory block, its corresponding tri-state driver circuit may be in a low-resistance state to effectively drive the data in the memory block to the output port of the memory. The low-resistance state is a strong drive state, which can also be understood as a conductive state. In this state, the output of the memory block can be normally transmitted to the output port of the memory. For an unselected memory block, its corresponding tri-state driver circuit may be in a high-resistance state. The high-resistance state can also be understood as an off state. In this state, its output port will enter a high-resistance state, that is, the output resistance of the circuit is high, which has almost no impact on the signal on the data output bus. This is done to prevent the unselected memory block from interfering with the normal operation of the data output bus, while ensuring that the selected memory block can correctly drive its output.

[0050] As memory storage capacity continues to increase, the number of data driver circuits and memory blocks mounted on the data output bus also continues to grow, leading to a continuous increase in the physical size of the data output bus. Since the data driver circuit needs to provide driving power for the entire data output bus during a read operation, the physical size of the data driver circuit increases as the physical size of the data output bus increases. Furthermore, whether reading data from a memory block close to the output terminal or from a memory block further away, the voltage of the entire data output bus changes. When a memory block switches, the data output bus experiences a period of instability before the selected memory block outputs stable data. All of these situations increase the power consumption of the data output bus during a read operation, thereby increasing the dynamic power consumption of the memory. Therefore, it is necessary to reduce the dynamic power consumption during a memory read operation to reduce the overall power consumption of the memory.

[0051] The peripheral circuit of this application will be described in detail below.

[0052] See Figure 4In the first aspect of the present application, a peripheral circuit is shown, comprising: a data output terminal, a plurality of local data buses and a plurality of data driving circuits. For example, the data driving circuit may be a multi-port device, and each data driving circuit may include an output terminal B, a first input terminal A1 and a second input terminal A2. The output terminal of the data driving circuit 0 is connected to the input terminal of the holding circuit via the local data bus (DON0), and the output terminal of the holding circuit is connected to the output terminal of the memory, the output terminal of the data driving circuit 1 is connected to the first input terminal of the data driving circuit 0 via the local data bus (DON1), and the output terminal of the data driving circuit n is connected to the first input terminal of the data driving circuit n-1 via the local data bus (DONn). The second input terminal of the data driving circuit 0 can be connected to the output terminal of the storage block 0, and the second input terminal of the data driving circuit n can be connected to the output terminal of the storage block n. The data driving circuit can select one input terminal from the first input terminal and the second input terminal as the input terminal. The peripheral circuit also includes a logic control circuit, which is used to

[0053] The data driver circuit can have two different states: a low-resistance state, i.e., a strong drive state. In the low-resistance state, the data path between the current data driver circuit and the next data driver circuit can be considered to be in an on state. In the high-resistance state, the data path between the current data driver circuit and the next data driver circuit can be considered to be in an off state. In the low-resistance state, the data driver circuit can have two data output states depending on its input terminals. For example, when the data driver circuit operates in the low-resistance state, the first data output state of the data driver circuit can be data input to the first input terminal, and the second data output state of the data driver circuit can be data input to the second input terminal. When the data driver circuit is in the first data output state, it functions to transfer data from the previous data driver circuit to the next data driver circuit, that is, to transfer data from the storage block from the far-end data output terminal to the near-end data output terminal. When the data driver circuit is in the second data output state, it functions to transfer data stored in the selected storage block to the data driver circuit.

[0054] During a read operation, the target data driving circuit connected to the selected memory block and the non-target data driving circuits connected to the unselected memory blocks need to be configured to different states.

[0055] In one feasible embodiment, when reading data stored in a memory block connected to the mth data driver circuit through a peripheral circuit, the mth data driver circuit is configured to output data inputted at the second input terminal through an output terminal, the 1st to m-1th data driver circuits are configured to output data inputted at the first input terminal through an output terminal, and the m+1th to nth data driver circuits are configured to output data inputted at the first input terminal through an output terminal. It should be noted that the first data driver circuit, the mth data driver circuit, etc., described above are logical concepts and do not refer to the first data driver circuit or the mth data driver circuit in a physical location.

[0056] By adopting a distributed drive approach, each memory block only needs to accommodate a smaller data driver circuit. When a selected memory block outputs data, only the voltage of the local data bus between the data driver circuit connected to the selected memory block and the data output terminal changes, reducing the memory's dynamic power consumption. Furthermore, in any state, the local data bus corresponding to the data driver circuit connected to the unselected memory blocks remains in a high-impedance state, preventing data flipping and charge / discharge, thus reducing the memory's static power consumption.

[0057] The logic control circuit can configure different data output states for the data driver circuit by sending different memory block selection signals to the data driver circuit. In one feasible embodiment, the data driver circuit further includes a first controlled terminal, the first controlled terminal being used to input the memory block selection signal, and the data driver circuit selects to output data inputted from the first input terminal or data inputted from the second input terminal in response to the memory block selection signal.

[0058] For example, when the memory block selection signal sent by the logic control circuit to the first controlled terminal of the data driving circuit is a first-level signal, which may be a low level signal, represented by 0, then the data driving circuit is configured to output the data inputted at the first input terminal after receiving the memory block selection signal. That is, the data driving circuit functions to transmit the data of the previous data driving circuit to the next data driving circuit. When the memory block selection signal sent by the logic control circuit to the first controlled terminal of the data driving circuit is a second-level signal, which may be a high level signal, represented by 1, then the data driving circuit is configured to output the data inputted at the second input terminal after receiving the memory block selection signal. That is, the data driving circuit functions to transmit the data stored in the memory block to the data driving circuit.

[0059] The logic control circuit can configure the state of each data driving circuit by sending different switching signals to the data driving circuit. In one feasible embodiment, the data driving circuit also includes a second controlled terminal, which is used to input the switching signal. The data driving circuit is configured to a high-impedance state or a low-impedance state in response to the switching signal.

[0060] For example, when the switching signal sent by the logic control circuit to the second controlled terminal of the data driving circuit is a first-level signal, which may be a low level signal, represented by 0, the data driving circuit is configured to a high-impedance state after receiving the switching signal, i.e., the data driving circuit cannot transmit data with an adjacent data driving circuit. When the switching signal sent by the logic control circuit to the second controlled terminal of the data driving circuit is a second-level signal, which may be a high level signal, represented by 1, the data driving circuit is configured to a low-impedance state after receiving the switching signal, i.e., the data driving circuit can transmit data with an adjacent data driving circuit via a local data bus.

[0061] The function of the data driving circuit is to connect the output end of the selected memory block and the second input end of the data driving circuit after receiving the memory block selection signal, so that the data stored in the selected memory block can be output to the output end of the memory. It can have multiple circuit implementation forms.

[0062] In one possible implementation, see Figure 5 Each data driving circuit 501 includes a selection circuit 502 and a switch circuit 503. The selection circuit 502 can be a two-select-one circuit, and the switch circuit 503 can be a three-state output circuit. The three-state output circuit and the two-select-one circuit can have a variety of circuit implementation structures, which is not limited in this application. The selection circuit 502 includes an output terminal b1, a first input terminal a1, a second input terminal a2, and a first control terminal c1. The switch circuit 503 includes an input terminal a3, an output terminal b2, and a second control terminal c2. The first input terminal a1 of the selection circuit 502 is connected to the first input terminal A1 of the data driving circuit 501, the second input terminal a2 of the selection circuit 502 is connected to the second input terminal A2 of the data driving circuit 501, the first control terminal c1 of the selection circuit 502 is connected to the first controlled terminal C1 of the data driving circuit 501, the output terminal b1 of the selection circuit 502 is connected to the input terminal a3 of the switch circuit 503, the second control terminal c2 of the switch circuit 503 is connected to the second controlled terminal C2 of the data driving circuit 501, and the output terminal b2 of the switch circuit 503 is connected to the output terminal B of the data driving circuit 501. The specific structure of the peripheral circuit can be found in Figure 6 shown.

[0063] In order to maintain a stable state of data output and ensure that the output data can be correctly maintained and transmitted, in a feasible embodiment, the peripheral circuit also includes a holding circuit, which is arranged between the output end of the first data driving circuit and the data output end of the peripheral circuit.

[0064] A hold circuit latches and holds an input signal at its output when it meets certain conditions. This ensures the output maintains its original state even if the input signal disappears or changes. In many scenarios, particularly during data transmission or processing, a hold circuit ensures that data is accurately output when needed, regardless of external signal fluctuations.

[0065] The local data bus connected to the holding circuit may be in a high impedance state, or due to the function of the holding circuit, the previous state is maintained. The holding circuit can have a variety of circuit implementation forms. In a feasible implementation, refer to Figure 7 , the holding circuit can be as follows Figure 7 (a) and Figure 7 The level-triggered latch shown in (b) can also be Figure 7 The edge-triggered latch shown in (c) or Figure 7 The first and second pulse signals are signals with opposite phases, and the size and drive capability of the first inverter are greater than those of the second inverter.

[0066] The three-state drive circuit can be realized in a variety of circuit forms, see Figure 8 In a feasible implementation, the circuit diagram of the three-state driving circuit is Figure 8 (a) or Figure 8 One of the circuits shown in (b) above, or other forms of three-state drive circuits, the circuit symbol diagram of the three-state drive circuit can be as follows Figure 8 As shown in (c).

[0067] The memory provided by the embodiments of the present application reduces the dynamic power consumption of the memory by reducing the impact of the reading of data stored in the selected memory block on the local data bus outside the data path range during the reading process. In scenarios other than read operations, the local data bus outside the data path range does not undergo data flipping, which reduces the static power consumption of the memory. By simultaneously reducing the dynamic and static power consumption of the memory, the overall power consumption of the memory is reduced.

[0068] In a second aspect, an embodiment of the present application provides a method for operating a memory, the method being applied to a logic control circuit coupled to the peripheral circuit provided in the first aspect, referring to Figure 9 , methods include:

[0069] S901: Configure the mth data driving circuit to output data of the second input terminal.

[0070] After receiving a data read instruction, the corresponding storage block can be determined based on the data read instruction, and then the data stored in the selected storage block can be transmitted to the data output terminal. The entire process can be divided into two operation stages. In the first operation stage, the data driver circuit connected to the selected storage block can be configured to output the data at the second input terminal, that is, output the data stored in the storage block. Then, the other data driver circuits can be configured to output the data at the first input terminal, so that only the data stored in the storage block can be transmitted to the data driver circuit.

[0071] In order to ensure that the data stored in the memory block can be read accurately, different selection signals can be sent to the first controlled end of the data driving circuit. Figure 10 , the specific steps may include:

[0072] S9011: Sending a first selection signal to the first controlled terminals of the 1st to m-1th data driving circuits and the m+1th to nth data driving circuits, so that the data driving circuits are configured to select and output data inputted from the first input terminals in response to the first selection signal;

[0073] S9012: Sending a second selection signal to the first controlled terminal of the mth data driving circuit, and the data driving circuit is configured to output data input from the second input terminal in response to the second selection signal.

[0074] For example, when the storage block selection signal sent by the logic control circuit to the first controlled terminal of the data driving circuit is a first-level signal, which may be a low level signal, represented by 0, then the data driving circuit, upon receiving the storage block selection signal, selects to output the data inputted at the first input terminal, i.e., the data driving circuit functions to transmit the data of the previous data driving circuit to the next data driving circuit. When the storage block selection signal sent by the logic control circuit to the first controlled terminal of the data driving circuit is a second-level signal, which may be a high level signal, represented by 1, then the data driving circuit, upon receiving the storage block selection signal, is configured to output the data at the second input terminal, i.e., the data driving circuit functions to transmit the data stored in the storage block to the data driving circuit.

[0075] To prevent the output data path from becoming unstable due to unstable data output from the selected memory block, the state of the data driver circuit needs to be configured based on whether the data output from the memory block is stable. In one feasible embodiment, the logic control circuit can send different switching signals to the data driver circuit in response to status information fed back by the data driver circuit.

[0076] When the data driver circuit connected to the selected memory block receives a memory block selection signal and outputs data input from the second input terminal, a timer can be initiated within the data driver circuit. When the timer result is greater than a preset time value, the input of the data driver circuit is considered to be in a stable state, and status information is fed back to the logic control circuit. This status information is used to indicate that the input of the data output by the selected memory block is in a stable state. When the timer result is less than or equal to the preset time value, the input of the data driver circuit is considered to be in an unstable state, and no status information is fed back to the logic control circuit. The entire output data path is in a high-impedance state. Therefore, when the logic control circuit receives the status information fed back by the data driver circuit, it can be considered that the data output by the selected memory block is in a stable state.

[0077] S902: configuring the 1st to mth data driving circuits to be in a low-impedance state, and configuring the m+1th to nth data driving circuits to be in a high-impedance state.

[0078] The second operation phase can be to configure the data driver circuit between the data driver circuit connected to the selected memory block and the data output terminal to a low-impedance state, thereby transmitting the data stored in the memory block to the data output terminal via the local data bus. The other data driver circuits are configured to a high-impedance state to reduce the power consumption of the memory.

[0079] In order to ensure that the data stored in the selected storage block can be accurately transmitted to the data output terminal, different switch signals can be sent to the second controlled terminal of the data driving circuit. Figure 10 , the specific steps may include:

[0080] S9021: Sending a first switching signal to the second controlled terminals of the first to mth data driving circuits, so that the data driving circuits are configured to be in a low-resistance state in response to the first switching signal;

[0081] S9022: Sending a second switching signal to the second controlled terminals of the (m+1)th to (n)th data driving circuits, and the data driving circuits are configured to be in a high-impedance state in response to the second switching signal.

[0082] For example, when the switching signal sent by the logic control circuit to the second controlled terminal of the data driver circuit is a first-level signal, which may be a low level signal, represented by 0, the data driver circuit is configured to a high-impedance state upon receiving the switching signal, i.e., the data driver circuit cannot transmit data with its adjacent data driver circuit via the local data bus. When the switching signal sent by the logic control circuit to the second controlled terminal of the data driver circuit is a second-level signal, which may be a high level signal, represented by 1, the data driver circuit is configured to a low-impedance state upon receiving the switching signal, i.e., the data driver circuit can transmit data with its adjacent data driver circuit via the local data bus.

[0083] In order to ensure that the data stored in the selected storage block is effectively transmitted to the data output terminal and that invalid data is not transmitted, when sending a switch signal to the data driving circuit, it is necessary to send it according to a certain time limit. The specific steps may include:

[0084] The first switching signal is sequentially sent to the second controlled end of the data driving circuit in order from the mth data driving circuit to the first data driving circuit.

[0085] When sending the first switching signal, the signals are sent in order from farthest to closest to the data holding circuit, thereby transmitting the data stored in the selected storage block step by step. For example, the selected storage block is the storage block connected to the fifth data driving circuit. First, a second level signal is sent to the second controlled terminal of the fifth data driving circuit. The second level signal can be a high level, represented by 1, so that the local data bus between the fifth data driving circuit and the fourth data driving circuit is in a low-impedance state, thereby transferring the data stored in the selected storage block to the fourth data driving circuit. Then, a second level signal is sent to the second controlled terminal of the fourth data driving circuit. The second level signal can be a high level, represented by 1, so that the local data bus between the fourth data driving circuit and the third data driving circuit is in a low-impedance state, thereby transferring the data stored in the selected storage block to the third data driving circuit... Finally, a second level signal is sent to the second controlled terminal of the fifth data driving circuit. The second level signal can be a high level, represented by 1, so that the local data bus between the first data driving circuit and the data holding circuit is in a low-impedance state, thereby transferring the data stored in the selected storage block to the data holding circuit. The distances between the first data driving circuit to the fifth data driving circuit and the data holding circuit increase in sequence.

[0086] When sending the second switching signal, it is sent in order from closest to the data holding circuit to furthest away. For example, if the selected memory block is the memory block connected to the fifth data driver circuit, first, a first-level signal is sent to the second controlled terminal of the sixth data driver circuit. The first-level signal can be a low level, represented by 0, causing the local data bus between the sixth and fifth data driver circuits to be in a high-impedance state. Then, a first-level signal is sent to the second controlled terminal of the seventh data driver circuit. The first-level signal can be a low level, represented by 0, causing the local data bus between the seventh and sixth data driver circuits to be in a low-impedance state. Finally, a first-level signal is sent to the second controlled terminal of the Nth data driver circuit. The first-level signal can be a low level, represented by 0, causing the local data bus between the N-1th data driver circuit and the Nth data holding circuit to be in a low-impedance state. This prevents data in the holding circuit from being corrupted due to the local data bus between the remote data driver circuits first being in a low-impedance state. The distances between the fifth to Nth data driver circuits and the data holding circuit increase in sequence.

[0087] In order to further reduce the power consumption of the memory, the dynamic power consumption of the memory can be reduced in the non-read state. In a feasible embodiment, the logic controller can send a second switch signal to the second controlled end of the data driving circuit in response to a non-data read instruction or a non-chip select enable signal. For example, when the logic controller receives a non-chip select enable signal or a data write instruction, it can send a first level signal to all data driving circuits. The first level signal can be a low level, represented by 0, so that the entire output data path is in a high-impedance state, and the memory will not flip due to changes in the storage block address, thereby reducing dynamic power consumption. Reducing power consumption in the non-read state does not affect the read performance of the memory. Therefore, when a read operation is required, the memory can still work normally and efficiently.

[0088] See Figure 11The overall process of the operation method provided by the present application is described. Only after receiving a data read instruction will the logic control circuit send a switch signal to the data driver circuit to reconfigure its state. Otherwise, the state of all data driver circuits is high-impedance, thereby reducing the dynamic power consumption of the memory. After receiving the data read instruction, the logic control circuit can determine the corresponding storage block according to the data read instruction and, by sending a selection signal to the first controlled terminal of the data driver circuit, configure the data driver circuit connected to the selected storage block to output the data at the second input terminal, that is, output the data stored in the selected storage block. Then, the non-target data driver circuit is configured to output the data at the first input terminal, so that only the data stored in the selected storage block can be transmitted to the data driver circuit. After the data output by the selected storage block stabilizes, the state of the target data driver circuit group is configured to be low-impedance by sending a switch signal to the second controlled terminal of the data driver circuit, thereby transmitting the data stored in the storage block to the data output terminal via the local data bus. The target data driver circuit group refers to the data driver circuit between the data driver circuit connected to the selected storage block and the data output terminal. The state of the non-target data driving circuit group is configured to be a high-impedance state to reduce the power consumption of the memory. The non-target data driving circuit group refers to the data driving circuit in the peripheral circuit that does not belong to the target data driving circuit group.

[0089] Those skilled in the art will appreciate that the modules and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0090] In the several embodiments provided in this application, it should be understood that the disclosed drivers and electronic devices can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the module division is merely a logical functional division. In actual implementation, there may be other division methods, such as multiple modules or components can be combined or integrated into another device, or some features can be ignored or not implemented. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be through some interface, indirect coupling or communication connection of devices or modules, and can be electrical, mechanical, or other forms.

[0091] The modules described as separate components may or may not be physically separate, and the components shown as modules may or may not be physical modules, that is, they may be located on a single device or distributed across multiple devices. Some or all of the modules may be selected to achieve the purpose of this embodiment based on actual needs.

[0092] In addition, the functional modules in the various embodiments of the present application may be integrated into one device, or each module may exist physically separately, or two or more modules may be integrated into one device.

[0093] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using a software program, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loading and executing computer program instructions on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website, computer, server or data center by wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) mode to another website, computer, server or data center. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that contains one or more media that can be integrated. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a DVD), or a semiconductor medium (eg, a solid state disk (SSD)).

[0094] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A peripheral circuit, characterized in that: The peripheral circuit includes: a data output terminal, a plurality of local data buses and a plurality of data driving circuits, wherein the data driving circuit includes an output terminal, a first input terminal and a second input terminal; An output terminal of a first data driving circuit among the multiple data driving circuits is connected to a data output terminal via a first local data bus, an output terminal of an (i+1)th data driving circuit is connected to a first input terminal of an (i+1)th data driving circuit via an (i+1)th local data bus, and a second input terminal of any of the data driving circuits is connected to a storage block corresponding to the data driving circuit, where i is an integer greater than or equal to 1 and less than n, and n is the number of the data driving circuits in the peripheral circuit; The data driving circuit is used to operate in a low-resistance state or a high-resistance state. When the data driving circuit operates in the low-resistance state, the data input to the first input end of the data driving circuit or the data input to the second input end of the data driving circuit is output through the output end of the data driving circuit.

2. The peripheral circuit according to claim 1, wherein: When the data stored in the storage block connected to the mth data driving circuit is read through the peripheral circuit, the mth data driving circuit is configured to output the data inputted at the second input terminal through the output terminal, the 1st to m-1th data driving circuits are configured to output the data inputted at the first input terminal through the output terminal, and the m+1th to nth data driving circuits are configured to output the data inputted at the first input terminal through the output terminal.

3. The peripheral circuit according to claim 1 or 2, characterized in that: The data driving circuit further includes a second controlled terminal, the second controlled terminal being used to input a switching signal, and the data driving circuit is configured to be in a high-impedance state or a low-impedance state in response to the switching signal.

4. The peripheral circuit according to any one of claims 1 to 3, characterized in that: The data driving circuit further includes a first controlled terminal for inputting a storage block selection signal. The data driving circuit selectively outputs data inputted from the first input terminal or data inputted from the second input terminal in response to the storage block selection signal.

5. The peripheral circuit according to any one of claims 1 to 4, characterized in that: The data driving circuit includes a selection circuit and a switch circuit, the selection circuit includes an output terminal, a first input terminal, a second input terminal and a first control terminal, and the switch circuit includes an input terminal, an output terminal and a second control terminal; The first input terminal of the selection circuit is connected to the first input terminal of the data driving circuit, the second input terminal of the selection circuit is connected to the second input terminal of the data driving circuit, the first control terminal of the selection circuit is connected to the first controlled terminal of the data driving circuit, and the output terminal of the selection circuit is connected to the input terminal of the switch circuit; The second control end of the switch circuit is connected to the second controlled end of the data driving circuit, and the output end of the switch circuit is connected to the output end of the data driving circuit.

6. The peripheral circuit according to any one of claims 1 to 5, characterized in that: The peripheral circuit further includes a holding circuit, and the holding circuit is arranged between the output end of the first data driving circuit and the data output end of the peripheral circuit.

7. The peripheral circuit according to claim 6, wherein: The holding circuit includes any one of a level-triggered latch, an edge-triggered latch, or a positive feedback latch-type holding circuit.

8. A method for operating a memory, characterized in that: Applicable to a logic control circuit, the logic control circuit being coupled to the peripheral circuit according to any one of claims 1 to 7, the peripheral circuit comprising: a data output terminal, a plurality of local data buses, and a plurality of data driving circuits, the data driving circuit comprising an output terminal, a first input terminal, and a second input terminal; An output terminal of a first data driving circuit among the multiple data driving circuits is connected to a data output terminal via a first local data bus, an output terminal of an (i+1)th data driving circuit is connected to a first input terminal of an (i+1)th data driving circuit via an (i+1)th local data bus, and a second input terminal of any of the data driving circuits is connected to a storage block corresponding to the data driving circuit, where i is an integer greater than or equal to 1 and less than n, and n is the number of the data driving circuits in the peripheral circuit; The method comprises: Configuring the mth data driving circuit to output data from the second input terminal; The 1st to mth data driving circuits are configured to be in a low resistance state, and the m+1th to nth data driving circuits are configured to be in a high resistance state to read data stored in a memory block connected to the mth data driving circuit.

9. The method according to claim 8, characterized in that The data driving circuit further includes a second controlled terminal, the second controlled terminal being configured to input a switching signal, and the data driving circuit is configured to be in a high-impedance state or a low-impedance state in response to the switching signal. The configuring the first to mth data driving circuits to be in a low-impedance state and the configuring the m+1th to nth data driving circuits to be in a high-impedance state includes: sending a first switching signal to the second controlled terminals of the first to mth data driving circuits, wherein the data driving circuits are configured to be in a low-impedance state in response to the first switching signal; A second switching signal is sent to the second controlled terminals of the (m+1)th to (n)th data driving circuits, and the data driving circuits are configured to be in a high-impedance state in response to the second switching signal.

10. The method according to claim 9, characterized in that: The sending of the first switching signal to the second controlled terminals of the first to mth data driving circuits includes: The first switching signal is sent to the second controlled end of the data driving circuit in sequence from the mth data driving circuit to the first data driving circuit.

11. The method according to claim 8, characterized in that: The data driving circuit further includes a first controlled terminal, the first controlled terminal being used to input a storage block selection signal, and the data driving circuit selectively outputs data input from the first input terminal or data input from the second input terminal in response to the storage block selection signal; configuring the mth data driving circuit to output data from the second input terminal, and configuring the 1st to m-1th, and m+1th to nth data driving circuits to output data from the first input terminal comprises: sending a first selection signal to the first controlled terminals of the 1st to m-1th data driving circuits and the m+1th to nth data driving circuits, wherein the data driving circuits are configured to select and output data inputted from the first input terminals in response to the first selection signal; A second selection signal is sent to the first controlled terminal of the mth data driving circuit, and the data driving circuit is configured to output data inputted from the second input terminal in response to the second selection signal.

12. A memory, characterized in that: The memory includes a peripheral circuit, a storage block coupled to the peripheral circuit, and a logic control circuit. The peripheral circuit is the peripheral circuit according to any one of claims 1 to 7.

13. A storage system, characterized in that: The invention comprises a memory controller and the memory according to claim 12 , wherein the memory controller is configured to control the memory.

14. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer-executable instructions; after the computer-executable instructions are executed, the method according to any one of claims 8 to 11 can be implemented.

15. A computer device, characterized in that: The method comprises a processor and a readable storage medium coupled to the processor, wherein the readable storage medium stores executable instructions. When the executable instructions are executed by the processor, the method according to any one of claims 8 to 11 can be implemented.

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