Failure chip screening method

Abstract

The invention provides a failure chip screening method, which comprises the following steps that a chip to be tested is provided, the chip comprises a substrate, gate structures located on the substrate and an ion implantation region, each gate structure comprises a gate oxide layer, a floating gate, an ONO layer, a control gate and word line grids, a plurality of word line grids in the same row are connected to form a word line, and the ion implantation region is located on the substrate; the plurality of control gates in the same row are connected to form a control line, the ion implantation regions in the same column are connected to form a bit line, and one word line gate, one control gate, one floating gate and one ion implantation region on one side form a storage unit; performing erasing operation on the storage unit; a first voltage and a second voltage are applied to the bit line and the control line, the voltage difference between the first voltage and the second voltage is larger than 8.2 V, the voltage difference between the first voltage and the floating gate voltage is smaller than the breakdown voltage of the gate oxide layer, the first voltage is larger than 0, and the second voltage is smaller than 0; and performing a write 00 operation and a read 00 operation on the storage unit, and if the read value is not 00, determining that the chip is invalid.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for screening failed chips. Background Art

[0002] During chip production, a small number of defective chips may occur due to process or design issues. Failure to effectively screen out these defective chips and ensure their distribution to customers increases the difficulty and cost of resolving the issues later. NORD flash memory is a component within a chip, and its failure can directly cause the failure of the chip itself. Multiple NORD flash memories can exist on a single wafer, arranged in rows and columns.

[0003] Please refer to Figure 1 The prior art NORD flash memory comprises a substrate 101 and a plurality of gate structures spaced apart on the substrate 101. The gate structures are arranged in multiple rows in a first direction and multiple columns in a second direction, with the first and second directions being perpendicular to each other. Each gate structure comprises a gate oxide layer 102, a floating gate 103, an ONO layer 104, a control gate 105, a wordline gate 106, a first spacer 107, and a second spacer 108. The gate oxide layer 102 is located on the surface of the substrate 101. The floating gate 103, the ONO layer 104, and the control gate 105 are located on a portion of the surface of the gate oxide layer 102. Wordline openings are formed within the floating gate 103, the ONO layer 104, and the control gate 105. The wordline gate 106 is located within the wordline opening and is separated from the sidewalls of the floating gate 103 and the sidewalls of the ONO layer 104 by a first spacer 107. The wordline gate 106 is further separated from the sidewalls of the control gate 105 by a first spacer 107 and a second spacer 108. It also includes a first ion implantation region 109 and a second ion implantation region 110. The first ion implantation region 109 is located in the substrate 101 on one side of the gate structure, and the second ion implantation region 110 is located in the substrate 101 on the other side of the gate structure. Wordline gates 106 connected in the same row in the first direction become wordlines, and control gates 105 connected in the same row become control lines, with one control line on each side of each wordline. The first ion implantation regions 109 connected in the same column in the second direction become first bitlines, and the second ion implantation regions 110 connected in the same column in the second direction become second bitlines.

[0004] However, as the area of ​​devices becomes smaller and smaller, the distance between the control gate and the bit line becomes closer and closer, which may lead to a weak connection between the control gate and the bit line, thereby reducing the quality and yield of the chip. Summary of the Invention

[0005] The object of the present invention is to provide a method for screening failed chips, which can screen out chips with weak connections between control gates and bit lines in advance, thereby improving the quality and pass rate of chips.

[0006] In order to achieve the above object, the present invention provides a method for screening failed chips, comprising:

[0007] A chip to be tested is provided, the chip comprising a substrate, gate structures arranged in multiple rows and columns on the substrate, and ion implantation regions within the substrate on both sides of each gate structure, each gate structure comprising: a gate oxide layer, a floating gate, an ONO layer, a control gate, and a wordline gate, the gate oxide layer being located on a surface of the substrate, the floating gate, the ONO layer, and the control gate being located sequentially on a surface of a portion of the gate oxide layer, wordline gates being formed within the floating gate, the ONO layer, and the control gate, multiple wordline gates in the same row being connected to form a word line, multiple control gates in the same row being connected to form a control line, and ion implantation regions in the same column being connected to form a bit line, and a wordline gate, a control gate, a floating gate, and an ion implantation region on one side forming a storage unit;

[0008] Performing an erasing operation on all the memory cells so that the charges of all the floating gates are positive;

[0009] Applying a first voltage and a second voltage to the bit line and the control line, respectively, wherein a voltage difference between the first voltage and the second voltage is greater than 8.2V and a voltage difference between the first voltage and the floating gate voltage is less than a breakdown voltage of the gate oxide layer, wherein the first voltage is greater than 0 and the second voltage is less than 0;

[0010] The write 00 operation and the read 00 operation are sequentially performed on all the storage units. If the read value is not 00, the chip fails.

[0011] Optionally, in the method for screening failed chips, the gate structure further includes a first side wall and a second side wall, the word line gate is separated from the side wall of the floating gate and the side wall of the ONO layer by the first side wall, and the word line gate is also separated from the side wall of the control gate by the first side wall and the second side wall respectively.

[0012] Optionally, in the method for screening failed chips, the first voltage is 0 to 8V.

[0013] Optionally, in the method for screening failed chips, the second voltage is 0 to -20V.

[0014] Optionally, in the failed chip screening method, the calculation method of the voltage difference between the first voltage and the floating gate voltage includes: V = -Vcg*CR + Vfg + Vbl, wherein V is the voltage difference between the first voltage and the floating gate voltage, Vcg is the second voltage, CR is the voltage coupling ratio from the control gate to the floating gate, Vfg is the floating gate voltage, and Vbl is the absolute value of the first voltage.

[0015] Optionally, in the method for screening failed chips, the voltage coupling rate from the control gate to the floating gate is 30% to 40%.

[0016] Optionally, in the method for screening failed chips, the breakdown voltage of the gate oxide layer is 7.5V to 10V.

[0017] Optionally, in the method for screening failed chips, the read value being non-00 includes: the read value being 01 or 11.

[0018] Optionally, in the method for screening failed chips, the method of performing an erasing operation on the storage unit includes:

[0019] A voltage of 0 V is applied to the control gate.

[0020] Optionally, in the method for screening failed chips, if the value read from the storage unit is "00", the chip is considered qualified.

[0021] The method for screening failed chips provided by the present invention includes: providing a chip to be tested, the chip including a substrate, a gate structure arranged in multiple rows and columns on the substrate, and an ion implantation region in the substrate on both sides of each gate structure, each gate structure including: a gate oxide layer, a floating gate, an ONO layer, a control gate, and a word line gate, the gate oxide layer being located on the surface of the substrate, the floating gate, the ONO layer, and the control gate being located on the surface of a portion of the gate oxide layer in sequence, word line gates being formed in the floating gate, the ONO layer, and the control gate, multiple word line gates in the same row being connected to form a word line, multiple control gates in the same row being connected to form a control line, and multiple control gates in the same column being connected to form a control line. The ion-implanted regions are connected to form bit lines, and a word line gate, a control gate on one side, a floating gate, and an ion-implanted region form a memory cell. An erase operation is performed on all memory cells to make the charge on all floating gates positive. A first voltage and a second voltage are applied to the bit line and control line, respectively, where the voltage difference between the first voltage and the second voltage is greater than 8.2V and the voltage difference between the first voltage and the floating gate voltage is less than the breakdown voltage of the gate oxide layer, wherein the first voltage is greater than 0 and the second voltage is less than 0. Write 00 and read 00 operations are performed on all memory cells in sequence. If the read value is not 00, the chip fails. By performing voltage tests on the bit lines and control gates in advance, chips with weak connections between the control gates and bit lines are screened out in advance, thereby improving chip quality and yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a structural diagram of NORD flash memory in the prior art;

[0023] Figure 2 is a flow chart of a method for screening failed chips according to an embodiment of the present invention;

[0024] 101 - substrate, 102 - gate oxide layer, 103 - floating gate, 104 - ONO layer, 105 - control gate, 106 - word line gate, 107 - first spacer, 108 - second spacer, 109 - first ion implantation region, 110 - second ion implantation region. DETAILED DESCRIPTION

[0025] The following is a more detailed description of the specific embodiments of the present invention with reference to schematic diagrams. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are greatly simplified and not to exact scale, and are only used for the purpose of conveniently and clearly illustrating the embodiments of the present invention.

[0026] Hereinafter, the terms "first," "second," and the like are used to distinguish between similar elements and are not necessarily used to describe a particular order or chronological sequence. It is to be understood that these terms used in this manner are interchangeable where appropriate. Similarly, if a method described herein comprises a series of steps, the order in which the steps are presented herein is not necessarily the only order in which the steps may be performed, and some of the steps described may be omitted and / or other steps not described herein may be added to the method.

[0027] Furthermore, it should be understood that when a layer (or film), region, pattern, or structure is referred to as being "on" a substrate, layer (or film), region, and / or pattern, it can be directly on another layer or substrate, and / or intervening layers can also be present. Additionally, it should be understood that when a layer is referred to as being "under" another layer, it can be directly under another layer, and / or one or more intervening layers can also be present. Additionally, references to being "on" and "under" various layers can be made based on the accompanying drawings.

[0028] Please refer to Figure 2 The present invention provides a method for screening failed chips, comprising:

[0029] S11: providing a chip to be tested, the chip comprising a substrate, gate structures arranged in multiple rows and columns on the substrate, and ion implantation regions in the substrate on both sides of each gate structure, each gate structure comprising: a gate oxide layer, a floating gate, an ONO layer, a control gate, and a word line gate, the gate oxide layer being located on a surface of the substrate, the floating gate, the ONO layer, and the control gate being located sequentially on a surface of a portion of the gate oxide layer, word line gates being formed in the floating gate, the ONO layer, and the control gate, multiple word line gates in the same row being connected to form a word line, multiple control gates in the same row being connected to form a control line, and ion implantation regions in the same column being connected to form a bit line, and a word line gate, a control gate, a floating gate, and an ion implantation region on one side forming a storage unit;

[0030] S12: performing an erase operation on all memory cells so that the charges on all floating gates are positive;

[0031] S13: applying a first voltage and a second voltage to the bit line and the control line, respectively, wherein a voltage difference between the first voltage and the second voltage is greater than 8.2V and a voltage difference between the first voltage and the floating gate voltage is less than a breakdown voltage of a gate oxide layer, wherein the first voltage is greater than 0 and the second voltage is less than 0;

[0032] S14: Perform write 00 and read 00 operations on all storage cells in sequence. If the read value is not 00, the chip fails.

[0033] First, provide a chip to be tested. The chip includes memory cells arranged in multiple rows and columns. Generally, a memory cell is composed of a word line gate, a control gate on one side, a floating gate, and an ion implantation area. Therefore, please refer to Figure 1 Specifically, the present invention comprises a substrate 101 and multiple gate structures spaced apart on the substrate 101. The multiple gate structures are arranged in multiple rows in a first direction and multiple columns in a second direction, with the first and second directions being perpendicular to each other. Each gate structure comprises a gate oxide layer 102, a floating gate 103, an ONO layer 104, a control gate 105, a wordline gate 106, a first spacer 107, and a second spacer 108. The gate oxide layer 102 is located on the surface of the substrate 101. The floating gate 103, the ONO layer 104, and the control gate 105 are located on a portion of the surface of the gate oxide layer 102. Wordline openings are formed within the floating gate 103, the ONO layer 104, and the control gate 105. The wordline gate 106 is located within the wordline opening and is separated from the sidewalls of the floating gate 103 and the sidewalls of the ONO layer 104 by a first spacer 107. The wordline gate 106 is also separated from the sidewalls of the control gate 105 by the first spacer 107 and the second spacer 108. The gate structure also includes a first ion implantation region 109 and a second ion implantation region 110. The first ion implantation region 109 is located in the substrate 101 on one side of the gate structure, and the second ion implantation region 110 is located in the substrate 101 on the other side of the gate structure. Wordline gates 106 connected in the same row in the first direction form a wordline, and control gates 105 connected in the same row form a control line. There is one control line on each side of each wordline. First ion implantation regions 109 connected in the same column in the second direction form a first bitline, and second ion implantation regions 110 connected in the same column in the second direction form a second bitline. A wordline gate 106, a control gate 105 on one side, a floating gate 103, and a first ion implantation region 109 form a memory cell. A wordline gate 106, a control gate 105 on one side, a floating gate 103, and a second ion implantation region 110 form a memory cell. Two memory cells can share a single wordline gate 106.

[0034] Next, an erase operation is performed on all memory cells, setting all memory cells to "FF" so that the charge on all floating gates is positive. This prevents breakdown between the bit line and the floating gate when the first voltage on the bit line is raised. The method for performing an erase operation on the memory cells includes applying a voltage of 0V to the control gate.

[0035] Next, a first voltage and a second voltage are applied to the bit line and the control line, respectively. The voltage difference between the first voltage and the second voltage is greater than 8.2V, and the voltage difference between the first voltage and the floating gate voltage is less than the breakdown voltage of the gate oxide. The first voltage is greater than 0, and the second voltage is less than 0. The first voltage is 0 to 8V. The second voltage is 0 to -20V. The voltage difference between the first voltage and the floating gate voltage is calculated as follows: V = -Vcg*CR + Vfg + Vbl, where V is the voltage difference between the first voltage and the floating gate voltage, Vcg is the second voltage, CR is the voltage coupling ratio from the control gate to the floating gate, Vfg is the floating gate voltage, and Vbl is the absolute value of the first voltage. The voltage coupling ratio from the control gate to the floating gate is 30% to 40%. The breakdown voltage of the gate oxide is 7.5V to 10V.

[0036] Next, all memory cells are sequentially written with 00 and read with 00. This is because if there is a weak connection between the bit line and the control gate, a breakdown may cause the write to 00 to fail. Therefore, if the read value is not 00, it proves that there is a weak connection between the bit line and the control gate. At this time, the chip can be judged to be failed and the chip can be screened out in advance. Among them, the read value non-00 includes: the read value is 01 or 11, and as long as the read value is 01 or 11, the chip can be judged to be failed. As long as there is a non-00 value in any memory cell, the chip is considered failed. If the read value of all memory cells is 00, it proves that there is no weak connection between the bit line and the control gate, and the chip is considered qualified. The chip can be supplied to the terminal for use. Therefore, performing this chip testing in advance before supplying to the terminal can improve the quality of the chip and reduce the probability of the terminal having a weak connection between the bit line and the control gate.

[0037] In summary, the method for screening failed chips provided in an embodiment of the present invention includes: providing a chip to be tested, the chip including a substrate, gate structures arranged in multiple rows and columns on the substrate, and ion implantation regions in the substrate on both sides of each gate structure, each gate structure including: a gate oxide layer, a floating gate, an ONO layer, a control gate, and a word line gate, the gate oxide layer being located on the surface of the substrate, the floating gate, the ONO layer, and the control gate being located on the surface of a portion of the gate oxide layer in sequence, word line gates being formed in the floating gate, the ONO layer, and the control gate, multiple word line gates in the same row being connected to form a word line, and multiple control gates in the same row being connected to form a control line, Ion-implanted regions in the same column are connected to form a bit line. A word line gate, a control gate on one side, a floating gate, and an ion-implanted region form a memory cell. An erase operation is performed on all memory cells to ensure that all floating gates have a positive charge. A first voltage and a second voltage are applied to the bit line and control line, respectively. The voltage difference between the first and second voltages is greater than 8.2V, and the voltage difference between the first voltage and the floating gate voltage is less than the breakdown voltage of the gate oxide. The first voltage is greater than 0 and the second voltage is less than 0. Write 00 and read 00 operations are performed on all memory cells in sequence. If the read value is not 00, the chip fails. By pre-testing the voltage of the bit line and control gate, chips with weak connections between the control gate and bit line are screened out, thereby improving chip quality and yield.

[0038] The above description is merely a preferred embodiment of the present invention and does not limit the present invention in any way. Any person skilled in the art who, without departing from the scope of the present invention, makes any equivalent substitution, modification, or other changes to the technical solution and technical content disclosed in the present invention shall be deemed to be within the scope of the present invention and still fall within the scope of protection of the present invention.

Claims

1. A method for screening failed chips, characterized in that: include: A chip to be tested is provided, the chip comprising a substrate, gate structures arranged in multiple rows and columns on the substrate, and ion implantation regions within the substrate on both sides of each gate structure, each gate structure comprising: a gate oxide layer, a floating gate, an ONO layer, a control gate, and a wordline gate, the gate oxide layer being located on a surface of the substrate, the floating gate, the ONO layer, and the control gate being located sequentially on a surface of a portion of the gate oxide layer, wordline gates being formed within the floating gate, the ONO layer, and the control gate, multiple wordline gates in the same row being connected to form a word line, multiple control gates in the same row being connected to form a control line, and ion implantation regions in the same column being connected to form a bit line, and a wordline gate, a control gate, a floating gate, and an ion implantation region on one side forming a storage unit; Performing an erasing operation on all the memory cells so that the charges of all the floating gates are positive; Applying a first voltage and a second voltage to the bit line and the control line, respectively, wherein a voltage difference between the first voltage and the second voltage is greater than 8.2V and a voltage difference between the first voltage and the floating gate voltage is less than a breakdown voltage of the gate oxide layer, wherein the first voltage is greater than 0 and the second voltage is less than 0; The write 00 operation and the read 00 operation are sequentially performed on all the storage units. If the read value is not 00, the chip fails.

2. The method for screening failed chips according to claim 1, wherein: The gate structure also includes a first sidewall and a second sidewall. The word line gate is separated from the sidewall of the floating gate and the sidewall of the ONO layer by the first sidewall. The word line gate is also separated from the sidewall of the control gate by the first sidewall and the second sidewall.

3. The method for screening failed chips according to claim 1, wherein: The first voltage is 0-8V.

4. The method for screening failed chips according to claim 1, wherein: The second voltage is 0 to -20V.

5. The method for screening failed chips according to claim 1, wherein: A method for calculating the voltage difference between the first voltage and the floating gate voltage includes: V=-Vcg*CR+Vfg+Vbl, wherein V is the voltage difference between the first voltage and the floating gate voltage, Vcg is the second voltage, CR is the voltage coupling ratio from the control gate to the floating gate, Vfg is the floating gate voltage, and Vbl is the absolute value of the first voltage.

6. The method for screening failed chips according to claim 5, wherein: The voltage coupling rate from the control gate to the floating gate is 30% to 40%.

7. The method for screening failed chips according to claim 1, wherein: The breakdown voltage of the gate oxide layer is 7.5V to 10V.

8. The method for screening failed chips according to claim 1, wherein: The read value is not 00, including: the read value is 01 or 11.

9. The method for screening failed chips according to claim 1, wherein: The method for performing an erasing operation on the storage unit includes: A voltage of 0 V is applied to the control gate.

10. The method for screening failed chips according to claim 1, wherein: If the value read from the storage unit is "00", the chip is considered qualified.

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