Semiconductor device and method of repair wafer

Abstract

A method of repairing a wafer includes grinding the wafer to form a damaged layer on a surface of the wafer, performing a first annealing process to convert a lower portion of the damaged layer into a regrown layer, and the regrown layer on the wafer, forming a metal layer on the damaged layer, and performing a second annealing process to convert the damaged layer and the metal layer into an alloy layer, and the alloy layer is arranged on the regrowth layer. According to the method, cracks caused by a wafer thinning process can be eliminated.

Description

Technical Field

[0001] Some embodiments of the present disclosure relate to a semiconductor device and a method for repairing a wafer. Background Art

[0002] Silicon carbide components are one of the most common semiconductor components. They have the advantages of high bandgap, high thermal conductivity and high breakdown electric field. The resistance of a silicon carbide component can be composed of the resistance of multiple parts in the component, such as the resistance of the contact, channel, gate, junction field effect transistor region, and substrate. Among them, in order to reduce the resistance of the substrate, after the integrated circuit is formed on the front of the wafer, the back of the wafer can be ground to reduce the thickness of the wafer. However, when grinding the wafer, it may cause the wafer to warp, which is not conducive to the subsequent processing of the wafer. Summary of the Invention

[0003] Some embodiments of the present disclosure provide a method for repairing a wafer, comprising grinding the wafer to form a damaged layer on the surface of the wafer, performing a first annealing process to convert a lower portion of the damaged layer into a regrown layer, with the regrown layer being on the wafer, forming a metal layer on the damaged layer, and performing a second annealing process to convert the damaged layer and the metal layer into an alloy layer, with the alloy layer being on the regrown layer.

[0004] In some embodiments, the first annealing process is an ultraviolet laser annealing process.

[0005] In some embodiments, the wafer has a first crystalline structure, the regrown layer has a second crystalline structure, and the first crystalline structure is different from the second crystalline structure.

[0006] In some embodiments, the temperature of the first annealing process is between 900 and 1300 degrees Celsius.

[0007] In some embodiments, a portion of the damaged layer is not converted into the alloy layer when the second annealing process is performed, and the portion of the damaged layer is between the alloy layer and the regrown layer after the second annealing process is performed.

[0008] In some embodiments, when performing the first annealing process, a portion of the damaged layer is not converted into the regrown layer, and the portion of the damaged layer is below the regrown layer, and after performing the first annealing process, the portion of the damaged layer is between the wafer and the regrown layer.

[0009] In some embodiments, the thickness of the portion of the damaged layer is less than the thickness of the regrown layer.

[0010] Some embodiments of the present disclosure provide a semiconductor device comprising a silicon carbide wafer, a crystallized silicon carbide layer, and an alloy layer. The silicon carbide wafer has a first crystal structure. The crystallized silicon carbide layer is formed on the silicon carbide wafer, and the crystallized silicon carbide layer has a second crystal structure, wherein the first crystal structure of the silicon carbide wafer is different from the second crystal structure of the crystallized silicon carbide. The alloy layer is formed on the crystallized silicon carbide layer.

[0011] In some embodiments, the semiconductor device further includes an amorphous silicon carbide layer between the silicon carbide wafer and the crystalline silicon carbide layer.

[0012] In some embodiments, the semiconductor device further includes an amorphous silicon carbide layer between the alloy layer and the crystalline silicon carbide layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figures 1 to 5 A cross-sectional view illustrating a method of repairing a wafer according to some embodiments of the present disclosure is shown.

[0014] Figure 6 1 is a cross-sectional view illustrating a method of repairing a wafer 110 according to another embodiment of the present disclosure.

[0015] Figure 7 1 is a cross-sectional view illustrating a method of repairing a wafer 110 according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0016] Some embodiments of the present disclosure provide a method for repairing wafer damage. This wafer damage may result from a wafer thinning process. Specifically, the present disclosure uses an annealing process to convert the amorphous structure in the damaged layer into a crystalline structure, thereby eliminating cracks caused by the wafer thinning process.

[0017] Figures 1 to 5 FIG2 is a cross-sectional view illustrating a method of repairing a wafer 110 according to some embodiments of the present disclosure. Figure 1 , providing a wafer 110. Wafer 110 can be any suitable wafer. In some embodiments, wafer 110 can be a silicon carbide wafer, and wafer 110 has a first crystalline structure.

[0018] refer to Figure 2, the wafer 110 is ground to form a damaged layer 120 on the surface of the wafer 110. The purpose of grinding the wafer 110 is to reduce the thickness of the wafer 110 to the thickness required by subsequent processes. In some embodiments, after grinding the wafer 110, the thickness of the wafer 110 can be reduced to less than half of its original thickness. In some embodiments, the wafer 110 can be ground using a grinding wheel or any suitable method. When grinding the wafer 110, the grinding process equipment will damage the surface of the wafer 110, for example, causing uneven stress on the surface of the wafer 110, and forming a damaged layer 120 on the surface of the wafer 110. In the damaged layer 120, the original crystalline structure of the wafer 110 is destroyed, so that the damaged layer 120 may have vertical cracks. Therefore, the damaged layer 120 does not have a crystalline structure. That is, the damaged layer 120 is an amorphous layer. In an embodiment where the wafer 110 is silicon carbide, the damaged layer 120 is an amorphous silicon carbide layer. In some embodiments, the thickness of the damaged layer 120 is between 300 nm and 700 nm. It should be noted that since the damaged layer 120 is caused by uneven stress, Figure 2 While the damaged layer 120 is depicted as a flat layer, in reality, the thickness of the damaged layer 120 varies. When the damaged layer 120 is present, the wafer 110 is susceptible to warping. A warped wafer 110 can cause problems in subsequent processes. For example, a warped wafer 110 can damage other wafers 110 during transfer. It can also prevent the warped wafer 110 from being cut into a perfect shape.

[0019] refer to Figure 3A first annealing process is performed to convert the lower portion of the damaged layer 120 into a regrown layer 130, and the regrown layer 130 is located on the wafer 110. Specifically, the first annealing process is an ultraviolet laser annealing process. The ultraviolet laser annealing process can provide sufficient heat at a relatively shallow depth, and the ultraviolet light easily couples with non-mirror surfaces (such as the surface of the damaged layer 120). Therefore, it is suitable for repairing the damaged layer 120 located on the surface of the wafer 110. In some embodiments, when performing the first annealing process, the energy of the ultraviolet laser can be controlled so that the ultraviolet laser hits the lower portion of the damaged layer 120 (for example, at a depth of approximately 600 to 700 nanometers). The heat provided by the first annealing process can repair cracks in the lower portion of the damaged layer 120 and rearrange the atoms in the lower portion of the damaged layer 120 to form a regrown layer 130 having a second crystal structure. The first crystal structure of the wafer 110 and the second crystal structure of the regrown layer 130 are different, and there is a clear boundary between the two. In some embodiments, the temperature of the first annealing process is between 900 and 1300 degrees Celsius, and the temperature of the first annealing process (i.e., the melting temperature of the damaged layer 120) is lower than the melting temperature of the wafer 110. Therefore, the temperature of the first annealing process disclosed above can ensure that cracks in the damaged layer 120 are repaired while still not damaging the crystal structure of the wafer 110. Due to the heat transfer limitations of the heat provided by the first annealing process, the heat cannot be transferred to the entire damaged layer 120. Therefore, during the first annealing process, only the lower portion of the damaged layer 120 is converted into the regrown layer 130. In some embodiments, after performing the first annealing process, the ratio of the thickness T1 of the regrown layer 130 to the thickness T2 of the damaged layer 120 is between 0.5 and 1. It should be noted that because damaged layer 120 is formed by polishing wafer 110, and regrown layer 130 is formed by annealing damaged layer 120, damaged layer 120, regrown layer 130, and wafer 110 are made of the same material. For example, damaged layer 120, regrown layer 130, and wafer 110 are all made of silicon carbide. The difference between the three lies in their crystalline structures. For example, wafer 110 has a first crystalline structure, regrown layer 130 has a second crystalline structure, and damaged layer 120 has an amorphous structure. In some embodiments, regrown layer 130 may also be referred to as a crystalline silicon carbide layer.

[0020] refer to Figure 4 , a metal layer 140 is formed on the damaged layer 120. Specifically, the metal layer 140 may include any suitable metal, such as nickel.

[0021] refer to Figure 5, a second annealing process is performed to convert the damaged layer 120 and the metal layer 140 into an alloy layer 150, and the alloy layer 150 is on the regrown layer 130. Specifically, the second annealing process can react the remaining damaged layer 120 with the metal layer 140 above it to form an alloy layer 150. In some embodiments, the damaged layer 120 is made of silicon carbide, so after the second annealing process is performed, the alloy layer 150 can be a silicided metal layer. In some embodiments, the alloy layer 150 also contains carbon. Due to the heat transfer limitation of the second annealing process, if it is not Figure 3 The lower part of the damaged layer 120 is converted into the regrown layer 130. Figure 5 In the second annealing process, the heat cannot be transferred to the lower portion of the damaged layer 120, so the lower portion of the damaged layer 120 cannot react with the metal layer 140 to transform into the alloy layer 150, and the remaining damaged layer 120 may still cause the wafer 110 to warp. Figure 3 The lower portion of the damaged layer 120 has been converted into the regrown layer 130. Therefore, after the damaged layer 120 and the metal layer 140 are converted into the alloy layer 150, the damaged layer 120 no longer exists. The problem of wafer 110 warping can also be solved.

[0022] After forming the alloy layer 150, the semiconductor device may include a wafer 110, a regrown layer 130, and the alloy layer 150. The wafer has a first crystalline structure. The regrown layer 130 is on the wafer 110, the regrown layer and the wafer are made of the same material, and the regrown layer 130 has a second crystalline structure, wherein the first crystalline structure of the wafer is different from the second crystalline structure of the regrown layer. In some embodiments, the regrown layer 130 and the wafer 110 are both made of silicon carbide, but the regrown layer 130 and the wafer 110 have different crystalline structures. The alloy layer 150 is on the regrown layer 130. In some embodiments, the alloy layer 150 contacts the regrown layer 130, and the wafer 110 contacts the regrown layer 130. The alloy layer 150 may serve as the first conductive layer (M1) on the surface of the wafer 110, and subsequent processes may be performed on the alloy layer 150. For example, other metal layers may be deposited on the alloy layer 150, and the wafer 110 may be diced. When the warping problem of the wafer 110 is solved, the subsequent processes can be performed more smoothly. For example, when the wafer 110 is cut, the wafer 110 can be cut into regular shapes.

[0023] Figure 6 1 is a cross-sectional view illustrating a method of repairing a wafer 110 according to another embodiment of the present disclosure. Figure 6 semiconductor devices and Figure 5 The semiconductor devices are similar, the difference is Figure 6The semiconductor device further includes a damaged layer 121, the damaged layer 121 is between the wafer 110 and the regrown layer 130, and the damaged layer 121 contacts the wafer 110 and the regrown layer 130. In some embodiments, when performing the first annealing process ( Figure 3 ), a portion of the damaged layer 120 is not converted into the regrown layer 130, and a portion of the damaged layer 120 is below the regrown layer 130, and after performing the first annealing process, a portion of the damaged layer is between the wafer 110 and the regrown layer 130. A portion of the damaged layer is the damaged layer 121. In some embodiments, when the damaged layer 120 is an amorphous silicon carbide layer, the damaged layer 121 is also an amorphous silicon carbide layer. The thickness T3 of the damaged layer 121 is less than the thickness T1 of the regrown layer 130, so even if the damaged layer 121 exists, after the second annealing process, most of the damaged layer 120 has been converted into the regrown layer 130 or the alloy layer 150. Therefore, the present disclosure can still alleviate the warpage problem of the wafer 110.

[0024] Figure 7 1 is a cross-sectional view illustrating a method of repairing a wafer 110 according to another embodiment of the present disclosure. Figure 7 semiconductor devices and Figure 5 The semiconductor devices are similar, the difference is Figure 7 The semiconductor device further includes a damaged layer 122, the damaged layer 122 being between the alloy layer 150 and the regrown layer 130, and the damaged layer 122 contacts the alloy layer 150 and the regrown layer 130. In some embodiments, when the second annealing process is performed ( Figure 5 ), a portion of the damaged layer 120 is not converted into the alloy layer 150. After the second annealing process, this portion of the damaged layer 120 is located between the alloy layer 150 and the regrown layer 130. In some embodiments, when the damaged layer 120 is an amorphous silicon carbide layer, the damaged layer 122 is also an amorphous silicon carbide layer. The thickness T4 of the damaged layer 122 is less than the thickness T1 of the regrown layer 130. Therefore, even though the damaged layer 122 exists, the majority of the damaged layer 122 has been converted into the regrown layer 130 or the alloy layer 150. Therefore, the present disclosure can still mitigate the warpage problem of the wafer 110.

[0025] In summary, some embodiments of the present disclosure can be used to convert a portion of a damaged layer into a regrown layer, and then react the remaining damaged layer with a metal layer to form an alloy layer. This way, after the alloy layer is formed, the damaged layer is virtually non-existent, thereby mitigating wafer warpage. When wafer warpage is minimal, subsequent wafer operations can proceed more smoothly.

[0026] The above descriptions are only some of the embodiments of the present disclosure, not all of the embodiments. Any equivalent changes made to the technical solution of the present disclosure by a person of ordinary skill in the art after reading the specification of the present disclosure are covered by the claims of the present disclosure.

[0027]

Explanation of symbols

[0028] 110: Wafer

[0029] 120, 121, 122: Damage layer

[0030] 130: Regrowth layer

[0031] 140: Metal layer

[0032] 150: alloy layer

[0033] T1, T2, T3, T4: thickness.

Claims

1. A method for repairing a wafer, characterized in that: Include: grinding the wafer to form a damaged layer on the surface of the wafer; performing a first annealing process to convert a lower portion of the damaged layer into a regrown layer, wherein the regrown layer is on the wafer; forming a metal layer on the damaged layer; as well as A second annealing process is performed to convert the damaged layer and the metal layer into an alloy layer, wherein the alloy layer is on the regrown layer.

2. The method according to claim 1, characterized in that The first annealing process is an ultraviolet laser annealing process.

3. The method according to claim 1, characterized in that The wafer has a first crystal structure, the regrown layer has a second crystal structure, and the first crystal structure is different from the second crystal structure.

4. The method according to claim 1, wherein The temperature of the first annealing process is between 900 and 1300 degrees Celsius.

5. The method according to claim 1, wherein When the second annealing process is performed, a portion of the damaged layer is not converted into the alloy layer, and after the second annealing process is performed, the portion of the damaged layer is between the alloy layer and the regrown layer.

6. The method according to claim 1, characterized in that Wherein, when performing the first annealing process, a portion of the damaged layer is not converted into the regrown layer, and the portion of the damaged layer is below the regrown layer, and after performing the first annealing process, the portion of the damaged layer is between the wafer and the regrown layer.

7. The method according to claim 6, characterized in that The thickness of the portion of the damaged layer is smaller than the thickness of the regrown layer.

8. A semiconductor device, characterized in that: Include: a silicon carbide wafer having a first crystalline structure; a crystalline silicon carbide layer on the silicon carbide wafer, the crystalline silicon carbide layer having a second crystalline structure, wherein the first crystalline structure of the silicon carbide wafer is different from the second crystalline structure of the crystalline silicon carbide; An alloy layer is formed on the crystalline silicon carbide layer.

9. The semiconductor device according to claim 8, wherein Also includes: An amorphous silicon carbide layer is between the silicon carbide wafer and the crystalline silicon carbide layer.

10. The semiconductor device according to claim 8, wherein Also includes: An amorphous silicon carbide layer is between the alloy layer and the crystalline silicon carbide layer.

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