Manufacturing method of semiconductor structure
The method of forming a passivation layer through multiple etching and nitrogen reaction solves the necking problem in semiconductor structure manufacturing, ensures the shape stability and dimensional accuracy of the semiconductor layer, and reduces the risk of high impedance and pattern collapse.
Patent Information
- Application Number
- CN202510815239.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-12-11
- Filing Date
- 2025-06-18
- Publication Date
- 2025-09-19
AI Technical Summary
When manufacturing semiconductor structures using existing technologies, the semiconductor layer is prone to necking and footing problems during high aspect ratio etching, which affects the critical dimensions of the product and increases risks in subsequent processes.
A method of forming a passivation layer using multiple etching steps combined with nitrogen reaction is used to first etch part of the semiconductor material to form a second trench, then form a passivation layer on the sidewall, and then further etch to form a semiconductor layer to avoid necking.
It effectively reduces the risk of semiconductor layer necking, ensures the accuracy of critical dimensions, reduces the possibility of high impedance and pattern collapse, and improves the reliability of the manufacturing process.
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Figure CN120674316A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to a method for manufacturing a semiconductor structure. Background Art
[0002] Semiconductor devices benefit the electronics industry due to their small size, multifunctionality, and low manufacturing cost. However, with the rapid development of the electronics industry, the integration of semiconductor devices continues to increase. To achieve this high level of integration, the line width of semiconductor device patterns is decreasing. Summary of the Invention
[0003] One aspect of the present invention is to provide a method for manufacturing a semiconductor structure. The method includes the following steps: a substrate is recessed from its upper surface toward its lower surface to form a trench. A semiconductor material is filled in the trench. A patterned metal layer is formed on the semiconductor material and a patterned hard mask layer is formed on the patterned metal layer. Using the patterned metal layer and the patterned hard mask layer as a first etching mask, a portion of the semiconductor material is etched, wherein the remaining portion of the semiconductor material includes a first portion and a second portion located below the first portion, and the second portion is wider than the first portion. A passivation layer is formed on the sidewalls of the first portion. The passivation layer is removed, and the second portion of the remaining portion is etched using the patterned metal layer and the patterned hard mask layer as a second etching mask, thereby forming a semiconductor layer.
[0004] According to one or more embodiments, the method further includes forming a passivation layer on a sidewall of the first portion including reacting nitrogen with the first portion.
[0005] According to one or more embodiments, the passivation layer includes nitride.
[0006] According to one or more embodiments, the passivation layer has a thickness of 2.0 nm to 5.0 nm.
[0007] In accordance with one or more embodiments, a height of the first portion of the semiconductor material is at least greater than half of a total height of the semiconductor material.
[0008] According to one or more embodiments, the semiconductor layer has a uniform width.
[0009] According to one or more embodiments, the width of the semiconductor layer is the same as the width of the patterned metal layer.
[0010] According to one or more embodiments, the method further includes conformally forming an insulating layer in the trench and on the upper surface of the substrate before filling the semiconductor material in the trench.
[0011] According to one or more embodiments, the method further includes forming spacers on a plurality of sidewalls of the semiconductor layer, the patterned metal layer, and the patterned hard mask layer.
[0012] According to one or more embodiments, the spacer is in direct contact with the semiconductor layer and in direct contact with the insulating layer in the trench.
[0013] Another aspect of the present invention is to provide a method for manufacturing a semiconductor structure. The method comprises the following steps: recessing a substrate from its upper surface toward its lower surface to form a first trench; filling the first trench with a semiconductor material; forming a patterned metal layer on the semiconductor material, and forming a patterned hard mask layer on the patterned metal layer, wherein the semiconductor material includes a first portion covered by the patterned metal layer and the patterned hard mask layer, and a second portion adjacent to the first portion; partially removing the second portion of the semiconductor material to form a second trench; forming a passivation layer to cover the sidewalls of the first portion; and removing the passivation layer and the second portion of the semiconductor material to form a third trench adjacent to the first portion of the semiconductor material.
[0014] According to one or more embodiments, the method further includes forming a passivation layer to cover a sidewall of the first portion including reacting nitrogen with the first portion.
[0015] According to one or more embodiments, reacting nitrogen with the first portion is performed at a temperature of 50°C to 70°C.
[0016] According to one or more embodiments, the passivation layer includes nitride.
[0017] According to one or more embodiments, the passivation layer has a thickness of 2.0 nm to 5.0 nm.
[0018] According to one or more embodiments, the depth of the second trench is at least greater than half the depth of the third trench.
[0019] According to one or more embodiments, the third trench has a uniform depth.
[0020] According to one or more embodiments, the method further includes forming a spacer in the third trench.
[0021] According to one or more embodiments, the method further includes conformally forming an insulating layer in the first trench and on the upper surface of the substrate before filling the semiconductor material in the first trench.
[0022] According to one or more embodiments, the insulating layer is exposed from the third trench.
[0023] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] A more complete understanding of the present invention may be obtained by reading the following detailed description of embodiments and referring to the accompanying drawings.
[0025] Figure 1 is a schematic diagram of a semiconductor structure configuration according to some embodiments of the present invention.
[0026] Figures 2 to 5 2 is a schematic cross-sectional view of different steps of a method for manufacturing a semiconductor structure according to some embodiments of the present invention.
[0027] Figure 6 FIG. 4 is a schematic cross-sectional view of a method for manufacturing a semiconductor structure according to a comparative example of the present invention at a certain step.
[0028] Figures 7 to 12 2 is a schematic cross-sectional view of different steps of a method for manufacturing a semiconductor structure according to some embodiments of the present invention. DETAILED DESCRIPTION
[0029] Reference will now be made in detail to the embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.
[0030] The following specifically lists the embodiments of the present invention and describes them in detail with reference to the accompanying drawings. The elements and designs of the following embodiments are intended to simplify the disclosed invention and are not intended to limit the present invention. The specification mentions that the first structural feature is formed above the second structural feature, which includes an embodiment in which the first structural feature and the second structural feature are in direct contact, and also includes an embodiment in which there are other structural features between the first structural feature and the second structural feature, that is, the first structural feature and the second structural feature are not in direct contact. In addition, the present invention may use repeated reference symbols and / or words in various embodiments. These repeated symbols or words are for the purpose of simplicity and clarity, and are not intended to limit the relationship between the various embodiments and / or the structures.
[0031] Furthermore, for ease of description, spatially relative terms, such as "beneath," "below," "lower," "above," and "upper," may be used herein to describe the relationship of one element or feature to another element or feature illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.
[0032] refer to Figure 1 , Figure 1FIG1 is a schematic diagram illustrating a configuration of a semiconductor structure 100 according to some embodiments of the present invention. The semiconductor structure 100 may include multiple active regions ACT. The active regions ACT have a short axis and a long axis. In some embodiments, the long axis of the active regions ACT may extend along a diagonal axis relative to the X-axis.
[0033] A plurality of word lines WL may be disposed on the active area ACT and extend along the X-axis. The word lines WL may be parallel to each other and spaced apart at substantially equal intervals.
[0034] Multiple bit lines BL can be arranged above word lines WL and can extend along the Y axis. Similarly, the bit lines BL are parallel to each other. In addition, the bit lines BL can be connected to the active area ACT via direct contacts DC. One active area ACT can be electrically connected to one direct contact DC.
[0035] A plurality of buried contacts BC may be formed between two adjacent bit lines BL. In some embodiments, the buried contacts BC may be spaced apart from each other along the Y-axis. The buried contacts BC may electrically connect the lower electrode (not shown) of the capacitor to the corresponding active region ACT. One active region ACT may be electrically connected to two buried contacts BC.
[0036] A plurality of landing pads LP may be disposed above the buried contacts BC and overlap at least a portion of the corresponding bit lines BL. The landing pads may be electrically connected to the buried contacts BC. Furthermore, the landing pads LP may also electrically connect the lower electrodes (not shown) of the capacitors to the corresponding active areas ACT. In other words, the lower electrodes (not shown) of the capacitors may be electrically connected to the corresponding active areas ACT via the corresponding buried contacts BC and the corresponding landing pads LP.
[0037] In some embodiments, one buried contact BC and one landing pad LP may be collectively referred to as a contact plug, and may be respectively referred to as a first contact plug (BC) and a second contact plug (LP).
[0038] Figures 2 to 5 and Figures 7 to 12 1 is a schematic cross-sectional view of a method for manufacturing a semiconductor structure (eg, semiconductor structure 100 ) at different steps according to some embodiments of the present invention. Figures 2 to 5 and Figures 7 to 12 The schematic diagram is based on Figure 1 The cross-sectional view is taken along line AA as a reference.
[0039] Various operations of the embodiments are provided herein. The order in which some or all operations are described should not be interpreted as implying that these operations are necessarily dependent on the order. With the help of this description, alternative orderings can be understood. In addition, it should be understood that not all operations are necessarily present in every embodiment provided herein. In addition, it should be understood that not all operations are necessary in some embodiments.
[0040] See also Figure 2 , receiving a substrate 110. Specifically, the substrate 110 includes a plurality of isolation regions 102 and a plurality of active regions 104 (eg Figure 1 The active region 104 is separated by the isolation region 102.
[0041] The substrate 110 may include, for example, silicon (e.g., crystalline silicon, polycrystalline silicon, or amorphous silicon). In some embodiments, the substrate 110 may include a compound semiconductor, such as gallium arsenide, silicon carbide, indium phosphide, or indium arsenide. In some embodiments, the substrate 110 may include other elemental semiconductors, such as germanium. In some embodiments, the substrate 110 may include alloy semiconductors such as silicon germanium, silicon germanium carbide, or gallium indium phosphide. Furthermore, the substrate 110 may optionally include a semiconductor-on-insulator (SOI) structure.
[0042] The isolation region 102 can be formed by a shallow trench isolation (STI) process. The isolation region 102 may include, for example, a material including at least one of silicon oxide, silicon nitride, and silicon oxynitride. The isolation region 102 may be a single layer including one insulator, a double layer including two insulators, or a multilayer including a combination of at least three insulators. For example, the isolation region 102 may include silicon oxide and silicon nitride. For another example, the isolation region 102 may include a triple layer of silicon oxide, silicon nitride, and silicon oxynitride.
[0043] See Figure 3 The substrate 110 is recessed from the upper surface 111 of the substrate 110 toward the lower surface 113 of the substrate 110 to form a groove 120. It should be noted that the groove 120 does not penetrate the substrate 110.
[0044] See Figure 4 First, an insulating layer 130 is conformally formed in the trench 120 and on the upper surface 111 of the substrate 110. Specifically, the insulating layer 130 covers the sidewalls and bottom of the trench 120. In other words, the insulating layer 130 does not completely fill the trench 120. In some embodiments, the insulating layer 130 can be made of any suitable dielectric material, such as silicon oxide, borophospho silicate glass (BPSG), or tetraethylorthosilicate (TEOS), but the present invention is not limited to these materials.
[0045] See Figure 4, and then semiconductor material 140 is filled into trench 120. More specifically, semiconductor material 140 is formed on insulating layer 130 within trench 120. In other words, semiconductor material 140 fills the remaining space within trench 120. In some embodiments, a top surface 143 of semiconductor material 140 is flush with a top surface 132 of insulating layer 130 disposed on upper surface 111 of substrate 110. In some embodiments, semiconductor material 140 includes polysilicon. In some embodiments, semiconductor material 140 may be doped.
[0046] See Figure 4 Next, a metal layer 150 is formed on the insulating layer 130 and the semiconductor material 140. More specifically, the metal layer 150 completely covers the insulating layer 130 and the semiconductor material 140. In some embodiments, the metal layer 150 may include tungsten, copper, aluminum, tantalum, titanium, and / or combinations thereof.
[0047] See Figure 4 , a hard mask 160 is continuously formed on the metal layer 150. More specifically, the hard mask 160 completely covers the metal layer 150. In some embodiments, the hard mask 160 may include a dielectric material, such as, but not limited to, silicon nitride. In some embodiments, the thickness of the hard mask 160 (e.g., the height along the Z-axis) may be greater than the thickness of the metal layer 150.
[0048] See Figure 5 The metal layer 150 and the hard mask 160 are patterned to form a first patterned metal layer 152 on the insulating layer 130, a second patterned metal layer 151 on the semiconductor material 140, a first patterned hard mask 162 on the first patterned metal layer 152, and a second patterned hard mask 161 on the second patterned metal layer 151. Specifically, the first patterned metal layer 152 is in direct contact with the insulating layer 130 on the upper surface 111 of the substrate 110. In some embodiments, the first patterned metal layer 152 and the first patterned hard mask 162 have a uniform and identical width W1. The first patterned metal layer 152 and the first patterned hard mask 162 constitute a first bitline structure 172.
[0049] See Figure 5, the second patterned metal layer 151 is in direct contact with the semiconductor material 140 within the trench 120. In some embodiments, the second patterned metal layer 151 and the second patterned hard mask 161 have a uniform and identical width W2. It should be understood that the width W2 of the second patterned metal layer 151 is less than the width W3 of the semiconductor material 140. In other words, the second patterned metal layer 151 only covers a portion of the top surface 143 of the semiconductor material 140. In other words, after forming the second patterned metal layer 151 and the second patterned hard mask 161, a portion of the top surface 143 of the semiconductor material 140 is exposed. On the other hand, the semiconductor material 140 can include a first portion 147 covered by the second patterned metal layer 151 and the second patterned hard mask 161, and a second portion 148 adjacent to the first portion. In other words, a vertical projection of the first portion 147 on the substrate 110 overlaps with a vertical projection of the second patterned metal layer 151 on the substrate 110.
[0050] Figure 6 2 is a schematic cross-sectional view of a method for manufacturing a semiconductor structure according to a comparative example of the present invention at a certain step. The semiconductor material is etched in one step to form a semiconductor layer 240, such as Figure 6 However, the semiconductor layer 240 is prone to necking problems, such as Figure 6 As shown. It should be understood that one of the challenges of etching is the increasing aspect ratio required to meet design requirements, especially for ultra-high density structures. Therefore, the difficulty in the high aspect ratio (HAR) etching process lies in the distortion or deformation, which is generally defined as the deviation of the position, orientation, shape and size near the bottom of the feature from the pattern defined by the mask at the top of the feature. For example, the semiconductor layer 240 obtained after etching has an undesirable "necking" or "footing" profile. The "necking" or "footing" profile will further affect the difference in the critical dimension (CD) of the product and increase the risk of high impedance or pattern collapse in subsequent processes.
[0051] Therefore, the following etching steps are employed to reduce the possibility of "necking" or "footing" the profile. Figures 7 to 12 2 is a schematic cross-sectional view of different steps of a method for manufacturing a semiconductor structure according to some embodiments of the present invention. Figure 7 Continued Figure 5 See Figure 7, using the second patterned metal layer 151 and the second patterned hard mask 161 as a first etching mask, a portion of the semiconductor material 140 is etched, so that the remaining portion of the semiconductor material 140 includes the first portion 141 and the second portion 142 located below the first portion 141, and the second portion 142 is wider than the first portion 141. Specifically, the width W4 of the first portion 141 of the semiconductor material 140 is the same as the width W2 of the second patterned metal layer 151. The width of the second portion 142 is still W3. In other words, the width W3 of the second portion 142 is greater than the width W4 of the first portion 141. In some embodiments, the height H1 of the first portion 141 of the semiconductor material 140 is at least greater than half the total height HT of the semiconductor material 140. In this way, excessive side-etching of the semiconductor material 140 can be prevented.
[0052] In other words, the second portion 148 of the semiconductor material 140 is partially removed to form the second trench 122. The second trench 122 does not penetrate the semiconductor material 140. The second trench 122 surrounds the first portion 147 of the semiconductor material 140. In some embodiments, the second trench 122 has a depth D1.
[0053] See Figure 8 , and then forming a passivation layer 180 on the sidewalls of the first portion 141 of the semiconductor material 140. In other words, the passivation layer 180 is then formed to cover the sidewalls of the first portion 147 of the semiconductor material 140. In some embodiments, the nitrogen gas reacts with the surface of the first portion 141 of the semiconductor material 140 to form the passivation layer 180 on the sidewalls of the first portion 141. In other words, the nitrogen gas reacts with the surface of the first portion 147 of the semiconductor material 140 to form the passivation layer 180 on the sidewalls of the first portion 147. In some embodiments, the passivation layer 180 includes a nitride, such as silicon nitride. In some embodiments, the thickness T1 of the passivation layer 180 is about 2.0 nm to about 5.0 nm, such as 2.2 nm, 2.4 nm, 2.6 nm, 2.8 nm, 3.0 nm, 3.2 nm, 3.4 nm, 3.6 nm, 3.8 nm, 4.0 nm, 4.2 nm, 4.4 nm, 4.6 nm, or 4.8 nm. In some embodiments, the reaction of nitrogen with the first portion 147 (or the first portion 141) is performed at a temperature of 50°C to 70°C.
[0054] See Figure 9, the passivation layer 180 is removed and the remaining second portion 142 is etched using the second patterned metal layer 151 and the second patterned hard mask 161 as a second etching mask, thereby forming the semiconductor layer 145 below the second patterned metal layer 151. In other words, the passivation layer 180 and the second portion 148 of the semiconductor material 140 are removed to form the third trench 123 adjacent to the first portion 147 of the semiconductor material 140. In some embodiments, the second trench 122 (e.g. Figure 7 The depth D1 of the third trench 123 is at least greater than half the depth D2 of the third trench 123. In some embodiments, the semiconductor layer 145 has a uniform width. In some embodiments, the width W5 of the semiconductor layer 145 is the same as the width W2 of the second patterned metal layer 151. At this time, the second patterned metal layer 151, the second patterned hard mask 161 and the semiconductor layer 145 constitute a second bit line structure 174. In some embodiments, the semiconductor layer 145 is spaced a certain distance from the insulating layer 130 in the trench 120 in the X-axis direction. That is, the semiconductor layer 145 in the trench 120 does not contact the insulating layer 130 in the X-axis direction. In some embodiments, the first bit line structure 172 and the second bit line structure 174 are alternately set on the substrate 110 at intervals. The two-step etching step reduces the possibility of a necking profile in the semiconductor layer. The present invention is not limited to this. For example, a three-step etching step or multiple etching steps can be performed on a bit line structure with a high aspect ratio. It will be appreciated that because a portion of the surface of the semiconductor material is protected by the passivation layer 180 , the likelihood of an undesirable necking profile may be reduced.
[0055] See Figure 10 A first spacer 192 is formed on the sidewalls of the first bitline structure 172, and a second spacer 194 is formed on the sidewalls of the second bitline structure 174. Specifically, the first spacer 192 extends along the sidewalls of the first bitline structure 172, while the second spacer 194 extends along the sidewalls of the second bitline structure 174. In other words, the first spacer 192 and the second spacer 194 extend in a direction substantially perpendicular to the substrate 110 (e.g., along the Z-axis direction). In some embodiments, each of the first spacer 192 and the second spacer 194 can be a multi-layer structure made of any suitable dielectric material. For example, the first spacer 192 and the second spacer 194 can be a three-layer structure or a four-layer structure. In some embodiments, the material of the first spacer 192 can include an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), and / or a combination thereof. In some embodiments, an air gap can be introduced into the confined space within the first spacer 192 and / or the second spacer 194, wherein the air gap has a dielectric constant of approximately 1, thereby reducing parasitic capacitance.
[0056] In some embodiments, the first spacer 192 and the second spacer 194 can be formed using any suitable deposition method, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD). In some embodiments, the first spacer 192 and the second spacer 194 can be etched using any suitable etching method, such as reactive ion etching (RIE), to form a specific configuration based on the design of the semiconductor device. For example, the heights of the layers in a multilayer structure may vary.
[0057] In some embodiments, the first spacer 192 covers a portion of the sidewall of the first patterned metal layer 152 and the sidewall of the first patterned hard mask 162, such as Figure 10 As shown. That is, the top surface of the first patterned hard mask 162 is higher than the top surface of the first spacer 192. In an alternative embodiment, the first spacer 192 completely covers the sidewalls of the first bit line structure 172. In other words, the top surface of the first patterned hard mask 162 is flush with the top surface of the first spacer 192.
[0058] In some embodiments, the second spacer 194 covers the sidewalls of the second patterned metal layer 151 and the semiconductor layer 145 and covers a portion of the sidewalls of the second patterned hard mask 161. Figure 10 As shown. That is, the top surface of the second patterned hard mask 161 is higher than the top surface of the second spacer 194. In an optional embodiment, the second spacer 194 completely covers the sidewalls of the second bit line structure 174. In other words, the top surface of the second patterned hard mask 161 is flush with the top surface of the second spacer 194. In some embodiments, the height of the second spacer 194 in the Y-axis direction is greater than the height of the first spacer 192. It is worth noting that the second spacer 194 will fill the remaining space in the trench 120. In other words, the second spacer 194 will directly contact the semiconductor layer 145 and directly contact the insulating layer 130 in the trench 120. That is, the second spacer 194 is formed in the third trench 123.
[0059] See Figure 11 A buried contact 210 is formed between the adjacent first bit line structure 172 and the second bit line structure 174 (eg Figure 1The buried contact 210 protrudes into the substrate 110 along the Z-axis direction and directly contacts the portion of the active region 104. In some embodiments, the buried contact 210 has a plug-like structure and can be considered a contact plug structure. Specifically, the buried contact 210 is disposed between the first spacer 192 and the second spacer 194. The buried contact 210 includes a silicon-containing material. In some embodiments, the buried contact 210 may include doped polysilicon.
[0060] See Figure 12 , a landing pad 220 is formed on the first bit line structure 172 and the second bit line structure 174 and between the first bit line structure 172 and the second bit line structure 174 (eg Figure 1 Landing pad 220 may cover first bitline structure 172, including a portion of a sidewall of first bitline structure 172 and a portion of a top surface of first bitline structure 172. Similarly, landing pad 220 may cover second bitline structure 174, including a portion of a sidewall of second bitline structure 174 and a portion of a top surface of second bitline structure 174. In some embodiments, landing pad 220 may be stacked with a material including a metal nitride or a metal (e.g., tungsten, tungsten nitride, and / or titanium nitride).
[0061] The above-described embodiments provide numerous advantages. Embodiments of the present invention disclose a method for fabricating a semiconductor structure that employs repeated (or multiple) etching of the semiconductor material instead of a conventional one-shot etching process, thereby avoiding the risk of bitline structure necking. Furthermore, nitrogen is introduced during the multiple etching processes to form a passivation layer, thereby protecting portions of the semiconductor layer from undercutting.
[0062] Although the present invention has been described in considerable detail with reference to certain embodiments, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.
[0063] It will be apparent to those skilled in the art that various modifications and variations may be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, the present invention is intended to cover modifications and variations of the present invention that fall within the appended claims.
[0064]
Explanation of symbols
[0065] 100:Semiconductor structure
[0066] 102: Isolation Area
[0067] 104: Active Zone
[0068] 110:Substrate
[0069] 111: Upper surface
[0070] 113: Lower surface
[0071] 120: Groove
[0072] 122: Second groove
[0073] 123: The third groove
[0074] 130: Insulation layer
[0075] 132: Top surface
[0076] 140:Semiconductor Materials
[0077] 141: Part 1
[0078] 142: Part 2
[0079] 143: Top surface
[0080] 145: semiconductor layer
[0081] 147: Part 1
[0082] 148: Part 2
[0083] 150:Metal layer
[0084] 151: second patterned metal layer
[0085] 152: first patterned metal layer
[0086] 160:Hard Mask
[0087] 161: Second patterned hard mask
[0088] 162: First patterned hard mask
[0089] 172: First bit line structure
[0090] 174: Second bit line structure
[0091] 180: passivation layer
[0092] 192: first spacer
[0093] 194: Second spacer
[0094] 210: buried contacts
[0095] 220: Landing Pad
[0096] AA:Line
[0097] ACT: Active Zone
[0098] BC:Buried Contact
[0099] BL: bit line
[0100] D1: Depth
[0101] D2: Depth
[0102] DC: Direct contact
[0103] H1: Height
[0104] HT:Total height
[0105] LP: Landing Pad
[0106] T1:Thickness
[0107] W1: width
[0108] W2: width
[0109] W3: Width
[0110] W4: Width
[0111] W5: width
[0112] WL: Word Line
[0113] X: axis
[0114] Y: axis
[0115] Z: axis.
Claims
1. A method for manufacturing a semiconductor structure, characterized in that: include: recessing the substrate from its upper surface toward its lower surface to form a groove; filling the trench with semiconductor material; forming a patterned metal layer on the semiconductor material, and forming a patterned hard mask layer on the patterned metal layer; Etching a portion of the semiconductor material using the patterned metal layer and the patterned hard mask layer as a first etch mask, wherein a remaining portion of the semiconductor material includes a first portion and a second portion located below the first portion, and the second portion is wider than the first portion; forming a passivation layer on the sidewalls of the first portion; as well as The passivation layer is removed, and the second portion of the remaining portion is etched using the patterned metal layer and the patterned hard mask layer as a second etching mask, thereby forming a semiconductor layer. 2 . The method for fabricating a semiconductor structure according to claim 1 , wherein forming the passivation layer on the sidewall of the first portion comprises reacting nitrogen gas with the first portion. The method for manufacturing a semiconductor structure according to claim 1 , wherein the passivation layer comprises nitride. The method for manufacturing a semiconductor structure according to claim 1 , wherein the passivation layer has a thickness of 2.0 nm to 5.0 nm. The method for manufacturing a semiconductor structure according to claim 1 , wherein a height of the first portion of the semiconductor material is at least greater than half of a total height of the semiconductor material. The method for manufacturing a semiconductor structure according to claim 1 , wherein the semiconductor layer has a uniform width. 7 . The method for manufacturing a semiconductor structure according to claim 1 , wherein a width of the semiconductor layer is the same as a width of the patterned metal layer.
8. The method for manufacturing a semiconductor structure according to claim 1, wherein: Further including: Before filling the semiconductor material in the trench, an insulating layer is conformally formed in the trench and on the upper surface of the substrate.
9. The method for manufacturing a semiconductor structure according to claim 8, wherein: Further including: Spacers are formed on a plurality of sidewalls of the semiconductor layer, the patterned metal layer and the patterned hard mask layer. 10 . The method for manufacturing a semiconductor structure according to claim 9 , wherein the spacer is in direct contact with the semiconductor layer and in direct contact with the insulating layer in the trench.
11. A method for manufacturing a semiconductor structure, characterized in that: include: recessing the substrate from its upper surface toward its lower surface to form a first groove; Filling the first trench with semiconductor material; forming a patterned metal layer on the semiconductor material and forming a patterned hard mask layer on the patterned metal layer, wherein the semiconductor material includes a first portion covered by the patterned metal layer and the patterned hard mask layer and a second portion adjacent to the first portion; partially removing the second portion of the semiconductor material to form a second trench; forming a passivation layer to cover sidewalls of the first portion; as well as The passivation layer and the second portion of the semiconductor material are removed to form a third trench adjacent to the first portion of the semiconductor material. 12 . The method for fabricating a semiconductor structure according to claim 11 , wherein forming the passivation layer to cover the sidewall of the first portion comprises reacting nitrogen with the first portion. 13 . The method for manufacturing a semiconductor structure according to claim 12 , wherein the reaction of the nitrogen gas with the first portion is performed at a temperature of 50° C. to 70° C. The method for manufacturing a semiconductor structure according to claim 11 , wherein the passivation layer comprises nitride. 15 . The method for manufacturing a semiconductor structure according to claim 11 , wherein the passivation layer has a thickness of 2.0 nm to 5.0 nm. 16 . The method for fabricating a semiconductor structure according to claim 11 , wherein a depth of the second trench is at least greater than half a depth of the third trench. The method for manufacturing a semiconductor structure according to claim 11 , wherein the third trench has a uniform depth.
18. The method for manufacturing a semiconductor structure according to claim 11, wherein: Further including: A spacer is formed in the third trench.
19. The method for manufacturing a semiconductor structure according to claim 11, wherein: Further including: Before filling the first trench with the semiconductor material, an insulating layer is conformally formed in the first trench and on the upper surface of the substrate. 20 . The method for manufacturing a semiconductor structure according to claim 19 , wherein the insulating layer is exposed from the third trench.