High performance semiconductor fan-out package

Abstract

The invention relates to a high performance semiconductor fan-out package. Embodiments described herein relate to various semiconductor device assemblies. In some embodiments, an apparatus includes: a plurality of first semiconductor dies; and a first molding layer surrounding the plurality of first semiconductor dies. A plurality of through-mold vias (TMVs) may extend through the first molding layer, and the plurality of TMVs may be filled with a conductive filler. The apparatus may include: a redistribution layer on the first molding layer; a plurality of second semiconductor dies electrically connected to the redistribution layer; and a second molding layer surrounding the plurality of second semiconductor dies. The redistribution layer may be between the first molding layer and the second molding layer. The apparatus may include a plurality of interconnects attached to the redistribution layer, where the plurality of interconnects are embedded in the conductive filler of a respective TMV of the plurality of TMVs.

Description

[0001] Cross-reference to related applications

[0002] This patent application claims priority to U.S. Provisional Patent Application No. 63 / 567,158, filed on March 19, 2024, and entitled “HIGH PERFORMANCE SEMICONDUCTOR FAN-OUT PACKAGING.” The disclosure of the prior application is considered part of and incorporated by reference into this patent application. Technical Field

[0003] The present disclosure generally relates to semiconductor devices and methods of forming semiconductor devices. For example, the present disclosure relates to high-performance semiconductor fan-out packaging. Background Art

[0004] A semiconductor package may include a semiconductor substrate, one or more semiconductor electronic components coupled to and / or embedded in the semiconductor substrate, and a housing formed on the semiconductor substrate to encapsulate the one or more semiconductor electronic components. The one or more semiconductor electronic components may be interconnected via electrical interconnects to form one or more semiconductor devices, such as one or more integrated circuits (ICs) (e.g., one or more bare dies or chips). For example, semiconductor electronic components and electrical interconnects may be fabricated on a semiconductor wafer to form one or more ICs before being cut into bare dies or chips and then packaged. A semiconductor package may be referred to as a semiconductor chip package that includes one or more ICs. The semiconductor package protects the semiconductor electronic components and electrical interconnects from damage and includes mechanisms for connecting the semiconductor electronic components and electrical interconnects to external components (e.g., a circuit substrate), such as via balls, pins, leads, contact pads, or other electrical interconnect structures. A semiconductor device assembly may be or may include one semiconductor package, multiple semiconductor packages, and / or one or more components of a semiconductor package (e.g., one or more semiconductor devices with or without a housing).

[0005] An electronic system assembly may include a plurality of semiconductor packages electrically coupled to a carrier substrate (e.g., a circuit substrate). The electronic system assembly may include additional system components electrically coupled to the carrier substrate. The carrier substrate may include electrical interconnects and conductive paths for interconnecting system components (including the plurality of semiconductor packages and other system components of the electronic system assembly). Thus, the plurality of semiconductor packages may be electrically connected to each other and / or one or more additional system components via the carrier substrate to form the electronic system assembly. For example, the other system components may include passive components (e.g., storage capacitors), processing units (e.g., central processing units (CPUs), graphics processing units (GPUs), microprocessors, and / or microcontrollers), control units (e.g., microcontrollers, memory controllers, and / or power management controllers), or one or more other electronic components. Summary of the Invention

[0006] On the one hand, the present disclosure relates to a device comprising: a plurality of first semiconductor dies; a first mold layer surrounding the plurality of first semiconductor dies, wherein a plurality of through-mold vias (TMVs) extend through the first mold layer, and wherein the plurality of TMVs are filled with a conductive filler; a redistribution layer on the first mold layer; a plurality of second semiconductor dies electrically connected to the redistribution layer; a second mold layer surrounding the plurality of second semiconductor dies, wherein the redistribution layer is between the first mold layer and the second mold layer; and a plurality of interconnects attached to the redistribution layer, wherein the plurality of interconnects are buried in the conductive filler of corresponding ones of the plurality of TMVs.

[0007] On the other hand, the present disclosure relates to a semiconductor device assembly, comprising: a first semiconductor package, comprising: one or more first semiconductor dies; and a first mold layer, which surrounds the one or more first semiconductor dies, wherein a plurality of through-mold vias (TMVs) extend through the first mold layer, and wherein the plurality of TMVs are filled with a conductive filler; and a second semiconductor package, stacked on the first semiconductor package, comprising: a redistribution layer; one or more second semiconductor dies electrically connected to the redistribution layer; a second mold layer, which surrounds the one or more second semiconductor dies; and a plurality of interconnects attached to the redistribution layer, wherein the plurality of interconnects protrude into the conductive filler of corresponding ones of the plurality of TMVs.

[0008] On the other hand, the present disclosure relates to a method comprising: placing one or more first semiconductor dies on a carrier; forming a first mold layer surrounding the one or more first semiconductor dies; forming a plurality of openings through the first mold layer; filling the plurality of openings with a conductive filler to form a plurality of through-mold vias (TMVs) through the first mold layer; and placing a semiconductor package on the first mold layer, the semiconductor package comprising: a redistribution layer; one or more second semiconductor dies electrically connected to the redistribution layer; a second mold layer surrounding the one or more second semiconductor dies; and a plurality of interconnects attached to the redistribution layer, wherein placing the semiconductor package on the first mold layer buries the plurality of interconnects in the conductive filler of corresponding TMVs among the plurality of TMVs. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a diagram of an example device that can be fabricated using the techniques described herein.

[0010] Figure 2 is a diagram of an example memory device that can be fabricated using the techniques described herein.

[0011] Figure 3 is a diagram of an instance device.

[0012] Figure 4 is a diagram of an instance device.

[0013] Figures 5A to 5E It is a diagram illustrating an example related to manufacturing equipment.

[0014] Figure 6 is a diagram of an example apparatus for fabricating the various semiconductor packages, memory devices, or similar components described herein.

[0015] Figure 7 is a flow chart of an example method of forming an integrated assembly or memory device with fan-out packaging. DETAILED DESCRIPTION

[0016] Memory devices with high performance, high capacity, and high bandwidth capabilities are useful in applications related to artificial intelligence (AI), data centers, and / or cloud computing, among other examples. Memory devices and similar components may include one or more semiconductor packages, also referred to as semiconductor device assemblies. At a high level, a semiconductor package may include one or more semiconductor devices, such as an IC or similar component. The semiconductor package may employ fan-out packaging (FOP) technology, which utilizes redistribution layers to redistribute input / output (I / O) connectors associated with one or more semiconductor dies of the semiconductor package. In some instances, multiple semiconductor packages employing FOP technology may be stacked (e.g., in a package-on-package (PoP) configuration). Generally speaking, such stacked assemblies may be susceptible to chip-package interaction stresses and may experience poor solder joint reliability and / or board-level reliability. In addition, because each of the stacked semiconductor packages includes a redistribution layer, the manufacture of the stacked assembly may involve multiple bonding operations (e.g., reflow operations, thermal compression bonding (TCB) operations, or the like) to bond the semiconductor dies to the multiple redistribution layers, thereby increasing cost and complexity.

[0017] Some embodiments described herein provide high-performance semiconductor fan-out packaging that provides a high-density, small form factor package that can be manufactured with high packaging throughput and relatively low manufacturing cost. In some embodiments, a device may include multiple semiconductor packages in a stacked arrangement. The bottom package may include a mold layer that encapsulates one or more semiconductor dies, and a plurality of through-mold vias (TMVs) may extend through the mold layer. The top package may include one or more semiconductor dies connected to a redistribution layer (e.g., the top package has a FOP configuration) and a plurality of interconnects attached to the redistribution layer. The interconnects may protrude into the conductive filler of the TMVs to physically and electrically connect the top and bottom packages.

[0018] Embedding the interconnects in the conductive filler provides a strong and reliable physical and electrical connection between the top and bottom packages, enabling improved resilience to chip-package interaction stresses and improving solder joint reliability and / or board-level reliability. Furthermore, the RDL embedded between the top and bottom packages can be the only RDL structure in the assembly, thereby improving solder joint reliability and / or board-level reliability and reducing the form factor of the device. Furthermore, using a single RDL eliminates the need for additional bonding operations (e.g., reflow operations or TCB operations), thereby reducing the cost and complexity of the device.

[0019] Figure 1 is a diagram of an example apparatus 100 that can be fabricated using the techniques described herein. Apparatus 100 may include any type of device or system that includes one or more integrated circuits 105. For example, apparatus 100 may include a memory device, a flash memory device, a NAND memory device, a NOR memory device, a random access memory (RAM) device, a read-only memory (ROM) device, a dynamic RAM (DRAM) device, a static RAM (SRAM) device, a solid-state drive (SSD), a microchip, and / or a system-on-a-chip (SoC), among other examples. In some cases, apparatus 100 may be referred to as a semiconductor package, an assembly, a semiconductor device assembly, or an integrated assembly.

[0020] like Figure 1 , the apparatus 100 may include one or more integrated circuits 105 disposed on a substrate 110, shown as a first integrated circuit 105-1 and a second integrated circuit 105-2. The integrated circuits 105 may include any type of circuit, such as an analog circuit, a digital circuit, a radio frequency (RF) circuit, a power supply, a power management circuit, an I / O chip, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), and / or a memory device (such as a NAND memory device, a NOR memory device, a RAM device, or a ROM device). The integrated circuits 105 may be mounted on or otherwise disposed on a surface of the substrate 110. Although the apparatus 100 is shown as including two integrated circuits 105 as an example, the apparatus 100 may include a different number of integrated circuits 105. In some implementations, the substrate 110 may incorporate Figure 3 and 4 A similar approach is described involving redistribution layers.

[0021] In some embodiments, the integrated circuit 105 can include a single semiconductor die 115 (sometimes referred to as a die), as shown by the first integrated circuit 105-1. In some embodiments, the integrated circuit 105 can include multiple semiconductor dies 115 (sometimes referred to as dies), as shown by the second integrated circuit 105-2, which is shown as including five semiconductor dies 115-1 through 115-5.

[0022] like Figure 1 , for an integrated circuit 105 that includes multiple dies 115, the dies 115 can be stacked on top of each other to reduce the footprint of the device 100. In some embodiments, there can be spacers between the dies 115 that are adjacent to each other in the stack to achieve electrical separation and heat dissipation. The stacked dies 115 can include three-dimensional electrical interconnects, such as through silicon vias (TSVs), to route electrical signals between the dies 115. Although the integrated circuit 105-2 is shown as including five dies 115, the integrated circuit 105 can include a different number of dies 115, such as at least two dies 115. A first die 115-1 (sometimes referred to as a bottom die or base die) can be disposed on the substrate 110, a second die 115-2 can be disposed on the first die 115-1, and so on. Although Figure 1 The die 115 are shown stacked in a straight stack (e.g., with aligned die edges), but in some implementations, the die 115 may be stacked in a different arrangement, such as a shingled stack (e.g., with misaligned die edges that provide space for wire bonding near the edges of the die 115).

[0023] Device 100 may include a housing 120 that protects internal components of device 100 (e.g., integrated circuit 105) from damage and environmental factors (e.g., particles) that may cause malfunction of device 100. Depending on the functional requirements of device 100, housing 120 may be a molding compound, plastic (e.g., epoxy plastic), ceramic, or another type of material.

[0024] In some implementations, the apparatus 100 can be included as part of a higher-level system (e.g., a computer, mobile phone, network device, SSD, vehicle, or Internet of Things device), for example, by electrically connecting the apparatus 100 to a circuit board 125, such as a printed circuit board. For example, the substrate 110 can be disposed on the circuit board 125 such that the electrical contacts 130 (e.g., bond pads) of the substrate 110 are electrically connected to the electrical contacts 135 (e.g., bond pads) of the circuit board 125.

[0025] In some implementations, the substrate 110 can be mounted on the circuit board 125 using solder balls 140 (e.g., arranged in a ball grid array), which can be melted to form a physical and electrical connection between the substrate 110 and the circuit board 125. Additionally or alternatively, the substrate 110 can be mounted on and / or electrically connected to the circuit board 125 using another type of connector, such as pins or leads. Similarly, the integrated circuit 105 can include electrical pads (e.g., bond pads) that are electrically connected to corresponding electrical pads (e.g., bond pads) of the substrate 110 using electrical bonding, such as wire bonding, bump bonding, or the like. The interconnections between the integrated circuit 105, the substrate 110, and the circuit board 125 enable the integrated circuit 105 to receive and transmit signals to other components of the device 100 and / or to higher-level systems.

[0026] As instructed above, Figure 1 For illustration only. Other examples may vary from the Figure 1 The content of the description.

[0027] Figure 2 is a diagram of an example memory device 200 that can be manufactured using the techniques described herein. Figure 1 1. The memory device 200 may be any electronic device configured to store data in memory. In some implementations, the memory device 200 may be an electronic device configured to persistently store data in the non-volatile memory 205. For example, the memory device 200 may be a hard drive, an SSD, a flash memory device (e.g., a NAND flash memory device or a NOR flash memory device), a universal serial bus (USB) thumb drive, a memory card (e.g., a secure digital (SD) card), a secondary storage device, a non-volatile memory express (NVMe) device, and / or an embedded multimedia card (eMMC) device.

[0028] As shown, the memory device 200 can include nonvolatile memory 205, volatile memory 210, and a controller 215. The components of the memory device 200 can be mounted or otherwise disposed on a substrate 220. In some implementations, the nonvolatile memory 205 includes a single die. Additionally or alternatively, the nonvolatile memory 205 can include multiple dies, such as stacked semiconductor dies 225 (e.g., in a straight stack, a shingled stack, or another type of stack), as described above in conjunction with Figure 1 describe.

[0029] The non-volatile memory 205 may be configured to maintain stored data after the memory device 200 loses power. For example, the non-volatile memory 205 may include NAND memory or NOR memory. The volatile memory 210 requires power to maintain stored data and may lose stored data after the memory device 200 loses power. For example, the volatile memory 210 may include one or more latches and / or RAM, such as DRAM and / or SRAM. As an example, the volatile memory 210 may cache data read from or written to the non-volatile memory 205 and / or may cache instructions executed by the controller 215.

[0030] The controller 215 can be any device configured to communicate with the non-volatile memory 205, the volatile memory 210, and the host device (e.g., via the host interface of the memory device 200). For example, the controller 215 can include a memory controller, a system controller, an ASIC, an FPGA, a processor, a microcontroller, and / or one or more processing components. In some implementations, the memory device 200 can be included in a system that includes a host device. The host device can include one or more processors configured to execute instructions and store data in the non-volatile memory 205.

[0031] The controller 215 may be configured to control the operation of the memory device 200, for example, by executing one or more instructions (sometimes referred to as commands). For example, the memory device 200 may store the one or more instructions as firmware, and the controller 215 may execute the one or more instructions. Additionally or alternatively, the controller 215 may receive the one or more instructions from a host device via a host interface and may execute the one or more instructions. For example, the controller 215 may transmit signals to and / or receive signals from the non-volatile memory 205 and / or the volatile memory 210 based on the one or more instructions, such as transferring (e.g., writing or programming) data to all or a portion of the non-volatile memory 205 (e.g., one or more memory cells, pages, sub-blocks, blocks, or planes of the non-volatile memory 205), transferring (e.g., reading) data from the non-volatile memory 205, and / or erasing the non-volatile memory 205.

[0032] As instructed above, Figure 2 For illustration only. Other examples may vary from the Figure 2 The content of the description. Figure 2 The number and arrangement of components shown in FIG are for illustration only. In practice, there may be Figure 2 Additional components, fewer components, different components, or a different arrangement of components than those shown.

[0033] Figure 3 is a diagram of an example apparatus 300. Apparatus 300 may be a semiconductor device assembly.

[0034] The apparatus 300 may include a first semiconductor package 310 and a second semiconductor package 350 in a stacked arrangement. For example, the second semiconductor package 350 may be stacked on the first semiconductor package 310. The first semiconductor package 310 and / or the second semiconductor package may be a multi-chip package, as described herein.

[0035] The first semiconductor package 310 may include one or more first semiconductor dies 312 (shown as semiconductor dies 312a and 312b). For example, the first semiconductor package 310 may include multiple first semiconductor dies 312, such as two semiconductor dies, four semiconductor dies, or a different number of semiconductor dies. Similarly, the second semiconductor package 350 may include one or more second semiconductor dies 352 (shown as semiconductor dies 352a and 352b). For example, the second semiconductor package 350 may include multiple second semiconductor dies 352, such as two semiconductor dies, four semiconductor dies, or a different number of semiconductor dies. The number of first semiconductor dies 312 may be the same as or different from the number of second semiconductor dies 352. In some implementations, the die thickness of the first semiconductor die 312 and / or the second semiconductor die 352 may be in a range from about 50 micrometers (μm) to about 250 μm.

[0036] The first semiconductor die 312 and the second semiconductor die 352 may be memory dies (e.g., DRAM dies, NAND dies, SRAM dies, and / or NOR dies, among other examples). For example, the first semiconductor die 312 and the second semiconductor die 352 may be copies of each other. Alternatively, the first semiconductor die 312 may include at least two different types of memory dies and / or the second semiconductor die 352 may include at least two different types of memory dies. In some embodiments, the first semiconductor die 312 may include one or more logic dies (and the second semiconductor die 352 may include one or more memory dies) and / or the second semiconductor die 352 may include one or more logic dies (and the first semiconductor die 312 may include one or more memory dies). For example, one of the first semiconductor package 310 or the second semiconductor package 350 may be a logic package, and the other of the first semiconductor package 310 or the second semiconductor package 350 may be a memory package.

[0037] A plurality of direct chip attach (DCA) bumps 314 (e.g., microbumps, solder balls, pillars, or the like) can be physically and electrically connected to each of the first semiconductor die 312, and a plurality of DCA bumps 354 can be physically and electrically connected to each of the second semiconductor die 352. The DCA bumps 314, 354 can include solder caps. The DCA bumps 314, 354 can be configured to electrically connect the first semiconductor die 312 and the second semiconductor die 352, respectively, to the device 300 or one or more other components external to the device 300 (e.g., via solder).

[0038] In some implementations, each of the first semiconductor dies 312 can include an integrated redistribution layer (not shown). The integrated redistribution layer can be configured to fan-in the I / O connectors (e.g., DCA bumps 314) of the semiconductor die 312 to a specific pitch (e.g., a chip scale package (CSP) pitch, e.g., approximately 0.3 millimeters (mm)). Thus, having an integrated redistribution layer in the first semiconductor die 312 allows package-level redistribution layers to be eliminated from the first semiconductor package 310.

[0039] The first semiconductor package 310 may include a first mold layer 316 surrounding a first semiconductor die 312. Similarly, the second semiconductor package 350 may include a second mold layer 356 surrounding a second semiconductor die 352. The first mold layer 316 may fully encapsulate the first semiconductor die 312, including the DCA bumps 314 associated with the first semiconductor die 312. Similarly, the second mold layer 356 may fully encapsulate the second semiconductor die 352, including the DCA bumps 354 associated with the second semiconductor die 352. By fully encapsulating the semiconductor dies 312, 352, the mold layers 316, 356 mitigate chip-package interaction stress.

[0040] A plurality of TMVs 318 may extend through the first molding layer 316. The TMVs 318 are filled with a conductive filler. TMVs 318 "filled" with a conductive filler may be partially filled with the conductive filler or completely filled with the conductive filler. The conductive filler may include a conductive paste (e.g., silver paste or silver sinter paste), a solder paste (e.g., a high-temperature solder such as tin-gold solder), and / or a metal filler (e.g., copper). The TMVs 318 may include a first one or more TMVs 318 at the periphery of the first semiconductor die 312 (e.g., defining a boundary around the first semiconductor die 312) and / or a second one or more TMVs 318 between semiconductor dies in the first semiconductor die 312. In some implementations, the pitch of the TMVs 318 may match the pitch of the DCA bumps 314 associated with the first semiconductor die 312 (e.g., approximately 0.3 mm).

[0041] The second semiconductor package 350 may include a redistribution layer 360 (e.g., the second semiconductor package may have a FOP configuration). The redistribution layer 360 may be arranged between the first mold layer 316 and the second mold layer 356 (e.g., the redistribution layer 360 is a buried redistribution layer). The second semiconductor die 352 may be arranged on the redistribution layer 360 and electrically connected to the redistribution layer 360 (e.g., via the DCA bumps 354). The redistribution layer 360 may include a dielectric material (e.g., polyimide or SiO2, among other examples) and one or more electrical connections, such as conductive traces, pads, or the like, for electrically coupling the redistribution layer 360 to the second semiconductor die 352 and / or the TMVs 318. The redistribution layer 360 may be configured to redistribute the I / O connectors of the second semiconductor die 352 to other locations of the device 300.

[0042] In some embodiments, a double-sided die configuration may be used for the redistribution layer 360. Here, the first semiconductor die 312 may include one or more additional semiconductor dies 312 arranged on a first surface of the redistribution layer 360 (e.g., which faces the first mold layer 316) and electrically connected to the first surface (e.g., via DCA bumps 314), and the second semiconductor die 352 may be arranged on a second surface of the redistribution layer 360 opposite the first surface (e.g., which faces the second mold layer 356) and electrically connected to the second surface (e.g., via DCA bumps 354). Thus, in some embodiments, the first semiconductor die 312 may include one or more additional semiconductor dies 312 positioned with its DCA bumps 314 facing away from the redistribution layer 360 (e.g., in a Figure 3 312) and one or more semiconductor dies 312 positioned with their DCA bumps 314 facing the redistribution layer 360 (not shown), such that the first semiconductor die 312 includes one or more groups of semiconductor dies 312 arranged back to back. In this configuration, the first semiconductor package 310 can include four first semiconductor dies 312, for a total of six semiconductor dies in the device 300 (including two second semiconductor dies 352).

[0043] A plurality of interconnects 362 may be physically and electrically connected to the redistribution layer 360. For example, the second semiconductor die 352 may be arranged on a first surface of the redistribution layer 360, and the interconnects 362 may extend from a second surface of the redistribution layer 360 opposite the first surface. The interconnects 362 may be conductive. The interconnects 362 may include DCA bumps, such as conductive pillars (e.g., copper pillars) or pillars. Each interconnect 362 may be sized to fit within an opening containing the TMV 318 (e.g., the diameter of the interconnect 362 is smaller than the diameter of the opening). For example, the opening of the TMV 318 may have a diameter of approximately 100 μm, and the interconnects 362 may have a diameter of approximately 30 μm. As another example, the opening of the TMV 318 may have a diameter in the range of from 10 μm to 300 μm, and the interconnects 362 may have a diameter in the range of from 3 μm to 150 μm (provided that the diameter of the interconnect 362 is smaller than the diameter of the opening). Thus, interconnects 362 may be embedded in (e.g., protrude into) the conductive filler of TMVs 318, thereby embedding interconnects 362 within the TMVs 318 themselves. For example, interconnects 362 may be embedded in the conductive filler of respective TMVs 318. Embedding interconnects 362 in the conductive filler provides a strong physical connection between first semiconductor package 310 and second semiconductor package 350. In this manner, apparatus 300 may exhibit improved resilience to chip-package interaction stresses, improved solder joint reliability, and / or improved board-level reliability.

[0044] As shown, the apparatus 300 may include a plurality of solder balls 320 (e.g., arranged in a ball grid array) configured to mount and electrically connect the apparatus 300 to a substrate (e.g., a circuit board). The solder balls 320 may include a first plurality of solder balls 320 attached to respective TMVs 318 (e.g., in a bump-on-via arrangement) and a second plurality of solder balls 320 attached to respective DCA bumps 314 of the first semiconductor die 312 (e.g., in a bump-on-bump arrangement). The solder balls 320 on the TMVs 318 facilitate electrical interconnection of the second semiconductor die 352, and the solder balls 320 on the DCA bumps 314 facilitate electrical interconnection of the first semiconductor die 312. Furthermore, the solder balls 320 provide low-stress interconnection, thereby improving solder joint reliability and board-level reliability with respect to chip-package interactions.

[0045] Although the first semiconductor package 310 and the second semiconductor package 350 are described herein as separate packages, the physical connection of the first semiconductor package 310 and the second semiconductor package 350 (e.g., by embedding the interconnect 362 in the conductive filler of the TMV 318) can form an integrated packaging assembly. In some implementations, the apparatus 300 can include more than two stacked semiconductor packages, such as three stacked semiconductor packages, four stacked semiconductor packages, etc. For example, in the case of three stacked semiconductor packages, the second semiconductor package 350 can include the TMVs described herein, and a third semiconductor package stacked on the second semiconductor package 350 can include a redistribution layer having interconnects embedded in the conductive filler of the TMVs of the second semiconductor package 350.

[0046] As instructed above, Figure 3 For illustration only. Other examples may vary from the Figure 3 The content of the description.

[0047] Figure 4 is a diagram of an alternative embodiment of device 300. Figure 4 , device 300 may include additional redistribution layers 322 (e.g., as part of first semiconductor package 310). Additional redistribution layers 322 may be arranged below first molding layer 316. First semiconductor die 312 may be arranged on additional redistribution layers 322 and electrically connected to additional redistribution layers 322 (e.g., via DCA bumps 314). Furthermore, TMVs 318 may be electrically connected to additional redistribution layers 322. For example, TMVs 318 may extend between redistribution layers 360 and additional redistribution layers 322 and electrically connect redistribution layers 360 and additional redistribution layers 322. Additional redistribution layers 322 may be configured to fan into I / O connectors of device 300 (e.g., according to an interconnect standard, a ball grid array standard, or the like). Solder balls 320 may be attached to and electrically connected to additional redistribution layers 322.

[0048] As instructed above, Figure 4 For illustration only. Other examples may vary from the Figure 4 The content of the description.

[0049] Figures 5A to 5E FIG. 5 is a diagram illustrating an example 500 associated with a manufacturing apparatus 300 (eg, a semiconductor device assembly or semiconductor package). Figure 5A, the device 300 can be manufactured on a carrier 502. In some embodiments, the carrier 502 can be a wafer-shaped carrier, a panel-shaped carrier, or a strip-shaped carrier. The carrier 502 can be constructed of any suitable material used in semiconductor package manufacturing processes. For example, the carrier 502 can be a rigid material that provides control and reduction of wafer warpage during the manufacture of the device. In some embodiments, the carrier 502 can be a glass carrier, which can facilitate a stripping process (e.g., a laser stripping process or other stripping process). In some embodiments, the carrier 502 can be laminated or otherwise coated with a sacrificial layer 504 (e.g., a release film) (also referred to as a release layer) and / or an adhesive layer 506 (e.g., a die attach film). The sacrificial layer 504 can assist during the stripping process by allowing the carrier 502 to be easily removed from the package wafer after wafer formation.

[0050] As shown by reference numeral 510, the first semiconductor die 312 can be placed on the carrier 502. In some implementations, as described herein, the first semiconductor die 312 can be arranged on the additional redistribution layer 322. Thus, in some implementations, prior to placing the first semiconductor die 312, the additional redistribution layer 322 can be formed on the carrier 502, and the first semiconductor die 312 can be placed on the additional redistribution layer 322, which is on the carrier 502. Furthermore, the first semiconductor die 312 can be bonded to the additional redistribution layer 322 (e.g., via the DCA bumps 314) by performing a reflow process, a thermal compression bonding (TCB) process, or the like.

[0051] As shown by reference numeral 515, a first molding layer 316 may be formed over the first semiconductor die 312. For example, the first molding layer 316 may surround the first semiconductor die 312, including beneath the first semiconductor die 312 between the DCA bumps 314. A compression molding process may be performed to form the first molding layer 316. The compression molding process may include compressing a molding compound (e.g., an epoxy molding compound) onto the first semiconductor die 312. The molding compound may be a moldable underfill (MUF) material to facilitate the molding compound surrounding the DCA bumps 314. Molding of the first molding layer 316 may be a panel-level process or a wafer-level process.

[0052] like Figure 5B, and shown by reference numeral 520, an opening 318a of the TMV 318 can be formed through the first mold layer 316. A laser ablation process can be performed to form the opening 318a. As shown by reference numeral 525, the opening 318a can be filled with a conductive filler to form the TMV 318 through the first mold layer 316. Filling the opening 318a with the conductive filler can include a microjet process (e.g., using a conductive paste, solder paste, copper paste, or the like as the conductive filler). In some implementations, the conductive filler can be a metal (e.g., copper) filler formed by physical vapor deposition (PVD) of a metal seed and electrochemical deposition (ECD) of a metal. In some examples, reference numerals 510 to 525 describe the formation of the first semiconductor package 310.

[0053] like Figure 5C , and shown by reference numeral 530, the second semiconductor package 350 may be placed on (e.g., stacked on) the first mold layer 316 (e.g., on the first semiconductor package 310), which buries the interconnect 362 in the conductive filler of the TMV 318. For example, the second semiconductor package 350 may be placed before the conductive filler solidifies or cures to allow the interconnect 362 to penetrate into the conductive filler. Figure 5D , and shown by reference numeral 535 , when the interconnect 362 is embedded into the TMV 318 , the conductive filler may be allowed to solidify or may be cured to harden the conductive filler and bond the second semiconductor package 350 to the first semiconductor package 310 .

[0054] The second semiconductor package 350 can be fabricated separately before being stacked on the first semiconductor package 310. For example, the redistribution layer 360 can be formed on a separate carrier (e.g., which can be coated with a sacrificial layer and / or an adhesive layer), and the second semiconductor die 352 can be placed on the redistribution layer 360 and bonded to the redistribution layer 360 (e.g., via DCA bumps 354) by performing a reflow process, a TCB process, or the like. In a manner similar to the first mold layer 316, a second mold layer 356 can be formed over the second semiconductor die 352 to surround the second semiconductor die 352. The carrier can be removed from the redistribution layer 360, and the interconnects 362 can be applied to the redistribution layer 360 (e.g., using electroplating or a similar process).

[0055] like Figure 5E , and shown by reference numeral 540, the carrier 502 (e.g., and the sacrificial layer 504 and / or the adhesive layer 506) can be removed from the first semiconductor package 310 (e.g., resulting in a separate packaged die and / or panel). For example, the carrier 502 can be removed using a lift-off process (e.g., a laser lift-off process). In some implementations, the lift-off process can include cleaning the bottom surface of the first semiconductor package 310 to remove residual adhesive or similar contaminants.

[0056] As shown by reference numeral 545, solder balls 320 can be applied to the first semiconductor package 310. In embodiments where additional redistribution layers 322 are not employed, the solder balls 320 can be applied directly to the TMVs 318 and DCA bumps 314. In embodiments where additional redistribution layers 322 are employed, the solder balls 320 can be applied to the additional redistribution layers 322. The solder balls 320 can be applied using a ball drop process, a screen printing process, or a similar process. The solder balls 320 can ultimately be used to provide electrical connectivity between the device 300 and a circuit board or similar structure. In some embodiments, after applying the solder balls 320, the individual package wafers and / or panels can be singulated (e.g., by dicing) into a plurality of devices 300.

[0057] As instructed above, Figures 5A to 5E For illustration only. Other examples may vary from the Figures 5A to 5E The content of the description.

[0058] Figure 6 is a diagram of an example apparatus 600 for manufacturing various semiconductor packages, memory devices, or similar components described herein. In some embodiments, the apparatus 600 may be used to manufacture the various semiconductor packages, memory devices, or similar components described herein. Figures 5A to 5E The manufacturing process described herein) manufactures the device 300. Figure 6 6, apparatus 600 may include a packaging system 602. Packaging system 602 may include one or more devices or tools, such as a printer 604, a wafer saw 606, a carrier 608, a die placement tool 610, a soldering tool 612, a reflow oven 614, a flux cleaner 616, a plasma chamber 618, a dispenser 620, and / or a curing device 622. The plurality of devices may be physically or communicatively coupled to one another. For example, the plurality of devices may be interconnected via wired and / or wireless connections (e.g., via bus 624). Additionally or alternatively, the plurality of devices may form part of an electronics assembly line.

[0059] The printer 604 can be a device capable of printing patterns in a material, such as silicon, a dielectric material, or the like, for the purpose of forming an integrated circuit or the like. In some embodiments, the printer 604 can be a photolithographic device capable of printing patterns in a material to form an integrated circuit. Additionally or alternatively, the printer 604 can apply solder or other conductive material to form part of the electrical connection to be formed between the die and the substrate. For example, the printer 604 can apply a grid of solder bumps to the die, which will be aligned with a grid of bump pads on the substrate during a flip-chip attach process or the like.

[0060] Wafer saw 606 can be a device capable of sawing dies (such as microcontrollers, memory dies, or other semiconductor dies) from a wafer. In some implementations, wafer saw 606 can include one or more blades and / or one or more lasers for sawing dies from a wafer.

[0061] Carrier 608 can be a device capable of supporting and / or carrying a substrate during a die and / or chip attach process or similar process. Carrier 608 can be constructed of a non-contaminating material such as quartz, glass, or the like and can withstand high temperatures. In this regard, carrier 608 can carry a substrate and / or one or more dies through one or more ovens, such as reflow oven 614 and / or curing device 622.

[0062] The die placement tool 610 can be a high-precision tool capable of placing a die onto a substrate. In some embodiments, the die placement tool 610 can flip the flip-chip die during the placement process so that the active surface of the flip-chip die, which may be facing upward during preliminary manufacturing steps, can face the substrate during the flip-chip die placement process. In some embodiments, the die placement tool 610 can include one or more sensors capable of aligning bump bonds on the die with bond pads on the substrate during the flip-chip die attach process.

[0063] Soldering tool 612 can form one or more solder connections between components of a semiconductor package. For example, soldering tool 612 can form wirebond connections between components of a semiconductor package by soldering a wire of a wirebond ribbon from one component to a wirebond pad of another component. In some embodiments, the soldering tool can apply a solder paste mask over one or more electrical connections and / or solder joints.

[0064] The reflow oven 614 is capable of heating the components to a suitable temperature to cause the solder or other joining material to reflow, thereby causing the solder or similar material to melt and form an electrical connection between the two components.

[0065] The flux cleaner 616 can be a device capable of removing residual flux from the soldering process. In some embodiments, the flux cleaner 616 can include a heater capable of removing residual flux through a heat treatment process. Additionally or alternatively, the flux cleaner 616 can include a nozzle or similar device capable of applying a cleaning agent to the component during the die attach process to remove residual flux therefrom.

[0066] The plasma chamber 618 can be a device capable of providing plasma treatment to a component. In some embodiments, the plasma chamber 618 can directly or indirectly apply a plasma stream to an area of ​​the component, such as for the purpose of preparing an area on the component for receiving epoxy underfill or the like.

[0067] The dispenser 620 can be a device capable of dispensing a molding compound around a die or similar component. In some embodiments, the dispenser 620 can dispense a molding compound (e.g., an epoxy molding compound) during a compression molding process. In some embodiments, the dispenser 620 can include a dispensing needle capable of applying an epoxy underfill by capillary action under pressure, for example, by dispensing the underfill material around the periphery of the die so that the underfill material flows under the die and fills the space between the die and the substrate.

[0068] The curing device 622 can be a device capable of curing a molding compound, such as an epoxy molding compound, an epoxy underfill material, MUF, or the like. In some embodiments, the curing device 622 can be an oven configured to heat the molding compound to a suitable curing temperature. Additionally or alternatively, the curing device 622 can cure the molding compound via a chemical reaction, by applying ultraviolet light, by applying other radiation, or the like.

[0069] Figure 6 The number and arrangement of devices and networks shown in FIG are for illustration only. In practice, there may be more than Figure 6 Additional devices, fewer devices, different devices, or differently arranged devices than those shown in FIG. Figure 6 Two or more devices shown in may be implemented in a single device, or Figure 6 A single device shown in FIG600 may be implemented as multiple distributed devices. Additionally or alternatively, one or more devices of apparatus 600 may perform one or more functions described as being performed by another set of devices of apparatus 600.

[0070] Figure 7 is a flow chart of an example method 700 of forming an integrated assembly or memory device with fan-out packaging. In some implementations, Figure 7 One or more process blocks of the present invention may be executed by various semiconductor manufacturing equipment, such as the above-mentioned Figure 6 Semiconductor manufacturing equipment is described.

[0071] like Figure 7 As shown in FIG, method 700 may include placing one or more first semiconductor dies on a carrier (block 710). Figure 7 As further shown in FIG. 7 , method 700 may include forming a first molding layer surrounding one or more first semiconductor dies (block 720 ). Figure 7 As further shown in FIG. 7 , method 700 may include forming a plurality of openings through the first mold layer (block 730 ). Figure 7 As further shown in FIG. 7 , method 700 may include filling the plurality of openings with a conductive filler to form a plurality of TMVs through the first mold layer (block 740 ). Figure 7As further shown in FIG, method 700 may include placing a semiconductor package on the first mold layer (block 750). The semiconductor package may include: a redistribution layer; one or more second semiconductor dies electrically connected to the redistribution layer; a second mold layer surrounding the one or more second semiconductor dies; and a plurality of interconnects attached to the redistribution layer. Placing the semiconductor package on the first mold layer may embed the plurality of interconnects in the conductive filler of corresponding TMVs in the plurality of TMVs.

[0072] Method 700 may include additional aspects, such as any single aspect or any combination of aspects described below and / or in conjunction with one or more other methods described elsewhere herein.

[0073] In a first aspect, the method 700 includes removing a carrier and applying a plurality of solder balls to corresponding TMVs of a plurality of TMVs and corresponding DCA bumps of one or more first semiconductor dies.

[0074] In a second aspect, alone or in combination with the first aspect, method 700 includes forming an additional redistribution layer on a carrier, wherein one or more first semiconductor dies are placed on the additional redistribution layer on the carrier.

[0075] In a third aspect, alone or in combination with one or more of the first and second aspects, method 700 includes removing the carrier and applying a plurality of solder balls to an additional redistribution layer.

[0076] In a fourth aspect, alone or in combination with one or more of the first to third aspects, method 700 includes forming a redistribution layer, placing one or more second semiconductor dies on the redistribution layer, forming a second mold layer surrounding the one or more second semiconductor dies, and applying a plurality of interconnects to the redistribution layer.

[0077] although Figure 7 Example blocks of method 700 are shown, but in some implementations, method 700 may include Figure 7 In some implementations, method 700 may include forming apparatus 300, an integrated assembly including apparatus 300, any portion described herein of apparatus 300, and / or any portion described herein of an integrated assembly including structure 300. For example, method 700 may include forming one or more of components 310-322 and / or 350-362.

[0078] In some embodiments, a semiconductor device assembly includes a first semiconductor package comprising: one or more first semiconductor dies; and a first mold layer surrounding the one or more first semiconductor dies, wherein a plurality of transversely coupled metal dies (TMVs) extend through the first mold layer, and wherein the plurality of TMVs are filled with a conductive filler. The semiconductor device assembly may include a second semiconductor package stacked on the first semiconductor package, comprising: a redistribution layer; one or more second semiconductor dies electrically connected to the redistribution layer; a second mold layer surrounding the one or more second semiconductor dies; and a plurality of interconnects attached to the redistribution layer, wherein the plurality of interconnects protrude into the conductive filler of respective ones of the plurality of TMVs.

[0079] In some embodiments, a device includes: a plurality of first semiconductor dies; a first mold layer surrounding the plurality of first semiconductor dies, wherein a plurality of TMVs extend through the first mold layer, and wherein the plurality of TMVs are filled with a conductive filler; a redistribution layer on the first mold layer; a plurality of second semiconductor dies electrically connected to the redistribution layer; a second mold layer surrounding the plurality of second semiconductor dies, wherein the redistribution layer is between the first mold layer and the second mold layer; and a plurality of interconnects attached to the redistribution layer, wherein the plurality of interconnects are buried in the conductive filler of corresponding TMVs among the plurality of TMVs.

[0080] In some embodiments, a method includes: placing one or more first semiconductor dies on a carrier; forming a first mold layer surrounding the one or more first semiconductor dies; forming a plurality of openings through the first mold layer; filling the plurality of openings with a conductive filler to form a plurality of transversely coupled metal (TMVs) through the first mold layer; and placing a semiconductor package on the first mold layer. The semiconductor package may include: a redistribution layer; one or more second semiconductor dies electrically connected to the redistribution layer; a second mold layer surrounding the one or more second semiconductor dies; and a plurality of interconnects attached to the redistribution layer, wherein placing the semiconductor package on the first mold layer embeds the plurality of interconnects in the conductive filler of corresponding TMVs in the plurality of TMVs.

[0081] The above disclosure provides illustration and description, but is not intended to be exhaustive or to limit the embodiments to the precise form disclosed. Modifications and variations may be made in light of the above disclosure or may be acquired from practice of the embodiments described herein.

[0082] The orientation of various elements in the figure is shown as an example, and the illustrated example can be rotated relative to the depicted orientation. The description provided herein and the appended claims relate to any structure with a description relationship between various features, whether the structure is in a specific orientation of the figure or rotated relative to this orientation. Similarly, for ease of description, spatial relative terms such as "below", "below", "lower", "above", "upper", "middle", "left" and "right" are used herein to describe the relationship between an element and one or more other elements, as illustrated in the figure. In addition to the orientation depicted in the figure, spatial relative terms are also intended to cover different orientations of elements, structures and / or assemblies in use or operation. Structures and / or assemblies can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly. In addition, unless otherwise indicated, the cross-sectional views in the figures only show the features in the plane of the cross section and do not show the material behind the plane of the cross section in order to simplify the diagram.

[0083] As used herein, the terms "substantially" and "approximately" mean "within reasonable manufacturing and measurement tolerances."

[0084] Even if the particular combination of features is narrated in the claims and / or disclosed in the specification, these combinations are not intended to limit the disclosure of the embodiments described herein. Many of these features can be combined in a manner not clearly narrated in the claims and / or not clearly disclosed in the specification. For example, the disclosure includes each dependent claim in the claim group in conjunction with each other individual claim in the claim group and each combination of multiple claims in the claim group. As used herein, the phrase "at least one of" related to the project list refers to any combination of the project, including single members. As an example, "at least one of a, b or c" is intended to encompass a, b, c, a+b, a+c, b+c and a+b+c and any combination of multiple identical elements (such as a+a, a+a+a, a+a+b, a+a+c, a+b+b, a+c+c, b+b, b+b+b, b+b+c, c+c and c+c+c or any other sorting of a, b and c).

[0085] The elements, actions or instructions used herein should not be interpreted as key or necessary unless clearly described as such. Moreover, as used herein, the article "one" is intended to include one or more items and can be used interchangeably with "one or more". In addition, as used herein, the article "said" is intended to include one or more items referenced in conjunction with the article "said" and can be used interchangeably with "said one or more". When only one item is desired, the phrase "only one", "single" or similar language is used. Moreover, as used herein, the term "having" or the like is intended to be an open term (for example, an element "having" A may also have B) that does not limit the elements it modifies. In addition, unless otherwise explicitly stated, the phrase "based on" is intended to mean "at least partially based on". As used herein, the term "multiple (multiple)" can be replaced with "a plurality (a plurality of)", and vice versa. Also, as used herein, the term "or" when used in a series is intended to be inclusive and interchangeable with "and / or" unless expressly stated otherwise (e.g., if used in combination with "either" or "only one of").

Claims

1. A device comprising: a plurality of first semiconductor dies; a first molding layer surrounding the plurality of first semiconductor dies, wherein a plurality of through-mold holes (TMVs) extend through the first molding layer, and wherein the plurality of TMVs are filled with a conductive filler; a redistribution layer on the first molding layer; a plurality of second semiconductor dies electrically connected to the redistribution layer; a second molding layer surrounding the plurality of second semiconductor dies, wherein the redistribution layer is between the first molding layer and the second molding layer; and a plurality of interconnects attached to the redistribution layer, The plurality of interconnects are embedded in the conductive filler of corresponding TMVs among the plurality of TMVs. 2 . The apparatus of claim 1 , wherein the plurality of TMVs comprises first one or more TMVs at a periphery of the plurality of first semiconductor dies and second one or more TMVs between semiconductor dies in the plurality of first semiconductor dies. The apparatus according to claim 1 , wherein the conductive filler comprises a conductive paste or a solder paste.

4. The apparatus of claim 1 , further comprising: A first plurality of solder balls is attached to respective ones of the plurality of TMVs, and a second plurality of solder balls is attached to respective direct chip attach (DCA) bumps of the plurality of first semiconductor dies.

5. The apparatus of claim 1 , further comprising: Extra heavy cloth layer, wherein the one or more first semiconductor dies are electrically connected to the additional redistribution layer; and A plurality of solder balls are attached to the additional redistribution layer. The apparatus of claim 1 , wherein the plurality of interconnects comprises a plurality of conductive pillars.

7. The apparatus of claim 1, wherein an interconnect of the plurality of interconnects is sized to fit within an opening containing a TMV of the plurality of TMVs.

8. A semiconductor device assembly comprising: A first semiconductor package comprising: one or more first semiconductor dies; and a first molding layer surrounding the one or more first semiconductor dies, wherein a plurality of through-mold holes (TMVs) extend through the first molding layer, and wherein the plurality of TMVs are filled with a conductive filler; and A second semiconductor package, stacked on the first semiconductor package, comprises: Heavy cloth layer; one or more second semiconductor dies electrically connected to the redistribution layer; a second molding layer surrounding the one or more second semiconductor dies; and a plurality of interconnects attached to the redistribution layer, wherein the plurality of interconnects protrude into the conductive filler of corresponding TMVs among the plurality of TMVs.

9. The semiconductor device assembly according to claim 8, further comprising: A first plurality of solder balls is attached to respective ones of the plurality of TMVs, and a second plurality of solder balls is attached to respective direct chip attach (DCA) bumps of the one or more first semiconductor dies.

10. The semiconductor device assembly according to claim 8, further comprising: Extra heavy cloth layer, wherein the one or more first semiconductor dies are electrically connected to the additional redistribution layer, and The plurality of TMVs electrically connect the redistribution layer and the additional redistribution layer.

11. The semiconductor device assembly according to claim 10, further comprising: A plurality of solder balls are attached to the additional redistribution layer. 12 . The semiconductor device assembly of claim 8 , wherein the one or more first semiconductor dies comprise a plurality of first semiconductor dies, and the one or more second semiconductor dies comprise a plurality of second semiconductor dies.

13. The semiconductor device assembly of claim 8, wherein the redistribution layer is on the first molding layer.

14. The semiconductor device assembly of claim 8, wherein the plurality of interconnects comprises a plurality of conductive pillars.

15. The semiconductor device assembly of claim 8, wherein the one or more first semiconductor dies and the one or more second semiconductor dies comprise memory dies.

16. A method comprising: placing one or more first semiconductor dies on a carrier; forming a first molding layer surrounding the one or more first semiconductor dies; forming a plurality of openings through the first molding layer; filling the plurality of openings with a conductive filler to form a plurality of through-mold vias (TMVs) passing through the first molding layer; and A semiconductor package is placed on the first molding layer, the semiconductor package comprising: Heavy cloth layer; one or more second semiconductor dies electrically connected to the redistribution layer; a second molding layer surrounding the one or more second semiconductor dies; and a plurality of interconnects attached to the redistribution layer, The semiconductor package is placed on the first molding layer, and the plurality of interconnects are embedded in the conductive fillers of corresponding TMVs among the plurality of TMVs.

17. The method according to claim 16, further comprising: removing the carrier; and A plurality of solder balls are applied to respective TMVs of the plurality of TMVs and respective direct chip attach (DCA) bumps of the one or more first semiconductor dies.

18. The method of claim 16, further comprising: forming an additional redistribution layer on the carrier, The one or more first semiconductor dies are placed on the additional redistribution layer on the carrier.

19. The method of claim 18, further comprising: removing the carrier; and A plurality of solder balls are applied to the additional redistribution layer.

20. The method of claim 16, further comprising: forming the redistribution layer; placing the one or more second semiconductor dies on the redistribution layer; forming the second mold layer surrounding the one or more second semiconductor dies; and The plurality of interconnects are applied to the redistribution layer.

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