Semiconductor device and preparation method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a packaging substrate, a base, an electric connecting piece and a plurality of chips. The packaging substrate comprises a first wiring layer and a first electrical pin, and the first electrical pin is located at the bottom of the packaging substrate and electrically connected with the first wiring layer; the base comprises a second wiring layer, a third wiring layer and a second electrical pin; the base is embedded into the packaging substrate, and the top surfaces and the bottom surfaces of the packaging substrate and the base are flush with each other; the second electrical pin is located at the bottom of the base and is electrically connected with the second wiring layer; a plurality of chips are attached to the top of the base, and an electrode at the top of at least one chip is electrically connected with the electric connecting piece and is connected to the first wiring layer through a frame with a semi-etching structure; at least one electrode at the bottom of the chip is connected to the second electrical pin; bottom electrodes of other chips are interconnected based on the third wiring layer. In addition, the invention also provides a preparation method of the semiconductor device. The semiconductor device prepared by using the preparation method of the semiconductor device has the advantages of strong current-carrying capability and small parasitic inductance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a preparation method thereof. Background Art

[0002] Chip technology is at the core of modern electronics, with applications in numerous semiconductor fields, including computers, communications, and consumer electronics. Chips contain delicate circuits that are extremely fragile and susceptible to physical damage, chemical corrosion, and environmental factors. Therefore, chip packaging is a critical step in the semiconductor manufacturing process.

[0003] Existing chip packaging includes the following steps: 1. Chip mounting: attaching the chip to the package substrate or lead frame; 2. Wire bonding: using thin metal wires to connect the chip pins to the corresponding pads on the package substrate or lead frame; 3. Package molding: wrapping the chip and wire bonding parts with packaging material to form a package body; 4. Cutting and separation: cutting the package body into individual devices.

[0004] Large, high-power semiconductor devices often require longer bond wires to ensure adequate operating conditions due to the high currents, high heat generation, and complex operating environments. Due to the inductance, longer bond wires tend to generate greater parasitic inductance, which can affect chip circuit performance, such as high-speed switching. Summary of the Invention

[0005] Based on this, the purpose of the present invention is to overcome the defects or shortcomings of the prior art and provide a semiconductor device.

[0006] A semiconductor device comprises a packaging substrate, a base, electrical connectors and a plurality of chips;

[0007] The package substrate includes a first wiring layer and a first electrical pin, wherein the first wiring layer is provided with a first electrical channel vertically penetrating the package substrate; the first electrical pin is located at the bottom of the package substrate and is electrically connected to the first wiring layer through the first electrical channel;

[0008] The base includes a second wiring layer, a third wiring layer, and a second electrical pin; the base is embedded in the packaging substrate, and the top surface and bottom surface of the packaging substrate and the base are respectively flush; the second wiring layer is provided with a second electrical channel vertically penetrating the base; the second electrical pin is located at the bottom of the base and is electrically connected to the second wiring layer through the second electrical channel; the third wiring layer is electrically connected between the first wiring layer and the second wiring layer;

[0009] The electrical connector includes a frame portion and a connecting portion; the frame portion extends along the edge of the packaging substrate at the top of the packaging substrate and is electrically connected to the first wiring layer, and the connecting portion extends from the top of the frame portion to above the base;

[0010] The several chips are mounted on the top of the base, and the electrode on the top of at least one chip is electrically connected to the connecting part; at least one electrode on the bottom of the chip is electrically connected to the second electrical pin based on the second wiring layer; the bottom electrodes of other chips are interconnected based on the third wiring layer.

[0011] Compared to existing technologies, the semiconductor device of the present invention uses electrical connectors instead of traditional leads for routing, increasing current-carrying capacity while reducing parasitic induction in the circuit between the chip and the package substrate. Furthermore, the top and bottom of the package substrate and the base are flush, with the frame positioned atop the package substrate and the chip mounted on the base embedded within the package substrate. This creates a compact structure for the entire semiconductor device, enabling miniaturization.

[0012] In one embodiment, the frame portion is provided with contact and non-contact regions spaced apart along its extension direction; the contact regions are located directly above and electrically connected to the first electrical path; and the non-contact regions are provided with semi-etched regions, forming a hollow structure between them and the packaging substrate. This structure not only ensures electrical connection between the frame portion and the packaging substrate, but also creates a hollow structure between the frame portion and the packaging substrate, optimizing material usage and achieving a lightweight semiconductor device. Furthermore, by reducing the need for soldering, metal conductive adhesive bonding, or polymer bonding, the efficiency of the packaging process is improved.

[0013] In one embodiment, the number of the non-contact areas is greater than or equal to two. The above structure facilitates injection molding.

[0014] In one embodiment, the width L2 of the contact area of ​​the frame portion is less than or equal to the width L3 of the pad on the package substrate for attaching the frame portion, and / or the first height H1 from the bottom of the package substrate to the bottom of the connecting portion is greater than or equal to the second height H2 from the bottom of the base to the top of the chip. This structure ensures a reliable connection between the frame portion and the package substrate.

[0015] In one embodiment, a hollow portion is provided in the middle of the connecting portion. Through the above structure, while ensuring the current carrying capacity, a heat dissipation channel can be formed in the hollow area to reduce thermal stress.

[0016] In one embodiment, the conductive area S1 between the connecting portion and the chip top electrode is greater than or equal to 50% of the conductive area S2 between the chip bottom electrode and the base. With the above structure, the flow capacity of the circuit can be ensured.

[0017] In one embodiment, the side length L1 of the connecting portion is greater than or equal to 50% of the width L2 of the frame portion. With the above structure, the flow capacity of the circuit can be ensured.

[0018] In one embodiment, the package substrate is tightly connected to the base on all sides, with the top and bottom surfaces of the package substrate exposed, and the first and second wiring layers are coplanar. This structure creates a compact structure while forming direct heat dissipation channels on both sides, greatly improving heat dissipation capabilities.

[0019] In one embodiment, a capacitor is further included; the second wiring layer is provided with a first pad, a second pad, a third pad, and a fourth pad; the plurality of chips include a first chip and a second chip, the first chip is provided with a first electrode, a second electrode, and a third electrode; the second chip is provided with a fourth electrode, a fifth electrode, and a sixth electrode; the first electrode is arranged on the top of the first chip and is electrically connected to the electrical connector; the first pad is connected between the second electrode of the first chip and the fourth electrode of the second chip; the second pad is connected between the third electrode of the first chip and the fifth electrode of the second chip; the sixth electrode of the second chip is connected to the fourth pad, the capacitor is connected between the third pad and the fourth pad, and the third pad and the fourth pad are used to connect to an external circuit. Through the above structure, a Kelvin bridge circuit connection can be formed on the line connection, which can realize fast switching control of the high-power semiconductor package.

[0020] In addition, the present invention also provides a method for preparing a semiconductor device, which is used to prepare the above-mentioned semiconductor device, comprising the following steps:

[0021] Prepare a base having a second wiring layer, a third wiring layer, a pad, a second electrical pin, a third electrical pin, and a fourth electrical pin;

[0022] preparing a packaging substrate having a first wiring layer and first electrical pins;

[0023] Embedding the base into the packaging substrate so that the top and bottom surfaces of the two are flush;

[0024] Fixing the chip to the corresponding pad on the top of the base;

[0025] Prepare an electrical connector having an integrated frame portion and a connecting portion, and provide a half-etched area on one side of the frame portion;

[0026] The electrical connector is connected to the top of the package substrate through at least one unetched contact area to form an electrical connection with the first wiring layer and to form an electrical connection with at least one chip electrode;

[0027] Covering the packaging substrate, the base, the chip and the electrical connector through a plastic packaging process to obtain a plastic-sealed semiconductor package;

[0028] The plastic-sealed semiconductor package is divided into a plurality of semiconductor devices.

[0029] Compared with the prior art, the method for preparing a semiconductor device of the present invention has the advantages of simplifying the production steps and improving the production efficiency of semiconductor devices.

[0030] For better understanding and implementation, the present invention is described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 This is a top view of the electrical connector of the semiconductor device in the first embodiment of the present invention when no hollow portion is provided;

[0032] Figure 2 A top view of the electrical connector of the semiconductor device in the first embodiment of the present invention with a hollow portion provided;

[0033] Figure 3 is a bottom view of the semiconductor device in the first embodiment of the present invention;

[0034] Figure 4 A top view of the base in the first embodiment of the present invention;

[0035] Figure 5 1 is a top view of the packaging substrate in the first embodiment of the present invention;

[0036] Figure 6 This is a top view of the assembled packaging substrate and base in the first embodiment of the present invention;

[0037] Figure 7 For the Figure 1 Sectional projection after cutting along line AA;

[0038] Figure 8 For the Figure 1 The sectional projection diagram after cutting along line BB;

[0039] Figure 9 Schematic diagram of the conductive area S1 between the electrical connector and the top of the chip in the first embodiment of the present invention;

[0040] Figure 10 Schematic diagram of the conductive area S2 between the electrode at the bottom of the chip and the base in the first embodiment of the present invention;

[0041] Figure 11 1 is a top view of the semiconductor package in the assembled state according to the first embodiment of the present invention;

[0042] Figure 12 is a top view of the semiconductor device in the second embodiment of the present invention;

[0043] Figure 13 is a top view of the semiconductor device in the third embodiment of the present invention;

[0044] Figure 14 Schematic diagram of the process for preparing a semiconductor device of the present invention;

[0045] Figure 15 This is a schematic diagram of the preparation of the base of the present invention;

[0046] Figure 16 This is a schematic diagram of the preparation of the packaging substrate of the present invention;

[0047] Figure 17 This is a schematic diagram of the chip and capacitor of the present invention when they are installed;

[0048] Figure 18 This is a schematic diagram of the electrical connector of the present invention during installation.

[0049] Figure markings: 1. Package substrate; 11. First wiring layer; 111. First electrical channel; 12. First electrical pin; 2. Base; 21. Second wiring layer; 211. Second electrical channel; 212. Third electrical channel; 213. Fourth electrical channel; 22. Third wiring layer; 23. Pad; 23A. First pad; 23B. Second pad; 23C. Third pad; 23D. Fourth pad; 24. Second electrical pin; 25. Third electrical pin; 26. Fourth electrical pin; 3. Electrical connector; 31. Frame portion; 311. Contact area; 312. Non-contact area; 32. Connecting portion; 33. Hollow portion; 4. Chip; 41. First chip; 42. Second chip; 5. Capacitor. DETAILED DESCRIPTION

[0050] To address the drawback of existing large-structure, high-power semiconductor devices, which are prone to generating large parasitic inductance, the applicant has proposed a semiconductor device that uses an electrical connector comprising a frame portion and a connecting portion to replace traditional wires to form a conductive surface. The first electrode of the chip is connected to the first electrical pin of the package substrate via the electrical connector, and the other electrodes are connected to the pads of the base. The conductive surface contact structure forms a low-impedance current path, thereby reducing the inductance peak caused by traditional wire bonding and reducing parasitic inductance. The following is a detailed description of the present invention with reference to the accompanying drawings.

[0051] Example 1:

[0052] Please refer to Figures 1 to 11 ,in, Figure 1A top view of a semiconductor device of the present invention using an electrical connector 3 having a square metal sheet structure; Figure 2 A top view of a semiconductor device of the present invention using an electrical connector 3 with a metal ring structure;

[0053] Figure 3 A bottom view of the semiconductor device of the present invention; Figure 4 A top view of the base 2 of the present invention; Figure 5 A top view of the packaging substrate 1 of the present invention; Figure 6 This is a top view of the package substrate 1 and the base 2 after assembly of the present invention; Figure 7 For the Figure 1 Sectional projection after cutting along line AA; Figure 8 For the Figure 1 The sectional projection diagram after cutting along line BB; Figure 9 is a schematic diagram of the conductive area S1 between the electrical connector and the top of the chip; Figure 10 Schematic diagram of the conductive area S2 between the electrode at the bottom of the chip and the base; Figure 11 It is a top view of the semiconductor package of the present invention in the assembled state.

[0054] Specifically, the semiconductor device of the present invention includes a package substrate 1 , a base 2 , a frame portion 31 , electrical connectors 3 and a plurality of chips 4 .

[0055] Among them, the packaging substrate 1 can be a traditional printed circuit board (PCB), which can meet the circuit layout design requirements, and the packaging substrate 1 includes a first wiring layer 11 and a first electrical pin 12. The first electrical pin 12 is arranged on the bottom surface of the packaging substrate 1 for connecting to an external working circuit. The first wiring layer 11 is provided with a first electrical channel 111 that vertically passes through the packaging substrate 1, and the electrical connection between the top surface of the packaging substrate 1 and the first electrical pin 12 at the bottom is realized through a vertical wiring structure. Based on the first wiring layer 11, the electrical connection between the electrical structure of the top surface of the packaging substrate 1 and the bottom electrical pin can be met. The first electrical pin 12 is used to electrically connect to the external working circuit, thereby meeting the electrical connection requirements of the semiconductor device and the external working circuit.

[0056] The base 2 can be a traditional copper-bonded ceramic plate (DBC), an aluminum-bonded ceramic plate (DAB), an active metal brazed ceramic plate (AMB) or an insulated metal substrate (IMS), and is embedded in the packaging substrate 1. The packaging substrate 1 is wrapped around the periphery of the base 2. The top surface of the base 2 is flush with and exposed to the top surface of the packaging substrate 1, and the bottom surface of the base 2 is flush with and exposed to the bottom surface of the packaging substrate 1, thereby improving the heat dissipation efficiency. In one embodiment, the four sides of the packaging substrate 1 and the base 2 are tightly connected by welding or sintering, and the front and back sides of the base 2 are not covered by substrate material, thereby forming a double-sided direct heat dissipation channel. The structure in which the bottom surface of the base 2 is flush with the bottom surface of the packaging substrate 1 allows the bottom surface of the base 2 to be directly mounted on the external working circuit along with the bottom surface of the semiconductor package. In conjunction with the heat dissipation structure of the external working circuit, efficient heat dissipation can be achieved, thereby improving the heat dissipation efficiency of the semiconductor device.

[0057] The base 2 includes a second wiring layer 21, a third wiring layer 22, a solder pad 23, a second electrical pin 24, a third electrical pin 25, and a fourth electrical pin 26. Based on the second wiring layer 21, a number of solder pads 23 are formed on the top surface of the base 2, and the chip 4 can be directly bonded to the solder pads 23. The second wiring layer 21 is provided with a second electrical channel 211, a third electrical channel 212, and a fourth electrical channel 213 that vertically penetrate the base 2 to electrically connect with the electrodes on the bottom surface of the chip 4. The second electrical pin 24, the third electrical pin 25, and the fourth electrical pin 26 are electrically connected to the second wiring layer 21 based on the second electrical channel 211, the third electrical channel 212, and the fourth electrical channel 213, respectively. The second electrical pin 24, the third electrical pin 25, and the fourth electrical pin 26 located at the bottom are used to electrically connect with an external working circuit. The second electrical pin 24 is connected to the first wiring layer 11 based on the second wiring layer 21, forming a loop between the first electrical pin 12 and the second electrical pin 24. The third wiring layer 22 is disposed on the base 2 and electrically connected to the second electrical channel 211, and is electrically connected to the first wiring layer 11 of the package substrate 1 and the second wiring layer 21 of the base 2, respectively. That is, the third wiring layer 22 is connected between the first wiring layer 11 and the second wiring layer 21.

[0058] The convenience of mounting the semiconductor device on other equipment can be improved by arranging the first electrical pin 12 and the second electrical pin 24 at the bottom of the package substrate 1 and the base 2. In addition, the vertical wiring structure can meet the requirements of miniaturization and compact packaging.

[0059] In one embodiment, the second wiring layer 21 and the third wiring layer 22 are planar circuit structures located at the same height in the base 2. The second wiring layer 21 is located on the top surface of the base 2. The third wiring layer 22 is arranged after the base 2 is embedded in the packaging substrate 1, so that the second wiring layer 21 and the third wiring layer 22 are connected. At the same time, the third wiring layer 22 is connected to the first wiring layer 11 located on the top surface of the packaging substrate 1, thereby achieving electrical connection between the first wiring layer 11 and the second wiring layer 21 through the third wiring layer 22.

[0060] In another embodiment, the third wiring layer 22 is laid on top of the second wiring layer 21 to form a stacked structure. The stacked structure can reduce the size of the entire structure.

[0061] Based on the electrical connection between the first wiring layer 11 inside the packaging substrate 1 and the second wiring layer 21 inside the base 2 and the chip 4, the connection method of wire bonding can be reduced, so that the internal circuit arrangement of the semiconductor device is compact, and miniaturized packaging and integrated packaging structure can be achieved.

[0062] The electrical connector 3 is a copper or aluminum component, and includes a frame portion 31 and a connecting portion 32 . The frame portion 31 is disposed on top of the package substrate 1 , and the connecting portion 32 is stacked on top of the frame portion 31 .

[0063] In this embodiment, a plurality of first electrical pathways 111 are sequentially arranged along two adjacent edges of the package substrate 1. Accordingly, the frame portion 31 extends along the adjacent edges of the package substrate 1 to cover the plurality of first electrical pathways 111 and form an electrical connection with the first wiring layer 11. The chip 4 is mounted on top of the base 2 to provide a compact structure. The connecting portion 32 covers the top of the frame portion 31 and extends from the frame portion 31 to the chip 4, electrically connecting thereto. Projected perpendicularly to the top surface of the base 2, in one embodiment, the outer contour of the connecting portion 32 is rectangular and flat, reducing manufacturing complexity while increasing current carrying capacity and reducing the effective area of ​​the current loop, thereby lowering inductance. In another embodiment, a hollow portion 33 is provided in the middle of the connecting portion 32, extending through the connecting portion 32 in an annular shape. While ensuring structural stability, the hollow portion 33 forms a heat dissipation channel, thereby reducing thermal stress and improving heat dissipation efficiency.

[0064] Furthermore, the bottom surface of the connecting portion 32 is substantially flush with the top surface of the chip 4. Figure 7, a first height H1 from the bottom of the package substrate 1 to the bottom of the connecting portion 32 is greater than or equal to a second height H2 from the bottom of the base 2 to the top of the chip 4 to further compact the structure.

[0065] The frame portion 31 is provided with a contact area 311 and a non-contact area 312. In the extension direction of the frame portion 31, the contact area 311 and the non-contact area 312 are arranged at intervals, and the thickness H3 of the contact area 311 is greater than the thickness H4 of the non-contact area 312. In one embodiment, the thickness H4 of the non-contact area 312 is 0. The contact area 311 is located directly above the first electrical channel 111 of the packaging substrate 1 and extends to the top of the packaging substrate 1, connecting with the packaging substrate 1 to form a conductive surface. The frame portion 31 is processed by half etching, so that the non-contact area 312 forms a half-etched area (not marked) on the bottom surface of the packaging substrate 1, and a hollow structure is formed between the non-contact area 312 and the top of the packaging substrate 1, thereby optimizing the utilization rate of the material and reducing the overall weight of the semiconductor device. The hollow structure has the function of heat dissipation, which can improve the heat dissipation efficiency. Preferably, the number of the non-contact areas 312 is greater than or equal to two to facilitate injection molding.

[0066] Furthermore, the width L2 of the contact area 311 of the frame portion 31 is less than or equal to the width L3 of the pad on the package substrate 1 for mounting the frame portion 31 , so as to ensure reliable connection between the frame portion 31 and the package substrate 1 .

[0067] By setting the electrical connector 3, the electrode on the top of the chip 4 is electrically connected to the first electrical pin 12 in sequence through the connecting portion 32 and the frame portion 31 of the electrical connector 3 and the first electrical channel 111 of the first wiring layer 11 of the packaging substrate 1.

[0068] Preferably, if Figure 9 and Figure 10 As shown, the conductive area S1 between the electrical connector 3 and the top of the chip 4 is greater than or equal to 50% of the conductive area S2 between the electrode at the bottom of the chip 4 and the base 2, and / or the side length L1 of the electrical connector 3 is greater than or equal to 50% of the width L2 of the frame portion 31 to ensure the flow of large current.

[0069] The chip 4 includes a first chip 41 and a second chip 42. A first electrode is provided on the top of the first chip 41, and a second electrode and a third electrode are provided on the bottom. A fourth electrode is provided on the top of the second chip 42, and a fifth electrode and a sixth electrode are provided on the bottom. The first electrode and the fourth electrode have the same electrical properties, the second electrode and the fifth electrode have the same electrical properties, and the third electrode and the sixth electrode have the same electrical properties. The bottoms of the first chip 41 and the second chip 42 are directly bonded to the base 2 based on a conductive medium. The base 2 serves as a heat dissipation base to directly dissipate heat from the first chip 41 and the second chip 42, thereby improving the heat dissipation effect.

[0070] The first electrical path 111 is provided with a pad, and the first electrode on the top of the first chip 41 and / or the second chip 42 is electrically connected to the pad of the first electrical path 111 via the electrical connector 3. Using the electrical connector 3 instead of traditional wire bonding can effectively increase current carrying capacity, reduce parasitic resistance in the loop between the chip and the package substrate, and thus reduce parasitic induction at the connection point.

[0071] The first pad 23A is electrically connected to the second electrode of the first chip 41, the second pad 23B is electrically connected to the fourth electrode of the second chip 42, and the second electrode and the fourth electrode are interconnected via the third wiring layer 22. The fifth electrode of the second chip 42 is attached to the third pad 23C, and the sixth electrode of the second chip 42 is attached to the fourth pad 23D. The third pad 23C is connected to the third electrical pin 25 via the third electrical path 212, and the fourth pad 23D is connected to the fourth electrical pin 26 via the fourth electrical path 213. The second wiring layer 21 is electrically connected to the third electrical pin 25 and the fourth electrical pin 26 respectively via the third electrical path 212 and the fourth electrical path 213. The third electrical pin 25 and the fourth electrical pin 26 are then connected to an external circuit, thereby effectively shortening the length of the electrical connection lines within the semiconductor package, simplifying the circuit layout of the semiconductor package, and achieving a compact package for the semiconductor package. The third wiring layer 22 is electrically connected between the third electrode of the first chip 41 and the fifth electrode of the second chip 42 .

[0072] Furthermore, a capacitor 5 is mounted between the third pad 23C and the fourth pad 23D, so that the capacitor 5 is connected between the fifth electrode and the sixth electrode, filtering the loop where the second chip 41 is located, thereby reducing the parasitic effects of the loop where the second chip 7 is located, and at the same time reducing the risk of high-frequency noise generated by the package during fast switching.

[0073] Furthermore, the second electrode of the first chip 41 and the fourth electrode of the second chip 42 form an interlaced electrical connection based on the third wiring layer 22; the third electrode of the first chip 41 and the fifth electrode of the second chip 42 are electrically connected based on the third wiring layer 22; the fifth electrode of the second chip 42 is connected to the external circuit through the third electrical pin 25, and the sixth electrode of the second chip 42 is connected to the external circuit through the fourth electrical pin 26, thereby forming a Kelvin bridge circuit connection on the line connection of the second chip 42, which can realize fast switching control of the high-power semiconductor package.

[0074] In this embodiment, the first electrode of the first chip 41 is the drain electrode, located at the top and connected to the electrical connector 3. The second electrode is the gate electrode of the first chip 41. The fourth electrode is the source electrode of the second chip 42. The second and fourth electrodes are interconnected via the first and second pads 23A and 23B. The fifth electrode is the gate electrode of the second chip 42. The capacitor 5 is a thin film capacitor such as a multilayer ceramic capacitor (MLCC) or a silicon-based capacitor, and is mounted to the base 2 via flip-chip or conductive adhesive.

[0075] Also, see Figure 11 The present invention further provides a semiconductor package comprising a plurality of the aforementioned semiconductor devices arranged in a panelized form. The electrical connectors 3 are mounted on corresponding positions of the assembled panelized structure of the package substrate 1 and the base 2. The semiconductor package is obtained by mounting the plurality of electrical connectors 3 one-to-one on the panelized structure and then performing a plastic encapsulation process. The plastic encapsulation process is then performed to fill the top of the chip 4. Finally, the semiconductor package is segmented using a laser segmentation device or the like to obtain the plurality of semiconductor devices, thereby improving the production efficiency of the semiconductor package.

[0076] Example 2:

[0077] The present invention also provides another semiconductor device. The difference between the semiconductor device of Example 2 and the semiconductor device of Example 1 is that: 1. The solder pads and wiring methods of the two are different; 2. In Example 2, the first electrical channel 111 is arranged along the edge of one side of the packaging substrate 1, so the frame portion 31 extends along the edge of one side of the packaging substrate 1, while the frame portion 31 of Example 1 extends along the two connected edges of the packaging substrate 1.

[0078] Specifically, see Figure 12In the second embodiment, the semiconductor device includes a packaging substrate 1, a base 2, an electrical connector 3, a plurality of chips 4 and a capacitor 5. The packaging substrate 1 includes a first wiring layer 11 and a first electrical pin 12. The first electrical pin 12 is electrically connected to the first wiring layer 11 and is used to connect to an external power supply. The base 2 is embedded in the packaging substrate 1 and includes a second wiring layer 21 and a second electrical pin 24. The second electrical pin 24 is electrically connected to the second wiring layer 21 and is used to connect to an external power supply. The connecting portion 32 of the electrical connector 3 is overlapped on the top surface of the frame portion 33, and the frame portion 33 extends along a side edge of the packaging substrate 1. The electrical connector 3 is electrically connected to the first wiring layer 11 of the packaging substrate 1. The plurality of chips 4 include a first chip 41 and a second chip 42 arranged on the top surface of the base 2. The second wiring layer of the base 2 is provided with a first solder pad 23A, a second solder pad 23B, a third solder pad 23C and a fourth solder pad 23D. The frame portion 31 of the electrical connector 3 is connected between the first electrodes at the top of the first chip 41. The first pad 23A is connected between the second electrode at the bottom of the first chip 41 and the fourth electrode of the second chip 42. The second pad 23B is connected between the third electrode at the bottom of the first chip 41 and the fifth electrode of the second chip 42. The sixth electrode of the second chip 42 is connected to the fourth pad 23D. The capacitor 5 is connected between the third pad 23C and the fourth pad 23D, and the third pad 23C and the fourth pad 23D are used to connect to an external power source.

[0079] The above configuration can make the structure of the semiconductor device more compact.

[0080] Example 3:

[0081] The present invention also provides another semiconductor device. The difference between the semiconductor device of Example 3 and the semiconductor device of Example 1 is that: 1. The solder pads and wiring methods of the two are different; 2. In Example 3, the first electrical channel 111 is arranged along the edge of one side of the packaging substrate 1, so the frame portion 31 extends along the edge of one side of the packaging substrate 1, while the frame portion 31 of Example 1 extends along the two connected edges of the packaging substrate 1.

[0082] Specifically, see Figure 13In embodiment three, the semiconductor device includes a packaging substrate 1, a base 2, an electrical connector 3, several chips 4 and a capacitor 5. The packaging substrate 1 includes a first wiring layer 11 and a first electrical pin 12. The first electrical pin 12 is electrically connected to the first wiring layer 11 and is used to connect to an external power supply. The base 2 is embedded in the packaging substrate 1 and includes a second wiring layer 21 and a second electrical pin 24. The second electrical pin 24 is electrically connected to the second wiring layer 21 and is used to connect to an external power supply. The connecting portion 32 of the electrical connector 3 is overlapped on the top surface of the frame portion 33, and the frame portion 33 extends along a side edge of the packaging substrate 1. The electrical connector 3 is electrically connected to the first wiring layer 11 of the packaging substrate 1. The several chips 4 include a first chip 41 and a second chip 42 arranged on the top surface of the base 2. The second wiring layer of the base 2 is provided with a first solder pad 23A, a second solder pad 23B, a third solder pad 23C and a fourth solder pad 23D. The frame portion 31 of the electrical connector 3 is connected between the first electrodes at the top of the first chip 41. The first pad 23A is connected between the second electrode at the bottom of the first chip 41 and the fourth electrode of the second chip 42. The second pad 23B is connected between the third electrode at the bottom of the first chip 41 and the fifth electrode of the second chip 42. The sixth electrode of the second chip 42 is connected to the fourth pad 23D. The capacitor 5 is connected between the third pad 23C and the fourth pad 23D, and the third pad 23C and the fourth pad 23D are used to connect to an external power source.

[0083] Through the above-mentioned configuration, the structure of the semiconductor device can be made more compact, and a Kelvin bridge circuit connection can be formed on the line connection, thereby realizing fast switching control of the high-power semiconductor package.

[0084] Further, refer to Figure 13 In order to simplify the process steps of the semiconductor device in the above-mentioned embodiments 1 to 3, improve the production efficiency of the semiconductor device, and achieve lightweight products and optimize material usage, the present invention also provides a method for preparing a semiconductor device, comprising the following steps:

[0085] S11 : preparing a base 2 having the second wiring layer 21 , the third wiring layer 22 , the pad 23 , the second electrical pin 24 , the third electrical pin 25 and the fourth electrical pin 26 .

[0086] Specifically, see Figure 15, select a copper-bonded ceramic plate (DBC), or aluminum-bonded ceramic plate (DAB), or active metal brazed ceramic plate (AMB) or insulated metal substrate (IMS) of appropriate size, and plate a metal layer, then use a patterned etching process to form the second wiring layer 21 and the third wiring layer 22 on the top of the base 2, and set the second electrical pin 24, the third electrical pin 25 and the fourth electrical pin 26 on the bottom of the base 2. At the same time, a laser drilling device is used to perform a drilling operation, opening a plurality of through-hole structures on the package substrate 1, and obtaining the second electrical channel 211, the third electrical channel 212 and the fourth electrical channel 213 by copper plug holes or coating a conductive layer.

[0087] Then, according to the mounting position of the chip 4 , a plurality of bonding pads 23 for die bonding are fixed on the second wiring layer 21 .

[0088] S12 : preparing a packaging substrate 1 having the first wiring layer 11 and the first electrical pins 12 .

[0089] Specifically, see Figure 16 A raw material plate of suitable size is selected to make the package substrate 1, and the thickness of the raw material plate used is substantially equal to the thickness of the base 2. The raw material plate is laser etched to remove the raw material plate in the middle area for the base 2 to fit into.

[0090] Then, a laser drilling device is used to perform a drilling operation to open a plurality of through-hole structures on the packaging substrate 1 , and the first electrical channel 111 is obtained by copper plug holes or coating a conductive layer.

[0091] S13: embed the base 2 into the packaging substrate 1 and make the top and bottom surfaces of the two flush.

[0092] Specifically, see Figure 16 The base 2 is placed in the hollow area in the middle of the package substrate 1, with the bottoms and tops of the base 2 aligned. The base 2 is tightly connected to the package substrate 1 by welding, sintering, or bonding with conductive adhesive to ensure electrical conductivity between the first wiring layer 11, the second wiring layer 21, and the third wiring layer 22.

[0093] S14: Fix the chip 4 and the capacitor 5 to the corresponding pads 23 on the top of the base 2.

[0094] Specifically, see Figure 17The electrodes at the bottom of the first chip 41 and the second chip 42 of the chip 4 are fixed to the top of the base 2 by a metal conductive adhesive or a polymer adhesive. The polymer adhesive can be epoxy resin or silicone, which has good bonding strength, good conductivity and thermal stability.

[0095] S15 : preparing the electrical connector 3 having an integrated frame portion 31 and a connecting portion 32 , and setting the half-etched area at the bottom of the frame portion 31 .

[0096] Specifically, see Figure 18 According to the position of the first electrical channel 111 on the packaging substrate 1, the copper or aluminum material is processed by photolithography-etching process to form a frame portion 31 extending along the top edge of the packaging substrate 1 and a connecting portion 32 arranged on the top of the frame portion 31 and integrally connected thereto, so that when the frame portion 31 is installed on the top of the packaging substrate 1, the bottom surface of the connecting portion 32 is basically flush with the top of the chip 4.

[0097] Then, a half-etched area is formed on the bottom of the frame portion 31 on the packaging substrate 1 by a half-etching process according to the first electrical channel 111. In this embodiment, a photoresist is used as a mask, and an etching process such as wet chemical etching or physical reactive ion etching is used to etch the bottom of the frame portion 31, and the pattern formed is the half-etched area. For the frame portion 31, in the extension direction of the frame portion 31, the portion with the half-etched area is the non-contact area 312, and the portion without the half-etched area is the contact area 311. The contact area 311 can be electrically connected to the first electrical channel 111, and the number thereof is at least one; the non-contact area 312 is spaced apart from the packaging substrate 1 to form a hollow structure, wherein, in one embodiment, the thickness H4 of the non-contact area 312 is 0.

[0098] Preferably, a hollow portion 33 is formed in the middle of the connecting portion 32 by a photolithography-etching process, etc., so as to improve the heat dissipation capability.

[0099] S16 : electrically connecting the electrical connector 3 to the top of the package substrate 1 , and electrically connecting the electrical connector 3 to the first wiring layer 11 and at least one chip 4 respectively.

[0100] Specifically, the bottom of the frame portion 31 faces the top of the package substrate 1, and the contact area 311 covers the first electrical channel 111, forming an electrical connection between the electrical connector 3 and the first wiring layer 11. The connecting portion 32 extends to the top of one of the chips 4 and is electrically connected to the electrode on its top.

[0101] S17: Obtain a semiconductor package through plastic encapsulation.

[0102] Specifically, the packaging substrate 1, the base 2 and the plurality of chips 4 are plastic-sealed by a plastic resin, and a plastic layer 1 is formed on top of the base 2 and the packaging substrate 1, so that the chip 4 is accommodated on the plastic layer, thereby obtaining Figure 11 The package of the imposition structure state shown.

[0103] The molding resin may be filled to the top of the panel structure, thereby improving the stability of the molding resin in molding the top of the panel structure.

[0104] S18: dividing the semiconductor package into a plurality of semiconductor devices.

[0105] Specifically, a cutting device is used to separate the package body along the cutting lines to obtain a plurality of semiconductor devices, and each semiconductor device is ensured to have a package substrate 1 and a base 2, and the semiconductor device is mechanically supported and protected by a plastic encapsulation colloid.

[0106] Compared with the prior art, the semiconductor device and the method for manufacturing the same of the present invention have the following advantages:

[0107] 1. Strong current carrying capacity and can reduce parasitic induction;

[0108] 2. It can realize the miniaturization and lightweight of semiconductor devices.

[0109] 3. Compact structure and high heat dissipation capacity.

[0110] 4. Simplify production steps and improve production efficiency.

[0111] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments and are not intended to limit the embodiments of the present application. The singular forms of "a", "said" and "the" used in the embodiments of the present application and the claims are also intended to include plural forms, unless the context clearly indicates other meanings. It should also be understood that, unless otherwise specified, "multiple" refers to two or more; the terms "first", "second", "third", etc. are only used to distinguish, and are not used to describe a specific order or sequence, nor can they be understood to indicate or imply relative importance. The term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items. When the above description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. In the description of the present application, for those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to the specific circumstances.

[0112] The above-described embodiments merely illustrate several implementations of the present invention. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, and all such variations and improvements fall within the scope of protection of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A packaging substrate, comprising a first wiring layer and a first electrical pin, wherein the first wiring layer is provided with a first electrical channel vertically penetrating the packaging substrate; the first electrical pin is located at the bottom of the packaging substrate and is electrically connected to the first wiring layer through the first electrical channel; A base, comprising a second wiring layer, a third wiring layer, and a second electrical pin; the base is embedded in the packaging substrate, and the top and bottom surfaces of the packaging substrate and the base are respectively flush; the second wiring layer is provided with a second electrical channel vertically penetrating the base; the second electrical pin is located at the bottom of the base and is electrically connected to the second wiring layer through the second electrical channel; the third wiring layer is electrically connected between the first wiring layer and the second wiring layer; An electrical connector includes a frame portion and a connecting portion; the frame portion extends along the edge of the packaging substrate at the top of the packaging substrate and is electrically connected to the first wiring layer, and the connecting portion extends from the top of the frame portion to above the base; and a plurality of chips are mounted on the top of the base, and the electrode on the top of at least one chip is electrically connected to the connecting portion; at least one electrode on the bottom of the chip is electrically connected to the second electrical pin based on the second wiring layer; the bottom electrodes of other chips are interconnected based on the third wiring layer.

2. The semiconductor device according to claim 1, wherein: The frame portion is provided with contact areas and non-contact areas at intervals in the extension direction; the contact areas are located directly above the first electrical channel and are electrically connected thereto; the non-contact areas are provided with half-etched areas to form a hollow structure between them and the packaging substrate.

3. The semiconductor device according to claim 2, wherein: The number of the non-contact areas is greater than or equal to two.

4. The semiconductor device according to claim 2, wherein: The width L2 of the contact area of ​​the frame part is less than or equal to the width L3 of the pad on the packaging substrate for mounting the frame part, and / or the first height H1 from the bottom of the packaging substrate to the bottom of the connecting part is greater than or equal to the second height H2 from the bottom of the base to the top of the chip.

5. The semiconductor device according to claim 1, wherein: Projected along a direction perpendicular to the top of the base, a hollow portion is provided in the middle of the connecting portion.

6. The semiconductor device according to claim 5, wherein: The conductive area S1 between the connecting portion and the chip top electrode is greater than or equal to 50% of the conductive area S2 between the chip bottom electrode and the base.

7. The semiconductor device according to claim 5, wherein: The side length L1 of the connecting portion is greater than or equal to 50% of the width L2 of the frame portion.

8. The semiconductor device according to claim 1, wherein: The packaging substrate is tightly connected to the base around its periphery, the top surface and the bottom surface of the packaging substrate are exposed respectively, and the first wiring layer and the second wiring layer are in the same plane.

9. The semiconductor device according to claim 1, wherein: It also includes a capacitor; the second wiring layer is provided with a first pad, a second pad, a third pad and a fourth pad; the several chips include a first chip and a second chip, the first chip is provided with a first electrode, a second electrode and a third electrode; the second chip is provided with a fourth electrode, a fifth electrode and a sixth electrode; the first electrode is arranged on the top of the first chip and is electrically connected to the electrical connector; the first pad is connected between the second electrode of the first chip and the fourth electrode of the second chip; the second pad is connected between the third electrode of the first chip and the fifth electrode of the second chip; the sixth electrode of the second chip is connected to the fourth pad, the capacitor is connected between the third pad and the fourth pad, and the third pad and the fourth pad are used to connect to an external circuit.

10. A method for preparing a semiconductor device, characterized in that: The preparation method is used to prepare the semiconductor device according to claim 1, comprising the following steps: Prepare a base having a second wiring layer, a third wiring layer, a pad, a second electrical pin, a third electrical pin, and a fourth electrical pin; preparing a packaging substrate having a first wiring layer and first electrical pins; Embedding the base into the packaging substrate so that the top and bottom surfaces of the two are flush; Fixing the chip to the corresponding pad on the top of the base; Prepare an electrical connector having an integrated frame portion and a connecting portion, and provide a half-etched area on one side of the frame portion; The electrical connector is connected to the top of the package substrate through at least one unetched contact area to form an electrical connection with the first wiring layer and to form an electrical connection with at least one chip electrode; Covering the packaging substrate, the base, the chip and the electrical connector through a plastic packaging process to obtain a plastic-sealed semiconductor package; The plastic-sealed semiconductor package is divided into a plurality of semiconductor devices.

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