Chip packaging structure and preparation method thereof

Abstract

The invention relates to a chip packaging structure and a preparation method thereof, the chip packaging structure comprises a substrate, a re-wiring layer, at least one insulation projection structure and at least one chip unit, the re-wiring layer is located on the substrate, and a plurality of bonding pads arranged at intervals are formed on the surface, far away from the substrate, of the re-wiring layer; the insulating convex structure is located on the surface, far away from the substrate, of the rewiring layer, and the insulating convex structure is located between the at least two bonding pads; the chip unit is arranged on the rewiring layer and is welded with the bonding pad. According to the chip packaging structure and the preparation method thereof, bridging short circuit in the welding process is prevented, the welding quality and the structural reliability of chip packaging are remarkably improved, and the electrical performance and the finished product yield of packaging are improved.

Description

Technical Field

[0001] The present application relates to the field of packaging technology, and in particular to a chip packaging structure and a preparation method thereof. Background Art

[0002] With the continuous development of chip packaging technology, flip chip (FC) welding technology has been widely used in the field of chip packaging process.

[0003] However, after the solder balls on the chip are directly soldered to the conductive pads on the substrate integrated structure through the flip-chip (FC) soldering process, the chip is prone to excessive warping and poor chemical copper plating in the subsequent process, which in turn causes the tin-silver alloy in the chip's solder balls to melt and cause bridging. This not only increases the risk of chip circuit short circuits, but also directly affects the normal function of the chip and the yield of the product.

[0004] In view of this, there is an urgent need for a chip packaging structure that can effectively solve the problem that bridging phenomenon is likely to occur during chip welding and thus lead to short circuit. Summary of the Invention

[0005] Based on this, it is necessary to provide a chip packaging structure and a preparation method thereof to address the problem that bridging phenomenon is easily generated during chip welding in the prior art, thereby causing short circuit.

[0006] To achieve the above objectives, the present application provides a chip packaging structure, including:

[0007] substrate;

[0008] A redistribution layer is located on the substrate, and a plurality of spaced-apart pads are formed on a surface of the redistribution layer away from the substrate;

[0009] At least one insulating protrusion structure is located on a surface of the redistribution layer away from the substrate, and the insulating protrusion structure is located between at least two adjacent pads;

[0010] At least one chip unit is disposed on the redistribution layer and welded to the pad.

[0011] In one embodiment, the chip unit also includes a welding structure, and the chip unit and the pad are welded through the welding structure. In the stacking direction of the substrate and the redistribution layer, the surface of the insulating protrusion structure away from the substrate is higher than the surface of the pad away from the substrate, and the thickness of the insulating protrusion structure is not greater than the sum of the thickness of the welding structure and the pad.

[0012] In one embodiment, the welding structure includes a conductive column provided on the chip unit and a welding portion provided on the conductive column, and the thickness of the insulating protrusion structure is not less than the sum of the thicknesses of the welding portion and the pad.

[0013] In one embodiment, the number of the insulating protrusion structures includes multiple, and the multiple insulating protrusion structures are arranged at intervals and distributed in multiple rows and columns, the solder pad is located between the insulating protrusion structures in adjacent columns, and / or the solder pad is located between the insulating protrusion structures in adjacent rows.

[0014] In one embodiment, at least one of the insulating protrusion structures surrounds the pad.

[0015] In one embodiment, the redistribution layer includes multiple metal routing layers and a dielectric layer located between the metal routing layers, wherein the metal routing layer located on the surface of the dielectric layer farthest from the substrate serves as the solder pad, and the insulating protrusion structure is located on the surface of the dielectric layer farthest from the substrate, and the material of the insulating protrusion structure is the same as that of the dielectric layer.

[0016] In one embodiment, the insulating protrusion structure comprises a flexible material.

[0017] On the other hand, the present application also provides a method for preparing a chip packaging structure, comprising:

[0018] providing a substrate;

[0019] forming a redistribution layer on the substrate, wherein a plurality of spaced-apart pads are formed on a surface of the redistribution layer away from the substrate;

[0020] forming at least one insulating protrusion structure on a surface of the redistribution layer away from the substrate, wherein the insulating protrusion structure is located between at least two adjacent pads;

[0021] At least one chip unit is arranged above the redistribution layer, and the chip unit is welded to the pad.

[0022] In one embodiment, forming at least one insulating protrusion structure on a surface of the redistribution layer away from the substrate includes:

[0023] At least one of dispensing process, printing process and inkjet printing is used to form at least one insulating protrusion structure on the surface of the redistribution layer away from the substrate, and the insulating protrusion structure is located between at least two adjacent pads.

[0024] In one embodiment, the chip unit further includes a welding structure, and the at least one chip unit disposed above the redistribution layer includes:

[0025] The welding structure is welded to the welding pad, so that the chip unit is welded to the welding pad.

[0026] The above-mentioned chip packaging structure and its preparation method, by providing an insulating protrusion structure around a plurality of spaced-apart pads formed on the surface of the redistribution layer away from the substrate, and at least one insulating protrusion structure is located between at least two adjacent pads, can effectively separate the adjacent pads during the welding process between the chip unit and the pad, prevent bridging short circuits during the welding process, significantly improve the welding quality and structural reliability of the chip package, and improve the electrical performance and finished product yield of the package. In addition, the provision of the insulating protrusion structure can provide effective spatial guidance during the mounting process of the chip unit, assist the welding structure in achieving coarse positioning, avoid mis-welding and excessive pressing of the pads during welding, help improve the mounting alignment efficiency and welding accuracy, and are suitable for high-density, high-consistency automated packaging processes. In addition, in some embodiments, the insulating protrusion structure is formed by at least one of a printing process, a dispensing process, or an inkjet printing process, with flexible graphics and high process compatibility. The size of the insulating protrusion structure can be freely adjusted and designed according to the chip size, pad layout, etc., and is widely applicable to advanced packaging technologies such as flip-chip and fan-out packaging, and has broad practical value and industrial application prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0028] Figure 1 A schematic cross-sectional view of a chip packaging structure provided in one embodiment;

[0029] Figure 2 A schematic top view of an insulating protrusion structure in a chip packaging structure provided in one embodiment;

[0030] Figure 3 Another schematic top view of the insulating protrusion structure in the chip packaging structure provided in one embodiment;

[0031] Figure 4 is a flow chart of a method for preparing a chip package provided in one embodiment;

[0032] Figure 5 A schematic diagram of the cross-sectional structure after forming an adhesion layer in the preparation method of a chip package provided in one embodiment;

[0033] Figure 6 A schematic diagram of the cross-sectional structure after forming a redistribution layer in a method for preparing a chip package provided in one embodiment;

[0034] Figure 7 A schematic diagram of the cross-sectional structure after forming an insulating protrusion structure in a chip package preparation method provided in one embodiment.

[0035] Description of reference numerals:

[0036] 1-substrate, 11-adhesion layer, 2-rewiring layer, 21-pad, 22-dielectric layer, 23-metal routing layer, 3-insulating protrusion structure, 4-chip unit, 5-welding structure, 51-conductive column, 52-welding part. DETAILED DESCRIPTION

[0037] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0039] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion.

[0040] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0041] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0042] See also Figure 1 The present application provides a chip packaging structure, including: a substrate 1, a redistribution layer 2, at least one insulating protrusion structure 3 and at least one chip unit 4, wherein the redistribution layer 2 is located on the substrate 1, and a plurality of spaced-apart pads 21 are formed on the surface of the redistribution layer 2 away from the substrate 1; the insulating protrusion structure 3 is located on the surface of the redistribution layer 2 away from the substrate 1, and the insulating protrusion structure 3 is located between at least two pads 21; the chip unit 4 is arranged on the redistribution layer 2 and is welded to the pads 21.

[0043] In the above example, by arranging an insulating protrusion structure 3 around a plurality of spaced-apart pads 21 formed on the surface of the redistribution layer 2 away from the substrate 1, and at least one insulating protrusion structure 3 is located between at least two adjacent pads 21, the adjacent pads 21 can be effectively separated during the welding process of the chip unit 4 and the pad 21, thereby preventing bridging short circuits from occurring during the welding process, significantly improving the welding quality and structural reliability of the chip package, and improving the electrical performance and finished product yield of the package. In addition, the setting of the insulating protrusion structure 3 can provide effective spatial guidance during the mounting process of the chip unit 4, assist in achieving coarse positioning of the welding structure, avoid mis-welding and excessive pressing of the pad 21 during welding, help improve the mounting alignment efficiency and welding accuracy, and is suitable for high-density, high-consistency automated packaging processes.

[0044] Illustratively, the substrate 1 is used to provide a stable support for the entire process, ensuring that the chip packaging structure can remain stable during the processing, thereby ensuring the smooth progress of the process and the reliability of the packaging quality.

[0045] In practical applications, substrate 1 is typically a temporary carrier. Once the chip package structure is effectively packaged and meets the established design requirements and performance indicators, a dissociation process can be performed to safely remove substrate 1 from the package structure. This design facilitates process operations while preventing substrate 1 from unnecessarily affecting the final package size and performance.

[0046] Substrate 1 can be made of glass, silicon, ceramic, or other suitable materials. In this embodiment, substrate 1 is made of glass. Glass substrates are widely used in chip packaging processes due to their excellent flatness, thermal stability, and chemical stability. The dimensions of substrate 1 can be selected based on actual conditions, provided that the chip packaging performance is met, and are not limited herein.

[0047] Exemplarily, the chip packaging structure also includes an adhesion layer 11, which is located on the upper surface of the substrate 1 and is used to achieve stable adhesion between the redistribution layer 2 and the substrate 1, ensuring that in subsequent process steps, the redistribution layer 2 and the chip unit 4 can remain stable and will not be displaced or fall off, thereby ensuring the accuracy and reliability of the process, and the adhesion layer 11 is also used for the dissociation of the substrate 1 in subsequent processes.

[0048] Adhesive layer 11 may be made from materials with excellent adhesion and thermal stability, such as epoxy adhesives, polyimide (PI), photopolymers, silicone materials, or other adhesive materials commonly used in semiconductor processes. The specific material selection can be adjusted based on actual process requirements, such as the need for subsequent stripping, delamination temperature, curing conditions, and adhesion strength.

[0049] In addition, the thickness of the adhesion layer 11 can be set according to the overall thickness control requirements of the desired packaging structure, usually between several microns and tens of microns, which not only ensures its adhesion function but also does not have a negative impact on the overall thickness of the structure.

[0050] By providing the adhesion layer 11, good interface stability is achieved between the substrate 1 and the redistribution layer 2, thereby improving the operation tolerance and yield of the overall chip packaging structure in subsequent multi-layer stacking, chip mounting and interconnection processes.

[0051] The chip packaging structure includes a redistribution layer 2, which is located on a substrate 1 and securely connected to the substrate 1 via an adhesive layer 11. The redistribution layer 2 comprises multiple metal routing layers 23 and a dielectric layer 22 located between the metal routing layers 23. The dielectric layer 22 is a polymer material with excellent electrical insulation, thermal stability, and mechanical strength, such as polyimide (PI), polyethylene terephthalate (PET), epoxy resin, photosensitive polyimide, BCB (benzocyclobutene), or other low-dielectric constant materials commonly used in semiconductor packaging. Adjacent metal routing layers 23 are electrically connected in sequence to form a complete, multi-layer interconnected circuit network, effectively optimizing signal transmission paths, reducing wiring complexity and length, and improving signal transmission efficiency and stability. The metal routing layers 23 are made of copper, gold, silver, aluminum, or other suitable highly conductive metal materials.

[0052] The metal trace layer 23 located on the surface of the dielectric layer 22 farthest from the substrate 1 serves as the solder pad 21. The solder pad 21 is used to achieve electrical connection with the solder structure 5, chip or other interconnected units in subsequent processes. To ensure the quality of the connection, the solder pad 21 has good flatness, weldability and conductivity, and the size and shape can be customized according to the chip packaging requirements. Furthermore, the solder pad 21 includes multiple and spaced pads. This layout can effectively avoid mutual interference between signals and ensure the accuracy and reliability of signal transmission. At the same time, the spaced pads 21 also provide sufficient operating space for subsequent packaging processes, facilitating process steps such as flip-chip (FC) soldering and wire bonding.

[0053] Therefore, the redistribution layer 2 not only enables electrical rerouting between the chip and external pins, but also improves the package's wiring density and functional scalability through a multi-layer stacked structure, supporting multi-chip integration or heterogeneous packaging. In this embodiment, the redistribution layer 2 includes five dielectric layers 22 and six metal routing layers 23.

[0054] In one embodiment, the insulating protrusion structure 3 is located on the surface of the dielectric layer 22 farthest from the substrate 1. The insulating protrusion structure 3 is made of the same material as the dielectric layer 22, thereby avoiding stress issues, preventing delamination or cracking, and enhancing structural stability. In this embodiment, the dielectric layer 22 and the insulating protrusion structure 3 are both made of polyimide.

[0055] In one embodiment, the insulating raised structure 3 comprises a flexible material or other suitable elastic polymer material, such as silicone, polyurethane, thermoplastic elastomer (TPE), or other materials with excellent flexibility, heat resistance, and stability. Flexible materials possess excellent elasticity and deformation recovery capabilities, absorbing and alleviating mechanical and thermal stresses experienced by the solder structure during thermal cycling or external shocks, reducing the risk of failures such as solder joint cracking and cold solder joints, and extending the service life of the packaged device. Furthermore, they effectively absorb and distribute thermal and mechanical stresses during chip operation, significantly reducing stress concentration-induced microcracks, solder joint fatigue, and even package failure, thereby improving the reliability and service life of the chip package structure in complex application environments such as thermal cycling and mechanical shock. Furthermore, the chip unit 4 experiences a certain degree of thermal expansion during operation. If structural stress is concentrated, this can easily lead to solder joint fatigue or failure. The insulating raised structure 3 is made of a flexible material, creating a certain degree of buffer space around the solder structure, effectively absorbing the thermal stress difference between the chip thermal expansion and the package structure, thereby reducing the effects of thermal fatigue during long-term use and improving the reliability and service life of the entire package structure.

[0056] It should be noted that the insulating protrusion structure 3 is made of insulating material, which not only prevents bridging or short circuiting during the welding process, but also provides local electric field shielding or edge insulation.

[0057] In one embodiment, see Figure 2 The number of insulating raised structures 3 includes multiple insulating raised structures 3, and the multiple insulating raised structures 3 are spaced apart and distributed in multiple rows and columns. The solder pads 21 are located between insulating raised structures 3 in adjacent columns, and / or the solder pads 21 are located between insulating raised structures 3 in adjacent rows, thereby forming an effective isolation area to prevent metal bridging during subsequent welding. This can significantly improve the independence and stability of the electrical connection, reduce the risk of short circuits, and improve product consistency and reliability. Exemplarily, the shape of the insulating raised structures 3 includes a quadrilateral.

[0058] In another embodiment, see Figure 3 , at least one insulating protrusion structure 3 surrounds the pad 21. Exemplarily, the insulating protrusion structure 3 is in a ring shape or a ring structure composed of multiple structures, which can uniformly mechanically buffer and protect the pad 21 from multiple directions, further enhancing the stress resistance and welding isolation effect of the insulating protrusion structure 3.

[0059] In one embodiment, the chip unit 4 also includes a welding structure 5, which is welded to the pad 21 through the welding structure 5. At least one chip unit 4 is arranged on the redistribution layer 2, and a signal transmission connection with the pad 21 is realized through the welding structure 5, thereby shortening the signal path, improving the signal transmission rate, and improving the thermal management performance.

[0060] In one embodiment, the soldering structure 5 includes a conductive column 51 disposed on the chip unit 4 and a soldering portion 52 disposed on the conductive column. The conductive column 51 is made of copper, which has good electrical conductivity, thermal conductivity, and mechanical strength, and can provide stable electrical connection and support. The soldering portion 52 is made of at least one of tin and silver and is disposed at or around the lower end of the conductive column 51 to achieve metal soldering between the chip unit 4 and the solder pad 21. The soldering portion 52 melts and wets the solder pad 21 during the reflow process, thereby completing the electrical connection. Therefore, during soldering, since the soldering portion 52 may expand and flow due to melting at high temperatures, the provision of the insulating protrusion structure 3 can effectively inhibit the molten solder ball from diffusing or bridging to the surrounding area, thereby reducing the risk of solder short circuits or cold solder joints.

[0061] In one embodiment, in the stacking direction of the substrate 1 and the redistribution layer 2, the surface of the insulating protrusion structure 3 away from the substrate 1 is higher than the surface of the pad 21 away from the substrate 1, and the thickness of the insulating protrusion structure 3 is not greater than the sum of the thicknesses of the welding structure 5 and the pad 21. Furthermore, the thickness of the insulating protrusion structure 3 is not less than the sum of the thicknesses of the welding portion 52 and the pad 21. Unlike the relatively thin insulating protrusion structure 3 formed by conventional photolithography, the prepared insulating protrusion structure 3 can reach a certain thickness, effectively avoiding the occurrence of bridging, and providing spatial coarse positioning assistance for the welding structure 5 without interfering with normal welding connections. This design helps to accurately align the welding structure 5 with the pad 21 during the automated packaging process, avoids mis-welding and excessive pressing of the pad 21 during welding, thereby improving welding efficiency and accuracy, and reducing the probability of solder joint offset or welding defects. Exemplarily, the thickness range of the pad 21 is 5~10µm, and in this embodiment, the thickness of the pad 21 is 7~8µm; the thickness range of the welding portion 52 is 20~25µm, and in this embodiment, the thickness of the welding portion 52 is 20µm; the thickness range of the insulating protrusion structure 3 is 30~35µm, and in this embodiment, the thickness of the insulating protrusion structure 3 is 30µm.

[0062] Therefore, by setting up the insulating protrusion structure 3 and flexibly designing the distribution position and size of the insulating protrusion structure 3, in the chip packaging structure, it can provide electrical isolation, prevent bridging, buffer thermal stress and mechanical stress, prevent packaging failure, provide welding auxiliary positioning, improve process consistency, and enhance the reliability and service life of the final package.

[0063] Exemplarily, the chip packaging structure also includes a packaging structure (not shown), which covers the chip unit 4 and is used to achieve physical protection, electrical isolation and environmental sealing of the chip unit 4, thereby improving the reliability and stability of the overall packaging.

[0064] In one embodiment, see Figure 4 , the present application also provides a method for preparing a chip packaging structure, comprising the following steps:

[0065] Step S1: providing a substrate 1;

[0066] Step S2: forming a redistribution layer 2 on the substrate 1, and providing a plurality of spaced-apart pads 21 on a surface of the redistribution layer 2 away from the substrate 1;

[0067] Step S3: forming at least one insulating protrusion structure 3 on the surface of the redistribution layer 2 away from the substrate 1 , and the insulating protrusion structure 3 is located between at least two adjacent pads 21 ;

[0068] Step S4 : disposing at least one chip unit 4 on the redistribution layer 2 , and soldering the chip unit 4 to the pad 21 .

[0069] Specifically, see Figure 5 , execute step S1 and provide a substrate 1.

[0070] In one embodiment, the method further includes forming an adhesion layer 11 on the substrate 1. Exemplarily, the method of forming the adhesion layer 11 on the substrate 1 includes coating, printing or other suitable methods to accurately control the thickness of the formed adhesion layer 11.

[0071] Specifically, see Figure 6 , executing step S2 , forming a redistribution layer 2 on the substrate 1 , and forming a plurality of spaced-apart pads 21 on a surface of the redistribution layer 2 away from the substrate 1 .

[0072] Exemplarily, the redistribution layer 2 includes multiple metal wiring layers 23 and dielectric layers 22 located between the metal wiring layers 23 , wherein the dielectric layer 22 is formed by spin coating, printing, lamination, or the like.

[0073] Forming the metal routing layer 23 includes: forming through holes or blind holes in the dielectric layer 22 by laser etching or photolithography; obtaining the metal routing layer 23 on the through holes or blind holes and the surface of the dielectric layer 22 by sputtering, chemical plating or electroplating, wherein the metal routing layer 23 on the surface of the dielectric layer 22 farthest from the substrate 1 serves as the pad 21.

[0074] It should be noted that the multi-layer dielectric layer 22 and metal routing layer 23 included in the above-mentioned redistribution layer 2 are all formed by the above-mentioned method, and it should be noted that after a dielectric layer 22 and a metal routing layer 23 are formed on the substrate 1, the subsequent dielectric layer 22 is formed on the previously formed dielectric layer 22, and the bottom of the subsequently formed metal routing layer 23 is electrically connected to the top of the previously formed metal routing layer 23.

[0075] Specifically, see Figure 7, executing step S3 , forming at least one insulating protrusion structure 3 on the surface of the redistribution layer away from the substrate, and the insulating protrusion structure 3 is located between at least two adjacent pads 21 .

[0076] In one embodiment, the step of forming at least one insulating protrusion structure 3 on the surface of the redistribution layer 2 away from the substrate 1 includes:

[0077] At least one insulating raised structure 3 is formed on the surface of the redistribution layer 2 facing away from the substrate 1 through at least one of a dispensing process, a printing process, and an inkjet printing process. The insulating raised structure 3 is located between at least two adjacent pads 21. Through at least one of the dispensing process, the printing process, and the inkjet printing process, the formed insulating raised structure 3 can be precisely controlled to form multiple spaced or surrounding structures. Furthermore, the thickness of the formed insulating raised structure 3 can be precisely controlled, allowing for flexible design adjustments based on chip size, pad 21 layout, and other factors. This makes the insulating raised structure 3 widely applicable to advanced packaging technologies such as flip-chip and fan-out packaging.

[0078] During the welding process between the chip unit 4 and the pad 21, the insulating protrusion structure 3 effectively isolates the adjacent welding structure 5, preventing the occurrence of solder bridges or short circuits during the welding process, thereby significantly reducing the probability of bridging defects and improving the electrical performance and overall reliability of the product; the insulating protrusion structure 3 serves as a buffer layer in the pad 21 area, which can effectively absorb and disperse mechanical stress and thermal stress from the outside world, reduce the risk of cracks or failures caused by stress concentration, thereby improving the stability of the packaging structure and extending the service life of the product; the insulating protrusion structure 3 also provides a coarse positioning reference during the packaging process, which helps to accurately align the pad 21 during the welding process, improve welding accuracy and consistency of batch production, and is conducive to achieving high-density and high-yield manufacturing requirements.

[0079] Specifically, see Figure 1 , executing step S4 , disposing at least one chip unit 4 above the redistribution layer 2 , and soldering the chip unit 4 to the pad 21 .

[0080] In one embodiment, the chip unit 4 further includes a soldering structure 5. At least one chip unit 4 is disposed above the redistribution layer 2, including:

[0081] The soldering structure 5 is soldered to the soldering pad 21, so that the chip unit 4 is soldered to the soldering pad 21. That is, the chip unit 4 is placed on the redistribution layer 2 in a flip-chip manner. A placement machine or a precision alignment system is used to assist in alignment with the insulating protrusion structure 3, so that the chip unit 4 is accurately placed in a preset position.

[0082] In one embodiment, after at least one chip unit 4 is set above the redistribution layer 2, it also includes: forming a packaging structure covering the chip unit 4 to achieve physical protection, electrical isolation and environmental sealing of the chip unit 4, thereby improving the reliability and stability of the overall packaging.

[0083] In one embodiment, after forming the packaging structure covering the chip unit 4, it also includes: removing the substrate 1. After the packaging structure is formed, the adhesion layer 11 can be subjected to laser dissociation, thermal stripping or wet etching process to remove the substrate 1.

[0084] The chip packaging structure prepared by the above-mentioned chip packaging structure preparation method exhibits excellent performance in a complex usage environment, meeting the requirements of modern chip packaging for high performance, high reliability and high precision.

[0085] It should be understood that although Figure 4 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. In addition, Figure 4 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The order of execution of these steps or stages is not necessarily one by one, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0086] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. Although these terms are used interchangeably throughout this specification, they do not necessarily refer to the same embodiment or example.

[0087] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0088] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A chip packaging structure, characterized in that: include: substrate; A redistribution layer is located on the substrate, and a plurality of spaced-apart pads are provided on a surface of the redistribution layer away from the substrate; At least one insulating protrusion structure is located on a surface of the redistribution layer away from the substrate, and the insulating protrusion structure is located between at least two adjacent pads; At least one chip unit is disposed on the redistribution layer and welded to the pad.

2. The chip packaging structure according to claim 1, wherein: The chip unit also includes a welding structure, and the chip unit and the welding pad are welded through the welding structure. In the stacking direction of the substrate and the redistribution layer, the surface of the insulating protrusion structure away from the substrate is higher than the surface of the welding pad away from the substrate, and the thickness of the insulating protrusion structure is not greater than the sum of the thickness of the welding structure and the welding pad.

3. The chip packaging structure according to claim 1, wherein: The welding structure includes a conductive column arranged on the chip unit and a welding portion arranged on the conductive column. The thickness of the insulating protrusion structure is not less than the sum of the thicknesses of the welding portion and the pad.

4. The chip packaging structure according to claim 1, wherein: There are multiple insulating protrusion structures, and the multiple insulating protrusion structures are spaced apart and distributed in multiple rows and columns. The solder pad is located between the insulating protrusion structures in adjacent columns, and / or the solder pad is located between the insulating protrusion structures in adjacent rows.

5. The chip packaging structure according to claim 1, wherein: At least one of the insulating protrusion structures surrounds the pad.

6. The chip packaging structure according to claim 1, wherein: The redistribution layer includes multiple metal routing layers and a dielectric layer located between the metal routing layers, wherein the metal routing layer located on the surface of the dielectric layer farthest from the substrate serves as the solder pad, and the insulating protrusion structure is located on the surface of the dielectric layer farthest from the substrate, and the material of the insulating protrusion structure is the same as that of the dielectric layer.

7. The chip packaging structure according to claim 1, wherein: The insulating protrusion structure includes a flexible material.

8. A method for preparing a chip packaging structure, characterized in that: include: providing a substrate; forming a redistribution layer on the substrate, wherein a plurality of spaced-apart pads are provided on a surface of the redistribution layer away from the substrate; forming at least one insulating protrusion structure on a surface of the redistribution layer away from the substrate, wherein the insulating protrusion structure is located between at least two adjacent pads; At least one chip unit is arranged above the redistribution layer, and the chip unit is welded to the pad.

9. The method for preparing a chip packaging structure according to claim 8, wherein: The step of forming at least one insulating protrusion structure on a surface of the redistribution layer away from the substrate comprises: At least one of dispensing process, printing process and inkjet printing is used to form at least one insulating protrusion structure on the surface of the redistribution layer away from the substrate, and the insulating protrusion structure is located between at least two adjacent pads.

10. The method for preparing a chip packaging structure according to claim 8, wherein: The chip unit further includes a welding structure, and the at least one chip unit is arranged above the redistribution layer, including: The welding structure is welded to the welding pad, so that the chip unit is welded to the welding pad.

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