Charge pump circuit, chip and electronic equipment

Abstract

The invention provides a charge pump circuit, a chip and electronic equipment, and relates to the field of integrated circuits. The non-overlapping unit is connected with the level conversion unit, and the non-overlapping unit is used for receiving a clock signal, converting the clock signal into a first signal and a second signal and transmitting the first signal and the second signal to the level shifting unit. The level shift unit is connected with the N-time boost charge pump unit, and the level shift unit is used for performing level shift on the first signal and the second signal by using the output voltage of the N-time boost charge pump unit to generate a third signal and a fourth signal, and transmitting the third signal and the fourth signal to the N-time boost charge pump unit. And the N-time boost charge pump unit is used for generating an output voltage based on the third signal and the fourth signal to realize cascade N-time boost. According to the invention, only one group of non-overlapping clock signals is utilized to carry out cascade N-time voltage amplification. The whole circuit has the advantages of small number of required capacitors, high loading capacity, simple circuit structure and the like, and can be applied to the fields of control circuits of low-voltage LDOs and the like.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a charge pump circuit, a chip, and an electronic device. Background Art

[0002] Current power supply chips typically have a wide input voltage range to accommodate complex operating conditions. In low-voltage environments, the control circuitry of power supply chips (such as LDOs) may not function properly, necessitating a boost circuit (such as a charge pump) to power the control circuitry.

[0003] Traditional charge pumps have the following characteristics: strong load capacity, minimal capacitance, simple circuitry, and low-voltage operation. Traditional doubler charge pumps can achieve even-frequency boosting through cascading, but cannot achieve N-fold voltage amplification. While Dickson charge pumps can achieve N-fold voltage amplification through cascading, they suffer from significant voltage losses and the high capacitance required.

[0004] Therefore, there is an urgent need to propose a charge pump with N-fold voltage amplification that has small cascade voltage loss and requires less capacitance. Summary of the Invention

[0005] In view of the above problems, the present invention proposes a charge pump circuit, a chip and an electronic device.

[0006] An embodiment of the present invention provides a charge pump circuit, the charge pump circuit comprising: a non-overlapping unit, a level shifting unit, and an N-fold boost charge pump unit;

[0007] The non-overlapping unit is connected to the level conversion unit, and is used to receive a clock signal, convert the clock signal into a first signal and a second signal, and transmit the first signal and the second signal to the level shifting unit, wherein the first signal and the second signal are two-phase non-overlapping clock signals;

[0008] The level shift unit is connected to the N-fold boost charge pump unit, and is used to use the output voltage of the N-fold boost charge pump unit to level-shift the first signal and the second signal respectively, generate a third signal and a fourth signal, and transmit them to the N-fold boost charge pump unit;

[0009] The N-fold boost charge pump unit is configured to generate the output voltage based on the third signal and the fourth signal, thereby achieving cascade N-fold boost;

[0010] The third signal and the fourth signal are respectively used to control the on or off of different switches in the N-fold boost charge pump unit.

[0011] Optionally, the N-fold boost charge pump unit includes: at least one basic unit;

[0012] A plurality of the basic units are cascaded to form the N-fold boost charge pump unit;

[0013] Wherein, when the N-fold boost charge pump unit is formed by only one basic unit, N=2, the N-fold boost charge pump unit is a 2-fold boost unit, and its output voltage is twice the power supply voltage;

[0014] When the N-fold boost charge pump unit is formed by n basic units, N=n+1, the N-fold boost charge pump unit is an N-fold boost unit, and its output voltage is N times the power supply voltage.

[0015] Optionally, the basic unit includes: a plurality of switches and a boost capacitor;

[0016] The first end of the upper plate input switch among the multiple switches receives the power supply voltage, and the second end is connected to the upper plate of the boost capacitor and the first end of the upper plate output switch among the multiple switches, respectively, and the second end of the upper plate output switch is the output end of the basic unit;

[0017] The first end of the lower plate input switch among the multiple switches receives the power supply voltage, and the second end is connected to the lower plate of the boost capacitor and the first end of the grounding switch among the multiple switches respectively, and the second end of the grounding switch is grounded.

[0018] Optionally, when multiple basic units are cascaded, the upper plate output switch in the front-stage basic unit serves as a cascade switch for cascading with the rear-stage basic unit, and it and the ground switch in the rear-stage basic unit are controlled by the same signal, and the remaining two switches in the rear-stage basic unit are controlled by another signal.

[0019] Optionally, the upper plate input switch and the ground switch are both controlled by the third signal, and the lower plate input switch and the upper plate output switch are both controlled by the fourth signal; or,

[0020] The upper plate input switch and the ground switch are both controlled by the fourth signal, and the lower plate input switch and the upper plate output switch are both controlled by the third signal.

[0021] Optionally, the level shift unit includes: a first shift subunit and a second shift subunit;

[0022] The first shift subunit receives the first signal, and performs level shift on the first signal using the output voltage to generate the third signal;

[0023] The second shift subunit receives the second signal, and performs level shift on the second signal using the output voltage to generate the fourth signal.

[0024] Optionally, the first signal becomes a high level at the rising edge of the clock signal, and its high level duration is shorter than the high level duration of the clock signal; the second signal becomes a high level at the falling edge of the clock signal, and its high level duration is shorter than the low level duration of the clock signal; or

[0025] The first signal becomes a high level at the falling edge of the clock signal, and its high level duration is shorter than the low level duration of the clock signal. The second signal becomes a high level at the rising edge of the clock signal, and its high level duration is shorter than the high level duration of the clock signal.

[0026] Optionally, the third signal is in phase with the first signal, and a voltage corresponding to the third signal is greater than a voltage corresponding to the first signal;

[0027] The fourth signal is in phase with the second signal, and a voltage corresponding to the fourth signal is greater than a voltage corresponding to the second signal;

[0028] The voltages corresponding to the third signal and the fourth signal are sufficient to make the corresponding control switches fully turned on or off.

[0029] An embodiment of the present invention provides a chip, comprising: a charge pump circuit as described in any one of the above items.

[0030] An embodiment of the present invention provides an electronic device, comprising: the charge pump circuit as described in any one of the above items.

[0031] The charge pump circuit of the present invention includes a non-overlapping unit, a level shifting unit, and an N-fold boost charge pump unit. The non-overlapping unit is connected to the level shifting unit and is configured to receive a clock signal and convert the clock signal into a first signal and a second signal, which are then transmitted to the level shifting unit. The first signal and the second signal are two non-overlapping clock signals.

[0032] The level shift unit is connected to the N-fold boost charge pump unit. The level shift unit is used to use the output voltage of the N-fold boost charge pump unit to level shift the first signal and the second signal respectively, generate a third signal and a fourth signal, and transmit them to the N-fold boost charge pump unit.

[0033] The N-fold boost charge pump unit is used to generate an output voltage based on a third signal and a fourth signal to achieve cascade N-fold boost; wherein the third signal and the fourth signal are respectively used to control different switches in the N-fold boost charge pump unit to turn on or off.

[0034] The charge pump circuit provided by the present invention creatively proposes cascading N-fold voltage amplification using only a set of non-overlapping clock signals (a third signal and a fourth signal). The non-overlapping clock signals are generated by clock signal conversion and level shifting by non-overlapping units. These two non-overlapping clock signals are used to control switches in the N-fold boost charge pump unit, enabling the charge pump circuit to achieve cascaded N-fold voltage amplification.

[0035] Since the conduction losses of the entire circuit are primarily determined by the switching frequency at low switching frequencies, and by the conduction losses of the switch tube at high switching frequencies, a higher switching frequency and switch size are beneficial for improving the charge pump's conversion efficiency. The entire circuit has advantages such as a small number of required capacitors, high load capacity, and a simple circuit structure, making it suitable for applications such as low-voltage LDO control circuits. The charge pump circuit proposed in this invention is highly practical. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the preferred embodiment below. The accompanying drawings are for illustration purposes only and are not to be considered as limiting the present invention. The same reference symbols are used throughout the drawings to represent the same components. In the drawings:

[0037] Figure 1 is a modular schematic diagram of a charge pump circuit according to an embodiment of the present invention;

[0038] Figure 2 1 is a structural diagram of a preferred charge pump circuit in an embodiment of the present invention;

[0039] Figure 3 1 is a schematic diagram of a circuit structure of an optimal N-fold boost charge pump unit 30 in an embodiment of the present invention;

[0040] Figure 4 is a timing waveform diagram of each signal in an embodiment of the present invention;

[0041] Figure 5 Schematic diagram of the output voltage and the upper board voltage of each stage of the boost capacitor when the input voltage VOUT is 1V in an embodiment of the present invention. DETAILED DESCRIPTION

[0042] In order to make the above-mentioned objects, features and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present invention, are only part of the embodiments of the present invention, not all of the embodiments, and are not intended to limit the present invention.

[0043] The charge pump circuit of the present invention comprises: a non-overlapping unit, a level shift unit and an N-fold boost charge pump unit. Figure 1 The modular schematic diagram of the charge pump circuit shown in FIG. 1 shows a non-overlapping unit 10 connected to a level shifting unit 20. The non-overlapping unit 10 is configured to receive a clock signal CLK (generated by a clock unit 40) and convert the clock signal CLK into a first signal CLK1 and a second signal CLK2, which are then transmitted to the level shifting unit 20. The first signal CLK1 and the second signal CLK2 are two clock signals with non-overlapping phases. That is, the first signal CLK1 and the second signal CLK2 are not simultaneously high or low. When the first signal CLK1 is high, the second signal CLK2 is definitely low; and when the first signal CLK1 is low, the second signal CLK2 is definitely high.

[0044] The level shift unit 20 is connected to the N-fold boost charge pump unit 30. The level shift unit 20 is used to use the output voltage VOUT of the N-fold boost charge pump unit 30 to level-shift the first signal CLK1 and the second signal CLK2 respectively to generate a third signal CLKA and a fourth signal CLKB, which are transmitted to the N-fold boost charge pump unit 30.

[0045] The N-fold boost charge pump unit 30 is used to generate an output voltage VOUT based on the third signal CLKA and the fourth signal CLKB, thereby achieving cascade N-fold boosting. The third signal CLKA and the fourth signal CLKB are respectively used to control different switches in the N-fold boost charge pump unit 30 to be turned on or off.

[0046] There are many ways for the clock unit 40 to generate a clock signal, and any one of these ways can be used to generate a clock signal to provide a stable clock for the charge pump circuit. For example, a fixed current can be used to charge and discharge a capacitor (this capacitor is not the capacitor in the N-fold boost charge pump unit 30, but the capacitor in the clock unit 40) to provide a stable clock for the charge pump circuit. According to the capacitor charge and discharge formula Q=C*U and Q=I*T, the charge and discharge time T=(C*U) / T can be obtained. Therefore, a current mirror can be used to replicate a fixed discharge current, and a comparator flip can be used to determine a fixed discharge voltage to obtain a certain clock frequency.

[0047]

[0048] The clock signal CLK generated by the clock unit 40 is received by the non-overlapping unit 10 and converted into two non-overlapping clock signals, namely the first signal and the second signal. A preferred method for converting a clock signal into two non-overlapping clock signals is to use a delay method to convert the clock signal into two non-overlapping clock signals.

[0049] Since the non-overlapping unit 10 does not affect the voltage of the clock signal, the voltages of the first signal and the second signal (i.e., the amplitudes of the two signals) are the same as the voltage of the clock signal CLK. Furthermore, since the voltage of the clock signal CLK is generally in the low voltage domain, this voltage may not be sufficient to fully turn on or off the switch in the N-fold boost charge pump unit 30. Therefore, it is necessary to boost the voltages of the first signal and the second signal so that both voltages are raised to the high voltage domain to fully turn on or off the switch in the N-fold boost charge pump unit 30. To achieve this goal, a preferred method is to use the level shift unit 20.

[0050] In one embodiment of the present invention, the preferred structure of the level shift unit 20 includes: a first shift subunit 201 and a second shift subunit 202; Figure 2 The structure of a preferred charge pump circuit is shown in FIG. A first shift subunit 201 receives a first signal CLK1 and uses the output voltage VOUT to level-shift the first signal CLK1, generating a third signal CLKA. A second shift subunit 202 receives a second signal CLK2 and uses the output voltage VOUT to level-shift the second signal CLK2, generating a fourth signal CLKB. The output voltage VOUT is used because only the output voltage VOUT of the entire charge pump circuit is in the high voltage domain. Therefore, the output voltage VOUT is used as the high level for level shifting in the level shift unit 20.

[0051] In one embodiment of the present invention, the N-fold boost charge pump unit 30 is a creative improvement to the traditional double boost circuit, and the preferred structure includes: at least one basic unit; when multiple basic units are cascaded, an N-fold boost charge pump unit can be formed.

[0052] When the N-fold boost charge pump unit 30 is formed by only one basic unit, N=2, and the N-fold boost charge pump unit 30 is a 2-fold boost unit, and its output voltage is twice the power supply voltage. In other words, when the N-fold boost charge pump unit 30 is formed by only one basic unit, it is functionally equivalent to a traditional 2-fold boost circuit, and its output voltage VOUT is twice the power supply voltage VDD.

[0053] Naturally, it can be understood that when the N - fold boost charge pump unit 30 is formed by two basic units, N = 3, and the N - fold boost charge pump unit 30 is a 3 - fold boost unit, and its output voltage is 3 times the power supply voltage. That is to say, when the N - fold boost charge pump unit 30 is composed of two basic units, it is functionally equivalent to a 3 - fold boost circuit, and its output voltage VOUT is 3 times the power supply voltage VDD. By analogy, when the N - fold boost charge pump unit 30 is formed by n basic units, N = n + 1, the N - fold boost charge pump unit is an N - fold boost unit, and its output voltage VOUT is N times the power supply voltage VDD. That is: the number of cascaded basic units plus 1 is equal to the multiple of the boost of the charge pump circuit.

[0054] To better understand the N - fold boost charge pump unit 30 proposed in the present invention, refer to Figure 3 the schematic diagram of the circuit structure of a preferred N - fold boost charge pump unit 30 shown in Figure 3 The left - most Stage1 in it is the circuit structure of the basic unit, which includes multiple switches: two switches S1, two switches S2, and a boost capacitor C1.

[0055] The first end of the upper - plate input switch S1 among the multiple switches receives the power supply voltage VDD, and the second end is respectively connected to the upper plate of the boost capacitor C1 and the first end of the upper - plate output switch S2 among the multiple switches. The second end of the upper - plate output switch S2 is the output end of the basic unit. The first end of the lower - plate input switch S2 among the multiple switches receives the power supply voltage VDD, and the second end is respectively connected to the lower plate of the boost capacitor C1 and the first end of the grounding switch S1 among the multiple switches. The second end of the grounding switch S1 is grounded.

[0056] That is, in the circuit structure shown in Stage1, exemplified by a "T - shaped" structure, the upper - plate input switch S1 and the upper - plate output switch S2 are the two switches located at the "-" position of the "T - shaped"; the grounding switch S1 and the lower - plate input switch S2 are the two switches located at the "|" position of the "T - shaped".

[0057] The top plate input switch S1 and the ground switch S1 are both designated "S1" to indicate that they are controlled by the same signal. Naturally, the top plate output switch S2 and the plate input switch S2 are both designated "S2" to indicate that they are controlled by the same signal. Specifically, the top plate input switch S1 and the ground switch S1 are both controlled by the third signal CLKA, while the bottom plate input switch S2 and the top plate output switch S2 are both controlled by the fourth signal CLKB. Alternatively, the top plate input switch S1 and the ground switch S1 are both controlled by the fourth signal CLKB, while the bottom plate input switch S2 and the top plate output switch S2 are both controlled by the third signal CLKA. This is sufficient as long as the switch designated "S1" and the switch designated "S2" are controlled by different signals.

[0058] Since the third signal and the fourth signal are two-phase non-overlapping clock signals, the switch labeled “ S1 ” and the switch labeled “ S2 ” will not be turned on or off at the same time. It is only possible that one is turned on while the other is turned off.

[0059] Reference Figure 4 In the timing waveforms of the various signals shown, the first signal CLK1 becomes high at the rising edge of the clock signal CLK, and its high-level duration is shorter than the high-level duration of the clock signal CLK. The second signal CLK2 becomes high at the falling edge of the clock signal CLK, and its high-level duration is shorter than the low-level duration of the clock signal CLK. Of course, it is also possible that the first signal CLK1 becomes high at the falling edge of the clock signal CLK, and its high-level duration is shorter than the low-level duration of the clock signal CLK, and the second signal CLK2 becomes high at the rising edge of the clock signal CLK, and its high-level duration is shorter than the high-level duration of the clock signal CLK.

[0060] Depend on Figure 4 It can also be seen that the third signal CLKA is in phase with the first signal CLK1, and the voltage corresponding to the third signal CLKA is greater than the voltage corresponding to the first signal CLK1; the fourth signal CLKB is in phase with the second signal CLK2, and the voltage corresponding to the fourth signal CLKB is greater than the voltage corresponding to the second signal CLK2; wherein, the voltages corresponding to the third signal CLKA and the fourth signal CLKB respectively satisfy the conditions for fully turning on or off the corresponding control switches.

[0061] Combine Figure 3 In the structure of the basic unit, it is assumed that the upper plate input switch S1 and the ground switch S1 are both controlled by the third signal CLKA, and the lower plate input switch S2 and the upper plate output switch S2 are both controlled by the fourth signal CLKB.

[0062] When the third signal CLKA goes high and the fourth signal CLKB goes low, both the top-plate input switch S1 and the ground switch S1 are turned on, while both the bottom-plate input switch S2 and the top-plate output switch S2 are turned off. The power supply voltage VDD charges the boost capacitor C1. The next moment, the third signal CLKA goes low and the fourth signal CLKB goes high. Both the bottom-plate input switch S2 and the top-plate output switch are turned on, while both the top-plate input switch S1 and the ground switch S1 are turned off. The power supply voltage VDD raises the voltage on the bottom plate of the boost capacitor C1 from 0 to VDD.

[0063] Since the voltage difference between the two ends of the boost capacitor C1 cannot change suddenly, the upper plate voltage of the boost capacitor C1 will be raised to 2VDD, and at the same time the upper plate output switch S2 is closed, so that the output voltage VOUT is proportional to the output capacitor ( Figure 3 (not shown) for charging to achieve a 2-fold voltage boost.

[0064] According to the capacitor charging formula Q = C * U, the boost capacitor C1 stores charge Q1 during the charging phase, which is Q1 = V DD *C1, the residual charge Q2 of the boost capacitor C1 after discharge is Q2 = (2V DD -V OUT )*C1. Among them, V DD Indicates the voltage value of the power supply voltage VDD, C1 indicates the capacitance value of the boost capacitor C1, V OUT Indicates the voltage value of the output voltage VOUT.

[0065] Assuming the switching frequency F S F S =1 / T, then the average charging current flowing to the output capacitor in one cycle is The equivalent internal resistance of switches S1 and S2 in the N-fold boost charge pump unit 30 is Then we know that: switching frequency F S When the switching frequency F is low, the conduction loss mainly depends on the switching frequency F S ;Switching frequency F S When the frequency is high, the conduction loss is mainly determined by the conduction loss and switching loss of the switch. Therefore, a higher switching frequency and switch size (usually a MOS transistor is used as the switch, and the switch size is generally the width and length of the MOS transistor) are beneficial to improving the conversion efficiency of the entire charge pump circuit.

[0066] Figure 3The middle Stage 2 exemplarily shows a circuit structure diagram of a 3x boost circuit when the N-fold boost charge pump unit 30 is composed of two basic units. That is, a circuit structure diagram of two basic units in cascade connection. When the two basic units are cascaded, the upper plate output switch S2 in the preceding basic unit serves as a switch for cascading with the subsequent basic unit. At this time, the lower plate of the corresponding boost capacitor C2 is grounded via the grounding switch S2, and the lower plate of the boost capacitor C2 receives the power supply voltage VDD via the lower plate input switch S1, while the upper plate output switch of the boost capacitor C2 becomes S1, and its second end outputs the voltage VOUT.

[0067] The principle is the same as that of the 2x boost circuit. For the 3x boost circuit: when the third signal CLKA is high, all S1 switches are turned on and all S2 switches are turned off, and the upper plate of the boost capacitor C1 is charged to the power supply voltage VDD; when the fourth signal CLKB is high, all S1 switches are turned off and all S2 switches are turned on, and the upper plate of the boost capacitor C2 is charged to 2VDD; when the third signal CLKA is high in the next cycle, all S1 switches are turned on again and all S2 switches are turned off again, and the voltage of the upper plate of the boost capacitor C2 is raised to 3VDD and discharged to the output capacitor at the same time, and the output voltage is 3VDD.

[0068] Simple reasoning shows that if it is a 4x boost circuit, then the switch S1 of the output voltage VOUT in the Stage 2 diagram acts as a cascade switch with the subsequent basic unit, then the boost capacitor C3 ( Figure 3 The output switch of the upper plate (not shown) changes to S2, and its second end outputs the voltage VOUT. That is, when multiple basic units are cascaded, the switch that serves as the cascade of adjacent basic units is always controlled by the same signal as the ground switch in the subsequent basic unit, and the remaining two switches in the subsequent basic unit are controlled by another signal. In this way, a circuit structure diagram of StageN can be obtained. Assuming that N-1 times boosting has been achieved, when the third signal CLKA is high, all S1 switches are turned on and all S2 switches are turned off, and the upper plates of the boost capacitors Cn-1 and Cn are charged to (n-1)VDD; then when the fourth signal CLKB is high, all S2 switches are turned on and all S1 switches are turned off. From the above process, it can be seen that the voltage of the upper plate of the boost capacitor Cn will be raised to nVDD. Thus, the entire charge pump circuit uses a set of non-overlapping clocks to achieve cascade N times boosting.

[0069] In order to better verify the effectiveness of the charge pump circuit proposed in the present invention, a 4-fold boost circuit was manufactured according to the circuit structure proposed in the present invention and a simulation test was performed to obtain Figure 5The following diagram shows the output voltage at an input voltage VOUT of 1V and the voltage on the upper board of each boost capacitor stage. As shown in the figure, NODE1, NODE2, NODE3, and NODE4 represent the voltages on the upper boards of boost capacitors C1, C2, C3, and C4, respectively. The output ripple of the input voltage VOUT of the entire charge pump circuit depends on the clock frequency and the size of the output capacitors. The actual output voltage VOUT ripple is approximately 3mV. This shows that the charge pump circuit proposed by the present invention can effectively achieve N-fold cascade voltage amplification.

[0070] Based on the above charge pump circuit, an embodiment of the present invention further provides a chip, which includes: the charge pump circuit as described in any one of the above items.

[0071] Based on the above charge pump circuit, an embodiment of the present invention further provides an electronic device, which includes: the charge pump circuit as described in any one of the above items.

[0072] In summary, the charge pump circuit of the present invention includes a non-overlapping unit, a level shifting unit, and an N-fold boost charge pump unit. The non-overlapping unit is connected to the level shifting unit and is configured to receive a clock signal and convert the clock signal into a first signal and a second signal, which are then transmitted to the level shifting unit. The first signal and the second signal are two non-overlapping clock signals.

[0073] The level shift unit is connected to the N-fold boost charge pump unit. The level shift unit is used to use the output voltage of the N-fold boost charge pump unit to level shift the first signal and the second signal respectively, generate a third signal and a fourth signal, and transmit them to the N-fold boost charge pump unit.

[0074] The N-fold boost charge pump unit is used to generate an output voltage based on a third signal and a fourth signal to achieve cascade N-fold boost; wherein the third signal and the fourth signal are respectively used to control different switches in the N-fold boost charge pump unit to turn on or off.

[0075] The charge pump circuit provided by the present invention creatively proposes cascading N-fold voltage amplification using only a set of non-overlapping clock signals (a third signal and a fourth signal). The non-overlapping clock signals are generated by clock signal conversion and level shifting by non-overlapping units. These two non-overlapping clock signals are used to control switches in the N-fold boost charge pump unit, enabling the charge pump circuit to achieve cascaded N-fold voltage amplification.

[0076] Since the entire circuit is at the switching frequency F S When the switching frequency F is low, the conduction loss mainly depends on the switching frequency F S ; and the switching frequency F SWhen the conduction loss is high, it is primarily determined by the conduction loss and switching loss of the switch. Therefore, a higher switching frequency and switch size are beneficial for improving the charge pump's conversion efficiency. The entire circuit has advantages such as a small number of required capacitors, strong load capacity, and a simple circuit structure. It can be applied in fields such as low-voltage LDO control circuits. The charge pump circuit proposed in this invention is highly practical.

[0077] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they become aware of the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0078] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "include", "comprises", or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, charge pump circuit, article, or terminal device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements that are inherent to such process, charge pump circuit, article, or terminal device. In the absence of further restrictions, an element defined by the sentence "includes a..." does not exclude the presence of other identical elements in the process, charge pump circuit, article, or terminal device that includes the element.

[0079] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are protected by the present invention.

Claims

1. A charge pump circuit, characterized in that: The charge pump circuit includes: a non-overlapping unit, a level shift unit and an N-fold boost charge pump unit; The non-overlapping unit is connected to the level conversion unit, and is used to receive a clock signal, convert the clock signal into a first signal and a second signal, and transmit the first signal and the second signal to the level shifting unit, wherein the first signal and the second signal are two-phase non-overlapping clock signals; The level shift unit is connected to the N-fold boost charge pump unit, and is used to use the output voltage of the N-fold boost charge pump unit to level-shift the first signal and the second signal respectively, generate a third signal and a fourth signal, and transmit them to the N-fold boost charge pump unit; The N-fold boost charge pump unit is configured to generate the output voltage based on the third signal and the fourth signal, thereby achieving cascade N-fold boost; The third signal and the fourth signal are respectively used to control the on or off of different switches in the N-fold boost charge pump unit.

2. The charge pump circuit according to claim 1, wherein: The N-fold boost charge pump unit includes: at least one basic unit; A plurality of the basic units are cascaded to form the N-fold boost charge pump unit; Wherein, when the N-fold boost charge pump unit is formed by only one basic unit, N=2, the N-fold boost charge pump unit is a 2-fold boost unit, and its output voltage is twice the power supply voltage; When the N-fold boost charge pump unit is formed by n basic units, N=n+1, the N-fold boost charge pump unit is an N-fold boost unit, and its output voltage is N times the power supply voltage.

3. The charge pump circuit according to claim 2, wherein: The basic unit includes: a plurality of switches and a boost capacitor; The first end of the upper plate input switch among the multiple switches receives the power supply voltage, and the second end is connected to the upper plate of the boost capacitor and the first end of the upper plate output switch among the multiple switches, respectively, and the second end of the upper plate output switch is the output end of the basic unit; The first end of the lower plate input switch among the multiple switches receives the power supply voltage, and the second end is connected to the lower plate of the boost capacitor and the first end of the grounding switch among the multiple switches respectively, and the second end of the grounding switch is grounded.

4. The charge pump circuit according to claim 3, wherein: When multiple basic units are cascaded, the upper plate output switch in the front basic unit serves as a cascade switch for cascading with the rear basic unit. It and the ground switch in the rear basic unit are controlled by the same signal, and the remaining two switches in the rear basic unit are controlled by another signal.

5. The charge pump circuit according to claim 3, wherein: The upper plate input switch and the ground switch are both controlled by the third signal, and the lower plate input switch and the upper plate output switch are both controlled by the fourth signal; or, The upper plate input switch and the ground switch are both controlled by the fourth signal, and the lower plate input switch and the upper plate output switch are both controlled by the third signal.

6. The charge pump circuit according to claim 1, wherein: The level shift unit includes: a first shift subunit and a second shift subunit; The first shift subunit receives the first signal, and uses the output voltage to perform level shift on the first signal to generate the third signal; The second shift subunit receives the second signal, and performs level shift on the second signal using the output voltage to generate the fourth signal.

7. The charge pump circuit according to claim 1, wherein: The first signal changes to a high level at the rising edge of the clock signal, and its high level duration is shorter than the high level duration of the clock signal; the second signal changes to a high level at the falling edge of the clock signal, and its high level duration is shorter than the low level duration of the clock signal; or, The first signal becomes a high level at the falling edge of the clock signal, and its high level duration is shorter than the low level duration of the clock signal. The second signal becomes a high level at the rising edge of the clock signal, and its high level duration is shorter than the high level duration of the clock signal.

8. The charge pump circuit according to claim 7, wherein: The third signal is in phase with the first signal, and a voltage corresponding to the third signal is greater than a voltage corresponding to the first signal; The fourth signal is in phase with the second signal, and a voltage corresponding to the fourth signal is greater than a voltage corresponding to the second signal; The voltages corresponding to the third signal and the fourth signal are sufficient to make the corresponding control switches fully turned on or off.

9. A chip, characterized in that: The chip includes: the charge pump circuit according to any one of claims 1-8.

10. An electronic device, characterized in that: The electronic device comprises: the charge pump circuit according to any one of claims 1 to 8.

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