High-speed serial receiver margin testing device and method

Abstract

The invention provides a high-speed serial receiver margin testing device and method, and the device comprises a high-speed digital signal generator module which is used for generating a high-speed serial signal; the jitter and noise injection module is used for injecting jitter and noise into the high-speed serial signal to obtain a test signal and sending the test signal to a high-speed serial receiver to be tested; the error code detection module is used for carrying out error code detection on a signal output after the high-speed serial signal receives the test signal to obtain real-time error code data; and the adaptive control module is used for determining a margin test area according to the real-time error code data, and searching in the margin test area to obtain a margin value of the high-speed serial receiver. The problems that in the prior art, a traditional margin test is long in test time and low in efficiency, only single-dimension (such as jitter or noise) injection is generally considered, and the real performance of the high-speed serial receiver under the multi-factor comprehensive action in the actual working condition is difficult to reflect are solved.

Description

Technical Field

[0001] The present invention relates to the field of digital communication technology, and in particular to a high-speed serial receiver margin testing device and method. Background Art

[0002] In current high-speed digital communication systems, high-speed serial receivers are critical modules, and their performance directly impacts the reliability of the entire communication link. Existing technologies primarily use bit error testing and eye diagram analysis under fixed parameters to evaluate the margin of high-speed serial receivers. Margin refers to the range of signal variations a receiver can tolerate during high-speed signal transmission to ensure correct signal reception and processing. However, current evaluation methods still have the following shortcomings: First, traditional margin testing typically only considers a single dimension (such as jitter or noise injection), making it difficult to reflect the true performance of a high-speed serial receiver under the combined effects of multiple factors in real-world operating conditions. Second, testing is time-consuming and inefficient. A fixed sweep mode requires numerous repetitive tests, which cannot quickly identify the performance boundaries of a high-speed serial receiver, resulting in long test cycles and low efficiency. Summary of the Invention

[0003] The present invention provides a high-speed serial receiver margin test device to solve the problems in the prior art of traditional margin testing, such as long test time and low efficiency, and usually only considering the injection of a single dimension (such as jitter or noise), which makes it difficult to reflect the actual performance of the high-speed serial receiver under the combined effects of multiple factors in actual working conditions.

[0004] The present invention provides a high-speed serial receiver margin test device, comprising: High-speed digital signal generator module, used to generate high-speed serial signals; a jitter and noise injection module, configured to inject jitter and noise into the high-speed serial signal to obtain a test signal, and send the test signal to the high-speed serial receiver to be tested; An error detection module is used to perform error detection on a signal outputted by a high-speed serial signal after receiving the test signal, and obtain real-time error data; The adaptive control module is used to determine a margin test area according to the real-time error code data, and search within the margin test area to obtain a margin value of the high-speed serial receiver.

[0005] In some embodiments, the high-speed serial receiver margin test device also includes a main control board, the core processor used by the main control board is FPGA, and the main control board is provided with multiple slots for inserting test modules, and the test modules include the high-speed digital signal generator module, the jitter and noise injection module, the error detection module and the adaptive control module.

[0006] In some embodiments, the main control board is further connected to the high-speed serial receiver to be tested through the slot; When the main control board detects that the high-speed serial receiver to be tested is inserted into the slot, the test module on the slot is initialized by the FPGA; When the main control board detects that a test module is removed from a slot or there is a signal disturbance in a high-speed serial signal, a spare test channel is enabled through the FPGA, and the spare test channel is used to simulate a margin test process of the test module.

[0007] In some embodiments, determining the margin test area according to the real-time bit error data includes: Obtain historical margin test data of the high-speed serial receiver to be tested; Training a machine learning model based on the historical margin test data to obtain a margin test model; The real-time error data is input into the margin test model to obtain a margin test area.

[0008] In some embodiments, searching within the margin test region to obtain a margin value of the high-speed serial receiver includes: In the margin test area, updating the test parameters of the test signal by binary search to obtain updated error data corresponding to the high-speed serial receiver; In each binary search process, adjusting the current test parameters of the test signal according to the updated error data includes: When the updated error data exceeds the tolerance threshold, the current test parameter is halved, and the margin test area for the next binary search is determined according to the halved test parameter; When the updated error data does not exceed the tolerance threshold, the current test parameter is increased by 1.5 times, and the margin test area for the next binary search is determined based on the 1.5 times current test parameter; If the number of binary searches reaches a preset number threshold or a preset test time is reached, the binary search is terminated, and the margin value of the high-speed serial receiver is determined based on the updated error data at the end of the binary search.

[0009] In some embodiments, the high-speed serial receiver margin test device further includes: a human-computer interaction and data storage module; The human-computer interaction and data storage module is used to display a graphical interface, which is used to visualize the test parameters and updated error data determined during each binary search process. The human-computer interaction and data storage module is also used to store the current test parameters corresponding to the test signal at the end of the binary search, and store the margin test area determined by the current test parameters, the updated error data, and the margin value of the high-speed serial receiver as historical margin test data.

[0010] The present invention also provides a high-speed serial receiver margin testing method, comprising: Generate high-speed serial signals; Injecting jitter and noise into the high-speed serial signal to obtain a test signal, and sending the test signal to a high-speed serial receiver to be tested; Performing error detection on a signal outputted by the high-speed serial signal after receiving the test signal to obtain real-time error data; A margin test area is determined according to the real-time error data, and a search is performed within the margin test area to obtain a margin value of the high-speed serial receiver.

[0011] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the high-speed serial receiver margin test method as described above when executing the computer program.

[0012] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the high-speed serial receiver margin test method as described above is implemented.

[0013] The present invention also provides a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the high-speed serial receiver margin test method as described above is implemented.

[0014] The high-speed serial receiver margin testing device and method provided by this invention implements a multi-dimensional parameter joint scanning test method, completing margin testing of high-speed serial receivers under the dual-dimensional injection of jitter and noise. Furthermore, during the testing phase, real-time bit error data is used to initially determine the margin test region. A further search is then performed within this region to determine the margin value of the high-speed serial receiver. Predicting the margin test region facilitates rapid identification of performance boundaries, reducing test time and improving test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced one by one below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0016] Figure 1 The diagram is a schematic diagram of an application of the high-speed serial receiver margin test device provided by the present invention.

[0017] Figure 2 It is a schematic diagram of the principle of controlling the test parameters provided by the present invention to perform a binary search.

[0018] Figure 3 The present invention provides a flow chart of a high-speed serial receiver margin testing method.

[0019] Figure 4 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0020] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0021] The high-speed serial receiver margin testing device and method of the present invention will be described below with reference to the accompanying drawings. Figure 1 FIG. 1 is an application diagram of the high-speed serial receiver margin test device provided by the present invention. Figure 1 As shown, the high-speed serial receiver margin test device includes multiple test modules, specifically including: a high-speed digital signal generator module, a jitter and noise injection module, an error detection module, and an adaptive control module. The multiple test modules can be connected through standardized interfaces to achieve communication between modules. Each test module is described one by one below.

[0022] The high-speed digital signal generator module is used to generate high-speed serial signals. It contains a built-in processor chip, such as a field programmable gate array (FPGA). This processor chip controls the signal modulation method within the high-speed digital signal generator module, generating standard high-speed serial signals for testing high-speed serial receivers. The high-speed digital signal generator module also includes a digital-to-analog converter (DAC) and an analog-to-digital converter (ADC) to achieve efficient conversion between digital and analog signals, ensuring the fidelity of the high-speed serial signal during injection and acquisition.

[0023] The jitter and noise injection module is used to inject jitter and noise into the high-speed serial signal to obtain a test signal, and send the test signal to the high-speed serial receiver to be tested.

[0024] The Jitter and Noise Injection Module communicates directly with the High-Speed ​​Digital Signal Generator Module via a standardized interface. It receives the high-speed serial signal generated by the High-Speed ​​Digital Signal Generator in real time and injects jitter and noise into the high-speed serial signal to generate a test signal. The Jitter and Noise Injection Module simultaneously generates jitter and injects noise. Jitter generation supports sinusoidal, pseudo-random, and periodic jitter patterns, utilizing a high-precision digital clock manager for sub-nanosecond control. Noise injection can generate white noise, impulse noise, and band-limited noise, with programmable noise amplitude and frequency.

[0025] In addition, the jitter and noise injection module has a built-in parameter matrix scanning algorithm that can simultaneously adjust jitter parameters and noise parameters. The jitter parameters and noise parameters are used as test parameters for margin testing, such as jitter frequency and noise level.

[0026] The jitter and noise injection module typically communicates directly with the high-speed serial receiver under test, transmitting the test signal generated by injecting jitter and noise to the high-speed serial receiver under test. Upon receiving the test signal, the high-speed serial receiver performs its normal operations and outputs the corresponding signal.

[0027] The error detection module performs error detection on the signal output after the high-speed serial signal receives the test signal, generating real-time error data. The error detection module communicates with the high-speed serial receiver under test via a standardized interface. The module incorporates a high-precision bit error rate detection system that receives the signal output after the high-speed serial signal receives the test signal in real time, performs real-time error statistics, and generates real-time error data. Furthermore, it can collect corresponding eye diagram parameters to assist in evaluating the high-speed serial receiver's margin based on the error data.

[0028] The adaptive control module is used to determine a margin test area according to real-time error code data, and to search within the margin test area to obtain a margin value of the high-speed serial receiver.

[0029] The adaptive control module and the error detection module also communicate via a standardized interface, receiving real-time error data generated by the error detection module. The margin test region is then determined based on this real-time error data. This real-time error data allows the approximate test parameter range within which the margin boundary of the high-speed serial receiver under test falls to be predicted. This test parameter range is then defined as the margin test region. This test parameter range can be determined based on empirically derived test parameters or using a machine learning algorithm. By determining the margin test region, the scan path can be optimized, eliminating the need for repeated blind searches with repeated adjustments to test parameters.

[0030] Furthermore, the adaptive control module searches within the margin test region to determine the high-speed serial receiver's margin value. During each search, the test parameters (i.e., noise and jitter parameters) are updated to narrow the margin test region, gradually approaching the high-speed serial receiver's margin boundary. The search is terminated until a preset number of searches is reached or a preset test is completed. Upon terminating the search, the high-speed serial receiver's margin value is determined. This is determined by estimating the receiver's margin value based on the bit error data and corresponding eye diagram parameters at the time the search stopped. The search is implemented using an intelligent control algorithm deployed within the adaptive control module, which can be either a binary search algorithm or a gradient descent algorithm.

[0031] This embodiment of the present invention performs margin testing on a high-speed serial receiver using both jitter and noise injection, implementing a multi-dimensional parameter joint scanning test method. This overcomes the drawback of single-dimensional injection (e.g., jitter or noise) that can hinder the performance of a high-speed serial receiver under the combined effects of multiple factors in real-world operating conditions, leading to inaccurate test results. Furthermore, during the testing phase, real-time bit error data is used to initially determine the margin test region. A further search is then performed within this region to determine the margin value of the high-speed serial receiver. This prediction of the margin test region optimizes the scan path, eliminating the need for repeated blind searches with multiple adjustments to test parameters. This facilitates rapid identification of performance boundaries, reduces test time, and improves test efficiency.

[0032] like Figure 1As shown, in some embodiments, the high-speed serial receiver margin test device also includes a main control board, the core processor used by the main control board is FPGA, and the main control board is provided with multiple slots for inserting test modules, and the test modules include a high-speed digital signal generator module, a jitter and noise injection module, an error detection module and an adaptive control module.

[0033] Specifically, each test module in the high-speed serial receiver margin test device is integrated onto a main control board with an FPGA as its core processor. Building upon the FPGA, the main control board also incorporates a microcontroller to implement high-speed data processing, interface management, and intelligent identification, centrally controlling the margin test process for the high-speed serial receiver. The FPGA also stores test data from each test module in real time during the margin test process.

[0034] Accordingly, each test module is designed to take hot-swap requirements into consideration, and is equipped with a mechanical locking device and redundant electrical contacts, which are connected to the main control board through a slot to achieve data communication and transmission with the main control board.

[0035] In an embodiment of the present invention, a main control board is provided in a high-speed serial receiver margin test device, and each test module is integrated on the main control board, eliminating the need to implement communication connections between the test modules through various standardized interfaces. This improves the module integration of the device and facilitates the updating and maintenance of the test modules. In addition, an FPGA is used to control the margin test processing flow of each test module, enabling real-time monitoring of the test process to ensure that the test process of each test module is accurate.

[0036] Furthermore, in the above embodiment, the main control board is also connected to the high-speed serial receiver to be tested via a slot. That is, when performing a margin test, the high-speed serial receiver to be tested can also be inserted into the slot of the main control board, thereby realizing hot plugging on the high-speed serial receiver to be tested.

[0037] When the main control board detects that a high-speed serial receiver under test has been inserted into a slot, the FPGA initializes the test module in the slot. During initialization, the FPGA immediately reads the data information of the high-speed serial receiver under test and the information of each test module through the bus, automatically identifying the type and parameters of the high-speed serial receiver under test. It then invokes a pre-set self-calibration algorithm to dynamically adjust the acquisition channels, test algorithms, and drive parameters of each test module. For example, the parameter matrix scanning algorithm built into the jitter and noise injection modules can be adjusted to adjust test parameters, including noise and jitter parameters. The intelligent control algorithm deployed in the adaptive control module can also be adjusted to initialize the algorithm parameters.

[0038] When the main control board detects that a test module is removed from a slot or that there is signal disturbance in the high-speed serial signal, the standby test channel is enabled through the FPGA.

[0039] During the test process, unexpected situations may occur, such as a test module being pulled out of the main control board's slot or a poor slot contact causing disconnection from the main control board. These situations can be immediately detected by the main control board's FPGA, which can then determine that a test module has been removed from the slot. Furthermore, during the test process, high-speed serial signals may experience signal disturbances, such as environmental interference or a test module failure or disconnection. These situations will also be immediately detected by the main control board's FPGA. At this point, the main control board will activate the backup test channel through the FPGA, which is used to simulate the margin test process of each test module. After the backup test channel is activated, the FPGA will read the test data of the margin test process stored in real time and continue executing the margin test process, ensuring that the test process is not affected by the removal of the test module and signal disturbances.

[0040] By integrating the high-speed serial receiver under test into a slot on the main control board, this embodiment of the present invention facilitates initialization of each test module and margin testing of the high-speed serial receiver under test. Furthermore, upon detecting the removal of a test module from a slot or disturbances in the high-speed serial signal, a backup channel is activated to ensure test data continuity, avoid interruptions in the margin test process, and effectively improve test efficiency.

[0041] In some embodiments, the adaptive control module determines the margin test area according to the real-time error data, which can be achieved in the following manner, which is described in detail below.

[0042] First, obtain historical margin test data for the high-speed serial receiver under test. This historical margin test data consists of historical test parameters, historical error data, and historical margin test ranges recorded during previous margin tests of the high-speed serial receiver under test. Historical test parameters include historical noise parameters and historical jitter parameters. After the high-speed serial receiver under test receives a high-speed serial signal injected with noise and jitter according to the historical test parameters, it outputs the corresponding signal. The error data obtained by performing an error test on the output signal is the historical error data. The historical margin test range is the range determined during previous margin tests based on the historical test parameters, specifically the historical jitter and / or noise parameters. For example, if the historical jitter parameter is set to 10 UI (UI stands for Unit Interval), the historical margin test range determined based on the historical error data is 0-10 UI.

[0043] Next, a machine learning model is trained based on the historical margin test data to obtain a margin test model. For example, the machine learning model can be a decision tree or support vector machine. Historical test parameters, historical bit error data, and historical margin test areas are input as data samples into the decision tree or support vector machine for training. The trained decision tree or support vector machine is then used as the margin test model. This model can predict the input bit error data and output the corresponding margin test area.

[0044] Therefore, when determining the margin test area, real-time bit error data can be input into the margin test model to obtain the margin test area. The margin test model can quickly predict the corresponding margin test area based on the input real-time bit error data, thus roughly determining the test scan path.

[0045] For example, the jitter parameter injected by the jitter and noise injection module is 10UI. The real-time error data output by the error detection module is input into the margin test model, which quickly predicts that the corresponding margin test area is 6-7UI. Subsequent searches only need to be performed within the range of 6-7UI, eliminating the need for blind searches within the range of 0-10UI. This narrows the test scope, saves test time, and improves efficiency.

[0046] In an embodiment of the present invention, when performing margin testing, a machine learning model is used to preliminarily predict the margin test area, which greatly narrows the test scope and optimizes the test scan path. There is no need to adjust the test parameters multiple times and search blindly as in a fixed scan mode, which is conducive to quickly locating performance boundaries, reducing test time and improving test efficiency.

[0047] Considering that existing margin testing solutions lack intelligent adaptability, they are unable to implement a real-time closed-loop feedback mechanism and dynamically adjust test parameters based on the immediate response of the high-speed serial receiver under test. This can lead to inadequate data collection for updating error data, resulting in misjudgments or insufficient data collection in margin testing results. Therefore, after initially predicting the margin test region using a machine learning model, the present invention employs a binary search algorithm to search within the margin test region. The following describes the specific process of using the binary search algorithm to search within the margin test region and obtain the margin value of a high-speed serial receiver.

[0048] Specifically, within the margin test region, the test signal's test parameters are updated through a binary search to obtain updated error data corresponding to the high-speed serial receiver. During each binary search, the test signal's current test parameters are adjusted based on the updated error data. These adjustments are made in two specific ways: First, when the updated error data exceeds the tolerance threshold, the current test parameters are halved, and the margin test region for the next binary search is determined based on the halved test parameters. Second, when the updated error data does not exceed the tolerance threshold, the current test parameters are multiplied by 1.5, and the margin test region for the next binary search is determined based on the 1.5-fold increase in the current test parameters.

[0049] like Figure 2 As shown, in the jitter and noise injection module, by setting the initial test parameters and outputting the corresponding real-time error data through the error detection module, the adaptive control module is further used to determine the corresponding margin test area. During the first binary search, first determine whether the error data exceeds the tolerance threshold in the margin test area, that is, determine whether the real-time error data exceeds the tolerance threshold. If so, the bit error rate test fails, and the parameter rollback is executed at this time, and the test parameters are updated, that is, the current test parameters are halved, and the margin test area for the next binary search is determined based on the halved test parameters. If not, it means that the bit error rate test has passed, and the parameter increase is executed at this time, and the test parameters are updated, and the current test parameters are increased to 1.5 times, and the margin test area for the next binary search is determined based on the 1.5 times current test parameters.

[0050] During the next binary search, that is, during the second binary search and even every binary search thereafter, the error data (i.e., the current error data, i.e., the updated error data during the current binary search) is determined to be within the margin test area determined after the test parameters were updated during the previous binary search to determine whether it exceeds the tolerance threshold. Because the margin test area is reduced by half after the test parameters are updated, the error data is also updated accordingly to obtain updated error data. When the updated error data exceeds the tolerance threshold, it means that the error rate test still fails. At this time, the parameter rollback is executed, and the test parameters are updated by halving the parameters to further reduce the margin test area. When the updated error data does not exceed the tolerance threshold, it means that the error rate test passes. At this time, the parameter increase is executed, and the parameters are multiplied by 1.5 times to update the test parameters to further reduce the margin test area.

[0051] For example, suppose the initial test parameter is jitter, set to 10UI, and the corresponding margin test range is 0-10UI. During the first binary search, if the real-time error data within 0-10UI exceeds the tolerance threshold, and the bit error rate test fails, the initial test parameter is halved to 5UI, and the margin test range is updated to 0-5UI. During the second binary search, if the updated error data obtained with the current test parameter of 5UI still exceeds the tolerance threshold and the bit error rate test still fails, the current test parameter is further halved to 2.5UI, and the margin test range is updated to 0-2.5UI. The third binary search is then performed. If the updated error data obtained with the current test parameter of 5UI still exceeds the tolerance threshold, the current test parameter of 5UI is increased by 1.5 times, that is, to 7.5UI. The margin test range is now updated to 5-7.5UI, and the third binary search is performed, and so on.

[0052] If the number of binary searches reaches a preset threshold or the preset test time, the binary search ends and the margin value of the high-speed serial receiver is determined based on the updated error data at the end of the binary search. Here, a scan termination condition is set, namely, the number of binary searches reaches a preset threshold or the preset test time is reached. For example, the binary search threshold is set to 5 times and the test time is set to 1 minute.

[0053] like Figure 2 As shown, after each binary search to update the test parameters, it is necessary to determine whether the number of binary searches has reached a preset threshold or the preset test time has been reached, that is, to determine whether to terminate the scan. If so, it indicates that the preset threshold or the preset test time has been reached, and the test process ends. The margin value of the high-speed serial receiver is determined based on the updated bit error data at the end of the binary search. In other words, the margin value of the high-speed serial receiver is directly estimated based on the updated bit error data and the corresponding collected eye diagram data. If not, it indicates that the preset threshold or the preset test time has not been reached, and the binary search is continued based on the updated test parameters.

[0054] The embodiment of the present invention continuously updates test parameters within the predicted margin test range through a binary search algorithm, narrows the margin test range, and enables the test process to gradually approach the margin boundary of the high-speed serial receiver. This implements a real-time closed-loop feedback mechanism, which not only improves the intelligent adaptability of the test process but also shortens the test cycle, achieves rapid margin positioning, and improves the efficiency of margin testing by approximately 50%.

[0055] In some embodiments, as Figure 1As shown, the high-speed serial receiver margin test device also includes: a human-computer interaction and data storage module, which can communicate with each test module through a standardized interface and can also be inserted into the main control board through a slot.

[0056] The human-computer interaction and data storage module has two functions. The first is human-computer interaction, which is used to display a graphical interface. The graphical interface is used to visualize the test parameters and updated error data determined during each binary search process. When the adaptive control module performs a binary search, the test parameters and updated error data determined during each binary search process are visualized. The visualization method can be drawn in the form of a curve graph or a line graph. When the tester operates the graphical interface to perform demand analysis, the data is visualized to show the tester. A margin heat map can also be formed based on the updated error data after each binary search process. It can intuitively show the tester the process of gradually approaching the margin boundary during the test, which is convenient for the tester to perform data analysis and trend prediction, and to formulate a better test strategy in the subsequent process.

[0057] The second aspect is data storage, which is used to store the current test parameters corresponding to the test signal at the end of the binary search. The margin test area, updated error data, and margin values ​​of the high-speed serial receiver determined by the current test parameters are stored as historical margin test data. At the end of the binary search, the test parameters, updated error data, margin test area, and margin values ​​of the high-speed serial receiver used during the test process can be stored as historical margin test data in a test log or database. This data is used to continuously optimize the margin test model deployed in the adaptive control module, ensuring the prediction accuracy of the margin test model and reducing the risk of human intervention. Furthermore, this historical margin test data can provide data support for the subsequent development of high-speed serial receiver margin test equipment.

[0058] An embodiment of the present invention further provides a high-speed serial receiver margin testing method. The high-speed serial receiver margin testing method is described below. The high-speed serial receiver margin testing method described below and the high-speed serial receiver margin testing device described above can refer to each other.

[0059] like Figure 3 As shown, the high-speed serial receiver margin test method can be implemented by following steps 101 to 104, which are described one by one below.

[0060] Step 101: Generate a high-speed serial signal.

[0061] Step 102: Inject jitter and noise into the high-speed serial signal to obtain a test signal, and send the test signal to the high-speed serial receiver to be tested.

[0062] Step 103: Perform error detection on the signal output after the high-speed serial signal receives the test signal to obtain real-time error data.

[0063] Step 104: Determine a margin test area based on the real-time error data, and perform a search within the margin test area to obtain a margin value of the high-speed serial receiver.

[0064] It should be noted that the high-speed serial receiver margin testing method herein corresponds to the beneficial effects of the high-speed serial receiver margin testing device described above, and therefore the beneficial effects of the high-speed serial receiver margin testing method will not be described in detail here.

[0065] Figure 4 An example of a physical structure diagram of an electronic device is shown below. Figure 4 As shown, the electronic device may include: a processor 410, a communications interface 420, a memory 430, and a communications bus 440, wherein the processor 410, the communications interface 420, and the memory 430 communicate with each other via the communications bus 440. The processor 410 may call logic instructions in the memory 430 to execute a high-speed serial receiver margin test method, which includes: generating a high-speed serial signal; injecting jitter and noise into the high-speed serial signal to obtain a test signal, and sending the test signal to the high-speed serial receiver to be tested; performing bit error detection on a signal output by the high-speed serial signal after receiving the test signal to obtain real-time bit error data; determining a margin test area based on the real-time bit error data, and searching within the margin test area to obtain a margin value of the high-speed serial receiver.

[0066] Furthermore, the logic instructions in the aforementioned memory 430 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product, stored in a storage medium, includes instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, a mobile hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0067] On the other hand, the present invention also provides a computer program product, which includes a computer program. The computer program can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the high-speed serial receiver margin test method provided by the above methods, which includes: generating a high-speed serial signal; injecting jitter and noise into the high-speed serial signal to obtain a test signal, and sending the test signal to the high-speed serial receiver to be tested; performing error detection on a signal output by the high-speed serial signal after receiving the test signal to obtain real-time error data; determining a margin test area based on the real-time error data, and searching within the margin test area to obtain a margin value of the high-speed serial receiver.

[0068] On the other hand, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, it is implemented to perform the high-speed serial receiver margin test method provided by the above methods. The method includes: generating a high-speed serial signal; injecting jitter and noise into the high-speed serial signal to obtain a test signal, and sending the test signal to the high-speed serial receiver to be tested; performing error detection on a signal output by the high-speed serial signal after receiving the test signal to obtain real-time error data; determining a margin test area based on the real-time error data, and searching within the margin test area to obtain a margin value of the high-speed serial receiver.

[0069] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., they may be located in one location or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of the present embodiment. Persons of ordinary skill in the art will be able to understand and implement the present invention without inventive effort.

[0070] Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented using software plus a necessary general-purpose hardware platform, or of course, hardware. Based on this understanding, the essence of the above technical solution, or the portion that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a magnetic disk, or an optical disk, and includes a number of instructions for causing a computer device (such as a personal computer, server, or network device) to execute the methods described in each embodiment or certain portions of the embodiments.

[0071] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A high-speed serial receiver margin test device, characterized in that: include: High-speed digital signal generator module, used to generate high-speed serial signals; a jitter and noise injection module, configured to inject jitter and noise into the high-speed serial signal to obtain a test signal, and send the test signal to the high-speed serial receiver to be tested; An error detection module is used to perform error detection on a signal outputted by a high-speed serial signal after receiving the test signal, and obtain real-time error data; The adaptive control module is used to determine a margin test area according to the real-time error code data, and search within the margin test area to obtain a margin value of the high-speed serial receiver.

2. The high-speed serial receiver margin test device according to claim 1, wherein: The high-speed serial receiver margin test device also includes a main control board, the core processor of which is FPGA. The main control board is provided with multiple slots for inserting test modules, and the test modules include the high-speed digital signal generator module, the jitter and noise injection module, the error detection module and the adaptive control module.

3. The high-speed serial receiver margin test device according to claim 2, wherein: The main control board is also connected to the high-speed serial receiver to be tested through the slot; When the main control board detects that the high-speed serial receiver to be tested is inserted into the slot, the test module on the slot is initialized by the FPGA; When the main control board detects that a test module is removed from a slot or there is a signal disturbance in a high-speed serial signal, a spare test channel is enabled through the FPGA, and the spare test channel is used to simulate a margin test process of the test module.

4. The high-speed serial receiver margin test device according to claim 1, wherein: The determining of the margin test area according to the real-time error data includes: Obtain historical margin test data of the high-speed serial receiver to be tested; Training a machine learning model based on the historical margin test data to obtain a margin test model; The real-time error data is input into the margin test model to obtain a margin test area.

5. The high-speed serial receiver margin test device according to claim 1, wherein: Searching within the margin test area to obtain a margin value of the high-speed serial receiver includes: In the margin test area, updating the test parameters of the test signal by binary search to obtain updated error data corresponding to the high-speed serial receiver; In each binary search process, adjusting the current test parameters of the test signal according to the updated error data includes: When the updated error data exceeds the tolerance threshold, the current test parameter is halved, and the margin test area for the next binary search is determined according to the halved test parameter; When the updated error data does not exceed the tolerance threshold, the current test parameter is increased by 1.5 times, and the margin test area for the next binary search is determined based on the 1.5 times current test parameter; If the number of binary searches reaches a preset number threshold or a preset test time is reached, the binary search is terminated, and the margin value of the high-speed serial receiver is determined based on the updated error data at the end of the binary search.

6. The high-speed serial receiver margin test device according to claim 1, wherein: The high-speed serial receiver margin test device further includes: a human-computer interaction and data storage module; The human-computer interaction and data storage module is used to display a graphical interface, which is used to visualize the test parameters and updated error data determined during each binary search process. The human-computer interaction and data storage module is also used to store the current test parameters corresponding to the test signal at the end of the binary search, and store the margin test area determined by the current test parameters, the updated error data, and the margin value of the high-speed serial receiver as historical margin test data.

7. A high-speed serial receiver margin testing method, characterized in that: include: Generate high-speed serial signals; Injecting jitter and noise into the high-speed serial signal to obtain a test signal, and sending the test signal to a high-speed serial receiver to be tested; Performing error detection on a signal outputted by the high-speed serial signal after receiving the test signal to obtain real-time error data; A margin test area is determined according to the real-time error data, and a search is performed within the margin test area to obtain a margin value of the high-speed serial receiver.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that: When the processor executes the computer program, the high-speed serial receiver margin testing method according to claim 7 is implemented.

9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the high-speed serial receiver margin testing method according to claim 7 is implemented.

10. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the high-speed serial receiver margin testing method according to claim 7 is implemented.

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