Master-slave device synchronization control method and device, and storage medium

By obtaining the timestamps and power ripple data of the master and slave devices, calculating the phase compensation value, and dynamically adjusting the control signal generation time, the coupling problem of power supply and communication errors in the medical equipment system is solved, precise synchronous control and reliability are achieved, and the diagnosis and treatment effects and safety of medical equipment are improved.

CN120675658AActive Publication Date: 2025-09-19SHENZHEN LONGXC POWER SUPPLY CO LTD
View PDF 5 Cites 0 Cited by

Patent Information

Application Number
CN202511163634.3
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-08-20
Publication Date
2025-09-19
Estimated Expiration
2045-08-20

Smart Images

  • Figure CN120675658A_ABST
    Figure CN120675658A_ABST
Patent Text Reader

Abstract

A master-slave device synchronization control method, device and storage medium, belonging to the technical field of medical power supply, the master-slave device synchronization control method comprising: acquiring a first timestamp carried by a master device to broadcast a signal to a slave device and a second timestamp of the slave device to receive the signal; calculating a communication transmission delay amount according to the first timestamp and the second timestamp; measuring power supply ripple data of the slave device, and converting the power supply ripple data into a time domain compensation amount; calculating a phase compensation value according to the time domain compensation amount and the communication transmission delay amount; and dynamically adjusting the generation time of the control signal according to the phase compensation value so as to synchronously control the master and slave devices. By establishing coupling compensation of power ripples and communication delay, accurate synchronous control and reliability of a medical equipment system are realized.
Need to check novelty before this filing date? Find Prior Art

Description

Technical Field

[0001] The present invention belongs to the technical field of frequency converters, and in particular relates to a master-slave device synchronization control method, device and storage medium. Background Art

[0002] In the field of precise coordinated control of multi-module medical device systems, the core challenge facing existing technologies lies in the coordinated handling of errors in the power supply and communication domains. Specifically, this manifests as a compound error effect caused by the medical-grade power supply system (such as the kHz-MHz high-frequency ripple interference of DSA equipment) and the medical Internet of Things communication (typical ±200μs delay jitter). This multi-physics coupling interference severely restricts the synchronization control accuracy and reliability of medical device clusters. In critical medical scenarios such as image-guided surgery and multimodal treatments, the interaction between power supply noise and communication delays can amplify system-level synchronization errors, directly impacting diagnostic and treatment effectiveness and medical safety. Summary of the Invention

[0003] In view of this, an embodiment of the present invention provides a master-slave device synchronization control method, device and storage medium, which realizes precise synchronization control and reliability of the medical device system by establishing coupling compensation between power ripple and communication delay.

[0004] A first aspect of an embodiment of the present invention provides a master-slave device synchronization control method, including: Obtain a first timestamp carried in a signal broadcast by the master device to the slave device and a second timestamp carried in a signal received by the slave device; Calculating a communication transmission delay amount according to the first timestamp and the second timestamp; Measuring power ripple data of the slave device, and converting the power ripple data into a time domain compensation amount; Calculating a phase compensation value according to the time domain compensation amount and the communication transmission delay amount; According to the phase compensation value, the generation time of the control signal is dynamically adjusted to synchronously control the master and slave devices.

[0005] In one embodiment, converting the power ripple data into a time domain compensation value includes: The output voltage of the isolated power supply module is synchronously sampled, the ripple signal amplitude is extracted through digital filtering, and the compensation time is obtained based on the ripple amplitude multiplied by a power compensation coefficient, wherein the power compensation coefficient is inversely proportional to the ripple frequency.

[0006] In one embodiment, the synchronous sampling of the output voltage of the isolated power supply module and the extraction of the ripple signal amplitude by digital filtering include: On the isolated power supply module side, the high voltage output is converted into an isolated analog-to-digital converter range through a resistor divider network; Oversampling the signal at a preset clock by a modulator on the primary side of the isolated analog-to-digital converter, transmitting a digital bit stream through magnetic isolation on the secondary side of the isolated analog-to-digital converter, and reconstructing the digital bit stream into a preset bit digital code value through a filter; After the preset digital code value is input into a digital filter for filtering, the ripple signal amplitude is extracted through a sliding window.

[0007] In one embodiment, while obtaining the compensation time based on multiplying the ripple amplitude by the dynamic coefficient, the method further includes: The ripple frequency is monitored in real time, and the power compensation coefficient is adjusted in real time according to the ripple frequency.

[0008] In one embodiment, calculating the phase compensation value based on the time domain compensation amount and the communication transmission delay amount includes: The time domain compensation amount and the communication transmission delay amount are fused into the phase compensation value through a preset mathematical model.

[0009] In one embodiment, the preset mathematical model is expressed as: ;in, is the time domain compensation, is the ripple amplitude, is the power compensation coefficient of the ith frequency band included in the ripple, is the communication compensation coefficient, is the communication transmission delay, is the frequency of the signal to be compensated, To convert the time offset to a phase radian value, is the phase compensation value.

[0010] In one embodiment, the communication compensation coefficient is inversely correlated with the sliding window variance of the communication transmission delay.

[0011] A second aspect of an embodiment of the present application provides a master-slave device synchronization control apparatus, comprising: An acquisition module, configured to acquire a first timestamp carried in a signal broadcast by the master device to the slave device and a second timestamp carried in a signal received by the slave device; A first calculation module, configured to calculate a communication transmission delay according to the first timestamp and the second timestamp; a conversion module, configured to measure power ripple data of the slave device and convert the power ripple data into a time domain compensation amount; A second calculation module is used to calculate a phase compensation value according to the time domain compensation amount and the communication transmission delay amount; The adjustment module is used to dynamically adjust the generation time of the control signal according to the phase compensation value to synchronously control the master and slave devices.

[0012] In one embodiment, the conversion module is specifically configured to: The output voltage of the isolated power supply module is synchronously sampled, the ripple signal amplitude is extracted through digital filtering, and the compensation time is obtained based on the ripple amplitude multiplied by a power compensation coefficient, wherein the power compensation coefficient is inversely proportional to the ripple frequency.

[0013] In one embodiment, the conversion module includes: A conversion unit, on the side of the isolated power supply module, is used to convert the high voltage output into an isolated analog-to-digital converter range through a resistor divider network; a reconstruction unit, configured to oversample the signal at a preset clock through a modulator on the primary side of the isolated analog-to-digital converter, transmit a digital bit stream through magnetic isolation on the secondary side of the isolated analog-to-digital converter, and reconstruct the digital bit stream into a preset bit digital code value through a filter; The extraction unit is used to input the preset digital code value into the digital filter for filtering, and then extract the ripple signal amplitude through a sliding window.

[0014] In one embodiment, the apparatus further comprises: The adjustment module is used to monitor the ripple frequency in real time and adjust the power compensation coefficient in real time according to the ripple frequency.

[0015] In one embodiment, the second calculation module is specifically configured to: The time domain compensation amount and the communication transmission delay amount are fused into the phase compensation value through a preset mathematical model.

[0016] In one embodiment, the preset mathematical model is expressed as: ;in, is the time domain compensation, is the ripple amplitude, is the power compensation coefficient of the ith frequency band included in the ripple, is the communication compensation coefficient, is the communication transmission delay, is the frequency of the signal to be compensated, To convert the time offset to a phase radian value, is the phase compensation value.

[0017] In one embodiment, the communication compensation coefficient is inversely correlated with the sliding window variance of the communication transmission delay.

[0018] A third aspect of an embodiment of the present application provides a master-slave device synchronization control device, comprising: a processor, a memory, and a computer program stored in the memory and executable on the processor; when the processor executes the computer program, the method described in the first aspect above is implemented.

[0019] A fourth aspect of an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method described in the first aspect above is implemented.

[0020] The beneficial effects of the embodiments of the present application include obtaining a first timestamp carried in a signal broadcast from a master device to a slave device and a second timestamp carried in a signal received by the slave device; calculating a communication transmission delay based on the first and second timestamps; measuring power ripple data from the slave device and converting the power ripple data into a time-domain compensation value; calculating a phase compensation value based on the time-domain compensation value and the communication transmission delay; and dynamically adjusting the generation time of a control signal based on the phase compensation value to synchronize control of the master and slave devices. By establishing coupled compensation for power ripple and communication delay, precise synchronous control and reliability of the medical device system are achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0022] Figure 1 A schematic diagram of a flow chart of a master-slave device synchronization control method provided in one embodiment of the present application; Figure 2 A schematic diagram of a master-slave device synchronization control apparatus provided in one embodiment of the present application; Figure 3 A schematic diagram of a master-slave device synchronization control device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0023] The following embodiments of the technical solution of the present application will be described in detail with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present application and are therefore only examples and are not intended to limit the scope of protection of the present application.

[0024] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" and any variations thereof in the specification and claims of this application and the above-mentioned figure descriptions are intended to cover non-exclusive inclusions.

[0025] In the description of the embodiments of this application, the technical terms "first" and "second" are used only to distinguish different objects and should not be understood to indicate or imply relative importance or implicitly specify the quantity, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, the meaning of "plurality" is more than two, unless otherwise clearly and specifically defined.

[0026] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0027] In the description of the embodiments of this application, the term "and / or" is simply a description of the association relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent the following three situations: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0028] In the description of the embodiments of the present application, the term "multi-frame" refers to two or more (including two).

[0029] In the description of the embodiments of the present application, the technical terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the embodiments of the present application.

[0030] See also Figure 1 , Figure 1This is a flow chart of a master-slave device synchronization control method provided in one embodiment of the present application. The master-slave device synchronization control method is implemented by a master-slave device synchronization control device. The master-slave device synchronization control device includes but is not limited to a terminal or a server.

[0031] Depend on Figure 1 It can be seen that the master-slave device synchronization control method provided in the embodiment of the present application includes the following steps S110 to S150. The details are as follows: S110: Acquire a first timestamp carried in a signal broadcast by the master device to the slave device and a second timestamp carried in a signal received by the slave device.

[0032] When medical equipment groups such as surgical robots, imaging equipment, and life monitors are powered on or switched to other modes, the master device, such as the surgical navigation host, will broadcast a synchronization signal carrying a high-precision first timestamp to slave devices such as robotic arms and ultrasonic scalpels. Specifically, the master device uses an improved precision time synchronization protocol such as the IEEE 1588 protocol frame structure, extending an 8-byte high-precision timestamp field at the end of the standard synchronization message type frame to ensure that time synchronization accuracy is improved from the traditional microsecond level to the nanosecond level. A GPS-disciplined rubidium atomic clock is used as the time reference to ensure that long-term time drift is less than 1 nanosecond, meeting the high stability requirements of medical equipment. The first timestamp is directly injected into the physical layer chip, bypassing the operating system protocol stack, avoiding the microsecond-level delay caused by software scheduling, and ensuring the real-time and deterministic nature of timestamp recording.

[0033] When a slave device such as a robotic arm receives a broadcast signal from the master device, it immediately triggers the hardware interrupt line to ensure that the timestamp recording is strictly synchronized with the arrival of the data frame, with a jitter of <1ns.

[0034] The master and slave devices synchronously control the devices to obtain the first timestamp and the second timestamp to determine the existence of communication delay and power supply noise.

[0035] S120: Calculate the communication transmission delay according to the first timestamp and the second timestamp.

[0036] In the embodiment of the present application, the initial communication transmission delay is first determined by a basic delay calculation model. Specifically, it is expressed as: ;in, Indicates the first timestamp, Indicates the second timestamp, represents the pre-calibrated inherent processing delay of the slave device, Indicates the initial communication transmission delay.

[0037] In view of the special working environment of medical equipment, after obtaining the initial communication transmission delay, the initial communication transmission delay is further subjected to temperature compensation and anti-interference filtering to obtain a high-precision communication transmission delay. For example, the communication transmission delay after temperature compensation and anti-interference filtering is expressed as: ; ; in, is the communication transmission delay, is the Kalman gain, is the compensation delay value at the i-th sampling moment, i is the index of the discrete time series, which is used to represent the sampling moment of the delayed data in the window. The window range is i∈[k-9, k], k is the current moment, k-1 is the previous moment, 、 is the calibration parameter, , is the temperature coefficient, Used to compensate for the time delay error caused by PCB thermal expansion and crystal oscillator first-order temperature drift. Used to correct the time delay error caused by the nonlinear characteristics of the crystal oscillator. As a communication transmission delay, it can not only ensure the stability of the final result but also ensure its accuracy.

[0038] S130: Measure power ripple data of the slave device, and convert the power ripple data into a time domain compensation value.

[0039] Power supply ripple refers to high-frequency AC noise superimposed on the DC power supply output. This high-frequency AC noise is typically caused by switching noise in the switching power supply, sudden changes in load current, and PCB layout defects. Power supply ripple can cause clock jitter and logic gate delay variations, affecting the accuracy of the second timestamp, ultimately manifesting as periodic errors in communication transmission delay.

[0040] In an embodiment of the present application, the power supply ripple data is converted into a time domain compensation amount, and the delay calculation is dynamically corrected together with the communication transmission delay amount.

[0041] Exemplarily, the power supply ripple data is converted into a time domain compensation amount, including: synchronously sampling the output voltage of the isolated power supply module, extracting the ripple signal amplitude through digital filtering, and obtaining the compensation time amount based on the ripple amplitude multiplied by the power supply compensation coefficient, wherein the power supply compensation coefficient is inversely proportional to the ripple frequency.

[0042] In one embodiment, synchronous sampling of the output voltage of the isolated power supply module and extraction of the ripple signal amplitude through digital filtering include: on the isolated power supply module side, converting the high-voltage output to the range of the isolated analog-to-digital converter through a resistor divider network; oversampling the signal with a preset clock through a modulator on the primary side of the isolated analog-to-digital converter, transmitting a digital bit stream through magnetic isolation on the secondary side of the isolated analog-to-digital converter, and reconstructing the digital bit stream into a preset bit digital code value through a filter; inputting the preset bit digital code value into a digital filter for filtering, and then extracting the ripple signal amplitude through a sliding window. The extracted ripple signal amplitude is multiplied by the power supply compensation coefficient to obtain the compensation time. Specifically, the power supply compensation coefficient is expressed as: Among them, A represents the amplitude-frequency coupling coefficient, and B represents the frequency attenuation constant. A and B are automatically calibrated when the power load change rate exceeds the threshold, and redundant channels are enabled during calibration to avoid affecting real-time communication. is the ripple frequency, It is the dividing point between the low frequency band and the high frequency band of the ripple frequency, and C is the basic compensation offset.

[0043] From the above formula of power supply compensation coefficient, we can know that the effect of ripple on delay in low frequency band is first-order attenuation, while the effect of ripple on delay in high frequency band is second-order rapid attenuation. And the dividing point between low frequency band and high frequency band of ripple frequency is The ripple spectrum can be analyzed by Fourier and dynamically adjusted to ensure full coverage of broadband ripples and avoid the problem of not being able to cover broadband ripples.

[0044] In one embodiment, while obtaining the compensation time based on the ripple amplitude multiplied by the dynamic coefficient, the method further includes: monitoring the ripple frequency in real time, and adjusting the power compensation coefficient in real time according to the ripple frequency.

[0045] S140: Calculate a phase compensation value based on the time domain compensation amount and the communication transmission delay amount.

[0046] By fusing the time domain compensation amount and the communication transmission delay amount into a phase compensation value, the influence of power supply ripple and communication link jitter on synchronization accuracy can be eliminated.

[0047] In one embodiment, the phase compensation value is calculated based on the time domain compensation amount and the communication transmission delay amount, including: fusing the time domain compensation amount and the communication transmission delay amount into the phase compensation value through a preset mathematical model.

[0048] Exemplarily, the preset mathematical model is expressed as: ;in, is the time domain compensation, is the ripple amplitude, is the power compensation coefficient of the ith frequency band included in the ripple, is the communication compensation coefficient, is the communication transmission delay, is the frequency of the signal to be compensated, To convert the time offset to a phase radian value, is the phase compensation value.

[0049] The communication compensation coefficient is inversely correlated with the sliding window variance of the communication transmission delay, which can be expressed as: ;in, The sliding window variance of the communication transmission delay is represented by C and D, which are calibration constants used to prevent the denominator from being zero. High), reduce To suppress unreliable compensation, when the communication delay is stable ( low), increase To enhance the compensation effect.

[0050] Since the time domain compensation amount representing the absolute time offset caused by power supply ripple is related to the hardware circuit, and the communication transmission delay amount representing the end-to-end delay of signal transmission is related to the network link, the physical sources and influencing mechanisms of the two are different, and direct superposition will lead to weight imbalance. This application not only maps the time offset to the relative position within the signal period by fusing it into a phase compensation value, which is suitable for periodic control signals, but also supports a unified compensation interface for cross-frequency systems. In the phase domain, adaptive weighting of communication delay is achieved through communication compensation coefficients, which can avoid hard truncation in the time domain and solve the weight distribution problem caused by the different physical sources of the two.

[0051] S150: Dynamically adjust the generation time of the control signal according to the phase compensation value to synchronously control the master and slave devices.

[0052] Specifically, dynamically adjusting the generation time of the control signal based on the phase compensation value includes: converting the phase compensation value into a time offset, dynamically adjusting the triggering time of the control signal based on the time offset, and generating the control signal based on the triggering time to synchronously control the master and slave devices.

[0053] In practical applications, the actual hardware triggers actions through time registers. Therefore, it is necessary to convert the phase compensation value into a time offset, and then dynamically adjust the trigger time point of the time register according to the time offset to accurately control the master and slave devices.

[0054] The above analysis demonstrates that the master-slave device synchronization control method provided in the embodiments of the present application obtains a first timestamp carried in the signal broadcast from the master device to the slave device and a second timestamp in the signal received by the slave device; calculates the communication transmission delay based on the first and second timestamps; measures the power ripple data of the slave device and converts it into a time-domain compensation value; calculates a phase compensation value based on the time-domain compensation value and the communication transmission delay; and dynamically adjusts the generation time of the control signal based on the phase compensation value to synchronize the master and slave devices. By establishing coupled compensation for power ripple and communication delay, precise synchronization control and reliability of the medical device system are achieved.

[0055] See Figure 2 , Figure 2 Schematic diagram of a master-slave device synchronization control device provided in one embodiment of the present application. The master-slave device synchronization control device includes modules or units for executing Figure 1 Each step in the corresponding embodiment. Please refer to Figure 1 For the convenience of explanation, only the parts related to this embodiment are shown. Figure 2 , a master-slave device synchronization control device 200, comprising: An acquisition module 210 is configured to acquire a first timestamp carried in a signal broadcast by the master device to the slave device and a second timestamp carried in a signal received by the slave device; A first calculation module 220, configured to calculate a communication transmission delay according to the first timestamp and the second timestamp; The conversion module 230 is configured to measure the power ripple data of the slave device and convert the power ripple data into a time domain compensation value; A second calculation module 240 is configured to calculate a phase compensation value based on the time domain compensation amount and the communication transmission delay amount; The adjustment module 250 is configured to dynamically adjust the generation time of the control signal according to the phase compensation value to synchronously control the master and slave devices.

[0056] In one embodiment, the conversion module 230 is specifically configured to: The output voltage of the isolated power supply module is synchronously sampled, the ripple signal amplitude is extracted through digital filtering, and the compensation time is obtained based on the ripple amplitude multiplied by a power compensation coefficient, wherein the power compensation coefficient is inversely proportional to the ripple frequency.

[0057] In one embodiment, the conversion module 230 includes: A conversion unit, on the side of the isolated power supply module, is used to convert the high voltage output into an isolated analog-to-digital converter range through a resistor divider network; a reconstruction unit, configured to oversample the signal at a preset clock through a modulator on the primary side of the isolated analog-to-digital converter, transmit a digital bit stream through magnetic isolation on the secondary side of the isolated analog-to-digital converter, and reconstruct the digital bit stream into a preset bit digital code value through a filter; The extraction unit is used to input the preset digital code value into the digital filter for filtering, and then extract the ripple signal amplitude through a sliding window.

[0058] In one embodiment, the apparatus 200 further includes: The adjustment module is used to monitor the ripple frequency in real time and adjust the power compensation coefficient in real time according to the ripple frequency.

[0059] In one embodiment, the second calculation module 240 is specifically configured to: The time domain compensation amount and the communication transmission delay amount are fused into the phase compensation value through a preset mathematical model.

[0060] In one embodiment, the preset mathematical model is expressed as: ;in, is the time domain compensation, is the ripple amplitude, is the power compensation coefficient of the ith frequency band included in the ripple, is the communication compensation coefficient, is the communication transmission delay, is the frequency of the signal to be compensated, To convert the time offset to a phase radian value, is the phase compensation value.

[0061] In one embodiment, the communication compensation coefficient is inversely correlated with the sliding window variance of the communication transmission delay.

[0062] See Figure 3 , Figure 3 A schematic diagram of a master-slave device synchronization control device provided in an embodiment of the present application. Figure 3 It can be seen that the master-slave device synchronization control device 300 includes: a processor 310, a memory 320, and a computer program 330 stored in the memory 320 and executable on the processor 310; when the processor 310 executes the computer program 330, the steps in the above-mentioned master-slave device synchronization control method embodiments are implemented, such as Figure 1 Alternatively, when the processor 310 executes the computer program 330, the functions of the modules / units in the above-mentioned device embodiments are realized, for example Figure 2 The functions of the modules 210 to 250 are shown.

[0063] Exemplarily, computer program 330 may be divided into one or more modules / units, one or more of which are stored in memory 320 and executed by processor 310 to implement the present application. One or more modules / units may be a series of computer program instruction segments capable of performing specific functions, and these instruction segments are used to describe the execution process of computer program 330 in the master-slave synchronization control device. For example, computer program 330 may be divided into an acquisition module, a first calculation module, a conversion module, a second calculation module, and an adjustment module.

[0064] The master-slave device synchronization control device provided in this embodiment may include, but is not limited to, a processor and a memory. It will be understood by those skilled in the art that Figure 3 It is only an example of a master-slave device synchronization control device and does not constitute a limitation of the master-slave device synchronization control device. It may include more or fewer components than shown in the figure, or a combination of certain components, or different components. For example, the master-slave device synchronization control device may also include input and output devices, network access devices, buses, etc.

[0065] The processor 310 may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor.

[0066] The memory 320 can be an internal storage unit of the master-slave synchronous control device, such as a hard drive or memory of the master-slave synchronous control device. The memory 320 can also be an external storage device of the master-slave synchronous control device, such as a plug-in hard drive, a Smart Media Card (SMC), a Secure Digital (SD) card, a flash memory card, etc. Furthermore, the master-slave synchronous control device can include both an internal storage unit and an external storage device. The memory 320 is used to store computer programs and other programs and data required by the master-slave synchronous control device. The memory 320 can also be used to temporarily store data that has been output or is about to be output.

[0067] It should be noted that the information interaction, execution process, etc. between the above-mentioned devices / units are based on the same concept as the method embodiment of this application. Their specific functions and technical effects can be found in the method embodiment section and will not be repeated here.

[0068] An embodiment of the present application also provides a network device, which includes: at least one processor, a memory, and a computer program stored in the memory and executable on the at least one processor, wherein the processor implements the steps of any of the above-mentioned method embodiments when executing the computer program.

[0069] An embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in the above-mentioned various method embodiments can be implemented.

[0070] An embodiment of the present application provides a computer program product. When the computer program product is run on a mobile terminal, the mobile terminal can implement the steps in the above-mentioned various method embodiments when executing the computer program product.

[0071] If the integrated unit is implemented as a software functional unit and sold or used as a standalone product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application can implement all or part of the process steps in the above-mentioned method embodiments by using a computer program to instruct the relevant hardware. The computer program can be stored in a computer-readable storage medium. When executed by a processor, the computer program can implement the steps of each of the above-mentioned method embodiments. The computer program includes computer program code, which can be in source code form, object code form, executable file, or some intermediate form. The computer-readable medium can include at least: any entity or device capable of carrying computer program code to a camera / terminal device, recording medium, computer memory, read-only memory (ROM), random access memory (RAM), electric carrier signals, telecommunication signals, and software distribution media. Examples include USB flash drives, removable hard drives, magnetic disks, or optical disks. In some jurisdictions, based on legislation and patent practice, computer-readable media cannot be electric carrier signals or telecommunication signals.

[0072] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.

[0073] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0074] In the embodiments provided in this application, it should be understood that the disclosed devices / network equipment and methods can be implemented in other ways. For example, the device / network equipment embodiments described above are merely illustrative. For example, the division of the modules or units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0075] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0076] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A master-slave device synchronization control method, characterized in that: The method comprises: Obtain a first timestamp carried in a signal broadcast by the master device to the slave device and a second timestamp carried in a signal received by the slave device; Calculating a communication transmission delay amount according to the first timestamp and the second timestamp; Measuring power ripple data of the slave device, and converting the power ripple data into a time domain compensation amount; Calculating a phase compensation value according to the time domain compensation amount and the communication transmission delay amount; According to the phase compensation value, the generation time of the control signal is dynamically adjusted to synchronously control the master and slave devices.

2. The master-slave device synchronization control method according to claim 1, wherein: The converting the power ripple data into a time domain compensation value comprises: The output voltage of the isolated power supply module is synchronously sampled, the ripple signal amplitude is extracted through digital filtering, and the compensation time is obtained based on the ripple amplitude multiplied by a power compensation coefficient, wherein the power compensation coefficient is inversely proportional to the ripple frequency.

3. The master-slave device synchronization control method according to claim 2, wherein: The synchronous sampling of the output voltage of the isolated power supply module and the extraction of the ripple signal amplitude by digital filtering include: On the isolated power supply module side, the high voltage output is converted into an isolated analog-to-digital converter range through a resistor divider network; Oversampling the signal at a preset clock by a modulator on the primary side of the isolated analog-to-digital converter, transmitting a digital bit stream through magnetic isolation on the secondary side of the isolated analog-to-digital converter, and reconstructing the digital bit stream into a preset bit digital code value through a filter; After the preset digital code value is input into a digital filter for filtering, the ripple signal amplitude is extracted through a sliding window.

4. The master-slave device synchronization control method according to claim 3, wherein: While obtaining the compensation time amount based on the ripple amplitude multiplied by the dynamic coefficient, the method further includes: The ripple frequency is monitored in real time, and the power compensation coefficient is adjusted in real time according to the ripple frequency.

5. The master-slave device synchronization control method according to claim 1, wherein: The calculating the phase compensation value according to the time domain compensation amount and the communication transmission delay amount includes: The time domain compensation amount and the communication transmission delay amount are fused into the phase compensation value through a preset mathematical model.

6. The master-slave device synchronization control method according to claim 5, wherein: The preset mathematical model is expressed as: ;in, is the time domain compensation, is the ripple amplitude, is the power compensation coefficient of the ith frequency band included in the ripple, is the communication compensation coefficient, is the communication transmission delay, is the frequency of the signal to be compensated, To convert the time offset to a phase radian value, is the phase compensation value.

7. The master-slave device synchronization control method according to claim 6, wherein: The communication compensation coefficient is inversely correlated with the sliding window variance of the communication transmission delay.

8. A master-slave device synchronization control device, characterized in that: include: An acquisition module, configured to acquire a first timestamp carried in a signal broadcast by the master device to the slave device and a second timestamp carried in a signal received by the slave device; A first calculation module, configured to calculate a communication transmission delay according to the first timestamp and the second timestamp; a conversion module, configured to measure power ripple data of the slave device and convert the power ripple data into a time domain compensation amount; A second calculation module is used to calculate a phase compensation value according to the time domain compensation amount and the communication transmission delay amount; The adjustment module is used to dynamically adjust the generation time of the control signal according to the phase compensation value to synchronously control the master and slave devices.

9. A master-slave device synchronization control device, characterized in that: include: A processor, a memory, and a computer program stored in the memory and executable on the processor; When the processor executes the computer program, the method according to any one of claims 1 to 7 is implemented.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.

Citation Information

Patent Citations

  • A synchronization system and method based on wireless or limited cable interconnection and an MR system

    CN109714143A

  • Digital receiving device, system and method for tracking and observing target radio-frequency power supply

    CN111314009A

  • Parallel clock synchronization method for DC-DC power supply module

    CN118138185A

  • Method for monitoring and controlling operation state of sapphire annealing furnace

    CN119877107A

  • Power supply dependent delay compensation

    US20040120437A1