Image sensor

Abstract

An image sensor is provided. The image sensor includes: a pixel array having a pixel region and a dummy region; a row driver configured to sequentially output driving signals to the pixel array; a detection circuit configured to receive a row output signal generated based on the driving signal from the dummy region, and to receive the driving signal; and a timing controller configured to provide the driving signal to the row driver and provide the driving signal and the clock signal to the detection circuit. The detection circuit is further configured to identify a difference between delay times corresponding to adjacent ones of the rows, determine whether the rows are defective by comparing the difference with a reference value, and output a result value indicating whether the rows are defective.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2024-0037387 filed on March 18, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to an image sensor, and more particularly, to an image sensor capable of detecting defective or faulty rows of a pixel array. Background Art

[0004] An image sensor is a device that captures two-dimensional or three-dimensional images of an object. Image sensors generate images of an object using a photoelectric conversion device that reacts to the intensity of light reflected by or emitted from the object. Recently, with the development of the computer and communications industries, there has been an increasing demand for image sensors with improved performance in various electronic devices, such as digital cameras, video cameras, personal communication systems (PCS), gaming devices, security cameras, medical miniature cameras, and mobile phones.

[0005] An image sensor may include a pixel array including a plurality of pixels and a row driver that drives the rows of pixels. When an error occurs in a driving signal output from the row driver or a signal transmission line, the image sensor may not operate normally. Summary of the Invention

[0006] One or more example embodiments provide an image sensor capable of generating a count result value by counting cycles of a clock signal within a time interval in which a selected M-th row output signal is delayed compared to a driving signal, generating a difference between a previous count result value and the count result value, comparing the difference with a reference value, and determining whether the selected row has a fault.

[0007] According to one aspect of an example embodiment, an image sensor includes: a pixel array including a pixel region and a dummy region adjacent to the pixel region and on the same plane as the pixel region, the pixel region including pixels arranged in a plurality of rows; a row driver configured to sequentially output drive signals to the pixel array; a detection circuit configured to receive a plurality of row output signals generated based on the drive signals from the dummy region and to receive the drive signals; and a timing controller configured to provide the drive signals to the row driver and to provide the drive signals and a clock signal to the detection circuit. The detection circuit is further configured to: identify a difference between delay times corresponding to adjacent rows of the plurality of rows, determine whether the plurality of rows are defective by comparing the difference with a reference value, and output a result value indicating whether the plurality of rows are defective.

[0008] According to another aspect of an example embodiment, an image sensor includes: a pixel array including a pixel region and a dummy region, the pixel region including a plurality of pixels; a row driver configured to output a drive signal to the pixel array; and a detection circuit configured to receive a plurality of row output signals from the dummy region, and receive the drive signal and a clock signal. The detection circuit includes: a signal selection circuit configured to select an Nth row output signal from the plurality of row output signals; a counter circuit configured to generate an Nth count result value by counting cycles of a clock signal during a time interval of the Nth row output signal based on the drive signal; a difference circuit configured to generate an Nth difference value between the Nth count result value and an N-1th count result value; and a comparison circuit configured to detect a defect in the Nth row output signal by comparing the Nth difference value with a reference value. The time interval includes a delay interval by which the Nth row output signal is delayed based on the drive signal.

[0009] According to another aspect of an example embodiment, a method of operating an image sensor includes: receiving a driving signal; receiving a plurality of row output signals; selecting an Nth row output signal from among the plurality of row output signals; generating an Nth count result value by counting cycles of a clock signal during a delay time interval between the driving signal and the Nth row output signal; generating an Nth difference value between the Nth count result value and an N-1th count result value; comparing the Nth difference value with a reference value; and detecting that the Nth row output signal is faulty based on the Nth difference value being greater than the reference value. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects will become more apparent from the following description of example embodiments taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a block diagram illustrating an image sensor according to example embodiments;

[0012] Figure 2 is a circuit diagram illustrating a detection circuit according to an example embodiment;

[0013] Figure 3 is a circuit diagram of a pixel included in an image sensor according to example embodiments;

[0014] Figure 4 is a circuit diagram illustrating a dummy region of a pixel array according to example embodiments;

[0015] Figure 5 and Figure 6 is a timing diagram illustrating a first driving signal and a plurality of row output signals received by a detection circuit according to an example embodiment;

[0016] Figure 7 and Figure 8 is a diagram illustrating a method of operating a detection circuit of a selected row according to an example embodiment;

[0017] Figure 9 is a flowchart illustrating a method of operating an image sensor according to example embodiments;

[0018] Figure 10 is a circuit diagram of a pixel included in an image sensor according to example embodiments;

[0019] Figure 11 is a circuit diagram illustrating a dummy region of a pixel array according to example embodiments;

[0020] Figure 12 and Figure 13 is a circuit diagram of a pixel included in an image sensor according to example embodiments;

[0021] Figure 14 is a diagram illustrating a stacked structure of an image sensor according to example embodiments;

[0022] Figure 15 is a block diagram schematically illustrating a computer system including an image sensor according to example embodiments;

[0023] Figure 16 is a block diagram of an electronic device including a multi-camera module according to example embodiments; and

[0024] Figure 17 is a detailed block diagram of a multi-camera module according to example embodiments. DETAILED DESCRIPTION

[0025] Hereinafter, example embodiments will be described in detail with reference to the accompanying drawings. Throughout the specification, similar components are represented by similar reference numerals, and repeated descriptions thereof are omitted. The embodiments described herein are example embodiments, and therefore, the present disclosure is not limited thereto and may be implemented in various other forms. Each embodiment provided in the following description does not exclude association with one or more features of another example or another embodiment also provided herein or not provided herein but consistent with the present disclosure.

[0026] Figure 1 is a block diagram illustrating an image sensor 10 according to example embodiments.

[0027] Image sensor 10 can be mounted on electronic devices with imaging or light-sensing capabilities. For example, image sensor 10 can be mounted on electronic devices such as cameras, smartphones, wearable devices, Internet of Things (IoT) devices, home appliances, tablet personal computers (PCs), personal digital assistants (PDAs), portable multimedia players (PMPs), navigation systems, drones, and advanced driver assistance systems (ADAS). Furthermore, image sensor 10 can be mounted on electronic devices that are provided as components in vehicles, furniture, manufacturing facilities, doors, various measurement devices, and the like.

[0028] refer to Figure 1 The image sensor 10 may include a pixel array 20 , a row driver 30 , a timing controller 60 , an analog-to-digital conversion circuit 40 (hereinafter, referred to as an ADC circuit), a column driver 50 , and a detection circuit 70 .

[0029] The timing controller 60 may control the row driver 30, the ADC circuit 40, the column driver 50, and the detection circuit 70. The timing controller 60 may output a drive signal CTRL to each of the row driver 30, the ADC circuit 40, the column driver 50, and the detection circuit 70 to control their operation or timing. The timing controller 60 may output a clock signal CLK to the detection circuit 70. In example embodiments, the timing controller 60 may include control logic, a phase-locked loop (PLL) circuit, a communication interface circuit, etc. In example embodiments, the timing controller 60 may output the drive signal CTRL to the row driver 30 and the detection circuit 70. The drive signal CTRL may include a first drive signal TS, a second drive signal RS, and a third drive signal SEL. The first drive signal TS may be a transmission control signal for the pixel PX, the second drive signal RS may be a reset signal for the pixel PX, and the third drive signal SEL may be a select signal SEL for the pixel PX.

[0030] In example embodiments, it is described that the detection circuit 70 and the row driver 30 detect defects or failures in the plurality of row lines R1 to Rn by receiving the first driving signal TS.

[0031] The pixel array 20 may include a pixel area PA and a dummy area DA. The dummy area DA may be disposed adjacent to the pixel area PA on the same plane as the pixel area PA. The pixel array 20 may include a plurality of row lines R1 to Rn (where n is a natural number of 2 or greater), a plurality of column lines CL, and a plurality of pixels PX connected to the plurality of row lines R1 to Rn and the plurality of column lines CL and arranged in rows and columns. In an example embodiment, the image sensor 10 may be an active pixel sensor (APS).

[0032] The dummy area DA may output a first driving signal TS and first to Nth row output signals RO_1 to RO_N. The first driving signal TS and the plurality of row output signals RO_1 to RO_N may be connected to a detection circuit 70 extending in a column direction.

[0033] Each of the plurality of pixels PX may include at least one photoelectric conversion device, and the pixel PX may detect light using the photoelectric conversion device and output an image signal, which is an electrical signal based on the detected light. For example, the photoelectric conversion device may be a light detection device including an organic material or an inorganic material, such as an inorganic photodiode, an organic photodiode, a perovskite photodiode, a phototransistor, a photogate, or a pinned photodiode. In example embodiments, each of the plurality of pixels PX may include a plurality of photoelectric conversion devices.

[0034] The row driver 30 can drive the pixel array 20 in units of one or more rows. For example, the row driver 30 can drive one row of the pixel array 20 at a time, and the rows of the pixel array 20 can be driven sequentially. The row driver 30 can decode the drive signal CTRL (e.g., a row control signal (address signal)) received from the timing controller 60 and select at least one of the row lines that constitute the pixel array 20 in response to the decoded row control signal. For example, the row driver 30 can generate a selection signal that selects one of the multiple rows. In addition, the pixel array 20 can output pixel signals from the row selected by the selection signal provided by the row driver 30.

[0035] The row driver 30 may transmit a control signal for outputting a pixel signal to the pixel array 20 , and the pixel PX may output the pixel signal by operating in response to the control signal. The row driver 30 may output a driving signal CTRL to the pixel area PA and the dummy area DA of the pixel array 20 .

[0036] In example embodiments, the dummy area DA may be disposed on a first side of the pixel area PA, and the row driver 30 may be disposed on a second side of the pixel area PA opposite to the first side. In this regard, the pixel area PA may be disposed between the row driver 30 and the dummy area DA.

[0037] The ADC circuit 40 may be connected to the column lines CL of the pixel array 20 and may convert analog signals output from the pixel array 20 into digital signals. For example, the ADC circuit 40 may be an analog-to-digital converter that converts analog signals into digital signals.

[0038] The ADC circuit 40 may include a plurality of correlated double sampling (CDS) circuits and a plurality of counters. The ADC circuit 40 may convert pixel signals (e.g., pixel voltages) input from the pixel array 20 into pixel values ​​as digital signals. The pixel signals received via each of the plurality of column lines CL may be converted into pixel values ​​as digital signals by the CDS circuits and the counters.

[0039] The column driver 50 can sequentially output the output data of the digital signal from the ADC circuit 40. The column driver 50 can temporarily store the pixel values ​​output from the ADC circuit 40 and then output the pixel values. For example, the column driver 50 can include multiple column memories (or buffers) and a column decoder. The column memories can store received pixel values. The multiple pixel values ​​stored in the multiple column memories can be output as image data under the control of the column decoder.

[0040] The detection circuit 70 can receive a drive signal CTRL from the timing controller 60 and a plurality of row output signals RO_1 to RO_N from the pixel array 20. For example, the detection circuit 70 can receive a first drive signal TS from the timing controller 60 and a plurality of row output signals RO_1 to RO_N from the dummy area DA. The detection circuit 70 can detect horizontal fixed pattern noise (HFPN) in the pixel array 20 based on the plurality of row output signals RO_1 to RO_N and the first drive signal TS. When HFPN occurs, the detection circuit 70 can output an error signal FAIL_RST to the timing controller 60. For example, when HFPN occurs, the timing controller 60 can generate an error message and display the error message to the user. For example, when the image sensor 10 is used as a front camera or a rear camera of a vehicle, the timing controller 60 can notify the user of HFPN to prevent accidents.

[0041] Detection circuit 70 may receive a first drive signal TS and a plurality of row output signals RO_1 to RO_N, select one of the plurality of row output signals RO_1 to RO_N based on the first drive signal TS, and detect whether the selected row output signal has failed. For example, detection circuit 70 may select a third row output signal from the plurality of row output signals RO_1 to RO_N and count cycles of clock signal CLK during a time interval delayed by the first drive signal TS when receiving the third row output signal through detection circuit 70, thereby generating a count result value.

[0042] The detection circuit 70 can generate a difference between the count result value and the previous count result value and compare the difference with a reference value to detect defects in the selected row. For example, if the difference exceeds the reference value, the selected row may include a defect. The detection circuit 70 can generate an error message or a failure message for the defect in the selected row and display the error message or failure message on the timing controller 60 to notify the user. For example, when the image sensor 10 is in the testing phase, the timing controller 60 can notify the manufacturer that the selected row is faulty or defective, and when the image sensor 10 is used as a front camera or rear camera of a vehicle, the driver is notified that the selected row is faulty or defective. In other words, the detection circuit 70 can detect whether the selected row is faulty among the row defects of the HFPN as the pixel array 20. When the selected row is faulty, the detection circuit 70 can detect whether the pixels in the selected row are faulty.

[0043] Figure 2 The detection circuit 70 is shown to receive the first drive signal TS and the plurality of row output signals RO_1 to RO_N from the dummy area DA, but this is merely an example, and in different example embodiments, the detection circuit 70 may receive the first drive signal TS and the plurality of row output signals RO_1 to RO_N from the pixel area PA.

[0044] Reference below Figure 2 A detailed description of the detection circuit 70 is described.

[0045] Figure 2 is a circuit diagram illustrating a detection circuit 70 according to an example embodiment.

[0046] refer to Figure 2 The detection circuit 70 may include a row output signal selection block (ie, a row output signal selection circuit) 120 , a counter block (ie, a counter circuit) 130 , a differential block (ie, a differential circuit) 140 , and a comparison block (ie, a comparison circuit) 150 .

[0047] The row output signal selection block 120 may include a multiplexer (Mux) 121. The multiplexer 121 may select a signal from the pixel array 20 or a dummy area ( Figure 1 The multiplexer 121 may provide one of a plurality of row output signals RO_1 to RO_N outputted by the multiplexer 121. The multiplexer 121 may provide the selected one row output signal (eg, the Mth row output signal RO_M (where 1<M<N)) to the counter block 130.

[0048] Counter block 130 may include a counter circuit 131. Counter circuit 131 may receive a clock signal and a first drive signal TS, and may receive an M-th row output signal RO_M from multiplexer 121. Counter circuit 131 may count cycles of clock signal CLK within a specific time interval of the M-th row output signal RO_M based on the first drive signal TS, thereby generating a count result value CNT_N. The time interval may be defined as the length of time that the M-th row output signal RO_M is delayed compared to the first drive signal TS. The time interval may also be referred to as a duration.

[0049] According to an example embodiment, a method of counting the cycles of the clock signal CLK in at least one time interval of the M-th row output signal RO_M may be selected as one of two options. Hereinafter, the counter block 130 may receive a first drive signal TS and an M-th row output signal RO_M, the first drive signal TS may be a signal that repeatedly rises or falls and switches between a logic high level and a logic low level in each row drive interval, and the M-th row output signal RO_M may be a signal that rises in the M-th row drive interval. For example, the first option may be a method of counting the cycles of the clock signal CLK in a time interval in which the M-th row output signal RO_M is delayed compared to the first drive signal TS in the selected row, and the second option may be a method of counting the cycles of the clock signal CLK in a time interval in which the M-th row output signal RO_M switches from a logic low level to a logic high level for the first time in the selected row. Reference is made below to Figure 6 and Figure 7 Describes a method for identifying time intervals.

[0050] According to example embodiments, a time interval for performing a counting operation (ie, a time interval for outputting the M-th row signal RO_M) may be determined according to whether a row of the pixel array is selected.

[0051] According to example embodiments, the counter circuit 131 may count cycles of the clock signal CLK during a specific time interval in which the M-th row output signal RO_M is delayed compared to the first drive signal TS, thereby generating a count result value CNT_N. Alternatively, the counter circuit 131 may count cycles of the clock signal CLK during a time interval in which the M-th row output signal RO_M is first switched from a logic low level to a logic high level in the selected row, thereby generating a count result value CNT_N.

[0052] Furthermore, according to example embodiments, the counter circuit 131 may count cycles of the clock signal CLK during a time interval in which the M-th row output signal RO_M is delayed relative to the first drive signal TS in the selected row. The counter circuit 131 may count cycles of the clock signal CLK during a time interval in which the first drive signal TS is input and the M-th row output signal RO_M transitions from a logic low level to a logic high level. Assuming that the M-th row output signal RO_M is input with a delay of 7 μs relative to the first drive signal TS, the counter circuit 131 may count 7 and output 7 corresponding to the count result value CNT_N.

[0053] The differential block 140 may include a register 141 and a differential circuit 142. The register 141 may receive and store the count result value CNT_N output from the counter circuit 131. The differential circuit 142 may receive the previous count result value CNT_(N-1) output from the register 141 and the count result value CNT_N output from the counter circuit 131. Here, the previous count result value CNT_(N-1) may indicate a time interval by which the M-1th row output signal RO_(M-1) is delayed compared to the first drive signal TS.

[0054] The difference circuit 142 may perform a subtraction operation to subtract the previous count result value CNT_(N-1) from the count result value CNT_N. The difference circuit 142 may calculate the difference between the count result value CNT_N and the previous count result value CNT_(N-1). The difference circuit 142 may generate a difference value DELTA_N by subtracting the previous count result value CNT_(N-1) from the count result value CNT_N. The difference value DELTA_N may be an absolute value obtained by subtracting the previous count result value CNT_(N-1) from the count result value CNT_N. For example, when the count result value CNT_N is 6 and the previous count result value CNT_(N-1) is 7, the difference value may be .

[0055] Comparison block 150 may include a comparison circuit 151. Comparison circuit 151 may receive a difference value DELTA_N from differential circuit 142 and an external reference value EXP. Comparison circuit 151 may compare difference value DELTA_N with reference value EXP during a specific time interval. Comparison circuit 151 may compare difference value DELTA_N with reference value EXP to detect defects in a selected row. Comparison circuit 151 may compare difference value DELTA_N with reference value EXP and output a result value RST based on the comparison.

[0056] The comparison circuit 151 can compare the magnitude or level between the difference value DELTA_N and the reference value EXP. The comparison circuit 151 can output a result value RST corresponding to a fail when the difference value DELTA_N is greater than the reference value EXP, and output a result value RST corresponding to a pass when the difference value DELTA_N is less than the reference value EXP. The comparison circuit 151 can output the result value RST corresponding to a fail to the timing controller ( Figure 1 60 in the ) to notify the user that a defect or failure has occurred in the selected row.

[0057] For example, when the difference value DELTA_N is 1 and the reference value EXP is 2, the comparison circuit 151 may output a result value RST corresponding to a pass because the difference value DELTA_N is less than the reference value EXP. When the difference value DELTA_N is 4 and the reference value EXP is 2, the difference value DELTA_N is greater than the reference value EXP, so the comparison circuit 151 may output a result value RST corresponding to a fail. The comparison circuit 151 may provide the result value RST corresponding to the fail to the timing controller ( Figure 1 60), and the timing controller ( Figure 1 60) may output an error message to inform the user that the selected row has a defect or failure.

[0058] The image sensor including the detection circuit 70 according to example embodiments may generate a count result value CNT_N by counting cycles of the clock signal CLK during a time interval in which the selected M-th row output signal RO_M is delayed compared to the first driving signal TS, generate a difference value DELTA_N by subtracting a previous count result value CNT_(N-1) from the count result value CNT_N, and determine and detect whether the selected row has a fault by comparing the difference value DELTA_N with a reference value EXP.

[0059] Figure 3 is a circuit diagram of a pixel PX included in an image sensor according to example embodiments. Figure 3 The pixel PX in Figure 1 An example of one of the pixels PX included in the pixel array 20 in FIG.

[0060] refer to Figure 3 , the pixel PX may include a photodiode PD, a transfer transistor TX, a reset transistor RX, a drive transistor DX, and a selection transistor SX.

[0061] The photodiode PD may be replaced with another light sensing device. The photodiode PD may also be referred to as a photoelectric conversion device. The photodiode PD may generate photocharges that vary according to the intensity of incident light.

[0062] One end of the transfer transistor TX may be connected to the photodiode PD and the other end thereof may be connected to the floating diffusion node FD. The transfer transistor TX may transfer photocharges from the photodiode PD to the floating diffusion node FD according to a transfer control signal TS supplied to a gate of the transfer transistor TX.

[0063] One end of the drive transistor DX may be connected to the selection transistor SX, and the other end thereof may be connected to one end of the reset transistor RX. The drive transistor DX may amplify the photocharge according to the potential generated by the photocharge accumulated in the floating diffusion node FD and output the photocharge through the selection transistor SX.

[0064] One end of the select transistor SX may be connected to the drive transistor DX, and the other end thereof may be connected to one of the plurality of column lines CL. A select control signal SEL may be supplied to the gate of the select transistor SX. The select transistor SX may be turned on in response to the select control signal SEL. When the select transistor SX is turned on in response to the select control signal SEL, a sensing signal (i.e., a light sensing signal) corresponding to the voltage level of the floating diffusion node FD may be output as, for example, a pixel signal.

[0065] One end of the reset transistor RX can be connected to the floating diffusion node FD, and the other end thereof can be connected to one end of the drive transistor DX. The gate of the reset transistor RX can be turned on in response to a reset control signal RS. The gate of the reset transistor RX can reset the floating diffusion node FD based on the power supply voltage VDD according to the reset control signal RS. At this time, a reset signal corresponding to the voltage level of the floating diffusion node FD can be output as a pixel signal.

[0066] The pixel signal can be output to the ADC circuit (for example, Figure 1 of 40). Figure 3 A pixel PX including one photodiode PD and four transistors including a transfer transistor TX, a reset transistor RX, a drive transistor DX, and a select transistor SX is illustrated, but example embodiments are not limited thereto.

[0067] Figure 4 is a circuit diagram illustrating a dummy area DA of a pixel array according to example embodiments. Figure 4 The dummy area DA shown may correspond to Figure 1 The dummy area DA is shown.

[0068] refer to Figure 3 and Figure 4The dummy area DA may receive a first drive signal TS. For example, the first drive signal TS may be a transmission control signal TS of the pixel PX. Furthermore, the dummy area DA may receive a second drive signal RS and a third drive signal SEL. For example, the second drive signal RS may be a reset control signal RS of the pixel PX, and the third drive signal SEL may be a selection control signal SEL.

[0069] refer to Figure 4 The dummy area DA can output a first row output signal RO_1, a second row output signal RO_2, and an N-th row output signal RO_N based on a first drive signal TS. In an example embodiment, a configuration and method are shown in which the dummy area DA counts cycles of a clock signal CLK during a time interval in which the first row output signal RO_1, the second row output signal RO_2, and the N-th row output signal RO_N are delayed based on the first drive signal TS.

[0070] Figure 4 The illustrated dummy area DA may include two or more N-type transistors connected in series, but example embodiments are not limited thereto.

[0071] The first row R1 of the dummy area DA may include a first reset transistor RX1 to which the second drive signal RS is applied and a first select transistor SX11 to which the third drive signal SEL is applied, and may include a first pass transistor TX1 to which the first drive signal TS is applied and a second select transistor SX12 to which the third drive signal SEL is applied. The first row R1 of the dummy area DA may output a first row output signal RO_1 based on the first drive signal TS.

[0072] The second row R2 of the dummy area DA may include a first reset transistor RX2 to which the second drive signal RS is applied and a first select transistor SX21 to which the third drive signal SEL is applied, and may include a first transfer transistor TX2 to which the first drive signal TS is applied and a second select transistor SX22 to which the third drive signal SEL is applied. The second row R2 of the dummy area DA may output a second row output signal RO_2 based on the first drive signal TS.

[0073] The Nth row Rn of the dummy area DA may include a first reset transistor RXn to which the second drive signal RS is applied and a first select transistor SXn1 to which the third drive signal SEL is applied, and may include a first pass transistor TXn to which the first drive signal TS is applied and a second select transistor SXn2 to which the third drive signal SEL is applied. The Nth row Rn of the dummy area DA may output an Nth row output signal RO_N based on the first drive signal TS.

[0074] The dummy area DA may be connected to the detection circuit 70 via column lines CL, which may include a first column line CL1 and a second column line CL2. The dummy area DA may output a first row output signal RO_1, a second row output signal RO_2, and an N-th row output signal RO_N to the first column line CL1 based on a first drive signal TS, and provide the first row output signal RO_1, the second row output signal RO_2, and the N-th row output signal RO_N to the detection circuit 70. The detection circuit 70 may receive the first row output signal RO_1, the second row output signal RO_2, and the N-th row output signal RO_N via the same second column line CL2.

[0075] Figure 5 and Figure 6 is a timing diagram illustrating a first driving signal TS and a plurality of row output signals received by a detection circuit according to example embodiments.

[0076] Figure 5 and Figure 6 1 is a timing chart showing that the counter circuit 131 counts the cycles of the clock signal CLK within a time interval and the difference circuit 142 generates a difference value by using the count result value.

[0077] refer to Figure 5 and Figure 6 , it is assumed that the first row output signal RO_1 , the second row output signal RO_2 , and the fourth row output signal RO_4 are row output signals of rows without defects, and the third row output signal RO_3 is a row output signal of a defective row.

[0078] refer to Figure 5 At a first time t1, the first drive signal TS may transition to a logic high level. At a second time t2, the first row output signal RO_1 may transition to a logic high level. At a third time t3, the second row output signal RO_2 may transition to a logic high level. At a fourth time t4, the fourth row output signal RO_4 may transition to a logic high level. At a fifth time t5, the third row output signal RO_3 may transition to a logic high level. Here, the transitions of the first row output signal RO_1 to the fourth row output signal RO_4 to a logic high level may indicate that the first to fourth rows may be selected.

[0079] Reference together Figure 2 and Figure 5The counter circuit 131 may count cycles of the clock signal CLK during a time interval in which the first row output signal RO_1 is delayed relative to the first drive signal TS. For example, the time interval may be from a first time t1 to a second time t2, and the counter circuit 131 may generate and output a first count result value CNT_1. The counter circuit 131 may count cycles of the clock signal CLK during a time interval in which the second row output signal RO_2 is delayed relative to the first drive signal TS. For example, the time interval may be from a first time t1 to a third time t3, and the counter circuit 131 may generate and output a second count result value CNT_2. The counter circuit 131 may count cycles of the clock signal CLK during a time interval in which the third row output signal RO_3 is delayed relative to the first drive signal TS. For example, the time interval may be from a first time t1 to a fifth time t5, and the counter circuit 131 may generate and output a third count result value CNT_3. The counter circuit 131 may count cycles of the clock signal CLK during a time interval in which the fourth row output signal RO_4 is delayed relative to the first drive signal TS. For example, the time interval may be from the first time t1 to the fourth time t4 , and the counter circuit 131 may generate and output the fourth counting result value CNT_4 .

[0080] Reference together Figure 2 and Figure 5 The differential circuit 142 may generate and output a second difference value DELTA_2, which is the difference between the second count result value CNT_2 and the first count result value CNT_1. For example, the second difference value DELTA_2 may be a value obtained by subtracting the first count result value CNT_1 from the second count result value CNT_2. The differential circuit 142 may generate and output a third difference value DELTA_3, which is the difference between the third count result value CNT_3 and the second count result value CNT_2. For example, the third difference value DELTA_3 may be a value obtained by subtracting the second count result value CNT_2 from the third count result value CNT_3. The differential circuit 142 may generate and output a fourth difference value DELTA_4, which is the difference between the fourth count result value CNT_4 and the third count result value CNT_3. For example, the fourth difference value DELTA_4 may be a value obtained by subtracting the third counting result value CNT_3 from the fourth counting result value CNT_4.

[0081] The comparison circuit 151 may compare the second difference value DELTA_2 with a reference value EXP.

[0082] For example, when the second difference DELTA_2 is less than the reference value EXP, the comparison circuit 151 may output a result value corresponding to a pass. The comparison circuit 151 may compare the third difference DELTA_3 with the reference value EXP. When the third difference DELTA_3 is greater than the reference value EXP, the comparison circuit 151 may output a result value corresponding to a fail. The comparison circuit 151 may compare the fourth difference DELTA_4 with the reference value EXP. When the fourth difference DELTA_4 is less than the reference value EXP, the comparison circuit 151 may output a result value corresponding to a pass.

[0083] The image sensor including the detection circuit 70 according to example embodiments may generate a third count result value CNT_3 by counting cycles of the clock signal CLK during a time interval in which the selected third row output signal RO_3 is delayed compared to the first drive signal TS, and generate a third difference value DELTA_3 between the second count result value CNT_2 and the third count result value CNT_3. The image sensor including the detection circuit 70 according to example embodiments may determine and detect whether the selected row has a fault by comparing the third difference value DELTA_3 with a reference value EXP.

[0084] refer to Figure 6 , the first driving signal TS may be converted from a logic low level to a logic high level in the first period P1 and then repeatedly converted from a logic low level to a logic high level in the second period P2, the third period P3, and the fourth period P4.

[0085] Reference together Figure 2 and Figure 6 During the first period P1, the first drive signal TS and the first row output signal RO_1 may transition from a logic low level to a logic high level. The counter circuit 131 may count cycles of the clock signal CLK during the time interval in which the first row output signal RO_1 is delayed relative to the first drive signal TS. The counter circuit 131 may output a first count result value CNT_1. The first count result value CNT_1 may be 7.

[0086] During the second period P2, the first drive signal TS and the second row output signal RO_2 may be switched from a logic low level to a logic high level. The counter circuit 131 may count the cycles of the clock signal CLK during the time interval in which the second row output signal RO_2 is delayed relative to the first drive signal TS. The counter circuit 131 may output a second count result value CNT_2. The second count result value CNT_2 may be 6. The differential circuit 142 may generate and output a second difference value DELTA_2 by subtracting the first count result value CNT_1 from the second count result value CNT_2. The second difference value DELTA_2 may be The comparison circuit 151 may compare the second difference value DELTA_2 with the reference value EXP. When the reference value EXP is 2, since the second difference value DELTA_2 is smaller than the reference value EXP, the comparison circuit 151 may output a result value corresponding to a pass.

[0087] During the third period P3, the first drive signal TS and the third row output signal RO_3 may transition from a logic low level to a logic high level. The counter circuit 131 may count cycles of the clock signal CLK during the time interval in which the third row output signal RO_3 is delayed relative to the first drive signal TS. The counter circuit 131 may output a third count result value CNT_3. The third count result value CNT_3 may be 10. The difference circuit 142 may generate and output a third difference value DELTA_3 by subtracting the second count result value CNT_2 from the third count result value CNT_3. The third difference value DELTA_3 may be 4. The comparison circuit 151 may compare the third difference value DELTA_3 with a reference value EXP. When the reference value EXP is 2, because the third difference value DELTA_3 is greater than the reference value EXP, the comparison circuit 151 may output a result value corresponding to a failure.

[0088] During a fourth period P4, the first drive signal TS and the fourth row output signal RO_4 may transition from a logic low level to a logic high level. The counter circuit 131 may count cycles of the clock signal CLK during a time interval in which the fourth row output signal RO_4 is delayed relative to the first drive signal TS. The counter circuit 131 may output a fourth count result value CNT_4. The fourth count result value CNT_4 may be 4. The difference circuit 142 may generate and output a fourth difference value DELTA_4 by subtracting the third count result value CNT_3 from the fourth count result value CNT_4. The fourth difference value DELTA_4 may be 6. The comparison circuit 151 may compare the fourth difference value DELTA_4 with a reference value EXP. When the fourth difference value DELTA_4 is greater than the reference value EXP, the comparison circuit 151 may output a result value corresponding to a fail. When the fourth difference value DELTA_4 is less than the reference value EXP, the comparison circuit 151 may output a result value corresponding to a pass.

[0089] Figure 7 and Figure 8 is a diagram illustrating a method of operating the detection circuit 70 of a selected row according to example embodiments.

[0090] Figures 5 to 7is a diagram illustrating the operation of detection circuit 70 when the first row is selected. Counter circuit 131 may receive first drive signal TS from timing controller 60, and multiplexer 121 may receive multiple row output signals RO_1 to RO_N to select and output first row output signal RO_1. Counter circuit 131 may receive first drive signal TS and first row output signal RO_1 and output a first count result value CNT_1. First count result value CNT_1 may be a value obtained by counting cycles of clock signal CLK during a time interval in which first row output signal RO_1 is delayed relative to first drive signal TS.

[0091] Figure 5 、 Figure 6 and Figure 8 is a diagram illustrating a method for operating detection circuit 70 when the second row is selected. Multiplexer 121 may select and output the second row output signal RO_2. Counter circuit 131 may receive first drive signal TS and second row output signal RO_2 and output a second count result value CNT_2. Second count result value CNT_2 may be a value obtained by counting cycles of clock signal CLK during a time interval in which second row output signal RO_2 is delayed relative to first drive signal TS. Second count result value CNT_2 may be provided to register 141 and difference circuit 142. Register 141 may provide first count result value CNT_1 to difference circuit 142. Difference circuit 142 may generate and output a second difference value DELTA_2 by subtracting first count result value CNT_1 from second count result value CNT_2. Comparison circuit 151 may compare second difference value DELTA_2 with reference value EXP. When the second difference value DELTA_2 is less than the reference value EXP, the comparison circuit 151 may output a result value PASS corresponding to a pass. When the second difference value DELTA_2 is greater than the reference value EXP, the comparison circuit 151 may output a result value corresponding to a fail.

[0092] Figure 9 is a flowchart illustrating a method of operating an image sensor according to example embodiments.

[0093] refer to Figure 9 , the timing controller 60 can provide a first driving signal TS (S110). For example, referring to Figure 1 and Figure 2 , the counter circuit 131 may receive the first driving signal TS from the timing controller 60 .

[0094] The row output signal selection block 120 may receive a plurality of row output signals RO_1 to RO_N (S120). Figure 1 and Figure 2, the multiplexer 121 may receive a plurality of row output signals RO_1 to RO_N from the dummy area DA.

[0095] The row output signal selection block 120 may select the Mth row output signal RO_M from among the plurality of row output signals RO_1 to RO_N (S130). Figure 2 , the multiplexer 121 may receive the plurality of row output signals RO_1 to RO_N and select the M-th row output signal RO_M as one of the plurality of row output signals RO_1 to RO_N.

[0096] The counter block 130 may generate an Mth counting result value CNT_M which is a time interval by which the Mth row output signal RO_M is delayed compared to the first driving signal TS (S140). Figure 2 The counter circuit 131 may receive the M-th row output signal RO_M and the first driving signal TS, and generate and output the M-th counting result value CNT_M as a time interval by which the M-th row output signal RO_M is delayed based on the first driving signal TS.

[0097] The difference block 140 may generate an Mth difference value DELTA_M by calculating the difference between the Mth count result value CNT_M and the M-1th count result value CNT_(M-1) ( S150 ). Figure 2 , the register 141 can provide the M-1th count result value CNT_(M-1) to the differential circuit 142, and the differential circuit 142 can generate the Mth difference value DELTA_M by subtracting the M-1th count result value CNT_(M-1) from the Mth count result value CNT_M.

[0098] The comparison block 150 may compare the Mth difference value DELTA_M with a reference value EXP (S160). Figure 2 , the comparison circuit 151 may receive a reference value EXP from the outside and receive the Mth count result value CNT_M from the difference circuit 142. When the Mth difference value DELTA_M is greater than the reference value EXP, the comparison circuit 151 may generate and output a result value corresponding to a fail (S170), and when the Mth difference value DELTA_M is less than the reference value EXP, it may output a result value corresponding to a pass (S180). When the comparison circuit 151 outputs a result value corresponding to a fail, the timing controller 60 may output an error message to notify the user.

[0099] Figure 10 is a circuit diagram of a pixel PXa included in an image sensor according to example embodiments. Figure 10 The pixel PXa shown represents Figure 1 An example of one of the pixels PX included in the pixel array 20.

[0100] refer to Figure 10 The pixel PXa may include multiple photodiodes and multiple transistors, for example, a first photodiode PD1, a second photodiode PD2, a first transfer transistor LTX, a second transfer transistor STX, a reset transistor RX, a selection transistor SX, a first switch SW1, a second switch SW2, a third switch SW3, a conversion gain transistor CGX, and a capacitor cap.

[0101] The first photodiode PD1 can be a photodiode with a larger light-receiving area, and the second photodiode PD2 can be a photodiode with a smaller light-receiving area than the first photodiode PD1. The larger the light-receiving area, the greater the exposure to incident light. Therefore, the first photodiode PD1 with a larger light-receiving area can be used in a dark environment.

[0102] The first photodiode PD1 and the second photodiode PD2 can convert externally incident light into an electrical signal. The photodiode generates charge according to the light intensity. The amount of charge generated by the first photodiode PD1 and the second photodiode PD2 can vary depending on the image capture environment (low illumination or high illumination).

[0103] The driving transistor DX may operate as a source follower and output a voltage corresponding to a photocharge packet accumulated in the first floating diffusion node FD1 as an output voltage to the column line CL through the selection transistor SX.

[0104] The selection transistor SX can select a pixel to output an output voltage. The selection transistor SX can be turned on in response to a selection control signal SEL having an activation level applied to a gate terminal of the selection transistor SX, and output the output voltage (or current) output from the drive transistor DX to the column line CL.

[0105] A capacitor (eg, a parasitic capacitor) may be formed in each of the floating diffusion nodes FD1, FD2, and FD3. The capacitor cap may be a passive device having a fixed or variable capacitance.

[0106] One end of the first switch SW1 may be connected to the third floating diffusion node FD3, and the other end thereof may be connected to the second floating diffusion node FD2. The first switch SW1 may be turned on in response to a first switching signal SS1 applied to a gate of the first switch SW1. The first switching signal SS1 may be a first switching signal from a timing controller ( Figure 1 One of the driving signals provided by 60).

[0107] One end of the second switch SW2 may be connected to the capacitor cap, and the other end thereof may be connected to one end of the reset transistor RX. The second switch SW2 may be turned on in response to a second switching signal SS2 applied to a gate of the second switch SW2. The second switching signal SS2 may be a signal from a timing controller ( Figure 1 One of the driving signals provided by 60).

[0108] One end of the third switch SW3 may be connected to the third floating diffusion node FD3, and the other end thereof may be connected to one end of the capacitor cap. The third switch SW3 may be turned on in response to a third switching signal SS3 applied to the gate of the third switch SW3. The third switching signal SS3 may be a signal from the timing controller ( Figure 1 One of the driving signals provided by 60).

[0109] The capacitor cap and the driving transistor DX may receive a power supply voltage VDD.

[0110] Figure 11 is a circuit diagram illustrating a dummy area DA of a pixel array according to example embodiments. Figure 11 The dummy area DA shown may correspond to Figure 1 The dummy area DA is shown.

[0111] refer to Figure 10 and Figure 11 The dummy area DA may receive a first drive signal LTS. For example, the first drive signal LTS may be a transmission control signal LTST of the pixel PX. Furthermore, the dummy area DA may receive a second drive signal RS and a third drive signal SEL. For example, the second drive signal RS may be a reset control signal RS of the pixel PX, and the third drive signal SEL may be a selection control signal SEL.

[0112] refer to Figure 11 The dummy area DA can output a first row output signal RO_1, a second row output signal RO_2, and an N-th row output signal RO_N based on the first drive signal LTS. In an example embodiment, a configuration and method are shown in which the dummy area DA counts cycles of the clock signal CLK during a time interval in which the first row output signal RO_1, the second row output signal RO_2, and the N-th row output signal RO_N are delayed based on the first drive signal LTS.

[0113] Figure 11 The illustrated dummy area DA may include two or more N-type transistors connected in series, but example embodiments are not limited thereto.

[0114] The first row R1 of the dummy area DA may include a first reset transistor RX1 to which the second drive signal RS is applied and a first select transistor SX11 to which the third drive signal SEL is applied, and may include a first pass transistor LTX1 to which the first drive signal LTS is applied and a second select transistor SX12 to which the third drive signal SEL is applied. The first row R1 of the dummy area DA may output a first row output signal RO_1 based on the first drive signal LTS.

[0115] The second row R2 of the dummy area DA may include a first reset transistor RX2 to which the second drive signal RS is applied and a first select transistor SX21 to which the third drive signal SEL is applied, and may include a first pass transistor LTX2 to which the first drive signal LTS is applied and a second select transistor SX22 to which the third drive signal SEL is applied. The second row R2 of the dummy area DA may output a second row output signal RO_2 based on the first drive signal LTS.

[0116] The Nth row Rn of the dummy area DA may include a first reset transistor RXn to which the second drive signal RS is applied, a first selection transistor SXn1 to which the third drive signal SEL is applied, and may include a first pass transistor LTXn to which the first drive signal LTS is applied, and a second selection transistor SXn2 to which the third drive signal SEL is applied. The Nth row Rn of the dummy area DA may output an Nth row output signal RO_N based on the first drive signal LTS.

[0117] The dummy area DA may be connected to the detection circuit 70 via column lines CL, which may include a first column line CL1 and a second column line CL2. The dummy area DA may output a first row output signal RO_1, a second row output signal RO_2, and an N-th row output signal RO_N to the second column line CL2 based on the first drive signal LTS, and provide the first row output signal RO_1, the second row output signal RO_2, and the N-th row output signal RO_N to the detection circuit 70. The detection circuit 70 may receive the first row output signal RO_1, the second row output signal RO_2, and the N-th row output signal RO_N via the same second column line CL2.

[0118] Figure 12 and Figure 13 is a circuit diagram of pixels PXb and PXc included in an image sensor according to example embodiments. Figure 12 and Figure 13 The pixels PXb and PXc represent Figure 1 An example of one of the pixels PX included in the pixel array 20.

[0119] refer to Figure 12, pixel PXb may include a photodiode PD as a light sensing device, and include a transfer transistor TX, a gate transistor GX, a reset transistor RX, a drive transistor DX, and a select transistor SX as a read circuit. That is, pixel PXb may have a 5-transistor structure. Gate transistor GX may selectively apply a transfer control signal TS to transfer transistor TX in response to a select signal SEL. At this time, three drive signals, including the transfer control signal TS, the second drive signal RS, and the select signal SEL, may be applied to pixel PXb.

[0120] refer to Figure 13 Pixel PXc can include a photodiode PD as a light sensing element, and a phototransistor PTr (or photogate), a transfer transistor TX, a reset transistor RX, a drive transistor DX, and a select transistor SX as a readout circuit. That is, pixel PXc can have a five-transistor structure. Alternatively, pixel PXc can have a six-transistor structure that also includes a gate transistor GX or a bias transistor.

[0121] The phototransistor PTr can be turned on / off in response to a photogate signal PS applied to the gate of the phototransistor PTr. When the phototransistor PTr is in the on state, the photodiode PD can detect incident light to generate photocharge. On the other hand, when the phototransistor PTr is in the off state, the photodiode PD may not detect incident light. At this time, four drive signals including the transmission control signal TS, the second drive signal RS, the photogate signal PS, and the select signal SEL can be applied to the pixel PXc.

[0122] Figure 14 is a diagram illustrating a stacked structure of an image sensor 1 according to an example embodiment.

[0123] refer to Figure 14 The image sensor 1 may include a first semiconductor layer L1 and a second semiconductor layer L2. The first semiconductor layer L1 may be stacked relative to the second semiconductor layer L2 in a vertical direction (e.g., Z). Specifically, the second semiconductor layer L2 may be disposed below the first semiconductor layer L1 in the vertical direction (Z). The first direction (X) and the second direction (Y) may be perpendicular to each other and parallel to the surfaces of the semiconductor layers.

[0124] The first direction (X) may be formed such that positions of pads on the lower surface of the first semiconductor layer L1 match positions of pads on the upper surface of the second semiconductor layer L2 , and the first semiconductor layer L1 may be electrically connected to the second semiconductor layer L2 by bonding the pads.

[0125] Reference together Figure 1 and Figure 14In an example embodiment, the pixel array 20 may be formed in the first semiconductor layer L1. For example, the pixel area PA and the dummy area DA of the pixel array 20, including the plurality of pixels PX, may be formed in the first semiconductor layer L1. Furthermore, the first semiconductor layer L1 may include a sensing area SA in which the plurality of pixels PX are disposed and a pad area PA1 surrounding the periphery of the sensing area SA. A plurality of upper pads PAD are disposed on the pad area PA1 and may be connected to devices disposed in the second semiconductor layer L2 through vias or the like.

[0126] The second semiconductor layer L2 may include a circuit region LC provided with devices for driving the plurality of pixels PX and a pad region PA2 surrounding the periphery of the circuit region LC, and the pixel array ( Figure 1 Peripheral circuits (e.g., row driver 30, ADC circuit 40, column driver 50, timing controller 60, and detection circuit 70) of the first semiconductor layer L2 (e.g., the second semiconductor layer L2) can be formed in the circuit region LC. For example, the second semiconductor layer L2 can include a storage region and a dummy region. A memory device (e.g., a dynamic random access memory (DRAM) device or a static random access memory (SRAM) device) can be provided in the storage region. However, the memory device provided in the storage region is not limited to a DRAM device or an SRAM device. The dummy region can be used to support the first semiconductor layer L1 rather than to store data.

[0127] In example embodiments, the dummy region of the pixel array 20 may be formed in the first semiconductor layer L1, and the detection circuit 70 may be formed in the second semiconductor layer L2, thereby minimizing the size of the image sensor 1 due to contact portions connected between the first and second semiconductor layers L1 and L2.

[0128] Figure 15 is a block diagram schematically illustrating a computer system 2000 including an image sensor 2600 according to example embodiments.

[0129] refer to Figure 15 , the computer system 2000 may include a processor 2100, a memory 2200, an input / output (I / O) device 2300, a power supply 2400, a storage device 2500, an image sensor 2600, and a system bus 2700. The processor 2100, the memory 2200, the I / O device 2300, the power supply 2400, the storage device 2500, and the image sensor 2600 may communicate with each other via the system bus 2700.

[0130] The processor 2100 may be implemented as a microprocessor, a central processing unit (CPU), any other type of control circuit (application specific integrated circuit (ASIC)), an application processor (AP), or the like.

[0131] The memory 2200 may be implemented as a volatile memory and / or a nonvolatile memory.

[0132] The I / O device 2300 may include an input interface (eg, a keyboard, a keypad, a mouse, etc.) and an output interface (eg, a printer or a display).

[0133] The power supply 2400 may supply an operating voltage required for the operation of the computer system 2000 .

[0134] The storage device 2500 may include a solid state drive (SSD), a hard disk drive (HDD), a CD-ROM, and the like.

[0135] Image sensor 2600 can be used with Figure 1 The image sensor 2600 is the same as the image sensor 10 shown in FIG. The image sensor 2600 can count cycles of the clock signal CLK during a time interval in which the output signal of the selected M-th row is delayed compared to the driving signal, generate a difference between a previous count result value and the count result value, compare the difference with a reference value, and determine and detect whether the selected row has a fault.

[0136] Figure 16 is a block diagram of an electronic device including a multi-camera module. Figure 17 yes Figure 16 Detailed block diagram of a multi-camera module in an electronic device.

[0137] refer to Figure 16 , the electronic device 1000 may include a camera module group 1100 , an application processor 1200 , a power management integrated circuit (PMIC) 1300 , and an external memory 1400 .

[0138] Camera module group 1100 may include a plurality of camera modules 1100a, 1100b, and 1100c. Although the accompanying drawings illustrate an example in which three camera modules 1100a, 1100b, and 1100c are provided, example embodiments are not limited thereto. In some example embodiments, camera module group 1100 may be modified to include only two camera modules. Furthermore, in some example embodiments, camera module group 1100 may be modified to include k (k is a natural number of 4 or greater) camera modules.

[0139] In the following, reference is made to Figure 17 A detailed configuration of the camera module 1100 b is described in detail, but the description provided below may also be applied to the other camera modules 1100 a and 1100 c .

[0140] refer to Figure 17, the camera module 1100 b may include a prism 1105 , an optical path folding element (OPFE) 1110 , an actuator 1130 , an image sensing device 1140 , and a storage device 1150 .

[0141] The prism 1105 may include a reflective surface 1107 of a light-reflective material and may deform a path of light L incident from the outside.

[0142] In some example embodiments, the prism 1105 can change the path of light L incident in a first direction (X direction) to a second direction (Y direction) perpendicular to the first direction (X direction). Furthermore, the prism 1105 can rotate the reflective surface 1107 having a light-reflecting material around the central axis 1106 in direction A or direction B, thereby changing the path of light L incident in the first direction (X direction) to a second direction (Y direction) perpendicular to the first direction (X direction). The OPFE 1110 can also move in a third direction (Z direction) perpendicular to the first direction (X direction) and the second direction (Y direction).

[0143] In some example embodiments, as shown in the drawings, the maximum rotation angle of the prism 1105 in the direction A is 15° or less in the positive A direction and greater than 15° in the negative A direction, but example embodiments are not limited thereto.

[0144] In some example embodiments, the prism 1105 may be moved by an angle of about 20°, or between 10° and 20°, or between 15° and 20°, in the positive B direction or the negative B direction. Here, the movement angle is the same in the positive B direction or the negative B direction, or may be similar within a range of about 1°.

[0145] In some example embodiments, the prism 1105 may move the reflective surface 1107 of the light reflective material in a third direction (eg, a Z direction) parallel to the direction in which the central axis 1106 extends.

[0146] OPFE 1110 may include, for example, optical lenses formed into m groups (where m is a natural number). The m lenses may be movable in the second direction (Y direction), thereby varying the optical zoom ratio of camera module 1100b. For example, when the basic optical zoom ratio of camera module 1100b is Z and the m optical lenses included in OPFE 1110 are moved, the optical zoom ratio of camera module 1100b may be varied to 3Z, 5Z, 10Z, or greater.

[0147] The actuator 1130 can move the OPFE 1110 (hereinafter referred to as the optical lens) to a specific position. For example, the actuator 1130 can adjust the position of the optical lens so that the image sensor 1142 can be located at the focal length of the optical lens for precise sensing operations.

[0148] The image sensing device 1140 may include an image sensor 1142, a control logic 1144, and a memory 1146. The image sensor 1142 may sense an image of a sensing target by using light L provided through an optical lens. Figures 2 to 16 The described pixel and pixel array can be applied to image sensor 1142. A pixel can include multiple sub-pixels (e.g., four sub-pixels), each including multiple photoelectric conversion devices and multiple floating diffusion regions. The multiple floating diffusion regions of the multiple sub-pixels can be electrically connected to each other via wiring. This can improve the sensitivity of the multiple sub-pixels. Consequently, the resolution and image quality of image sensor 1142 can be improved.

[0149] The control logic 1144 may control the overall operation of the camera module 1100b. For example, the control logic 1144 may control the operation of the camera module 1100b according to a control signal provided through the control signal line CSLb.

[0150] The memory 1146 may store information necessary for the operation of the camera module 1100b (e.g., calibration data 1147). The calibration data 1147 may include information necessary for the camera module 1100b to generate image data using externally provided light L. The calibration data 1147 may include, for example, the aforementioned information regarding the degree of rotation, information regarding the focal length, information regarding the optical axis, and the like. If the camera module 1100b is implemented as a multi-state camera in which the focal length varies depending on the position of the optical lens, the calibration data 1147 may include information regarding the focal length value of the optical lens depending on its position (or state) and autofocus.

[0151] The storage device 1150 may store image data sensed by the image sensor 1142. The storage device 1150 may be provided outside the image sensing device 1140, or may be implemented in a form of being stacked with a sensor chip constituting the image sensing device 1140.

[0152] In some example embodiments, the storage device 1150 may be implemented as an electrically erasable programmable read-only memory (EEPROM), but example embodiments are not limited thereto. In some example embodiments, the image sensor 1142 is configured as a pixel array, and the control logic 1144 may include an analog-to-digital converter and an image signal processor that processes a sensed image.

[0153] Reference together Figure 16 and Figure 17 In some example embodiments, each of the plurality of camera modules 1100a, 1100b, and 1100c may include an actuator 1130. Therefore, each of the plurality of camera modules 1100a, 1100b, and 1100c may include calibration data 1147 that is the same as or different from one another depending on the operation of the actuator 1130 included therein.

[0154] In some example embodiments, one of the multiple camera modules 1100a, 1100b and 1100c (e.g., 1100b) may be a folded lens type camera module including the above-mentioned prism 1105 and OPFE 1110, and the other camera modules (e.g., 1100a and 1100c) may be vertical type camera modules not including the prism 1105 and OPFE 1110, but example embodiments are not limited thereto.

[0155] One of the plurality of camera modules 1100a, 1100b, and 1100c (eg, 1100c) may include Figure 1 An image sensor 10 is shown.

[0156] The image sensor may include a detection circuit, and the detection circuit may generate a count result value by counting cycles of a clock signal CLK within a time interval in which an output signal of the selected Mth row is delayed compared to a driving signal, generate a difference between a previous count result value and the count result value, compare the difference with a reference value, and determine and detect whether the selected Mth row is defective.

[0157] In some example embodiments, at least two camera modules (e.g., 1100a and 1100b) among the plurality of camera modules 1100a, 1100b, and 1100c may have different fields of view (different viewing angles). In this case, for example, the optical lenses of at least two camera modules (e.g., 1100a and 1100b) among the plurality of camera modules 1100a, 1100b, and 1100c may be different from each other, but example embodiments are not limited thereto.

[0158] Furthermore, in some example embodiments, the plurality of camera modules 1100a, 1100b, and 1100c may have different fields of view. For example, camera module 1100a may be an ultra-wide-angle camera, camera module 1100b may be a wide-angle camera, and camera module 1100c may be a telephoto camera, but example embodiments are not limited thereto. In this case, the optical lenses included in the plurality of camera modules 1100a, 1100b, and 1100c may be different from each other, but example embodiments are not limited thereto.

[0159] In some example embodiments, each of the plurality of camera modules 1100a, 1100b, and 1100c may be arranged to be physically separated from each other. That is, the plurality of camera modules 1100a, 1100b, and 1100c do not divide and use the sensing area of ​​one image sensor 1142, and an independent image sensor 1142 may be provided inside each of the plurality of camera modules 1100a, 1100b, and 1100c.

[0160] Return Reference Figure 16 , the application processor 1200 may include an image processing device 1210, a memory controller 1220, and an internal memory 1230. The application processor 1200 may be implemented separately from the plurality of camera modules 1100a, 1100b, and 1100c. For example, the application processor 1200 and the plurality of camera modules 1100a, 1100b, and 1100c may be implemented separately as separate semiconductor chips.

[0161] The image processing device 1210 may include a plurality of sub-image processors 1212 a , 1212 b , 1212 c , an image generator 1214 , and a camera module controller 1216 .

[0162] The image processing device 1210 may include a plurality of sub-image processors 1212 a , 1212 b , and 1212 c corresponding to the number of camera modules 1100 a , 1100 b , and 1100 c , respectively.

[0163] Image data generated by camera modules 1100a, 1100b, and 1100c may be provided to corresponding sub-image processors 1212a, 1212b, and 1212c via separate image signal lines ISLa, ISLb, and ISLc, respectively. For example, image data generated by camera module 1100a may be provided to sub-image processor 1212a via image signal line ISLa, image data generated by camera module 1100b may be provided to sub-image processor 1212b via image signal line ISLb, and image data generated by camera module 1100c may be provided to sub-image processor 1212c via image signal line ISLc. Such image data transmission may be performed using, for example, a camera serial interface (CSI) based on the Mobile Industry Processor Interface (MIPI), but example embodiments are not limited thereto.

[0164] In some example embodiments, a single sub-image processor may be configured to correspond to multiple camera modules. For example, sub-image processor 1212a and sub-image processor 1212c may not be implemented separately as shown, but may be integrated into a single sub-image processor. Image data provided by camera modules 1100a and 1100c may be selected by a selection device (e.g., a multiplexer) and then provided to the integrated sub-image processor. In this case, sub-image processor 1212b may not be integrated and may receive image data from camera module 1100b.

[0165] In addition, in some example embodiments, the image data generated by the camera module 1100a may be provided to the sub-image processor 1212a via the image signal line ISLa, the image data generated by the camera module 1100b may be provided to the sub-image processor 1212b via the image signal line ISLb, and the image data generated by the camera module 1100c may be provided to the sub-image processor 1212c via the image signal line ISLc. Furthermore, the image data processed by the sub-image processor 1212b may be directly provided to the image generator 1214, but one of the image data processed by the sub-image processor 1212a and the image data processed by the sub-image processor 1212c may be selected by a selection device (e.g., a multiplexer) and then provided to the image generator 1214.

[0166] The sub-image processors 1212a, 1212b and 1212c can perform image processing (e.g., bad pixel correction and 3A adjustment (auto focus correction, auto white balance and auto exposure), noise reduction, sharpening, gamma control, re-mosaicing, etc.) on the image data provided from the camera modules 1100a, 1100b and 1100c, respectively.

[0167] In some example embodiments, re-mosaic signal processing may be performed by each of the camera modules 1100 a , 1100 b , and 1100 c , and then provided to the sub-image processors 1212 a , 1212 b , and 1212 c .

[0168] Image data processed by each of the sub-image processors 1212a, 1212b, and 1212c may be provided to the image generator 1214. The image generator 1214 may generate an output image by using the image data provided from each of the sub-image processors 1212a, 1212b, and 1212c according to image generation information or a mode signal.

[0169] Specifically, the image generator 1214 may generate an output image by combining at least some of the image data generated from the camera modules 1100a, 1100b, and 1100c having different fields of view according to the image generation information or the mode signal. Furthermore, the image generator 1214 may generate an output image by selecting one of the image data generated from the camera modules 1100a, 1100b, and 1100c having different fields of view according to the image generation information or the mode signal.

[0170] In some example embodiments, the image generation information may include a zoom signal or a zoom factor. Furthermore, in some example embodiments, the mode signal may be a signal based on a mode selected by a user, for example.

[0171] When the image generation information is a zoom signal (zoom factor) and camera modules 1100a, 1100b, and 1100c have different fields of view (angles of view), image generator 1214 may perform different operations depending on the type of zoom signal. For example, when the zoom signal is a first signal, image generator 1214 may generate an output image using image data output from sub-image processor 1212a, image data output from sub-image processor 1212b, and image data output from sub-image processor 1212c, respectively. When the zoom signal is a second signal different from the first signal, image generator 1214 may generate an output image using image data output from sub-image processor 1212a, image data output from sub-image processor 1212b, and image data output from sub-image processor 1212c, respectively. When the zoom signal is a third signal different from the first signal and the second signal, the image generator 1214 may not merge the image data, but may generate an output image by selecting one of the image data output from the sub-image processors 1212a, 1212b, and 1212c. However, example embodiments are not limited thereto, and the method of processing image data may be modified as needed.

[0172] In some example embodiments, the image processing apparatus 1210 may further include a selector that selects outputs of the sub-image processors 1212 a , 1212 b , and 1212 c and transmits the selected outputs to the image generator 1214 .

[0173] In this case, the selector may perform different operations according to the zoom signal or zoom factor. For example, when the zoom signal is the fourth signal (e.g., the zoom magnification is the first magnification), the selector may select one of the outputs of the sub-image processors 1212a, 1212b, and 1212c and transmit the selected output to the image generator 1214.

[0174] Furthermore, when the zoom signal is a fifth signal different from the fourth signal (for example, the zoom magnification is the second magnification), the selector may sequentially transmit p outputs (p is a natural number of 2 or greater) from among the outputs of the sub-image processors 1212a, 1212b, and 1212c to the image generator 1214. For example, the selector may sequentially transmit the outputs of the sub-image processor 1212b and the sub-image processor 1212c to the image generator 1214. Furthermore, the selector may sequentially transmit the outputs of the sub-image processor 1212a and the sub-image processor 1212b to the image generator 1214. The image generator 1214 may generate one output image by combining the p sequentially provided outputs.

[0175] Here, image processing (e.g., demosaicing, downsizing to a video / preview resolution size, gamma correction, high dynamic range (HDR) processing, etc.) may be performed in advance by the sub-image processors 1212a, 1212b, and 1212c, and then the processed image data may be transmitted to the image generator 1214. Therefore, even if the processed image data is supplied to the image generator 1214 through one signal line via the selector, the image merging operation of the image generator 1214 can be performed at high speed.

[0176] In some example embodiments, the image generator 1214 may receive a plurality of image data having different exposure times from at least one of the plurality of sub-image processors 1212a, 1212b, and 1212c and perform HDR processing on the plurality of image data to generate merged image data having an increased dynamic range.

[0177] The camera module controller 1216 may provide control signals to each of the camera modules 1100a, 1100b, and 1100c. The control signals generated by the camera module controller 1216 may be provided to the corresponding camera modules 1100a, 1100b, and 1100c through separate control signal lines CSLa, CSLb, and CSLc.

[0178] One of the plurality of camera modules 1100a, 1100b, and 1100c can be designated as a master camera (e.g., 1100b) based on image generation information including a zoom signal or a mode signal, and the remaining camera modules (e.g., 1100a and 1100c) can be designated as slave cameras. This information can be included in a control signal and provided to the corresponding camera modules 1100a, 1100b, and 1100c via separate control signal lines CSLa, CSLb, and CSLc.

[0179] The camera modules that operate as the master camera and the slave camera can be changed according to the zoom factor or the operation mode signal. For example, when the viewing angle of camera module 1100a is wider than that of camera module 1100b and the zoom factor indicates a low zoom ratio, camera module 1100b can operate as the master camera and camera module 1100a can operate as the slave camera. Conversely, when the zoom factor indicates a high zoom magnification, camera module 1100a can operate as the master camera and camera module 1100b can operate as the slave camera.

[0180] In some example embodiments, the control signal provided from the camera module controller 1216 to each of the camera modules 1100a, 1100b, and 1100c may include a synchronization enable signal. For example, when the camera module 1100b is a master camera and the camera modules 1100a and 1100c are slave cameras, the camera module controller 1216 may send the synchronization enable signal to the camera module 1100b. Upon receiving the synchronization enable signal, the camera module 1100b may generate a synchronization signal based on the synchronization enable signal and provide the generated synchronization signal to the camera modules 1100a and 1100c via the synchronization signal line SSL. The camera module 1100b and the camera modules 1100a and 1100c may synchronize with the synchronization signal and send image data to the application processor 1200.

[0181] In some example embodiments, the control signal provided from the camera module controller 1216 to the plurality of camera modules 1100a, 1100b, and 1100c may include mode information according to the mode signal. The plurality of camera modules 1100a, 1100b, and 1100c may operate in a first operating mode and a second operating mode related to the sensing speed based on the mode information.

[0182] In the first operating mode, the plurality of camera modules 1100a, 1100b, and 1100c may generate image signals at a first speed (e.g., generate image signals at a first frame rate), encode the image signals at a second speed faster than the first speed (e.g., encode image signals at a second frame rate greater than the first frame rate), and transmit the encoded image signals to the application processor 1200. Here, the second speed may be 30 times or less than the first speed.

[0183] Application processor 1200 may store the received image signal (i.e., the encoded image signal) in internal memory 1230 provided within application processor 1200 or in external memory 1400 provided outside application processor 1200. It may then read and decode the encoded signal from internal memory 1230 or external memory 1400, and may display image data generated based on the decoded image signal. For example, a corresponding sub-image processor among the multiple sub-image processors 1212a, 1212b, and 1212c of image processing device 1210 may perform decoding and may also perform image processing on the decoded image signal.

[0184] In the second operating mode, the plurality of camera modules 1100a, 1100b, and 1100c may generate image signals at a third speed slower than the first speed (e.g., generate image signals at a third frame rate lower than the first frame rate) and transmit the image signals to the application processor 1200. The image signals provided to the application processor 1200 may be unencoded signals. The application processor 1200 may perform image processing on the received image signals or store the image signals in the internal memory 1230 or the external memory 1400.

[0185] The PMIC 1300 may supply power (e.g., a source voltage) to each of the plurality of camera modules 1100a, 1100b, and 1100c. For example, under the control of the application processor 1200, the PMIC 1300 may supply a first power to the camera module 1100a via a power signal line PSLa, supply a second power to the camera module 1100b via a power signal line PSLb, and supply a third power to the camera module 1100c via a power signal line PSLc.

[0186] In response to the power control signal PCON from the application processor 1200, the PMIC 1300 can generate power corresponding to each of the multiple camera modules 1100a, 1100b, and 1100c, and can also adjust the power level. The power control signal PCON may include a power adjustment signal for each operating mode of the multiple camera modules 1100a, 1100b, and 1100c. For example, the operating mode may include a low power mode, and in this case, the power control signal PCON may include information related to the camera module operating in the low power mode and the set power level. The power levels provided to the multiple camera modules 1100a, 1100b, and 1100c can be the same as or different from each other. In addition, the power levels can be dynamically changed.

[0187] In some embodiments, according to example embodiments, Figure 1 、 Figure 2 、 Figure 7 、 Figure 8 and Figures 15 to 17 Each component represented by the illustrated blocks can be implemented as any number of hardware and / or firmware structures that perform the various functions described above. For example, at least one of these components may include various hardware components (e.g., memory, processor, logic circuit, lookup table, etc.) including digital circuits, programmable or non-programmable logic devices or arrays, application-specific integrated circuits (ASICs), transistors, capacitors, logic gates, or other circuits using direct circuit structures. These hardware components can be controlled by one or more microprocessors or other control devices to perform the various functions. In addition, at least one of these components may also include a processor, microprocessor, or the like, such as a central processing unit (CPU) to perform the various functions, or may be implemented by a processor, microprocessor, or the like, such as a central processing unit (CPU) to perform the various functions. The functional aspects of the example embodiments may be implemented as algorithms executed on one or more processors. Furthermore, the components, elements, modules, units, or processing steps represented by the blocks may utilize any number of related art techniques for electronic configuration, signal processing and / or control, data processing, and the like.

[0188] While aspects of the example embodiments have been particularly shown and described, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An image sensor, comprising: A pixel array comprising a pixel area and a dummy area adjacent to the pixel area and on the same plane as the pixel area, wherein the pixel area comprises pixels arranged in a plurality of rows; a row driver configured to sequentially output drive signals to the pixel array; a detection circuit configured to receive a plurality of row output signals generated based on the drive signal from the dummy region and receive the drive signal; as well as a timing controller configured to provide the driving signal to the row driver and provide the driving signal and a clock signal to the detection circuit, The detection circuit is further configured to: identify a difference between delay times corresponding to adjacent rows among the multiple rows, determine whether the multiple rows are defective by comparing the difference with a reference value, and output a result value indicating whether the multiple rows are defective.

2. The image sensor according to claim 1, wherein A second output signal among the plurality of row output signals is first switched from a logic low level to a logic high level within a delay time.

3. The image sensor according to claim 1, wherein The dummy area is disposed on a first side of the pixel area, and The row driver is arranged on a second side of the pixel area opposite to the first side.

4. The image sensor according to claim 1, wherein The plurality of rows include a first row and a second row, and Wherein, the detection circuit is configured as follows: selecting a second row output signal from among the plurality of row output signals, generating a second counting result value corresponding to the second row by counting a period of the clock signal corresponding to a delay time of the second row output signal based on the driving signal, generating a second difference between the second count result value and the first count result value corresponding to the first row, and Whether the second row is defective is determined by comparing the second difference value with the reference value.

5. The image sensor according to claim 4, wherein: The detection circuit comprises: a signal selection circuit configured to select the second row output signal from among the plurality of row output signals; a counter circuit configured to generate the second counting result value by counting cycles of the clock signal within a time interval of the second row output signal; a difference circuit configured to generate a second difference value, the second difference value being a difference value between the second count result value and the first count result value; and The comparison circuit is configured to output a result value according to a result of comparing the second difference value with the reference value.

6. The image sensor according to claim 5, wherein: The image sensor is configured to output a result value corresponding to a failure based on the second difference value being greater than the reference value.

7. The image sensor according to claim 5, wherein: The signal selection circuit includes a multiplexer, and The multiplexer is configured to receive the plurality of row output signals and select the second row output signal.

8. The image sensor according to claim 5, wherein: The counter circuit is configured to: receiving the clock signal, the driving signal and the second row output signal, and The second count result value is generated by counting a period of the clock signal corresponding to a time by which the second row output signal is delayed compared to the driving signal.

9. The image sensor according to claim 5, further comprising: a register configured to store the second count result value generated by the counter circuit, The differential circuit is configured to receive the second counting result value and the first counting result value output from the register, and generate the second difference value, which is an absolute value of a difference between the first counting result value and the second counting result value.

10. The image sensor according to claim 5, wherein The comparison circuit is further configured to: receive the second difference value and the reference value, and determine whether the second difference value is greater than the reference value, and The reference value is one of a value input from the outside and a value stored in the comparison circuit.

11. The image sensor according to claim 1, wherein: The pixel array is provided in the first semiconductor layer, and The row driver, the detection circuit and the timing controller are arranged in a second semiconductor layer below the first semiconductor layer.

12. An image sensor comprising: A pixel array includes a pixel area and a dummy area, wherein the pixel area includes a plurality of pixels; a row driver configured to output a driving signal to the pixel array; as well as a detection circuit configured to receive a plurality of row output signals from the dummy region and receive the drive signal and the clock signal, Wherein, the detection circuit includes: a signal selection circuit configured to select an Nth row output signal from among the plurality of row output signals; a counter circuit configured to generate an Nth count result value by counting cycles of the clock signal during a time interval of the Nth row output signal based on the driving signal; a difference circuit configured to generate an Nth difference value between the Nth count result value and the N-1th count result value; and a comparison circuit configured to detect a defect of the Nth row output signal by comparing the Nth difference value with a reference value, and The time interval includes a delay interval in which the N-th row output signal is delayed based on the driving signal.

13. The image sensor according to claim 12, wherein: In the pixel array, The pixel area and the dummy area are arranged on the same plane, The dummy area is arranged in the second direction of the pixel area, and The row driver is provided in a direction opposite to the second direction of the pixel area.

14. The image sensor according to claim 12, wherein: The time interval includes a delay interval, and the delay interval is a difference between the driving signal received by the detection circuit and the N-th row output signal.

15. The image sensor according to claim 12, wherein: The signal selection circuit includes a multiplexer, and The multiplexer is configured to receive the plurality of row output signals and select the Nth row output signal from among the plurality of row output signals.

16. The image sensor according to claim 12, wherein: The detection circuit further includes: a register configured to store the Nth count result value generated by the counter circuit, and The differential circuit is configured to receive the N-1th count result value output from the register and the Nth count result value generated by the counter circuit, and generate the Nth difference value, which is the absolute value of the difference between the N-1th count result value and the Nth count result value.

17. The image sensor according to claim 12, wherein: The comparison circuit is further configured to: receiving the Nth difference value and the reference value, comparing the Nth difference value with the reference value, Based on the Nth difference being less than the reference value, outputting a result value corresponding to a pass, and Based on the Nth difference value being greater than the reference value, a result value corresponding to a failure is output.

18. A method of operating an image sensor, the method comprising: receiving a driving signal; receiving a plurality of row output signals; selecting an Nth row output signal from among the plurality of row output signals; generating an Nth count result value by counting cycles of a clock signal during a delay time interval between the driving signal and the Nth row output signal; generating an Nth difference between the Nth counting result value and the N-1th counting result value; comparing the Nth difference value with a reference value; as well as Based on the Nth difference being greater than the reference value, it is detected that the Nth row output signal has a fault.

19. The method according to claim 18, wherein Generating the Nth difference value includes: Outputting the N-1th counting result value; and The N-1th counting result value is subtracted from the Nth counting result value.

20. The method according to claim 18, wherein Generating the Nth count result value includes counting cycles of the clock signal during a time interval between a rising edge of the driving signal and a rising edge of the Nth row output signal by using a counter circuit.

Images