Method for improving impedance precision of microstrip line of 2oz thick copper PCB

Abstract

The invention discloses a method for improving the impedance precision of a microstrip line of a 2oz thick copper PCB, and relates to the technical field of PCB manufacturing, and the method comprises the steps: 1, employing a three-core board laminated structure; 2, manufacturing an inner-layer circuit: carrying out whole-board exposure anti-corrosion treatment on the outer-layer copper foil of the core board positioned on the top layer and the outer-layer copper foil of the core board positioned on the bottom layer, and carrying out normal exposure and etching on the inner-layer copper foil of the three core boards; step 3, browning treatment; step 4, pressing; step 5, drilling and electroplating; step 6; and manufacturing an outer-layer circuit. The three-core-board laminated structure is adopted, the outer-layer copper foil of the laminated structure is derived from the core board adopting the 2oz copper foil, the dielectric thickness uniformity of the core board is relatively high, and the dielectric thickness fluctuation range between Layer1-Layer2 is only about 5%, so that the dielectric thickness fluctuation range of the microstrip line is reduced, the influence of the dielectric thickness on impedance is reduced, and the performance of the microstrip line is improved. And the tolerance of the outer-layer impedance line can be controlled in a range of + / -10%.

Description

Technical Field

[0001] The present invention relates to the technical field of PCB manufacturing, and in particular to a method for improving the impedance accuracy of a 2oz thick copper PCB microstrip line. Background Art

[0002] Because impedance consistency directly impacts signal integrity, the current market requirement for microstrip / stripline impedance fluctuations is to be within ±10% of the design value. Currently, for PCBs with impedance requirements, the copper thickness is typically ≤1oz. However, with market trends shifting to higher power and current-carrying PCBs, the existing ≤1oz copper thickness is no longer sufficient for these products. Consequently, designs are emerging where the copper thickness of the inner and outer layers of PCBs is increased to 2oz. However, customers prefer to maintain the same impedance tolerance to maintain good signal integrity.

[0003] Currently, a commonly used PCB stackup, such as a six-layer board, consists of two core boards, three layers of prepreg, and two layers of copper foil, laminated together under high-temperature vacuum pressure. In this stackup, the copper foil for the microstrip lines is attached to the prepreg. This stackup has a drawback: after the inner layers are fabricated, the distribution of the transmission lines on the inner substrate is uneven, resulting in local variations in residual copper content. This leads to variations in thickness at different locations on the finished PCB, as prepreg is used to fill gaps between the lines during the lamination process. Summary of the Invention

[0004] The purpose of the present invention is to provide a method for improving the impedance accuracy of 2oz thick copper PCB microstrip lines to address the above-mentioned deficiencies in the technology.

[0005] To achieve the above objectives, the present invention provides the following technical solution: a method for improving the impedance accuracy of a 2oz thick copper PCB microstrip line, comprising:

[0006] Step 1: Using a three-core laminate structure, wherein the core board on the top layer and the core board on the bottom layer both comprise an outer copper foil and an inner copper foil, the outer copper foil being a 2oz thick copper layer, and the core board in the middle comprises two inner copper foils;

[0007] Step 2: Inner layer circuit production:

[0008] The outer copper foil of the core board located on the top layer and the outer copper foil of the core board located on the bottom layer are subjected to full-board exposure and anti-etching treatment to retain their complete copper surfaces to form a microstrip line layer, and the inner copper foil of the three core boards are subjected to normal exposure and etching to form inner-layer circuits;

[0009] Step 3: Browning treatment: Browning the core board with the inner layer circuit to enhance the bonding strength between layers;

[0010] Step 4: Lamination: Alternately stack the three processed core boards and prepregs, and form a PCB substrate with a predetermined interlayer structure through a hot pressing process;

[0011] Step 5: Drilling and electroplating: mechanical drilling and chemical electroplating processes are performed on the laminated PCB substrate to form interlayer conductive through holes;

[0012] Step 6: outer layer circuit production, pattern transfer and etching are performed on the retained outer layer copper foil to form an outer layer microstrip circuit;

[0013] Step 7: Solder mask, surface treatment and shape processing, solder mask ink printing, surface immersion gold treatment and shape cutting are carried out in sequence to obtain the finished PCB.

[0014] Preferably, the outer copper foil of the core board located on the top layer corresponds to Layer 1 of the finished PCB, and the inner copper foil corresponds to Layer 2;

[0015] The two inner copper foils of the core board located in the middle correspond to Layer 3 and Layer 4 of the finished PCB respectively;

[0016] The inner copper foil of the core board located at the bottom layer corresponds to Layer 5 of the finished PCB, and the outer copper foil corresponds to Layer 6 of the finished PCB; the prepreg is filled in the dielectric layer between Layer 2-Layer 3 and Layer 4-Layer 5.

[0017] Preferably, in step 2, the whole-board exposure and anti-corrosion treatment adopts a dry film covering process with full-area coverage, and a solder mask photoresist is used simultaneously to achieve full-area protection of the outer copper surface.

[0018] Preferably, in step 4, after lamination, the dielectric layer between Layer 1 and Layer 2 is composed of the substrate of the core board located on the top layer, and its thickness fluctuation range is controlled within ±5% to achieve a microstrip line impedance tolerance less than ±10% of the design value.

[0019] Preferably, in step four, the dielectric constant of the semi-cured sheet matches the dielectric constant of the substrate of the core board, and after lamination, the thickness of the dielectric layer between Layer2-Layer3 and Layer4-Layer5 is filled with the semi-cured sheet, and the effect of its thickness fluctuation on the strip line impedance remains consistent with the conventional stacking structure.

[0020] Preferably, in step six, when transferring the pattern, a dry film is used on the retained 2oz outer copper foil for pattern transfer, and the amount of undercut is corrected by photolithography precision compensation.

[0021] Preferably, in step six, during etching, sulfuric acid-hydrogen peroxide etching solution is used, the line width tolerance is controlled to be ±10%, and the inclination angle of the trapezoidal cross section is ≤70° to reduce impedance fluctuation.

[0022] Preferably, in step seven, low Dk ink is used during the solder mask printing process to avoid interference of traditional ink on the impedance of the microstrip line.

[0023] Preferably, in step seven, the surface immersion gold treatment adopts a chemical nickel-gold process to form a nickel layer with a thickness of 2-5 μm and a gold layer with a thickness of 0.05-0.1 μm on the surface of the microstrip line.

[0024] In the above technical solution, the technical effects and advantages provided by the present invention are:

[0025] By adopting a three-core laminate structure, the outer copper foil of the laminate comes from the core board using 2oz copper foil. Because the dielectric thickness of the core board is relatively uniform, the dielectric thickness fluctuation between Layer 1 and Layer 2 is only about 5%, which reduces the fluctuation of the microstrip line dielectric thickness, thereby reducing the impact of the dielectric thickness on the impedance, and achieving the outer layer impedance line tolerance within the range of ±10%. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments described in the present invention. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0027] Figure 1 Schematic diagram of the method flow of the present invention;

[0028] Figure 2 It is a schematic diagram of the three-core board laminated structure of the present invention. DETAILED DESCRIPTION

[0029] In order to enable those skilled in the art to better understand the technical solution of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings.

[0030] The present invention provides Figures 1 to 2 A method for improving the impedance accuracy of a 2oz thick copper PCB microstrip line is shown, including:

[0031] Step 1: Using a three-core laminate structure, wherein the core board on the top layer and the core board on the bottom layer both comprise an outer copper foil and an inner copper foil, the outer copper foil being a 2oz thick copper layer, and the core board in the middle comprises two inner copper foils;

[0032] Step 2: Inner layer circuit production:

[0033] The outer copper foil of the core board located on the top layer and the outer copper foil of the core board located on the bottom layer are subjected to full-board exposure and anti-etching treatment to retain their complete copper surfaces to form a microstrip line layer, and the inner copper foil of the three core boards are subjected to normal exposure and etching to form inner-layer circuits;

[0034] Step 3: Browning treatment: Browning the core board with the inner layer circuit to enhance the bonding strength between layers;

[0035] Step 4: Lamination: Alternately stack the three processed core boards and prepregs, and form a PCB substrate with a predetermined interlayer structure through a hot pressing process;

[0036] Step 5: Drilling and electroplating: mechanical drilling and chemical electroplating processes are performed on the laminated PCB substrate to form interlayer conductive through holes;

[0037] Step 6: outer layer circuit production, pattern transfer and etching are performed on the retained outer layer copper foil to form an outer layer microstrip circuit;

[0038] Step 7: Solder mask, surface treatment and shape processing, solder mask ink printing, surface immersion gold treatment and shape cutting are carried out in sequence to obtain the finished PCB.

[0039] The outer copper foil of the core board located on the top layer corresponds to Layer 1 of the finished PCB, and the inner copper foil corresponds to Layer 2;

[0040] The two inner copper foils of the core board located in the middle correspond to Layer 3 and Layer 4 of the finished PCB respectively;

[0041] The inner copper foil of the core board located at the bottom layer corresponds to Layer 5 of the finished PCB, and the outer copper foil corresponds to Layer 6 of the finished PCB; the prepreg is filled in the dielectric layer between Layer 2-Layer 3 and Layer 4-Layer 5.

[0042] In the step 2, the whole-board exposure and anti-corrosion treatment adopts a dry film covering process with full-area coverage, and the solder mask photoresist is used simultaneously to achieve full-area protection of the outer copper surface.

[0043] In the step 4, after lamination, the dielectric layer between Layer 1 and Layer 2 is composed of the substrate of the core board located on the top layer, and the thickness fluctuation range is controlled within ±5% to achieve a microstrip line impedance tolerance of less than ±10% of the design value;

[0044] The dielectric constant of the prepreg matches the dielectric constant of the substrate of the core board, and after lamination, the thickness of the dielectric layer between Layer2-Layer3 and Layer4-Layer5 is filled with the prepreg, and the effect of its thickness fluctuation on the stripline impedance is consistent with that of the conventional stacking structure.

[0045] In step 6, when transferring the pattern, dry film is used on the retained 2oz outer copper foil to transfer the pattern, and the amount of undercut is corrected by photolithography accuracy compensation;

[0046] During etching, sulfuric acid-hydrogen peroxide etching solution is used to control the line width tolerance to ±10%, the trapezoidal cross-section inclination angle ≤70°, and reduce impedance fluctuations.

[0047] In step seven, low Dk ink is used during the solder mask printing process to avoid interference of traditional ink on the impedance of the microstrip line;

[0048] The surface immersion gold treatment adopts a chemical nickel-gold process to form a nickel layer with a thickness of 2-5 μm and a gold layer with a thickness of 0.05-0.1 μm on the surface of the microstrip line.

[0049] In the present invention, a three-core laminate structure is adopted, the outer copper foil and the inner copper foil of the top core board correspond to Layer 1 and Layer 2 of the PCB, the two inner copper foils of the middle core board correspond to Layer 3 and Layer 4 of the PCB, the inner copper foil and the outer copper foil of the bottom core board correspond to Layer 5 and Layer 6 of the PCB, and the prepreg fills Layer 2-Layer 3 and Layer 4-Layer 5;

[0050] The outer copper foil retains its complete copper surface to form the microstrip line layer, and the inner copper foil is exposed and etched to form the signal layer. The interlayer dielectric is alternately filled with core board substrate and prepreg to achieve a stable thickness of the impedance key layer;

[0051] The outer copper foil is exposed to anti-etching to preserve the copper surface, reducing the loss of copper thickness during the etching process. Solder resist is used to protect the copper surface to ensure the consistency of the initial thickness of the microstrip layer.

[0052] By matching the dielectric constants of the core substrate and prepreg, the impact of thickness fluctuations in the Layer 2-Layer 3 and Layer 4-Layer 5 dielectric layers on stripline impedance after lamination is consistent with that of traditional stack-up structures, while the thickness tolerance of the key microstrip layer, Layer 1-Layer 2, is compressed to ±5%.

[0053] During the pattern transfer stage, photolithography precision compensation is used to correct the side etching amount, and sulfuric acid-hydrogen peroxide etching solution is used to control the line width tolerance to ±10%, the trapezoidal cross-section inclination angle ≤70°, and reduce impedance fluctuations.

[0054] By adopting a three-core laminate structure, the outer copper foil of the laminate comes from the core board using 2oz copper foil. Because the dielectric thickness of the core board is relatively uniform, the dielectric thickness fluctuation between Layer 1 and Layer 2 is only about 5%. After simulation calculation, the impedance fluctuation caused by the change in dielectric thickness does not exceed 3%, so that the outer layer impedance line tolerance can be controlled within the range of ±10% of the design value; at the same time, the inner layer strip line laminate is just the interchange of the two dielectric positions of the core board and the prepreg. The impedance influencing factors do not change, and the tolerance control of the strip line is not affected.

[0055] The above description is merely illustrative of certain exemplary embodiments of the present invention. It goes without saying that those skilled in the art will be able to modify the described embodiments in various ways without departing from the spirit and scope of the present invention. Therefore, the above drawings and description are illustrative in nature and should not be construed as limiting the scope of protection of the claims.

Claims

1. A method for improving the impedance accuracy of a 2oz thick copper PCB microstrip line, characterized in that: include: Step 1: Using a three-core laminate structure, wherein the core board on the top layer and the core board on the bottom layer both comprise an outer copper foil and an inner copper foil, the outer copper foil being a 2oz thick copper layer, and the core board in the middle comprises two inner copper foils; Step 2: Inner layer circuit production: The outer copper foil of the core board located on the top layer and the outer copper foil of the core board located on the bottom layer are subjected to full-board exposure and anti-etching treatment to retain their complete copper surface to form a microstrip line layer, and the inner copper foil of the three core boards are subjected to normal exposure and etching to form inner-layer circuits; Step 3: Browning treatment: Browning the core board with the inner layer circuit to enhance the bonding strength between layers; Step 4: Lamination: Alternately stack the three processed core boards and prepregs, and form a PCB substrate with a predetermined interlayer structure through a hot pressing process; Step 5: Drilling and electroplating: mechanical drilling and chemical electroplating processes are performed on the laminated PCB substrate to form interlayer conductive through holes; Step 6: Fabrication of outer layer circuits: Pattern transfer and etching are performed on the retained outer layer copper foil to form outer layer microstrip circuits; Step 7: Solder mask, surface treatment and shape processing, solder mask ink printing, surface immersion gold treatment and shape cutting are carried out in sequence to obtain the finished PCB.

2. The method for improving the impedance accuracy of a 2oz thick copper PCB microstrip line according to claim 1, characterized in that: The outer copper foil of the core board located on the top layer corresponds to Layer 1 of the finished PCB, and the inner copper foil corresponds to Layer 2; The two inner copper foils of the core board located in the middle correspond to Layer 3 and Layer 4 of the finished PCB respectively; The inner copper foil of the core board located at the bottom layer corresponds to Layer 5 of the finished PCB, and the outer copper foil corresponds to Layer 6 of the finished PCB; the prepreg is filled in the dielectric layer between Layer 2-Layer 3 and Layer 4-Layer 5.

3. The method for improving the impedance accuracy of a 2oz thick copper PCB microstrip line according to claim 1, characterized in that: In the step 2, the whole-board exposure and anti-corrosion treatment adopts a dry film covering process with full-area coverage, and the solder mask photoresist is used simultaneously to achieve full-area protection of the outer copper surface.

4. The method for improving the impedance accuracy of a 2oz thick copper PCB microstrip line according to claim 2, characterized in that: In step 4, after lamination, the dielectric layer between Layer 1 and Layer 2 is composed of the substrate of the core board located on the top layer, and its thickness fluctuation range is controlled within ±5% to achieve a microstrip line impedance tolerance of less than ±10% of the design value.

5. The method for improving the impedance accuracy of a 2oz thick copper PCB microstrip line according to claim 4, characterized in that: In step 4, the dielectric constant of the semi-cured sheet matches the dielectric constant of the substrate of the core board, and after lamination, the thickness of the dielectric layer between Layer2-Layer3 and Layer4-Layer5 is filled with the semi-cured sheet, and the effect of its thickness fluctuation on the stripline impedance is consistent with that of the conventional stacking structure.

6. The method for improving the impedance accuracy of a 2oz thick copper PCB microstrip line according to claim 1, characterized in that: In step six, during pattern transfer, dry film is used on the retained 2oz outer copper foil for pattern transfer, and the amount of undercut is corrected by photolithography accuracy compensation.

7. The method for improving the impedance accuracy of a 2oz thick copper PCB microstrip line according to claim 1, characterized in that: In step six, during etching, sulfuric acid-hydrogen peroxide etching solution is used, the line width tolerance is controlled to be ±10%, and the trapezoidal cross-section inclination angle is ≤70°.

8. The method for improving the impedance accuracy of a 2oz thick copper PCB microstrip line according to claim 1, characterized in that: In the step seven, low Dk ink is used in the solder mask printing process.

9. The method for improving the impedance accuracy of a 2oz thick copper PCB microstrip line according to claim 1, characterized in that: In the step seven, the surface immersion gold treatment adopts a chemical nickel-gold process to form a nickel layer with a thickness of 2-5 μm and a gold layer with a thickness of 0.05-0.1 μm on the surface of the microstrip line.

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