Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

The embodiment of the invention provides a semiconductor device, a manufacturing method thereof and electronic equipment, and relates to the technical field of semiconductors. The semiconductor device comprises a reading transistor and a writing transistor which are sequentially stacked on one side of a substrate; the read transistor comprises a first gate electrode, a first gate insulating layer and a first semiconductor layer; the first gate electrode extends along a first direction perpendicular to the substrate, and the first gate electrode is electrically connected with the write transistor; the first gate insulating layer surrounds the periphery and the bottom of the first gate electrode; the first semiconductor layer is arranged on the periphery of the first gate insulating layer; the first semiconductor layer comprises a first source and drain electrode region, a first channel region and a second source and drain electrode region which are sequentially distributed in the direction away from the substrate; materials of the first source and drain region, the first channel region and the second source and drain region comprise silicon materials. According to the embodiment of the invention, the electrical performance of the semiconductor device can be improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art

[0002] Integrated circuit technology is currently developing towards increasing integration density and reducing component size. To minimize product costs, people hope to create as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor device designs and process optimizations to meet current product demands. Summary of the Invention

[0003] The present application provides a semiconductor device, a manufacturing method thereof, and an electronic device.

[0004] In a first aspect, an embodiment of the present application provides a semiconductor device, comprising:

[0005] a read transistor and a write transistor stacked sequentially on one side of the substrate;

[0006] The read transistor comprises:

[0007] a first gate electrode extending along a first direction perpendicular to the substrate, the first gate electrode being electrically connected to the write transistor;

[0008] a first gate insulating layer, disposed around the outer periphery of the first gate electrode;

[0009] A first semiconductor layer is arranged on the periphery of the first gate insulating layer; the first semiconductor layer includes a first source-drain region, a first channel region, and a second source-drain region distributed in sequence in a direction away from the substrate; the materials of the first source-drain region, the first channel region, and the second source-drain region all contain silicon material.

[0010] In a second aspect, an embodiment of the present application provides an electronic device, including: a semiconductor device as described above.

[0011] In a third aspect, an embodiment of the present application provides a method for manufacturing a semiconductor device, comprising:

[0012] growing a first initial semiconductor layer on a silicon-containing substrate using an epitaxial process;

[0013] The first initial semiconductor layer comprises a first initial source-drain region, a first initial channel region, and a second initial source-drain region, which are sequentially away from the substrate; the first initial source-drain region, the first initial channel region, and the second initial source-drain region are all made of silicon material;

[0014] forming a first hole penetrating the first initial semiconductor layer and exposing the substrate to obtain a first semiconductor layer, wherein the first semiconductor layer sequentially comprises a first source-drain region, a first channel region, and a second source-drain region in a direction away from the substrate;

[0015] sequentially depositing a first gate insulating layer and a first gate electrode of a read transistor in the first hole;

[0016] A write transistor electrically connected to the first gate electrode is formed on a side of the read transistor away from the substrate.

[0017] The beneficial technical effects brought about by the technical solutions provided in the embodiments of the present application include:

[0018] In the semiconductor device of the embodiment of the present application, the first source-drain region, the first channel region, and the second source-drain region of the read transistor are all made of silicon. That is, the read transistor is a silicon transistor. Compared to a read transistor whose channel region is made of a metal oxide semiconductor, silicon has higher mobility, thereby improving the read speed of the read transistor. Furthermore, a read transistor whose channel region is made of silicon is compatible with peripheral processes on the substrate and below the read transistor.

[0019] Additional aspects and advantages of the present application will be given in part in the following description, which will become apparent from the following description, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0021] Figure 1 A schematic structural diagram of a semiconductor device provided in an embodiment of the present application;

[0022] Figure 2a 、 2b A schematic structural diagram of another semiconductor device provided in an embodiment of the present application;

[0023] Figure 3a A schematic diagram of the three-dimensional structure of a semiconductor device provided in an embodiment of the present application;

[0024] Figure 3b A schematic diagram of the three-dimensional structure of another semiconductor device provided in an embodiment of the present application;

[0025] Figure 4 A schematic diagram of the cross-sectional structure of a semiconductor device taken at line AA provided in an embodiment of the present application;

[0026] Figure 5 A schematic diagram of the cross-sectional structure of a semiconductor device at section BB provided in an embodiment of the present application;

[0027] Figure 6 A schematic cross-sectional structure diagram of another semiconductor device taken along line AA provided in an embodiment of the present application;

[0028] Figure 7 A schematic cross-sectional structure diagram of a semiconductor device taken at section BB provided in an embodiment of the present application;

[0029] Figure 8 A schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present application;

[0030] Figures 9a to 12b 、 Figure 14a 、 Figure 14b 、 Figures 16a to 21b Schematic diagrams of various structures obtained in various steps of a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0031] Figure 13a 、 Figure 13b 、 Figure 15a 、 Figure 15b 、 Figure 22a 、 Figure 22b Schematic diagrams of various structures obtained in different steps of another method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0032] Figure 23a 、 Figure 23b This is a schematic structural diagram obtained in step S434 of another method for manufacturing a semiconductor device provided in an embodiment of the present application.

[0033] Reference numerals:

[0034] 11-substrate; 111-first groove;

[0035] 12 - read transistor; 121 - first gate electrode; 122 - first gate insulating layer; 123 - first semiconductor layer; 1231 - first initial source-drain region; 1232 - first initial channel region; 1233 - second initial source-drain region; 123a - first source-drain region; 123b - first channel region; 123c - second source-drain region;

[0036] 13-write transistor; 131-second gate electrode; 132-second gate insulating layer; 133-second semiconductor layer;

[0037] 14-first conductive structure;

[0038] 15- second conductive structure;

[0039] 16-read bit line;

[0040] 17-read word line;

[0041] 18-write word line; 181-initial write word line; 183-third source and drain;

[0042] 19-write bit line;

[0043] 20 - first dielectric layer; 21 - second dielectric layer; 22 - third dielectric layer; 23 - fourth dielectric layer; 24 - fifth dielectric layer; 25 - sixth dielectric layer; 26 - seventh dielectric layer; 27 - eighth dielectric layer; 28 - ninth dielectric layer; 32 - tenth dielectric layer; 33 - eleventh dielectric layer; 34 - twelfth dielectric layer;

[0044] 29-third conductive structure;

[0045] 30-first hole;

[0046] 31-Second hole. DETAILED DESCRIPTION

[0047] The following describes the embodiments of the present application in conjunction with the accompanying drawings. It should be understood that the embodiments described below in conjunction with the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions of the embodiments of the present application.

[0048] Those skilled in the art will understand that, unless otherwise stated, the singular forms "a," "an," "said," and "the" used herein may also include the plural forms. It should be further understood that the term "comprising" used in the specification of this application refers to the presence of the described features, integers, steps, operations, elements, and / or components, but does not exclude the implementation of other features, information, data, steps, operations, elements, components, and / or combinations thereof supported by the technical field. It should be understood that when we refer to an element as being "connected" or "coupled" to another element, the element may be directly connected or coupled to the other element, or it may refer to the element and the other element establishing a connection relationship through an intermediate element. In addition, the "connection" or "coupling" used herein may include wireless connection or wireless coupling. The term "and / or" used herein refers to at least one of the items defined by the term, for example, "A and / or B" may be implemented as "A," or as "B," or as "A and B."

[0049] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0050] An embodiment of the present application provides a semiconductor device, which may be a memory cell, a memory cell array, a transistor, etc. The transistor may be used in the storage field or other fields of integrated circuits.

[0051] The embodiment of the present application provides a semiconductor device. The structural diagram of the semiconductor device is shown in FIG. Figure 1 、 Figure 2a and Figure 2b As shown, it includes: a read transistor 12 and a write transistor 13 stacked in sequence on one side of a substrate 11.

[0052] The read transistor 12 may include a first gate electrode 121 , a first gate insulating layer 122 , and a first semiconductor layer 123 .

[0053] The first gate electrode 121 extends along a first direction perpendicular to the substrate 11 , and the first gate electrode 121 is electrically connected to the write transistor 13 .

[0054] The first gate insulating layer 122 is disposed around the periphery and bottom of the first gate electrode 121 .

[0055] The first semiconductor layer 123 is disposed on the periphery of the first gate insulating layer 122. The first semiconductor layer 123 includes a first source-drain region 123a, a first channel region 123b, and a second source-drain region 123c, which are sequentially spaced away from the substrate 11. The first source-drain region 123a, the first channel region 123b, and the second source-drain region 123c are all made of silicon.

[0056] In the semiconductor device of the embodiment of the present application, the first source-drain region 123a, the first channel region 123b, and the second source-drain region 123c of the read transistor 12 are all made of silicon. That is, the read transistor is a silicon transistor. Compared to a read transistor whose channel region is made of a metal oxide semiconductor, silicon has higher mobility, thereby improving the read speed of the read transistor 12. Furthermore, a read transistor whose channel region is made of silicon is compatible with the peripheral processes on the substrate and below the read transistor, allowing the peripheral circuits to be manufactured simultaneously with the read transistor.

[0057] In the semiconductor device of the present embodiment, the first semiconductor layer 123 is cylindrical, surrounding the sidewalls of the first gate insulating layer 122. This utilizes a vertical ring-channel 2TOC structure. Compared to the planar 2TOC structure used in related art, the vertical ring-channel 2TOC structure offers the advantages of being smaller and stackable, saving unit area, increasing semiconductor device density, and reducing manufacturing costs. Furthermore, the 2TOC structure employed in the semiconductor device of the present embodiment features read-write separation, eliminating the need for data destruction or rewriting.

[0058] The read transistor 12 in the embodiment of the present application adopts a ring channel structure of silicon material. Compared with the read transistor 12 in the related art adopting a surrounding gate structure, the ring channel structure adopted by the read transistor 12 in this embodiment is less difficult to manufacture.

[0059] Moreover, since the first gate electrode 121 of the read transistor 12 serves as a plate of the capacitor, and the first gate insulating layer 122 of the read transistor 12 serves as the dielectric layer of the capacitor, it is equivalent to adding a capacitor to the substrate. The threshold voltage of the read transistor 12 can be adjusted by applying a voltage to the first gate electrode 121 through the write transistor, thereby suppressing the charge sharing problem in the reading process of the 2T0C structural unit.

[0060] Optionally, in some embodiments, the materials of the substrate 11 and the first semiconductor layer 123 may both be single crystal silicon, or the materials of the substrate 11 and the first semiconductor layer 123 may both be polycrystalline silicon.

[0061] In other words, the materials of the substrate 11 , the first source / drain region 123 a , the first channel region 123 b , and the second source / drain region 123 c may all be single crystal silicon or polycrystalline silicon.

[0062] For example, the material of the first semiconductor layer 123 may be single crystal silicon. In this case, the read transistor 12 is a single crystal silicon transistor. Since single crystal silicon has a high mobility, the read speed of the read transistor 12 can be increased.

[0063] Alternatively, the single crystal silicon transistor can be manufactured using an epitaxial method, wherein the epitaxial method described in the present application is a method of growing a film layer of a single crystal material as the first semiconductor layer on a single crystal semiconductor material substrate through an epitaxial process.

[0064] As an example, one method is to use the substrate 11 (the material of the substrate 11 is single crystal silicon) as a base to form the first semiconductor layer 123 by using an epitaxial method.

[0065] Another method is to use a single crystal germanium layer on the surface of the substrate 11 as a base to form the first semiconductor layer 123 by epitaxial growth. Due to the high etching selectivity between germanium (Ge) and silicon (Si), the single crystal germanium layer can be selectively etched away to form a third trench, and then the twelfth dielectric layer 34 can be formed in the third trench.

[0066] As another example, the material of the first semiconductor layer 123 may be polysilicon. In this case, the read transistor 12 is a polysilicon transistor.

[0067] Since the process temperature of polycrystalline silicon (such as LTPS, low-temperature polycrystalline silicon) is not high, this temperature will not damage single-crystalline silicon. Therefore, in terms of technology, the peripheral circuit containing single-crystalline silicon can be made on the single-crystalline silicon substrate first, and then the polycrystalline silicon transistor can be made. Therefore, when the read transistor 12 is a polycrystalline silicon transistor, the peripheral circuit of single-crystalline silicon can be made on the side of the read transistor 12 away from the write transistor 13. In addition, polycrystalline silicon can also grow on the wall (single-crystalline silicon can usually only be grown by methods such as epitaxy). In summary, when the read transistor 12 is a polycrystalline silicon transistor, the application prospects in embedded random access memory (Embedded RAM) and storage and computing integration are better.

[0068] In some embodiments, the materials of the first source / drain regions 123a and the second source / drain regions 123c are both N-type silicon, while the material of the first channel region 123b is P-type silicon. In other words, the materials of the first source / drain regions 123a and the second source / drain regions 123c are both N-type doped, while the material of the first channel region 123b is P-type doped. This means that the read transistor is an NMOS inversion mode transistor.

[0069] In other embodiments, the materials of the first source-drain region 123a, the first channel region 123b, and the second source-drain region 123c are all N-type silicon; and the doping concentration of the first source-drain region 123a and the second source-drain region 123c is higher than the doping concentration of the first channel region 123b. In other words, the materials of the first source-drain region 123a, the first channel region 123b, and the second source-drain region 123c all contain N-type dopant ions, i.e., the read transistor is an NMOS junction-less transistor.

[0070] In some embodiments, the materials of the first source / drain region 123a and the second source / drain region 123c are both P-type silicon, and the material of the first channel region 123b is N-type silicon. In other words, the materials of the first source / drain region 123a and the second source / drain region 123c are both P-type dopant ions, and the material of the first channel region 123b is N-type dopant ions, i.e., the read transistor is a PMOS inversion transistor.

[0071] In some embodiments, the materials of the first source / drain region 123a, the first channel region 123b, and the second source / drain region 123c are all P-type silicon; the doping concentration of the first source / drain region 123a and the second source / drain region 123c is higher than the doping concentration of the first channel region 123b. In other words, the materials of the first source / drain region 123a, the first channel region 123b, and the second source / drain region 123c all contain P-type dopant ions, meaning that the read transistor is a PMOS junction-less transistor.

[0072] See also Figure 1 、 Figure 2a and Figure 2bIn some embodiments, the write transistor 13 may include: a second gate electrode 131 , a second gate insulating layer 132 , and a second semiconductor layer 133 .

[0073] The second gate electrode 131 extends along a first direction perpendicular to the substrate 11 .

[0074] The second gate insulating layer 132 is disposed around the periphery and bottom of the second gate electrode 131 .

[0075] The second semiconductor layer 133 is disposed around the periphery and bottom of the second gate insulating layer 132 and is electrically connected to the first gate electrode 121 . The second semiconductor layer 133 is a metal oxide semiconductor layer.

[0076] In this embodiment, the write transistor 13 adopts a ring channel structure, which has a simple processing technology and is less difficult to manufacture.

[0077] The material of the second semiconductor layer 133 may be IGZO (Indium Gallium Zinc Oxide). IGZO has a large band gap (Eg), which can reduce leakage of the write transistor 13 and increase retention time.

[0078] Furthermore, the second semiconductor layer 133 is manufactured using IGZO using a low-temperature process, which is compatible with BEOL (Back End of Line) processes.

[0079] In some embodiments, the material of the second semiconductor layer 133 may further include one or more of the following: indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InWO , IWO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO) and other materials, which can be adjusted according to actual conditions.

[0080] See also Figure 1 、 Figure 2a and Figure 2bIn this embodiment, the semiconductor device may further include a first conductive structure 14 and a second conductive structure 15 sequentially arranged on a side of the first gate electrode 121 away from the substrate 11 .

[0081] The first conductive structure 14 and the second conductive structure 15 are extensions of the first gate electrode 121 , and the extensions also serve as the source or drain of the write transistor.

[0082] The orthographic projection of the first conductive structure 14 on the substrate 11 is located within the orthographic projection of the first gate insulating layer 122 on the substrate 11 .

[0083] The orthographic projection of the first gate electrode 121 on the substrate 11 is located within the orthographic projection of the second conductive structure 15 on the substrate 11 ; the second conductive structure 15 is located below the second semiconductor layer 133 and electrically connected to the second semiconductor layer 133 .

[0084] Compared to a solution that directly electrically connects the first gate electrode 121 to the second semiconductor layer 133, in this embodiment, the first gate electrode 121 is connected to the second semiconductor layer 133 via the first conductive structure 14, the second conductive structure 15, and the second semiconductor layer 133. This increases the contact area between the first gate electrode 121 and the second semiconductor layer 133. Furthermore, because the orthographic projection of the first conductive structure 14 on the substrate 11 is located within the orthographic projection of the first gate insulating layer 122 on the substrate 11, a short circuit between the first conductive structure 14 and the second source / drain region 123 c can be avoided.

[0085] See also Figure 1 、 Figure 2a and Figure 2b Optionally, the second conductive structure 15 is arranged on a side of the second semiconductor layer 133 close to the substrate 11 and in a partial area of ​​the periphery of the second semiconductor layer 133 .

[0086] Such an arrangement can ensure reliable contact between the second semiconductor layer 133 and the second conductive structure 15 .

[0087] See also Figure 2a In another embodiment, the substrate 11 may include a first groove 111 .

[0088] The first gate electrode 121 includes a first end located in the first groove 111 and a second end located outside the first groove 111 .

[0089] The first gate insulating layer 122 includes a first portion disposed on the surface of the first end and a second portion disposed at the periphery of the second end; the first source and drain regions 123a, the first channel region 123b and the second source and drain regions 123c are all disposed at the periphery of the second portion.

[0090] That is to say, in the semiconductor device in the embodiment of the present application, the first gate electrode 121 of the read transistor 12 partially extends into the interior of the substrate 11, while the first source and drain 123a, the first channel region 123b and the second source and drain 123c are arranged on the surface of the substrate 11, so that the contact area between the first gate electrode 121 (as a plate of the capacitor) and the first gate insulating layer 122 (as a dielectric layer of the capacitor) is increased, thereby increasing the capacitance of the first gate electrode 121 (SN end) without increasing the area of ​​the semiconductor device, and then applying a voltage to the first gate electrode 121 through the write transistor to adjust the threshold voltage of the read transistor 12, thereby suppressing the charge sharing problem in the reading process of the 2T0C structural unit while ensuring the integration of the semiconductor device.

[0091] See also Figure 2b Optionally, a twelfth dielectric layer 34 may be provided between the first source / drain region 123a and the substrate 11, and the first recess 111 may be provided in the twelfth dielectric layer 34 and the substrate 11. The twelfth dielectric layer 34 may be silicon oxide.

[0092] In practical applications, a single crystal germanium layer may be manufactured on one side of the substrate 11 ; and a first N-type silicon layer may be epitaxially grown on a side of the single crystal germanium layer away from the substrate 11 .

[0093] Since the etching selectivity between germanium (Ge) and silicon (Si) is relatively high, the single crystal germanium layer can be selectively etched away to form a third trench, and then the twelfth dielectric layer 34 is formed in the third trench.

[0094] In this embodiment, the depth of the first groove 111 may range from 45 nanometers to 200 nanometers, for example, about 45 nanometers. The size of the semiconductor device is 4F2, and the distance between each semiconductor device is about 90 nanometers.

[0095] In this embodiment, the thicknesses of the first source-drain region 123 a , the first channel region 123 b , and the second source-drain region 123 c are 20 nanometers, 40 nanometers, and 20 nanometers, respectively.

[0096] Taking a memory cell as an example, the Id-Vg curve of a memory cell is related to its channel length. The longer the channel, the larger the current switching ratio (Ion / Ioff). However, after the channel length exceeds 60 nanometers, further increasing the channel length has little effect on the Id-Vg curve.

[0097] For a memory cell with a channel length of 60 nanometers, Ioff (drain current in the off state) can reach the order of e-12, and Ion (drain current in the on state) can reach the order of e-4.

[0098] In some embodiments, the semiconductor device may further include multiple read bit lines 16 and multiple read word lines 17, the read bit lines 16 and the first source and drain regions 123a connected thereto are different regions of the same film layer; the read word lines 17 and the second source and drain regions 123c connected thereto are different regions of the same film layer.

[0099] The semiconductor device in the embodiment of the present application can be a memory or a storage unit that can be used for a memory. Taking the memory as an example, the structural diagram of the memory is as follows: Figures 3a to 7 As shown, it includes: a plurality of read bit lines 16, a plurality of read word lines 17, and the memory cells arranged in an array as described above.

[0100] A plurality of read bit lines 16 extend along a second direction parallel to the substrate 11 and are arranged along a third direction. The read bit lines 16 connect the first source and drain regions 123 a of a row of memory cells.

[0101] A plurality of read word lines 17 extending along a third direction parallel to the substrate 11 and arranged along the second direction, the read word lines 17 connecting the second source and drain regions 123c of a column of memory cells; the third direction and the second direction form an angle of 90 degrees or other angles, which are not specifically limited in this application.

[0102] Figure 4 、 Figure 5 FIG. 1 is a schematic diagram showing that the first gate insulating layer 122 is only disposed on the surface of the substrate 11 . Figure 6 、 Figure 7 Schematic diagram showing that the first gate electrode 121 and the first gate insulating layer 122 are both partially located in the first groove 111 of the substrate 11 .

[0103] Continue to refer Figures 3a to 7 Optionally, the semiconductor device may further include a plurality of write word lines 18 and a plurality of write bit lines 19 .

[0104] A plurality of write word lines 18 extend along a second direction parallel to the substrate 11 and are arranged along a third direction. The write word lines 18 wrap around the periphery of the second semiconductor layer 133 of each row of semiconductor devices, and the second semiconductor layer 133 of each row of memory cells is electrically connected via one write word line 18 .

[0105] A plurality of write bit lines 19 extend along a third direction parallel to the substrate 11 and are arranged along the second direction; the write bit lines 19 are located on the side of the second gate electrode 131 of each memory cell in each column away from the substrate 11, and the second gate electrode 131 of each memory cell in each column is electrically connected to one write bit line 19.

[0106] Optionally, the write bit line 19 is electrically connected to the second gate electrode 131 of the memory cell via the third conductive structure 29 .

[0107] In this embodiment, the orthographic projection of the third conductive structure 29 on the substrate 11 overlaps with the orthographic projection of the second gate electrode 131 of the memory cell on the substrate 11. Of course, the orthographic projection of the third conductive structure 29 on the substrate 11 may also be located within the orthographic projection of the second gate electrode 131 of the memory cell on the substrate 11. This is sufficient as long as the third conductive structure 29 and the second semiconductor layer 133 of the memory cell are spaced apart from each other to maintain insulation.

[0108] It should be noted that Figures 3a to 7 Taking a memory cell as an example, in fact, the memory includes a plurality of read bit lines 16, a plurality of read word lines 17, a plurality of write word lines 18, a plurality of write bit lines 19, and a plurality of memory cells arranged in an array.

[0109] In order to show the structure of the memory more clearly, Figures 3a to 7 Various dielectric layers are omitted. Figure 3a 、 Figure 3b The substrate 11 is also omitted, and the plurality of read bit lines 16, the plurality of read word lines 17, the plurality of write word lines 18 and the plurality of write bit lines 19 are all presented in the form of semi-transparent graphics.

[0110] See also Figure 4 、 Figure 6 The write word line 18 includes a third source and drain 183 disposed on the periphery of the second semiconductor layer 133 and adjacent to the second semiconductor layer 133 , and a first connecting line away from the second semiconductor layer 133 , wherein the first connecting line is connected between the third source and drain 183 of adjacent memory cells.

[0111] Optionally, the second conductive structure 15 may serve as a fourth source and drain. The fourth source and drain of the write transistor 13 are electrically connected to the first gate of the read transistor 12 .

[0112] In this embodiment, the third source-drain electrode 183 can serve as the drain of the write transistor 13, and the fourth source-drain electrode can serve as the source of the write transistor 13. Of course, the third source-drain electrode 183 can also serve as the source of the write transistor 13, and the fourth source-drain electrode can also serve as the drain of the write transistor 13.

[0113] It can be understood that the memory includes multiple rows of memory cells arranged along a third direction parallel to the substrate 11, and the memory cells in each row of memory cells are arranged along the second direction parallel to the substrate 11. In other words, the memory includes multiple columns of memory cells arranged along the second direction parallel to the substrate 11, and the memory cells in each column of memory cells are arranged along the third direction parallel to the substrate 11.

[0114] In this embodiment, the memory may further include an isolation layer (not shown), which is disposed between the substrates 11 of any adjacent memory cells to insulate the substrates 11 of any adjacent memory cells from each other.

[0115] The isolation layer may be made of a material with a high dielectric constant.

[0116] By forming an isolation layer between different memory cells on the substrate 11 , it is possible to ensure that the substrates 11 corresponding to different memory cells are isolated from each other, so that different memory cells can be opened independently.

[0117] Optionally, an isolation layer may be formed between different memory cells in the same row of the substrate 11, thereby ensuring that different memory cells in the same row can be independently opened, thereby achieving separate control of each row of memory cells.

[0118] This embodiment is an embodiment of a memory corresponding to the embodiment of the aforementioned storage unit. Specific technical details and technical effects can be referenced with each other and will not be repeated here.

[0119] Based on the same inventive concept, an embodiment of the present application provides an electronic device, including: any memory or semiconductor device provided in the above embodiments.

[0120] In this embodiment, since the electronic device adopts any of the memories or semiconductor devices provided in the aforementioned embodiments, its principles and technical effects can be referred to in the aforementioned embodiments and will not be described in detail here.

[0121] Optionally, the electronic device may include a storage device, a smart phone, a computer, a tablet computer, artificial intelligence, a wearable device or a smart mobile terminal.

[0122] It should be noted that electronic devices are not limited to the above-mentioned ones. Those skilled in the art can set any semiconductor device provided in the above-mentioned embodiments of this application in different devices according to actual application requirements, thereby obtaining the electronic device provided in the embodiments of this application.

[0123] Based on the same inventive concept, the present invention provides a method for manufacturing a semiconductor device. The flowchart of the manufacturing method is as follows: Figure 8 As shown, the method includes steps S1 to S4:

[0124] S1: growing a first initial semiconductor layer on a silicon-containing substrate 11 using an epitaxial process.

[0125] In some embodiments, step S1 may include: using an epitaxial process and a patterning process to manufacture an array-arranged first initial semiconductor layer, a read bit line 16, and a read word line 17 on one side of a silicon-containing substrate 11, wherein the first initial semiconductor layer includes a first initial source-drain region 1231, a first initial channel region 1232, and a second initial source-drain region 1233 distributed in sequence in a direction away from the substrate 11; the materials of the first initial source-drain region 1231, the first initial channel region 1232, and the second initial source-drain region 1233 all contain silicon material; the read bit line 16 connects the first initial source-drain region 1231, and the read word line 17 connects the second initial source-drain region 1233, and the read bit line 16 and the read word line 17 extend in different directions in a plane parallel to the substrate, and the extension directions are at a designed angle.

[0126] After step S1, the obtained structural diagram is as follows Figures 9a to 11b shown.

[0127] Specifically, step S1 may include steps S11 to S13.

[0128] S11 : epitaxially growing a first N-type silicon layer on one side of a silicon-containing substrate 11 ; patterning the first N-type silicon layer to obtain a first initial source / drain region 1231 and a read bit line 16 , and exposing a portion of the surface of the substrate 11 .

[0129] After step S11, the obtained structural diagram is as follows Figure 9a 、 9b shown.

[0130] Continue to see Figure 9a 、 9b In practical applications, after step S11 , the following step may further include: manufacturing a tenth dielectric layer 32 on the exposed surface of the substrate 11 , where the tenth dielectric layer 32 is disposed on the same layer as the first initial source / drain region 1231 and the read bit line 16 .

[0131] S12: epitaxially grow a first P-type silicon layer on the side of the first initial source-drain region 1231 and the read bit line 16 away from the substrate 11 and on the surface of the substrate 11; pattern the first P-type silicon layer to obtain a first groove, an array-arranged first initial channel region 1232 and a plurality of read bit lines 16, the read bit lines 16 and the first initial source-drain region 1231 connected thereto are different regions of the same film layer; deposit a first dielectric layer 20 in the first groove.

[0132] After step S12, the obtained structural diagram is as follows Figure 10a 、 10b shown.

[0133] S13: epitaxially grow a second N-type silicon layer on the side of the first initial channel region 1232 away from the substrate 11 and on the side of the first dielectric layer 20 away from the substrate 11; pattern the second N-type silicon layer to obtain a second trench, an array-arranged second initial source and drain region 1233 and a plurality of read word lines 17, wherein each read word line 17 and the second initial source and drain region 1233 connected thereto are different regions of the same film layer; and deposit a second dielectric layer 21 in the second trench.

[0134] After step S13, the obtained structural diagram is as follows Figure 11a 、 11b shown.

[0135] Since the read bit line 16 and the first source-drain region 123a of the read transistor 12 are formed by the same epitaxial process and patterning process, and the read word line 17 and the second source-drain region 123c of the read transistor 12 are formed by the same epitaxial process and patterning process, the process steps can be reduced and the manufacturing cost can be reduced.

[0136] In an alternative embodiment of step S1, step S11 may epitaxially grow a first P-type silicon layer on one side of the silicon-containing substrate 11; accordingly, in step S12, epitaxially grow a first N-type silicon layer on the side of the first initial source-drain region 1231 and the read bit line 16 away from the substrate 11 and on the surface of the substrate 11; accordingly, in step S13, epitaxially grow a second P-type silicon layer on the side of the first initial channel region 1232 away from the substrate 11 and on the side of the first dielectric layer 20 away from the substrate 11.

[0137] It can be understood that the first initial semiconductor layer is grown on the silicon-containing substrate 11 using an epitaxial process, including: epitaxially growing a first P-type silicon layer on one side of the substrate 11; patterning the first P-type silicon layer to obtain a first initial source-drain region 1231, exposing a portion of the surface of the substrate 11; epitaxially growing a first N-type silicon layer on the side of the first initial source-drain region 1231 away from the substrate 11 and on the surface of the substrate 11; patterning the first N-type silicon layer to obtain a first trench, and depositing a first dielectric layer 20 in the first trench. Epitaxially growing a second P-type silicon layer on the side of the first initial channel region 1232 away from the substrate 11 and on the side of the first dielectric layer 20 away from the substrate 11; patterning the second P-type silicon layer to obtain a second trench, and depositing a second dielectric layer 21 in the second trench.

[0138] S2: forming a first hole 30 penetrating the first initial semiconductor layer and exposing the substrate 11 to obtain a first semiconductor layer 123 , wherein the first semiconductor layer 123 sequentially includes a first source-drain region 123 a , a first channel region 123 b , and a second source-drain region 123 c in a direction away from the substrate 11 .

[0139] In some embodiments, each first initial semiconductor layer is patterned to obtain a first hole 30 and a first source / drain region 123 a , a first channel region 123 b , and a second source / drain region 123 c surrounding the first hole 30 and sequentially away from the substrate 11 .

[0140] After step S2, the obtained structural diagram is as follows Figure 12a 、 12b or Figure 13a 、 13b shown.

[0141] In this embodiment, step S2 includes: patterning each first initial semiconductor layer to obtain a first hole 30 and a first source-drain region 123a, a first channel region 123b and a second source-drain region 123c surrounding the first hole 30 and sequentially away from the substrate 11.

[0142] Correspondingly, after step S2 in this embodiment, the obtained structural diagram is as follows Figure 12a 、 12b shown.

[0143] In another embodiment, step S2 includes: forming a hole through the first initial semiconductor layer and continuing to etch downward the substrate 11 to form a first hole located in the first initial semiconductor layer and extending into the substrate, and the first gate insulating layer and the first gate electrode extend into the substrate 11.

[0144] Correspondingly, in another embodiment, after step S2, the obtained structural diagram is as follows Figure 13a 、 13b shown. Figure 13a 、 13b In the embodiment, the first hole 30 extends into a partial thickness of the substrate 11 .

[0145] S3 : depositing the first gate insulating layer 122 and the first gate electrode 121 of the read transistor 12 in sequence in the first hole 30 .

[0146] In this embodiment, after step S3, the obtained structural diagram is as follows: Figure 14a 、 14b shown.

[0147] In another embodiment, after step S3, the obtained structural diagram is as follows Figure 15a 、 15b Specifically, the substrate 11 may include a first groove 111. The first gate electrode 121 includes a first end located within the first groove 111 and a second end located outside the first groove 111. The first gate insulating layer 122 includes a first portion disposed on the surface of the first end and a second portion disposed on the periphery of the second end.

[0148] S4 : forming a second gate electrode 131 of the write transistor 13 and a second semiconductor layer 133 electrically connected to the first gate electrode 121 on a side of the read transistor 12 away from the substrate 11 .

[0149] The first gate electrode 121 may be electrically connected to the second semiconductor layer 133 of the write transistor 13 .

[0150] Specifically, step S4 may include: forming a second semiconductor layer 133 on the first gate electrode 121 and surrounding the sidewall of the second gate electrode 121 , wherein the second semiconductor layer 133 is a metal oxide semiconductor layer.

[0151] In some embodiments, a first conductive structure 14, a second conductive structure 15, a write transistor 13, a write word line 18, and a write bit line 19 can be manufactured in sequence on the side of the first gate electrode 121 away from the substrate 11, so that the vertical ring-shaped second semiconductor layer 133 of the write transistor 13 is electrically connected to the second conductive structure 15, the write word line 18 connects the second semiconductor layers 133 of any two adjacent write transistors 13, and the write bit line 19 connects the second gate electrodes 131 of any two adjacent write transistors 13. The write word line 18 and the write bit line 19 are at a designed angle and are both parallel to the substrate 11.

[0152] Since the manufacturing methods of the write transistor 13 in the two embodiments are similar, Figure 14a 、 14b The structure shown is an example of manufacturing the write transistor 13 on a substrate. It is understandable that steps S1 and S4 can be shared by both semiconductor devices and will not be described in detail here.

[0153] Specifically, step S4 may include steps S41 to S43.

[0154] S41: A third dielectric layer 22 is manufactured on the first gate electrode 121, the first gate insulating layer 122, the second source and drain region 123c, and the second dielectric layer 21 on the side away from the substrate 11; the third dielectric layer 22 is patterned to obtain second holes arranged in an array to expose the first gate electrode 121; and the first conductive structure 14 is filled in the second hole to electrically connect the first conductive structure 14 to the first gate electrode 121.

[0155] In this embodiment, after step S41, the obtained structural diagram is as follows: Figure 16a 、 16b shown.

[0156] S42: Manufacturing a fourth dielectric layer 23 on a side of the first conductive structure 14 and the third dielectric layer 22 away from the substrate 11; patterning the fourth dielectric layer 23 to obtain third holes arranged in an array to expose the first conductive structure 14 and a portion of the third dielectric layer 22; and filling the third holes with the second conductive structure 15 to electrically connect the second conductive structure 15 to the first conductive structure 14.

[0157] In this embodiment, after step S42, the obtained structural diagram is as follows: Figure 17a 、 17b shown.

[0158] S43 : manufacturing a write transistor 13 , a write word line 18 and a write bit line 19 on a side of the second conductive structure 15 away from the substrate 11 , and electrically connecting the second semiconductor layer 133 of the write transistor 13 to the second conductive structure 15 .

[0159] In this embodiment, after step S43, the obtained structural diagram is as follows: Figures 18a to 21b shown.

[0160] Specifically, step S43 may include steps S431 to S434.

[0161] S431 : sequentially manufacturing a stacked fifth dielectric layer 24 , an initial write word line 181 and a sixth dielectric layer 25 on the side of the second conductive structure 15 and the fourth dielectric layer 23 away from the substrate 11 .

[0162] In this embodiment, after step S431, the obtained structural diagram is as follows: Figure 18a 、 18b shown.

[0163] S432 : performing patterning on the fifth dielectric layer 24 , the initial write word line 181 , the sixth dielectric layer 25 and the partial depth of the second conductive structure 15 to obtain the second hole 31 and the write word line 18 .

[0164] In this embodiment, after step S432, the obtained structural diagram is as follows: Figure 19a 、 19b shown.

[0165] See also Figure 19a Specifically, the write line 18 may include a third source and drain 183 and a fourth source and drain 184 respectively arranged on both sides of the second hole 31 and close to the second hole 31, and a first connecting line away from the second semiconductor layer 133, and the first connecting line is connected between the third source and drain 183 and the fourth source and drain 184 of the adjacent semiconductor device.

[0166] In this embodiment, one of the third source-drain 183 and the fourth source-drain 184 serves as the source of the write transistor 13 , and the other serves as the drain of the write transistor 13 .

[0167] Continue to see Figure 19a 、 19b In practical applications, an eleventh dielectric layer 33 is provided between any two adjacent write word lines 18 , and the eleventh dielectric layer 33 is provided on the same layer as the write word lines 18 .

[0168] S433 : manufacturing a second semiconductor layer 133 and a second gate insulating layer 132 in sequence along the second hole 31 , and manufacturing a second gate electrode 131 to form the write transistor 13 .

[0169] In this embodiment, after step S433, the obtained structural diagram is as follows: Figure 20a 、 20b shown.

[0170] S434 : A third conductive structure 29 , a write bit line 19 , a seventh dielectric layer 26 , an eighth dielectric layer 27 and a ninth dielectric layer 28 are manufactured on the side of the second gate electrode 131 away from the substrate 11 , so that the write bit line 19 is electrically connected to the second gate electrode 131 via the third conductive structure 29 .

[0171] In this embodiment, after step S434, the obtained structural diagram is as follows: Figure 21a 、 21b shown.

[0172] In another embodiment, after step S434, the obtained structural diagram is as follows Figure 22a 、 22b shown.

[0173] Optionally, in another embodiment, step S11 may include: manufacturing a single crystal germanium layer on one side of the substrate 11 ; and epitaxially growing a first N-type silicon layer on a side of the single crystal germanium layer away from the substrate 11 .

[0174] Furthermore, since the etching selectivity between germanium (Ge) and silicon (Si) is relatively high, the single crystal germanium layer can be selectively etched away in a subsequent step to form a third trench, and then the twelfth dielectric layer 34 is formed in the third trench.

[0175] In another embodiment, after step S434, the obtained structural diagram is as follows Figure 23a 、 23b shown. Figure 23a 、 23b In the embodiment, a twelfth dielectric layer 34 is further provided between the first source / drain region 123a and the substrate 11, and the first groove can be provided in the twelfth dielectric layer 34 and the substrate 11. The twelfth dielectric layer 34 can be silicon oxide.

[0176] The first gate electrode 121 includes a first end located in the first groove and a second end located outside the first groove. The first gate insulating layer 122 includes a first portion disposed on a surface of the first end and a second portion disposed around the second end.

[0177] It should be noted that the process of forming the third conductive structure 29 and the write bit line 19 is similar to the process of forming the first conductive structure 14 and the second conductive structure 15 , and will not be described in detail here.

[0178] In practical applications, the material of each dielectric layer may be a material with a low dielectric constant, and the first gate insulating layer 122 and the second gate insulating layer 132 may be a material with a high dielectric constant.

[0179] The beneficial technical effects brought about by the technical solutions provided in the embodiments of the present application include:

[0180] Since the first source-drain region 123a, the first channel region 123b, and the second source-drain region 123c of the read transistor 12 are all made of silicon, i.e., the read transistor is a silicon transistor, the higher mobility of silicon compared to a read transistor whose channel region is made of a metal oxide semiconductor can improve the read speed of the read transistor 12. Furthermore, the read transistor whose channel region is made of silicon is compatible with the peripheral processes on the substrate and below the read transistor, allowing the peripheral circuits to be manufactured simultaneously with the read transistor.

[0181] Furthermore, the read bit line 16 and the first source-drain region 123a of the read transistor 12 are formed by the same epitaxial process and patterning process, and the read word line 17 and the second source-drain region 123c of the read transistor 12 are formed by the same epitaxial process and patterning process, which can reduce process steps and lower manufacturing costs.

[0182] Those skilled in the art will appreciate that the steps, measures, and schemes in the various operations, methods, and processes discussed in this application may be interchanged, modified, combined, or deleted. Furthermore, other steps, measures, and schemes in the various operations, methods, and processes discussed in this application may also be interchanged, modified, rearranged, decomposed, combined, or deleted. Furthermore, steps, measures, and schemes in the related art that are similar to those disclosed in this application may also be interchanged, modified, rearranged, decomposed, combined, or deleted.

[0183] In the description of this application, the directions or positional relationships indicated by words such as "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", and "outside" are exemplary directions or positional relationships based on the accompanying drawings. They are intended to facilitate or simplify the description of the embodiments of this application, and do not indicate or imply that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they should not be understood as limitations on this application.

[0184] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of such features. Throughout this application, unless otherwise specified, "plurality" means two or more.

[0185] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to direct connections, indirect connections through an intermediate medium, or internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0186] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0187] It should be understood that, although the various steps in the flowchart of the accompanying drawings are displayed in sequence as indicated by the arrows, the order of implementation of these steps is not limited to the order indicated by the arrows. Unless otherwise clearly stated herein, in some implementation scenarios of the embodiments of the present application, the steps in each process can be performed in other orders as required. Moreover, some or all of the steps in each flowchart may include multiple sub-steps or multiple stages based on actual implementation scenarios. Some or all of these sub-steps or stages may be executed at the same time, or may be executed at different times in different scenarios at the execution time. The execution order of these sub-steps or stages may be flexibly configured as required, and the embodiments of the present application do not limit this.

[0188] The above is only part of the implementation methods of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the technical concept of the solution of the present application, other similar implementation methods based on the technical ideas of the present application also fall within the protection scope of the embodiments of the present application.

Claims

1. A semiconductor device, characterized in that: include: a read transistor and a write transistor stacked sequentially on one side of the substrate; The read transistor comprises: a first gate electrode extending along a first direction perpendicular to the substrate, the first gate electrode being electrically connected to the write transistor; a first gate insulating layer, disposed around the outer periphery of the first gate electrode; A first semiconductor layer is arranged on the periphery of the first gate insulating layer; the first semiconductor layer includes a first source-drain region, a first channel region, and a second source-drain region distributed in sequence in a direction away from the substrate; the materials of the first source-drain region, the first channel region, and the second source-drain region all contain silicon material.

2. The semiconductor device according to claim 1, wherein Materials of the first source-drain region, the first channel region, and the second source-drain region are all single-crystal silicon or polycrystalline silicon.

3. The semiconductor device according to claim 2, wherein The materials of the first source-drain region and the second source-drain region are both N-type silicon; the material of the first channel region is P-type silicon.

4. The semiconductor device according to claim 2, wherein Materials of the first source-drain region, the first channel region, and the second source-drain region are all N-type silicon; and the doping concentrations of the first source-drain region and the second source-drain region are higher than the doping concentration of the first channel region.

5. The semiconductor device according to claim 2, wherein The materials of the first source-drain region and the second source-drain region are both P-type silicon; the material of the first channel region is N-type silicon.

6. The semiconductor device according to claim 2, wherein Materials of the first source-drain region, the first channel region, and the second source-drain region are all P-type silicon; and the doping concentrations of the first source-drain region and the second source-drain region are higher than the doping concentration of the first channel region.

7. The semiconductor device according to any one of claims 1 to 6, wherein: The write transistor comprises: a second gate electrode extending along a first direction perpendicular to the substrate; a second gate insulating layer, disposed around the periphery and bottom of the second gate electrode; The second semiconductor layer is arranged around the periphery and bottom of the second gate insulating layer and is electrically connected to the first gate electrode; the second semiconductor layer is a metal oxide semiconductor layer.

8. The semiconductor device according to claim 7, wherein: It also includes a first conductive structure and a second conductive structure sequentially arranged on a side of the first gate electrode away from the substrate; The orthographic projection of the first conductive structure on the substrate is located within the orthographic projection of the first gate insulating layer on the substrate; The orthographic projection of the first gate electrode on the substrate is located within the orthographic projection of the second conductive structure on the substrate; The second conductive structure is located below the second semiconductor layer and is electrically connected to the second semiconductor layer.

9. The semiconductor device according to claim 8, wherein The second conductive structure is disposed on a side of the second semiconductor layer close to the substrate and in a partial area of ​​an outer periphery of the second semiconductor layer.

10. The semiconductor device according to claim 1 or 2, wherein: The substrate includes a first groove; The first gate electrode includes a first end located in the first groove and a second end located outside the first groove.

11. The semiconductor device according to claim 1, wherein The materials of the substrate and the first semiconductor layer are both single-crystal silicon, or the materials of the substrate and the first semiconductor layer are both polycrystalline silicon.

12. The semiconductor device according to claim 1, wherein Also includes: a plurality of read bit lines, wherein the read bit lines and the first source and drain regions connected to the read bit lines are different regions of the same film layer; A plurality of read word lines, wherein the read word lines and the second source and drain regions connected to the read word lines are different regions of the same film layer.

13. An electronic device, characterized in that: include: A semiconductor device as claimed in any one of claims 1 to 12.

14. A method for manufacturing a semiconductor device, characterized in that: include: growing a first initial semiconductor layer on a silicon-containing substrate using an epitaxial process; The first initial semiconductor layer comprises a first initial source-drain region, a first initial channel region, and a second initial source-drain region, which are sequentially away from the substrate; the first initial source-drain region, the first initial channel region, and the second initial source-drain region are all made of silicon material; forming a first hole penetrating the first initial semiconductor layer and exposing the substrate to obtain a first semiconductor layer, wherein the first semiconductor layer sequentially comprises a first source-drain region, a first channel region, and a second source-drain region in a direction away from the substrate; sequentially depositing a first gate insulating layer and a first gate electrode of a read transistor in the first hole; A write transistor electrically connected to the first gate electrode is formed on a side of the read transistor away from the substrate.

15. The method for manufacturing a semiconductor device according to claim 14, wherein: Growing a first initial semiconductor layer on a silicon-containing substrate using an epitaxial process, comprising: epitaxially growing a first N-type silicon layer on one side of the substrate; patterning the first N-type silicon layer to obtain a first initial source and drain region, exposing a portion of the surface of the substrate; epitaxially growing a first P-type silicon layer on a side of the first initial source / drain region away from the substrate and on a surface of the substrate; patterning the first P-type silicon layer to obtain a first trench, and depositing a first dielectric layer in the first trench; A second N-type silicon layer is epitaxially grown on a side of the first initial channel region away from the substrate and on a side of the first dielectric layer away from the substrate; the second N-type silicon layer is patterned to obtain a second trench, and a second dielectric layer is deposited in the second trench.

16. The method for manufacturing a semiconductor device according to claim 14, wherein: Growing a first initial semiconductor layer on a silicon-containing substrate using an epitaxial process, comprising: epitaxially growing a first P-type silicon layer on one side of the substrate; patterning the first P-type silicon layer to obtain a first initial source and drain region, exposing a portion of the surface of the substrate; epitaxially growing a first N-type silicon layer on a side of the first initial source / drain region away from the substrate and on a surface of the substrate; patterning the first N-type silicon layer to obtain a first trench, and depositing a first dielectric layer in the first trench; A second P-type silicon layer is epitaxially grown on a side of the first initial channel region away from the substrate and on a side of the first dielectric layer away from the substrate; the second P-type silicon layer is patterned to obtain a second trench, and a second dielectric layer is deposited in the second trench.

17. The method for manufacturing a semiconductor device according to claim 14, wherein: A write transistor electrically connected to the first gate electrode is formed on a side of the read transistor away from the substrate, comprising: A second semiconductor layer is formed above the first gate electrode and surrounds a sidewall of the second gate electrode. The second semiconductor layer is a metal oxide semiconductor layer.

18. The method for manufacturing a semiconductor device according to claim 14, wherein: Forming a first hole penetrating the first initial semiconductor layer and exposing the substrate includes: A hole is formed through the first initial semiconductor layer and the substrate is continuously etched downward to form a first hole located in the first initial semiconductor layer and extending into the substrate. The first gate insulating layer and the first gate electrode extend into the substrate.

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