Semiconductor memory device and method for manufacturing semiconductor memory device

Abstract

The embodiment of the invention relates to a semiconductor memory device and a manufacturing method of the semiconductor memory device. A semiconductor memory device according to one embodiment of the present invention is provided with a laminate and a first wiring. The laminated body includes a plurality of first layers and a plurality of second layers. The first wiring extends in a first direction in the laminated body. Each of the plurality of first layers includes a second wiring, a capacitor electrode, a semiconductor layer, and a first protruding portion. The second wiring extends in a second direction that intersects the first direction. At least a portion of the semiconductor layer is disposed between the second wiring and the capacitor electrode. The first protruding portion protrudes from the second wiring in a third direction intersecting the first direction and the second direction, and covers at least a portion of the semiconductor layer from one side of the first direction.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor memory device and a method for manufacturing the semiconductor memory device. Background Art

[0002] A semiconductor memory device is proposed in which a plurality of capacitors are arranged three-dimensionally. Summary of the Invention

[0003] In one embodiment, a semiconductor memory device includes a laminate and a first wiring. The laminate includes a plurality of first layers and a plurality of second layers. The plurality of first layers and the plurality of second layers are alternately laminated layer by layer in a first direction. The first wiring extends in the laminate along the first direction. Each of the plurality of first layers includes a second wiring, a capacitor electrode, a semiconductor layer, a first protrusion, and a second protrusion. The second wiring extends along a second direction intersecting the first direction. At least a portion of the semiconductor layer is disposed between the second wiring and the capacitor electrode. The first protrusion protrudes from the second wiring in a third direction intersecting the first and second directions. The first protrusion covers at least a portion of the semiconductor layer from one side in the first direction. The second protrusion protrudes from the second wiring in the third direction. The second protrusion covers at least a portion of the semiconductor layer from the other side in the first direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 This is a perspective view showing a portion of the semiconductor memory device according to the first embodiment.

[0005] Figure 2 It is along Figure 1 sectional view of the semiconductor memory device shown in FIG. 1 along the line F2 - F2.

[0006] Figure 3 It is along Figure 1 sectional view of the semiconductor memory device shown in FIG. 1 along the line F3 - F3.

[0007] Figure 4 It is a perspective view for explaining the conductive layer of the first embodiment.

[0008] Figure 5 It is an enlarged representation Figure 4 A perspective view of the area surrounded by line F5 in the configuration shown in FIG.

[0009] Figure 6 It is a plan view for explaining the conductive layer of the first embodiment.

[0010] Figure 7 yes Figure 6 A cross-sectional view taken along line F7-F7 in the configuration shown in FIG.

[0011] Figure 8 It is a cross-sectional view showing a first example of the method for manufacturing the semiconductor memory device according to the first embodiment.

[0012] Figure 9 It is a cross-sectional view showing a first example of the method for manufacturing the semiconductor memory device according to the first embodiment.

[0013] Figure 10 It is a cross-sectional view showing a first example of the method for manufacturing the semiconductor memory device according to the first embodiment.

[0014] Figure 11 It is a cross-sectional view showing a first example of the method for manufacturing the semiconductor memory device according to the first embodiment.

[0015] Figure 12 It is a cross-sectional view showing a second example of the method for manufacturing the semiconductor memory device according to the first embodiment.

[0016] Figure 13 It is a cross-sectional view showing a second example of the method for manufacturing the semiconductor memory device according to the first embodiment.

[0017] Figure 14 This is a diagram showing a portion of a semiconductor memory device according to a first modification of the first embodiment.

[0018] Figure 15 This is a diagram showing a portion of a semiconductor memory device according to a second modification of the first embodiment.

[0019] Figure 16 This is a diagram showing a portion of a semiconductor memory device according to a third modification of the first embodiment.

[0020] Figure 17 It is a cross-sectional view showing a portion of the semiconductor memory device according to the second embodiment.

[0021] Figure 18 This is a cross-sectional view showing a portion of a semiconductor memory device according to a third embodiment. DETAILED DESCRIPTION

[0022] Hereinafter, semiconductor memory devices and methods for manufacturing semiconductor memory devices according to embodiments will be described with reference to the accompanying drawings. In the following description, components having identical or similar functions are denoted by identical reference numerals. Furthermore, duplicate descriptions of these components may be omitted. Furthermore, in the following description, reference numerals or letters may be omitted if they are followed by a suffix that makes them indistinguishable.

[0023] In this application, the terms are defined as follows. "Parallel", "orthogonal" or "same" may include "approximately parallel", "approximately orthogonal" or "approximately the same" respectively. "Connected" is not limited to mechanical connection, and may include electrical connection. That is to say, "connected" is not limited to the situation where multiple elements are directly connected, and may also include the situation where multiple elements are connected with other elements interposed therebetween. "Overlap" is not limited to the situation where multiple elements overlap by being in contact with each other, and may also include the situation where multiple elements are separated (the situation where the projected images of multiple elements overlap with each other when observed from a certain direction). "Adjacent" is not limited to the situation where multiple elements are adjacent by being in contact with each other, and may also include the situation where other elements are interposed between multiple elements and the multiple elements are adjacent.

[0024] The +X direction, -X direction, +Y direction, -Y direction, +Z direction, and -Z direction are defined as follows. The +X direction is the direction from the word line WL of the first laminate 20A described later toward the capacitor 50 (see Figure 1 ). The -X direction is the opposite direction of the +X direction. In the case where the +X direction and the -X direction are not distinguished, it is simply referred to as the X direction. The +Y direction is a direction that intersects (for example, is perpendicular to) the X direction. The +Y direction is the direction in which the word line WL extends (refer to Figure 1 ). The -Y direction is the opposite direction of the +Y direction. In the case where the +Y direction and the -Y direction are not distinguished, it is simply referred to as the Y direction. The +Z direction is a direction that intersects (for example, is orthogonal to) the X direction and the Y direction. The +Z direction is a direction from the semiconductor substrate 10 described later toward the laminate 20 (refer to Figure 1 ). The -Z direction is the opposite direction of the +Z direction. When the +Z direction and the -Z direction are not distinguished, they are simply referred to as the Z direction. The Z direction is an example of the "first direction". The Y direction is an example of the "second direction". The X direction is an example of the "third direction". In the following description, the +Z direction side is referred to as "upper" and the -Z direction side is referred to as "lower". However, these expressions are for convenience of explanation and do not specify the direction of gravity.

[0025] (First embodiment)

[0026] <1. Structure of a Semiconductor Memory Device>

[0027] Figure 1 It is a perspective view showing a portion of semiconductor memory device 1 . Figure 1 In order to make the internal structure of the semiconductor memory device 1 easier to understand, a portion of the upper layer side is deleted for illustration. In fact, the deleted portion also has the same structure as the other parts. Figure 1 The structure shown includes a plurality of the unit structures in each of the X direction and the Y direction as one unit structure.

[0028] The semiconductor memory device 1 is, for example, a DRAM (Dynamic Random Access Memory) having a three-dimensional structure. The semiconductor memory device 1 includes a plurality of memory cells arranged in three dimensions. The semiconductor memory device 1 includes, for example, a semiconductor substrate 10, a laminate 20, a plurality of bit lines BL, a plurality of body contacts BC, a common electrode 60, an insulating portion 71, an insulating portion 72, and an insulating portion 73. Figure 1 In FIG, only one of the plurality of bit lines BL is shown, and only one of the plurality of body contacts BC is shown.

[0029] <1.1 Semiconductor Substrate>

[0030] The semiconductor substrate 10 is, for example, a substrate serving as a base of the semiconductor memory device 1. At least a portion of the semiconductor substrate 10 is in a plate shape extending in the X and Y directions. The semiconductor substrate 10 is formed of, for example, a semiconductor material such as silicon.

[0031] <1.2 Laminated body>

[0032] Next, the laminate 20 will be described. The laminate 20 includes a first laminate 20A and a second laminate 20B. The first laminate 20A is arranged on the -X direction side relative to the common electrode 60. The second laminate 20B is arranged on the +X direction side relative to the common electrode 60. The first laminate 20A and the second laminate 20B have a symmetrical structure with the common electrode 60 as the center. Therefore, the structure of the first laminate 20A will be described below as a representative. The structure of the second laminate 20B can be changed by simply replacing "+X direction" with "-X direction" in the description related to the first laminate 20A.

[0033] Figure 2 It is along Figure 1 1 is a cross-sectional view taken along line F2-F2 of the semiconductor memory device 1 shown in FIG. The first stacked body 20A includes, for example, a plurality of first layers 21 and a plurality of second layers 22. The plurality of first layers 21 and the plurality of second layers 22 are alternately stacked layer by layer in the Z direction.

[0034] <1.2.1 Layer 1>

[0035] The first layer 21 is a layer extending along the X and Y directions. The first layer 21 includes, for example, a conductive layer 31, a semiconductor layer 32, a gate insulating film 33, and a capacitor 50. In this embodiment, the conductive layer 31, the semiconductor layer 32, the gate insulating film 33, and the capacitor 50 are located on the same layer within the laminate 20. The conductive layer 31, the semiconductor layer 32, the gate insulating film 33, and the capacitor 50 are arranged, for example, in the X direction.

[0036] (Conductive layer)

[0037] The conductive layer 31 is disposed between the insulating portion 71 described later and the semiconductor layer 32. The conductive layer 31 extends in the Y direction. The conductive layer 31 is made of a conductive material such as tungsten and has conductivity. The conductive layer 31 includes, for example, a word line WL and a pair of protrusions 42 (see FIG. 1 ). Figure 4 The pair of protrusions 42 will be described later.

[0038] Figure 3 It is along Figure 1 is a cross-sectional view of the semiconductor memory device 1 along the line F3-F3 shown in FIG. Word line WL is arranged between insulating portion 71 and semiconductor layer 32. Word line WL extends linearly in the Y direction. For example, word line WL extends in the Y direction, extending laterally across multiple capacitors 50. Current flows in the Y direction on word line WL. Word line WL is an example of a "second wiring."

[0039] (Semiconductor layer)

[0040] At least a portion (e.g., the entirety) of the semiconductor layer 32 is disposed between the word line WL and the capacitor 50. In this embodiment, at least a portion (e.g., the entirety) of the semiconductor layer 32 is disposed between the word line WL and the capacitor 50 in the X direction. The semiconductor layer 32 is adjacent to the word line WL in the X direction via the gate insulating film 33. The semiconductor layer 32 is adjacent to the capacitor 50 in the X direction.

[0041] The semiconductor layer 32 extends, for example, in the Y direction along the word line WL. In this embodiment, the width W32y of the semiconductor layer 32 in the Y direction is greater than the width (e.g., maximum width) W32x of the semiconductor layer 32 in the X direction. With respect to the Y direction, an insulating portion 72 is provided between the plurality of semiconductor layers 32. The plurality of semiconductor layers 32 are electrically insulated by the insulating portion 72. The semiconductor layer 32 includes a semiconductor material such as silicon (e.g., polycrystalline silicon). The semiconductor layer 32 may be doped with impurities. When a voltage is applied to the word line WL, the semiconductor layer 32 may form a channel (current path P, refer to FIG. 1 ). Figure 6 ) to electrically connect the bit line BL to the capacitor 50.

[0042] (Gate insulating film)

[0043] The gate insulating film 33 is disposed between the word line WL and the semiconductor layer 32. The gate insulating film 33 extends in the Y direction along the boundary between the word line WL and the semiconductor layer 32. The gate insulating film 33 is formed, for example, from a film containing silicon and oxygen. In this embodiment, the conductive layer 31, the semiconductor layer 32, and the gate insulating film 33 form a single MOS (metal oxide semiconductor) transistor for a DRAM.

[0044] (Capacitor)

[0045] The capacitor 50 is disposed between the semiconductor layer 32 and the common electrode 60. The capacitor 50 is a charge storage unit for the DRAM and includes, for example, a first capacitor electrode 51, a second capacitor electrode 52, and a capacitor dielectric layer 53.

[0046] A portion of the first capacitor electrode 51 is adjacent to the semiconductor layer 32 in the X direction and is connected to the semiconductor layer 32. For example, a portion of the first capacitor electrode 51 is in contact with the semiconductor layer 32 in the X direction. The first capacitor electrode 51 is formed of a metal material such as tungsten.

[0047] In this embodiment, the first capacitor electrode 51 includes a first portion 51a, a second portion 51b, and a third portion 51c. The first portion 51a is adjacent to the semiconductor layer 32 in the X direction. The first portion 51a is in contact with the semiconductor layer 32 (see FIG. Figure 7 ). The first portion 51a extends in the Z direction. The first portion 51a is a film along the Z and Y directions. The second portion 51b extends in the X direction from the end of the first portion 51a on the +Z direction side toward the common electrode 60. The second portion 51b is a film along the X and Y directions. The second portion 51b is in contact with the second layer 22 located on the +Z direction side relative to the capacitor 50. The third portion 51c extends in the X direction from the end of the first portion 51a on the -Z direction side toward the common electrode 60. The third portion 51c is a film along the X and Y directions. The third portion 51c is in contact with the second layer 22 located on the -Z direction side relative to the capacitor 50.

[0048] The second capacitor electrode 52 is connected to the common electrode 60 in the X direction. The second capacitor electrode 52 is formed of a metal material such as tungsten. At least a portion of the second capacitor electrode 52 faces the first capacitor electrode 51 in the Z direction. In this embodiment, the second capacitor electrode 52 is a film extending along the X and Y directions. The second capacitor electrode 52 is arranged in the Z direction between the second portion 51b and the third portion 51c of the first capacitor electrode 51. At least a portion of the second capacitor electrode 52 faces the second portion 51b and the third portion 51c of the first capacitor electrode 51 in the Z direction.

[0049] The capacitor dielectric layer 53 is provided between the first capacitor electrode 51 and the second capacitor electrode 52. In this embodiment, the capacitor dielectric layer 53 is provided between the first portion 51a of the first capacitor electrode 51 and the second capacitor electrode 52. The capacitor dielectric layer 53 is provided between the second portion 51b of the first capacitor electrode 51 and the second capacitor electrode 52. The capacitor dielectric layer 53 is provided between the third portion 51c of the first capacitor electrode 51 and the second capacitor electrode 52. The capacitor dielectric layer 53 is made of hafnium oxide (HfO x) and other dielectric materials.

[0050] <1.2.2 Layer 2>

[0051] The second layer 22 is an insulating layer extending along the X and Y directions. The second layer 22 is formed, for example, from a film containing silicon and oxygen. The second layer 22 is provided between two adjacent first layers 21 in the Z direction. The second layer 22 is an insulating layer (interlayer insulating film) that insulates the two first layers 21 from each other. In this embodiment, the second layer 22 overlaps with the conductive layer 31, the semiconductor layer 32, the gate insulating film 33, and the capacitor 50 when viewed from the Z direction.

[0052] <1.3 bit lines>

[0053] The bit line BL extends in the Z direction within the laminate 20. In this embodiment, the bit line BL is located on the opposite side of the semiconductor layer 32 in the X direction from the word line WL. The bit line BL is adjacent to the semiconductor layer 32 in the X direction. The bit line BL is connected to the semiconductor layer 32. For example, a portion of the bit line BL is in contact with the semiconductor layer 32 in the X direction. The bit line BL is made of a conductive material such as tungsten and has conductivity. Thus, by combining the word line WL and the bit line BL, a capacitor 50 can be arbitrarily selected from a plurality of capacitors 50 arranged three-dimensionally. The bit line BL is an example of a "first wiring."

[0054] In this embodiment, the bit line BL is formed in a cylindrical shape and has a circular outer shape when viewed from the Z direction. The edge 32e of the semiconductor layer 32 includes an arc portion 32c1 formed in an arc shape along the outer shape of the bit line BL.

[0055] <1.4 Main body contact>

[0056] The main body contact BC extends along the Z direction within the laminate 20. The main body contact BC extends parallel to the bit line BL. In the present embodiment, the main body contact BC is arranged at a position overlapping with at least a portion of the bit line BL when viewed from the Y direction. The main body contact BC is adjacent to the semiconductor layer 32 at least in the X direction. The main body contact BC is connected to the semiconductor layer 32. For example, a portion of the main body contact BC is in contact with the semiconductor layer 32 in the X direction. The main body contact BC includes a conductive material such as tungsten and has conductivity. The main body contact BC is a contact for suppressing the substrate floating effect. A specified potential is applied to the main body contact BC via a wiring not shown. The main body contact BC suppresses the semiconductor layer 32 from becoming electrically floating. The main body contact BC suppresses the accumulation of holes. The main body contact BC is an example of a "contact".

[0057] In this embodiment, the body contact BC is formed in a cylindrical shape. The body contact BC has a circular outer shape when viewed from the Z direction. The edge 32e of the semiconductor layer 32 includes an arc portion 32c2 formed in an arc shape along the outer shape of the body contact BC.

[0058] <1.5 Common Electrode>

[0059] The common electrode 60 is provided between the first laminate 20A and the second laminate 20B. The common electrode 60 extends in the Z direction within the laminate 20. The common electrode 60 extends in the Y direction between the first laminate 20A and the second laminate 20B. The common electrode 60 is a plate-shaped electrode extending in the Y and Z directions. The common electrode 60 is connected to the second capacitor electrode 52 of the capacitor 50 in the X direction.

[0060] <1.6 Insulation>

[0061] The semiconductor memory device 1 includes an insulating portion 71, an insulating portion 72, and an insulating portion 73 (see Figure 2 ). The insulating portion 71 is provided on the opposite side of the common electrode 60 relative to the conductive layer 31. The insulating portion 71 extends in the Z direction so as to penetrate the laminate 20. The insulating portion 71 reaches the semiconductor substrate 10. In addition, the insulating portion 71 extends in the Y direction. The insulating portion 72 is located on the opposite side of the conductive layer 31 relative to the semiconductor layer 32, the bit line BL, and the main body contact BC. The insulating portion 72 is provided between the semiconductor layer 32, the bit line BL, the main body contact BC, and the common electrode 60. The insulating portion 72 extends in the Z direction so as to penetrate the laminate 20. The insulating portion 72 reaches the semiconductor substrate 10. The insulating portion 73 is provided on the opposite side of the semiconductor substrate 10 relative to the laminate 20.

[0062] <2. Structure of the Conductive Layer>

[0063] Next, the configuration of the conductive layer 31 will be described.

[0064] Figure 4 It is a perspective view for explaining the conductive layer 31 . Figure 5 It is an enlarged representation Figure 4 A perspective view of the area surrounded by line F5 in the configuration shown in FIG. Figure 4 and Figure 5 In the figure, the gate insulating film 33 is omitted for the convenience of explanation. Figure 4 and Figure 5 The direction of strabismus Figure 1 different.

[0065] In the present embodiment, the conductive layer 31 includes, for example, a word line WL and a pair of protrusions 42 (a first protrusion 42A and a second protrusion 42B).

[0066] <2.1 Character Line>

[0067] The word line WL includes a first portion 41a and a second portion 41b. The first portion 41a extends along the Y direction (see FIG. Figure 3 The second portion 41b is provided in a region corresponding to the semiconductor layer 32 (refer to Figure 3 An insulating portion 72 is provided between the plurality of second portions 41b arranged in the Y direction. The plurality of second portions 41b are electrically insulated by the insulating portion 72. The second portion 41b extends from the first portion 41a toward the semiconductor layer 32. The second portion 41b is plate-shaped and extends in the X and Y directions.

[0068] The width W41by of the second portion 41b in the Y direction is equal to or greater than the width W32y of the semiconductor layer 32 in the Y direction (see Figure 6 In this embodiment, the width W41by of the second portion 41b in the Y direction is equal to the width W32y of the semiconductor layer 32 in the Y direction. Alternatively, the width W41by of the second portion 41b in the Y direction may be smaller than the width W32y of the semiconductor layer 32 in the Y direction. Furthermore, the word line WL may be formed from the first portion 41a without the second portion 41b. The word line WL is a gate electrode that faces the semiconductor layer 32 in the X direction.

[0069] <2.2 First protrusion>

[0070] The first protrusion 42A protrudes from a portion of the word line WL in the X direction. In this embodiment, the first protrusion 42A protrudes from a portion of the second portion 41b of the word line WL in the X direction. For example, the first protrusion 42A protrudes from a portion of the word line WL including the end on the +Z direction side in the X direction. The first protrusion 42A covers at least a portion of the semiconductor layer 32 from one side in the Z direction (the +Z direction side). The first protrusion 42A is one of the gate electrodes that faces the semiconductor layer 32 in the Z direction.

[0071] <2.3 Second protrusion>

[0072] The second protrusion 42B protrudes from the word line WL in the X direction. In this embodiment, the second protrusion 42B protrudes from a portion of the second portion 41b of the word line WL in the X direction. For example, the second protrusion 42B protrudes from a portion of the word line WL end that includes the -Z direction side in the X direction. The second protrusion 42B covers at least a portion of the semiconductor layer 32 from the other side in the Z direction (the -Z direction side). The second protrusion 42B is one of the gate electrodes that faces the semiconductor layer 32 in the Z direction.

[0073] Figure 6This is a top view for explaining the conductive layer 31. In this embodiment, when viewed from the Z direction, the shape of the first protrusion 42A and the shape of the second protrusion 42B are the same. Therefore, the first protrusion 42A and the second protrusion 42B will be collectively referred to as "protrusion 42" in the following description.

[0074] Protrusion 42 has an edge 42e in the X direction. Edge 42e is spaced apart from bit line BL, body contact BC, and capacitor 50. Edge 42e includes a first arc portion 42c1 and a second arc portion 42c2. First arc portion 42c1 is formed in an arc shape that follows the outline of bit line BL. First arc portion 42c1 is concentric with the outline of bit line BL. Second arc portion 42c2 is formed in an arc shape that follows the outline of body contact BC. Second arc portion 42c2 is concentric with the outline of body contact BC.

[0075] The protrusion 42 covers more than half of the semiconductor layer 32 when viewed in the Z direction. For example, the width W42y of the protrusion 42 in the Y direction is equal to or greater than the width W32y of the semiconductor layer 32 in the Y direction. In this embodiment, the width W42y of the protrusion 42 in the Y direction is equal to the width W32y of the semiconductor layer 32 in the Y direction. Alternatively, the width W42y of the protrusion 42 in the Y direction may be smaller than the width W32y of the semiconductor layer 32 in the Y direction.

[0076] When viewed in the Z direction, the semiconductor layer 32 includes a first portion 32a that overlaps with the protrusion 42 and a second portion 32b that does not overlap with the protrusion 42. In at least a portion of the semiconductor layer 32, a width W32ax in the X direction of the first portion 32a is greater than a width W32bx in the X direction of the second portion 32b.

[0077] Figure 7 yes Figure 6 is a cross-sectional view taken along line F7-F7 in the configuration shown in . In this embodiment, the width W32ax of the first portion 32a in the X direction is, for example, greater than the thickness (e.g., minimum thickness) T32z of the semiconductor layer 32 in the Z direction. The width W32bx of the second portion 32b in the X direction is, for example, less than the thickness (e.g., minimum thickness) T32z of the semiconductor layer 32 in the Z direction. In this embodiment, the width W42x of the protrusion 42 in the X direction is, for example, greater than the thickness (e.g., minimum thickness) T32z of the semiconductor layer 32 in the Z direction.

[0078] <3. Manufacturing Method>

[0079] <3.1 First Example of Manufacturing Method>

[0080] Next, a first example of a method for manufacturing semiconductor memory device 1 will be described.

[0081] Figures 8 to 11 1 is a cross-sectional view showing a first example of a method for manufacturing a semiconductor memory device 1. First, a laminate 120 (see FIG. 1 ) is formed on a semiconductor substrate 10. Figure 8 (a) in FIG. 1 ). The laminate 120 includes a plurality of first layers 121 and a plurality of second layers 122. The plurality of first layers 121 and the plurality of second layers 122 are alternately stacked layer by layer in the Z direction. The first layer 121 is formed of a semiconductor material including silicon (e.g., polycrystalline silicon). The first layer 121 may be doped with impurities. The first layer 121 forms the semiconductor layer 32 described later. The second layer 122 is formed of, for example, silicon germanium (SiGe). The second layer 122 is a sacrificial layer that is replaced by other layers in subsequent steps.

[0082] Next, a groove G1 is formed in the laminate 120 (see Figure 8 (b) in FIG. 1 ). The groove G1 penetrates the laminate 120 in the Z direction and reaches the semiconductor substrate 10. Next, etching through the groove G1 removes at least a portion (e.g., all) of each of the plurality of second layers 122. Thus, a first space S1 is formed in the laminate 120 instead of the second layer 122 (see FIG. 1 ). Figure 8 (c) in the figure.

[0083] Next, a first insulating material is supplied to the first space S1 through the groove G1 to form a first insulating layer 131 on the first layer 121. The first insulating layer 131 is formed of, for example, silicon nitride (SiN). Next, a second insulating material is supplied between the plurality of first insulating layers 131 through the groove G1 to form a second insulating layer 132 between the plurality of first insulating layers 131 (see FIG. Figure 8 (d) in FIG. 2 ). The second insulating layer 132 is formed of, for example, silicon oxide (SiO). The second insulating layer 132 is an insulating layer that becomes the second layer 22.

[0084] Next, a portion of the first layer 121 is removed by etching through the groove G1 (see Figure 9 (e) in FIG. 1 ). As a result, a second space S2 is formed in the layered body 120 instead of a portion of the first layer 121. The second space S2 is a space extending in the Y direction.

[0085] Next, a portion of the first insulating layer 131 is removed by etching through the groove G1 (see FIG. Figure 9 (f) in FIG. 1 ). As a result, a third space S3 is formed in the laminate 120 instead of a portion of the first insulating layer 131. The third space S3 protrudes in a direction (X direction) away from the groove G1 relative to the second space S2.

[0086] Next, an oxidant is supplied to the spaces S2 and S3 to oxidize the surface of the first layer 121 exposed in the spaces S2 and S3. Thus, a gate insulating film 33 (see FIG. 1 ) is formed on the surface of the first layer 121. Figure 9 (g) in the above). In the present application, “forming a gate insulating film on the surface of the first layer” may include a case where a portion of the first layer is converted into a gate insulating film by oxidizing the surface of the first layer.

[0087] Next, conductive material is supplied to the spaces S2 and S3 through the groove G1. Thus, word lines WL are formed in the second space S2 and a portion of the third space S3. A protrusion 42 (first protrusion 42A or second protrusion 42B) is formed in the other portion of the third space S3 (see FIG. Figure 9 (h) in the figure.

[0088] Next, an insulating material is supplied to the groove G1 to form an insulating portion 71 (see Figure 10 (i) in FIG. 1 ). Next, a groove G2 is formed in the laminate 120. The groove G2 penetrates the plurality of first layers 121, the plurality of first insulating layers 131, and the plurality of second insulating layers 132 along the Z direction and reaches the semiconductor substrate 10 (refer to FIG. 1 ). Figure 10 Next, a portion of the first layer 121 is removed by etching through the groove G2 (see Figure 10 (k) in FIG. 1 ). As a result, the remaining portion of the first layer 121 becomes the semiconductor layer 32 .

[0089] Next, a portion of the first insulating layer 131 is removed by etching through the groove G2 (see FIG. Figure 11 (1) in FIG. 1 ). Thus, a fourth space S4 is formed in the laminate 120 to replace a portion of the second insulating layer 132 and a portion of the first insulating layer 131. Next, the first capacitor electrode 51, the capacitor dielectric layer 53, and the second capacitor electrode 52 are sequentially formed inside the fourth space S4. Thus, the capacitor 50 is formed inside the fourth space S4. In addition, in the process of forming the second capacitor electrode 52, the interior of the groove G2 is buried with a conductive material. Thus, a common electrode 60 (see FIG. 1 ) is formed. Figure 10 (m) in FIG. 1 ). Thereafter, the bit line BL, the body contact BC, the insulating portion 72 and the insulating portion 73 are provided, and the semiconductor memory device 1 is completed.

[0090] <3.2 Second Example of Manufacturing Method>

[0091] Next, a second example of the method for manufacturing semiconductor memory device 1 will be described.

[0092] Figure 12 and Figure 13 1 is a cross-sectional view showing a second example of a method for manufacturing the semiconductor memory device 1. Figure 12 Steps (a) to (c) and references Figure 8 The manufacturing method described in steps (a) to (c) is the same as that in the first example. Therefore, description of these steps will be omitted.

[0093] In the second example of the manufacturing method, an oxidant is supplied to the first space S1 to oxidize the surface of the first layer 121 exposed in the first space S1. As a result, a portion of the gate insulating film 33 is formed on the surface of the first layer 121 (see FIG. Figure 12 (d') in.

[0094] Next, a conductive material is supplied to the first space S1 through the groove G1 to form a conductive layer 151 on the first layer 121. The first conductive layer 151 is formed of, for example, titanium nitride (TiN). Next, an insulating material is supplied between the plurality of first conductive layers 151 through the groove G1 to form an insulating layer 152 between the plurality of first conductive layers 151 (see FIG. Figure 13 (e') in FIG. 1 ). The insulating layer 152 is formed of, for example, silicon oxide (SiO). The insulating layer 152 is an insulating layer that becomes the second layer 22.

[0095] Next, a portion of the first layer 121 is removed by etching through the groove G1 (see Figure 13 (f')). Thus, in the laminate 120, a second space S2 is formed to replace a portion of the first layer 121. Next, an oxidizing agent is supplied to the second space S2 to oxidize the surface of the first layer 121 exposed in the second space S2. Thus, the remaining portion of the gate insulating film 33 is formed on the surface of the oxidized first layer 121 (refer to Figure 13 Then, the conductive material is supplied to the second space S2 through the groove G1. Thus, the second conductive layer 161 is formed in the second space S2 (refer to Figure 13 (h') in FIG. 1 ). In this embodiment, a word line WL is formed by a portion of the first conductive layer 151 and the second conductive layer 161. In addition, the protrusion 42 (the first protrusion 42A or the second protrusion 42B) is formed by another portion of the first conductive layer 151. The subsequent steps are the same as those in the reference numerals. Figure 10 and Figure 11 The same is true for the first example of the manufacturing method described above.

[0096] <4. Advantages>

[0097] As a first comparative example, consider a structure in which word lines WL are arranged above and below the semiconductor layer 32. According to the structure of the first comparative example, the pitch in the stacking direction becomes large, making it difficult to reduce the cell size.

[0098] As a second comparative example, consider a structure in which the semiconductor layer 32 is disposed lateral to the word line WL (a structure in which the gate electrode is disposed only on the side of the channel). In this second comparative example, the semiconductor layer 32 forming the channel is not covered by the gate electrode. Therefore, the semiconductor layer 32 is easily affected by the potential of other word lines WL adjacent in the +Z direction or -Z direction, potentially resulting in at least one of a decrease in on-state current and an increase in off-state leakage.

[0099] On the other hand, in this embodiment, the semiconductor memory device 1 includes a laminate 20 and a bit line BL. The laminate 20 includes a plurality of first layers 21 and a plurality of second layers 22. The plurality of first layers 21 and the plurality of second layers 22 are alternately stacked in the Z direction. The bit line BL extends in the Z direction within the laminate 20. Each of the plurality of first layers 21 includes a word line WL, a first capacitor electrode 51, a semiconductor layer 32, a first protrusion 42A, and a second protrusion 42B. The word line WL extends in the Y direction. The semiconductor layer 32 is arranged between the word line WL and the first capacitor electrode 51. The first protrusion 42A protrudes from the word line WL in the X direction and covers at least a portion of the semiconductor layer 32 from the +Z direction side. The second protrusion 42B protrudes from the word line WL in the X direction and covers at least a portion of the semiconductor layer 32 from the -Z direction side.

[0100] According to this structure, the word line WL and the semiconductor layer 32 are arranged in the same layer. Therefore, compared with the first comparative example, the spacing in the stacking direction can be reduced, and the cell size can be miniaturized. In addition, if the first protrusion 42A and the second protrusion 42B are provided, the semiconductor layer 32 is less susceptible to the potential of other word lines WL adjacent in the +Z direction or -Z direction than in the second comparative example. Therefore, while maintaining the cell size reduction structure, the interference between the upper and lower cells can be suppressed, and at least one of the increase in on-current and the reduction in off-leakage can be achieved. As a result, the electrical characteristics of the semiconductor memory device 1 can be improved. In addition, according to the above structure, the on-current increases due to the increase in gate width, so the semiconductor layer 32 can be made thinner.

[0101] In this embodiment, the width W42x of the first protrusion 42A in the X direction is greater than the thickness T32z of the semiconductor layer 32 in the Z direction. This configuration allows the first protrusion 42A to cover a relatively wide area of ​​the semiconductor layer 32. This further improves the electrical characteristics of the semiconductor memory device 1.

[0102] In this embodiment, the width W42y of the first protrusion 42A in the Y direction is equal to or greater than the width W32y of the semiconductor layer 32 in the Y direction. This configuration allows the first protrusion 42A to cover a relatively wide area of ​​the semiconductor layer 32. This further improves the electrical characteristics of the semiconductor memory device 1.

[0103] In this embodiment, the bit line BL has a circular outer shape when viewed from the Z direction. When viewed from the Z direction, the first protrusion 42A has an edge 42e. This edge 42e is separated from the bit line BL and includes an arc-shaped portion that follows the outer shape of the bit line BL. This configuration avoids interference with the bit line BL while allowing the first protrusion 42A to cover a relatively wide area of ​​the semiconductor layer 32. This further improves the electrical characteristics of the semiconductor memory device 1.

[0104] In this embodiment, semiconductor memory device 1 includes a body contact BC extending in the Z direction within laminate 20. Semiconductor layer 32 extends in the Y direction. Bit line BL is adjacent to semiconductor layer 32 at least in the X direction. Body contact BC is positioned so as to overlap at least a portion of bit line BL when viewed from the Y direction. Body contact BC is adjacent to semiconductor layer 32 at least in the X direction. This configuration allows for a smaller pitch between memory cells arranged in the X direction.

[0105] <5. Variations>

[0106] Next, several modified examples will be described. In each modified example, the configuration other than that described below is the same as that of the first embodiment.

[0107] <5.1 First Variation>

[0108] Figure 14 FIG3 is a diagram showing a portion of a semiconductor memory device 1 according to a first variation. In the first variation, semiconductor layer 32 extends in the X direction. Width W32x of semiconductor layer 32 in the X direction is greater than width W32y of semiconductor layer 32 in the Y direction.

[0109] The bit line BL is located on the +Y direction side relative to the semiconductor layer 32. The bit line BL is adjacent to the semiconductor layer 32 in the Y direction. The bit line BL is connected to the semiconductor layer 32. For example, at least a portion of the bit line BL is in contact with the semiconductor layer 32 in the Y direction.

[0110] The body contact BC is located on the +Y direction side relative to the semiconductor layer 32. The body contact BC is adjacent to the semiconductor layer 32 in the Y direction. The body contact BC is connected to the semiconductor layer 32. For example, at least a portion of the body contact BC is in contact with the semiconductor layer 32 in the Y direction. The body contact BC is arranged at a position that overlaps with at least a portion of the bit line BL when viewed from the X direction. The body contact BC is arranged between the bit line BL and the capacitor 50 in the X direction.

[0111] According to this configuration, the presence of protrusion 42 can improve the electrical characteristics of semiconductor memory device 1 .

[0112] <5.2 Second Modification>

[0113] Figure 15 FIG2 is a diagram showing a portion of a semiconductor memory device 1 according to a second variation. In the second variation, semiconductor layer 32 extends in the X direction. Width W32x of semiconductor layer 32 in the X direction is greater than width W32y of semiconductor layer 32 in the Y direction.

[0114] The bit line BL is located on the +Y direction side relative to the semiconductor layer 32. The bit line BL is adjacent to the semiconductor layer 32 in the Y direction. The bit line BL is connected to the semiconductor layer 32. For example, at least a portion of the bit line BL is in contact with the semiconductor layer 32 in the Y direction.

[0115] The body contact BC is located on the -Y direction side relative to the semiconductor layer 32. The body contact BC is adjacent to the semiconductor layer 32 in the Y direction. The body contact BC is connected to the semiconductor layer 32. For example, at least a portion of the body contact BC is in contact with the semiconductor layer 32 in the Y direction. The body contact BC is located on the opposite side of the semiconductor layer 32 from the bit line BL in the Y direction. The body contact BC is disposed between the bit line BL and the capacitor 50 in the X direction.

[0116] According to this configuration, the presence of protrusion 42 can improve the electrical characteristics of semiconductor memory device 1 .

[0117] <5.3 Third Variation>

[0118] Figure 16 This diagram shows a portion of a semiconductor memory device 1 according to a third variation. In the third variation, semiconductor layer 32 extends in the X direction. The width W32x of semiconductor layer 32 in the X direction is greater than the width W32y of semiconductor layer 32 in the Y direction. Bit line BL is arranged so as to correspond to the center of semiconductor layer 32 in the X direction when viewed from the Z direction. Bit line BL penetrates semiconductor layer 32 in the Z direction.

[0119] According to this configuration, the presence of protrusion 42 can improve the electrical characteristics of semiconductor memory device 1 .

[0120] (Second embodiment)

[0121] Next, the second embodiment will be described. The second embodiment differs from the first embodiment in that the second layer 22 includes a capacitor electrode 202. The configuration other than that described below is the same as that of the first embodiment.

[0122] Figure 17 This diagram shows a portion of the semiconductor memory device 1 according to the second embodiment. In this embodiment, each of the plurality of second layers 22 includes, for example, an insulating layer 201 , a capacitor electrode 202 , and a capacitor dielectric layer 203 .

[0123] The insulating layer 201 is provided in a portion of the second layer 22 that is separate from the capacitor electrode 202 and the capacitor dielectric layer 203. For example, the insulating layer 201 is provided between the capacitor electrode 202 and the insulating portion 72. Furthermore, the insulating layer 201 is provided between the capacitor dielectric layer 203 and the insulating portion 72. The insulating layer 201 is formed of an insulating material such as silicon oxide (SiO), for example.

[0124] The capacitor electrode 202 is connected to the common electrode 60 in the X direction. The capacitor electrode 202 is formed of a metal material such as tungsten. At least a portion of the capacitor electrode 202 faces the first capacitor electrode 51 in the Z direction. In this embodiment, the capacitor electrode 202 is a film extending along the X and Y directions. The capacitor electrode 202 is arranged between the third portion 51c and the second portion 51b. The third portion 51c is the portion of the first capacitor electrode 51 located on the +Z direction side. The second portion 51b is the portion of the first capacitor electrode 51 located on the -Z direction side. The capacitor electrode 202 faces the third portion 51c of the first capacitor electrode 51 located on the +Z direction side in the Z direction. Furthermore, the capacitor electrode 202 faces the second portion 51b of the first capacitor electrode 51 located on the -Z direction side in the Z direction.

[0125] The capacitor dielectric layer 203 is provided between the capacitor electrode 202 and the first capacitor electrode 51. In this embodiment, the capacitor dielectric layer 203 is provided between the capacitor electrode 202 and the third portion 51c of the first capacitor electrode 51 located on the +Z direction side. In addition, the capacitor dielectric layer 203 is provided between the capacitor electrode 202 and the second portion 51b of the first capacitor electrode 51 located on the -Z direction side. The capacitor dielectric layer 203 is made of hafnium oxide (HfO x) or other dielectric materials. In this embodiment, the capacitor electrode 202 and the capacitor dielectric layer 203 form a portion of the capacitor 50. In this embodiment, the first capacitor electrode 51, the capacitor electrode 202, and the capacitor dielectric layer 203 form a single charge storage unit.

[0126] According to this configuration, the electrical characteristics of semiconductor memory device 1 can be improved by including protrusion 42. Furthermore, while capacitor 50 includes capacitor electrode 202 and capacitor dielectric layer 203, it may not include second capacitor electrode 52 and capacitor dielectric layer 53.

[0127] (Third embodiment)

[0128] Next, the third embodiment will be described. The third embodiment differs from the first embodiment in that the bit line BL, semiconductor layer 32, and capacitor 50 are arranged in the Y direction. The configuration other than that described below is the same as that of the first embodiment.

[0129] Figure 18 FIG. 1 is a diagram showing a portion of a semiconductor memory device 1 according to a third embodiment. Figure 18 For ease of explanation, the second layer 22 is omitted. The structure of the first layer 21 is captured and enlarged. In this embodiment, the bit line BL extends along the Z direction. Each of the plurality of first layers 21 includes, for example, a conductive layer 31, a semiconductor layer 32, and a capacitor 50. A portion of the bit line BL, the semiconductor layer 32, and the capacitor 50 are arranged in the Y direction.

[0130] The conductive layer 31 includes, for example, a word line WL, a wiring 301, and a pair of protrusions 42. The word line WL extends in the X direction. The wiring 301 branches from the word line WL and extends in the Y direction. A portion of the wiring 301 faces the semiconductor layer 32 in the X direction. The wiring 301 is an example of a "second wiring." The wiring 301 is a gate electrode facing the semiconductor layer 32 in the X direction. In addition, in this application, "at least a portion of the semiconductor layer is arranged between the second wiring and the capacitor" means, for example, Figure 18 As shown in the example, there may be a case where the second wiring (eg, wiring 301 ) and the capacitor 50 are adjacent to the semiconductor layer 32 from different directions.

[0131] The first protrusion 42A protrudes from the wiring 301 in the X direction. For example, the first protrusion 42A protrudes in the X direction from a portion of the wiring 301 including the end on the +Z direction side. The first protrusion 42A covers at least a portion of the semiconductor layer 32 from one side in the Z direction (the +Z direction side). The first protrusion 42A is one of the gate electrodes that faces the semiconductor layer 32 in the Z direction.

[0132] The second protrusion 42B protrudes from the wiring 301 in the X direction. For example, the second protrusion 42B protrudes in the X direction from a portion of the wiring 301 including the end on the -Z direction side. The second protrusion 42B covers at least a portion of the semiconductor layer 32 from the other side (-Z direction side) in the Z direction. The second protrusion 42B is one of the gate electrodes that faces the semiconductor layer 32 in the Z direction.

[0133] According to this configuration, the presence of protrusion 42 can improve the electrical characteristics of semiconductor memory device 1 .

[0134] Although several embodiments and variations have been described above, the embodiments and variations are not limited to the embodiments described above. For example, the embodiments and variations described above may be implemented in combination with each other.

[0135] According to at least one embodiment described above, a semiconductor memory device includes a laminate and a first wiring. The laminate includes a plurality of first layers and a plurality of second layers. The plurality of first layers and the plurality of second layers are alternately stacked in a first direction. The first wiring extends within the laminate along the first direction. Each of the plurality of first layers includes a second wiring, a capacitor electrode, a semiconductor layer, a first gate electrode, and a second gate electrode. The second wiring extends along a second direction intersecting the first direction. The semiconductor layer is disposed between the second wiring and the capacitor electrode in a third direction intersecting the first and second directions. The first gate electrode is connected to the second wiring in the third direction and covers at least a portion of the semiconductor layer from one side in the first direction. The second gate electrode is connected to the second wiring in the third direction and covers at least a portion of the semiconductor layer from the other side in the first direction. This configuration can improve the electrical characteristics of the semiconductor memory device.

[0136] Although several embodiments of the present invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways and can be omitted, replaced, or modified in various ways without departing from the scope of the invention. These embodiments or their variations are also included in the scope or spirit of the invention and are included in the invention described in the patent application and its equivalents.

[0137] [Explanation of Symbols]

[0138] 1 Semiconductor memory device

[0139] 20 laminated body

[0140] 21 Level 1

[0141] 22 Level 2

[0142] 31 conductive layer

[0143] 32 semiconductor layer

[0144] 33 Gate insulating film

[0145] 42A 1st protrusion

[0146] 42B Second protrusion

[0147] 42e Edge

[0148] 42c1 arc part

[0149] 42c2 arc part

[0150] 50 capacitors

[0151] 51 1st capacitor electrode

[0152] 52 Second capacitor electrode

[0153] 53 capacitor dielectric layer

[0154] 60 common electrode

[0155] 121 1st floor

[0156] 122 2nd Floor

[0157] 131 First insulation layer

[0158] 132 Second insulation layer

[0159] 151 1st conductive layer

[0160] 152 insulation layer

[0161] 161 Second conductive layer

[0162] WL word line (second wiring)

[0163] BL bit line (first wiring)

[0164] BC body contact (contact)

[0165] S1 Space 1

[0166] S2 Second Space

[0167] S3 The third space.

Claims

1. A semiconductor memory device comprising: A layered body comprising a plurality of first layers and a plurality of second layers, wherein the plurality of first layers and the plurality of second layers are alternately stacked layer by layer in a first direction; and a first wiring extending in the first direction within the laminate; and Each of the plurality of layer 1s comprises: a second wiring extending in a second direction intersecting the first direction; capacitor electrodes; a semiconductor layer, at least a portion of which is disposed between the second wiring and the capacitor electrode; a first protrusion protruding from the second wiring in a third direction intersecting the first direction and the second direction, and covering at least a portion of the semiconductor layer from one side in the first direction; and The second protrusion protrudes from the second wiring in the third direction and covers at least a portion of the semiconductor layer from the other side in the first direction.

2. The semiconductor memory device according to claim 1, wherein At least a portion of the semiconductor layer is arranged between the second wiring and the capacitor electrode in the third direction.

3. The semiconductor memory device according to claim 1 or claim 2, wherein A width of the first protrusion in the third direction is greater than a thickness of the semiconductor layer in the first direction.

4. The semiconductor memory device according to claim 1 or claim 2, wherein The width of the first protrusion in the second direction is equal to or greater than the width of the semiconductor layer in the second direction.

5. The semiconductor memory device according to claim 1 or claim 2, wherein The width of the semiconductor layer in the second direction is greater than the width of the semiconductor layer in the third direction.

6. The semiconductor memory device according to claim 1 or claim 2, wherein When viewed from the first direction, The first wiring has a circular shape; and The first protrusion has an edge that is spaced apart from the first wiring and includes an arc-shaped portion along the outer shape of the first wiring.

7. The semiconductor memory device according to claim 1 or claim 2, further comprising: The contact extends in the first direction within the laminate; and The first wiring is adjacent to the semiconductor layer at least in the third direction; The contact is arranged at a position overlapping with at least a portion of the first wiring when viewed from the second direction, and is adjacent to the semiconductor layer at least in the third direction.

8. The semiconductor memory device according to claim 1 or claim 2, further comprising: The contact extends in the first direction within the laminate; and The first wiring is adjacent to the semiconductor layer at least in the second direction; The contact is adjacent to the semiconductor layer at least in the second direction.

9. A method for manufacturing a semiconductor memory device, the method Alternatingly stacking a first layer and a second layer including silicon in a first direction to form a laminate; A groove extending in the first direction is formed in the laminate; Etching through the groove to remove at least a portion of the second layer to form a first space in the laminate; forming a first insulating layer on the first layer in the first space; forming a second insulating layer on the first insulating layer in the first space; Etching through the groove to remove a portion of the first layer and form a second space in the laminate extending in a second direction intersecting the first direction; Etching through the groove to remove a portion of the first insulating layer to form a third space in the laminate, the third space protruding in a third direction away from the groove relative to the second space; and A conductive material is supplied to the second space and the third space to form wiring, and a protrusion is formed that protrudes from the wiring in the third direction and covers at least a portion of the first layer in the first direction.

10. A method for manufacturing a semiconductor memory device, the method Alternatingly stacking a first layer and a second layer including silicon in a first direction to form a laminate; A groove extending in the first direction is formed in the laminate; Etching through the groove to remove at least a portion of the second layer to form a first space in the laminate; forming a gate insulating film on a surface of the first layer; forming a first conductive layer on the gate insulating film in the first space; forming an insulating layer on the first conductive layer in the first space; Etching through the groove to remove a portion of the first layer and form a second space in the laminate extending in a second direction intersecting the first direction; and A conductive material is supplied to the second space to form a second conductive layer in the second space, a wiring is formed by a portion of the first conductive layer and the second conductive layer, and a protrusion is formed by another portion of the first conductive layer, which protrudes from the wiring in a third direction away from the groove and covers at least a portion of the first layer in the first direction.

Images