Semiconductor device and data storage system including the same

Abstract

A semiconductor device and a data storage system including the same are provided. The semiconductor device includes a first semiconductor structure including a lower interconnect structure electrically connected to a circuit device and a capacitor structure spaced apart from the lower interconnect structure; and a second semiconductor structure including a memory cell array. The capacitor structure includes: a first electrode structure including first electrodes spaced apart from each other in a first direction parallel to an upper surface of the substrate and extending in a vertical direction and a second direction crossing the first direction; and a second electrode structure including second electrodes alternately arranged with the first electrodes and extending in the second direction. The first electrode and the second electrode each include a first wall pattern having a first side surface and a second wall pattern having a second side surface extending from the first side surface. The side surface profile varies non-linearly at a boundary between the first side surface and the second side surface.

Description

Technical Field

[0001] Some example embodiments of the present disclosure relate to a semiconductor device and a data storage system including the semiconductor device. Background Art

[0002] Semiconductor devices capable of storing large amounts of data in data storage systems requiring data storage have been in demand. Consequently, methods for increasing the data storage capacity of semiconductor devices have been studied. Furthermore, semiconductor devices with increased integration density have been in demand. For example, as a method for increasing the integration density of semiconductor devices, semiconductor devices including vertically arranged memory cells and peripheral circuit regions have been proposed. Summary of the Invention

[0003] Some example embodiments of the present disclosure provide a semiconductor device including a capacitor structure having improved integration density and reliability, and a data storage system including the semiconductor device.

[0004] Some example embodiments of the present disclosure provide a semiconductor device comprising: a first semiconductor structure including a substrate, a circuit device on the substrate, a lower interconnect structure electrically connected to the circuit device, and a capacitor structure spaced apart from the lower interconnect structure; and a second semiconductor structure including a plate layer on the first semiconductor structure, the second semiconductor structure including gate electrodes spaced apart from each other and stacked in sequence in a vertical direction perpendicular to an upper surface of the plate layer, and a channel structure penetrating the gate electrodes and extending in the vertical direction. The capacitor structure includes: a first electrode structure including first electrodes spaced apart from each other in a first direction parallel to the upper surface of the substrate, the first electrodes extending in the vertical direction and in a second direction intersecting the first direction; and a second electrode structure including second electrodes arranged alternately with the first electrodes along the first direction, the second electrodes extending in the second direction. The first and second electrodes each include a first wall pattern having a first side surface and a second wall pattern having a second side surface extending from the first side surface. The side surface profiles of the first and second electrodes change nonlinearly at the boundary between the first and second side surfaces.

[0005] Some example embodiments of the present disclosure also provide a semiconductor device comprising: a first lower electrode structure on a substrate, the first lower electrode structure comprising first lower electrodes and a first lower connecting portion, the first lower electrodes being spaced apart from each other in a first direction parallel to an upper surface of the substrate and extending in a second direction intersecting the first direction, the first lower connecting portion connecting the first lower electrodes to each other and extending in the first direction; a second lower electrode structure comprising second lower electrodes and a second lower connecting portion, the second lower electrodes being arranged alternately with the first lower electrodes along the first direction, the second lower connecting portion connecting the second lower electrodes to each other and extending in the first direction; a first insulating layer disposed between the first lower electrode structure and the second lower electrode structure. Between the lower electrode structures; a first intermediate electrode structure comprising a first intermediate electrode and a first intermediate connecting portion, the first intermediate electrode being on the first lower electrode, the first intermediate connecting portion connecting the first intermediate electrodes to each other and extending in a first direction, the first intermediate connecting portion vertically overlapping the second lower connecting portion; a second intermediate electrode structure comprising a second intermediate electrode and a second intermediate connecting portion, the second intermediate electrode being on the second lower electrode, the second intermediate connecting portion connecting the second intermediate electrodes to each other and extending in the first direction, the second intermediate connecting portion vertically overlapping the first lower connecting portion; and a second insulating layer between the first and second intermediate electrode structures. The first and second intermediate electrodes each include a first wall pattern having a first side surface and a second wall pattern having a second side surface extending from the first side surface. The side surface profiles of the first and second intermediate electrodes change nonlinearly at the boundary between the first and second side surfaces.

[0006] Some example embodiments of the present disclosure also provide a data storage system comprising: a semiconductor memory device including a circuit device, a memory cell, a capacitor structure, and an input / output pad on a substrate; and a controller for controlling the semiconductor memory device, the controller being electrically connected to the semiconductor memory device via the input / output pad. The capacitor structure comprises: a first electrode structure including first electrodes and a first connecting portion, the first electrodes being spaced apart from each other in a first direction parallel to the upper surface of the substrate and extending in a second direction intersecting the first direction, the first connecting portion connecting the first electrodes to each other and extending in the first direction; a second electrode structure including second electrodes and a second connecting portion, the second electrodes being arranged alternately with the first electrodes along the first direction and extending in the second direction, the second connecting portion connecting the second electrodes to each other and extending in the first direction; and an insulating layer between the first electrode structure and the second electrode structure. The first electrode and the second electrode each include a first wall pattern having a first side surface and a second wall pattern having a second side surface extending from the first side surface. The lower surface of the first connecting portion and the lower surface of the second connecting portion are at a higher level than the lower surface of the first wall pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The above and other aspects, features and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0008] Figure 1A is a block diagram illustrating a semiconductor device according to some example embodiments of the present disclosure;

[0009] Figure 1B is a circuit diagram illustrating a charge pump circuit included in a voltage generator of a semiconductor device according to some example embodiments of the present disclosure;

[0010] Figure 1C is a perspective view illustrating a semiconductor device according to some example embodiments of the present disclosure;

[0011] Figure 2A is a perspective view illustrating a capacitor structure of a semiconductor device according to some example embodiments of the present disclosure;

[0012] Figure 2B Some example embodiments of the present disclosure are described Figure 2A a plan view of a first lower electrode structure and a second lower electrode structure of a capacitor structure;

[0013] Figure 2C Some example embodiments of the present disclosure are described Figure 2A A plan view of a first electrode structure and a second electrode structure of a capacitor structure;

[0014] Figure 3 is a description Figure 2B and Figure 2C A cross-sectional view of the capacitor structure taken along line II';

[0015] Figure 4A is a perspective view illustrating a lower interconnect structure of a semiconductor device according to some example embodiments of the present disclosure;

[0016] Figure 4B Some example embodiments of the present disclosure are described Figure 4A A plan view of the lower interconnection structure in FIG;

[0017] Figure 5 Some example embodiments of the present disclosure are described Figure 4B A cross-sectional view of the lower interconnect structure taken along line II-II';

[0018] Figure 6A is a perspective view illustrating a capacitor structure of a semiconductor device according to some example embodiments of the present disclosure;

[0019] Figure 6B Some example embodiments of the present disclosure are described Figure 6A a plan view of a first upper electrode structure and a second upper electrode structure of a capacitor structure;

[0020] Figure 7 Some example embodiments of the present disclosure are described Figure 6B A cross-sectional view of the capacitor structure taken along line III-III';

[0021] Figure 8A is a perspective view illustrating a lower interconnect structure of a semiconductor device according to some example embodiments of the present disclosure;

[0022] Figure 8B Some example embodiments of the present disclosure are described Figure 8A A plan view of the lower interconnection structure in FIG;

[0023] Figure 9 Some example embodiments of the present disclosure are described Figure 8B A cross-sectional view of the lower interconnect structure taken along line IV-IV';

[0024] Figure 10 is a cross-sectional view illustrating a semiconductor device according to some example embodiments of the present disclosure;

[0025] Figure 11A 、 Figure 11B 、 Figure 11C 、 Figure 11D 、 Figure 11E 、 Figure 11F and Figure 11G are diagrams describing a method of manufacturing a semiconductor device according to some example embodiments of the present disclosure; and

[0026] Figure 12 are diagrams illustrating a data storage system including a semiconductor device according to some example embodiments. DETAILED DESCRIPTION

[0027] Hereinafter, embodiments of the present disclosure will be described as follows with reference to the accompanying drawings.

[0028] When the terms "about" or "substantially" are used in conjunction with a numerical value in this specification, it is intended that the relevant numerical value include a manufacturing tolerance or operating tolerance (e.g., ±10%) around the stated numerical value. In addition, when the words "approximately" and "substantially" are used in conjunction with a geometric shape, it is intended that the geometric shape is not required to be precise, but rather that the tolerance of the shape is within the scope of the present disclosure. In addition, regardless of whether a numerical value or shape is modified as "about" or "substantially", it will be understood that these values ​​and shapes should be interpreted as including a manufacturing tolerance or operating tolerance (e.g., ±10%) around the stated numerical value or shape. When a range is specified, the range includes all values ​​therebetween, such as increments of 0.1%.

[0029] In addition, for example, "at least one of A, B, and C" and similar language (e.g., "at least one selected from the group consisting of A, B, and C") may be interpreted as only A, only B, only C, or any combination of two or more of A, B, and C, such as, for example, ABC, AB, BC, and AC.

[0030] Figure 1A is a block diagram illustrating a semiconductor device according to some example embodiments.

[0031] Reference Figure 1A , the semiconductor device 10 may include a memory cell array 20 and a peripheral circuit 30. The semiconductor device 10 may be configured as a memory device, for example, a nonvolatile memory such as a flash memory, or a volatile memory such as a dynamic random access memory (DRAM), a static random access memory (SRAM), etc.

[0032] The memory cell array 20 may include a plurality of memory cells. The plurality of memory cells may be connected to a row decoder 33 via a plurality of word lines WL, and may be connected to a read / write circuit 35 via a bit line BL. In some example embodiments, a plurality of memory cells arranged along the same row may be connected to the same word line WL, and a plurality of memory cells arranged along the same column may be connected to the same bit line BL. In some example embodiments, a plurality of memory blocks may be included, each of which may include a plurality of memory cells.

[0033] The peripheral circuit 30 may receive an address ADDR, a command CMD, and a control signal CTRL from an entity external to the semiconductor device 10, and may transmit and receive data DATA to and from an external device of the semiconductor device 10. The peripheral circuit 30 may include a row decoder 33, a read / write circuit 35, control logic (e.g., a circuit) 37, and a voltage generator 38 that generates various voltages required for operation. In some example embodiments, the peripheral circuit 30 may further include various sub-circuits such as an input / output circuit and an error correction circuit for correcting errors in the data DATA read out from the memory cell array 20.

[0034] The control logic 37 may be connected to the row decoder 33, the voltage generator 38, and the input / output circuit (not shown). The control logic 37 may control the overall operation of the semiconductor device 10. The control logic 37 may generate various internal control signals used in the semiconductor device 10 in response to the control signal CTRL. For example, when performing a memory operation such as a program operation or an erase operation, the control logic 37 may adjust the voltage levels provided by the word line WL and the bit line BL.

[0035] The row decoder 33 may select a portion of the plurality of memory cells in response to the address ADDR and may select at least one word line WL. The row decoder 33 may transfer a voltage for performing a memory operation to the selected word line WL.

[0036] The read / write circuit 35 can be connected to the memory cell array 20 through the bit line BL. The read / write circuit 35 may include a write driver or a sense amplifier. For example, during a program operation, the read / write circuit 35 may operate as a write driver to apply a voltage according to the data DATA to be stored in the memory cell array 20 to the bit line BL. During a read operation, the read / write circuit 35 may operate as a sense amplifier and may detect the data DATA stored in the memory cell array 20.

[0037] The voltage generator 38 may include a controller 52 , an oscillator 54 , and a charge pump circuit 56 .

[0038] The charge pump circuit 56 may include a plurality of charge pump circuits, each of which may include at least one switching device and at least one pumping capacitor. The charge pump circuit 56 may provide current through the row decoder 33 to apply an operating voltage to the word line WL of the memory cell array 20.

[0039] The controller 52 may control the operation of the oscillator 54. For example, the controller 52 may determine a selected charge pump circuit among a plurality of charge pump circuits based on at least one of PVT (process, voltage, and temperature) data of the semiconductor device 10 and a target level of a power supply voltage to be supplied. The controller 52 may deactivate charge pump circuits other than the selected charge pump circuit.

[0040] The oscillator 54 may output a clock signal CLK. The oscillator 54 may operate in response to a control signal VGC from the controller 52. For example, the oscillator 54 may output the clock signal CLK to at least a portion of the plurality of charge pump circuits in response to the control signal VGC sent by the controller 52.

[0041] Figure 1B is a circuit diagram illustrating a charge pump circuit included in a voltage generator of a semiconductor device according to some example embodiments.

[0042] Reference Figure 1B The charge pump circuit 56a may include a plurality of diodes DI, a plurality of pumping capacitors CAP1, and an output capacitor CAP2. The plurality of diodes DI may be connected in series with each other, and the plurality of pumping capacitors CAP1 may be connected to a node between the plurality of diodes DI. The first diode may receive a power supply voltage VCC having a desired (and / or optionally, predetermined) level, and the last diode may emit an output current IOUT to an output node.

[0043] Each of the plurality of pumping capacitors CAP1 can be charged or discharged by the clock signal CLK or the complementary clock signal CLKB, which is phase-shifted by an inverter to have a phase opposite to that of the clock signal CLK. For example, odd-numbered pumping capacitors CAP1 can be charged or discharged by the clock signal CLK, and even-numbered pumping capacitors CAP1 can be charged or discharged by the complementary clock signal CLKB.

[0044] Figure 1C is a perspective view illustrating a semiconductor device according to some example embodiments.

[0045] Reference Figure 1C The semiconductor device 10 may include a peripheral circuit structure PERI which may be a first semiconductor structure and a memory cell structure CELL which may be a second semiconductor structure. The memory cell structure CELL may be disposed on the peripheral circuit structure PERI. The memory cell structure CELL may be configured such that Figure 1A In the region of the memory cell array 20, the peripheral circuit structure PERI may be configured to set Figure 1AIn some example embodiments, the memory cell structure CELL may be optionally disposed below the peripheral circuit structure PERI.

[0046] The memory cell structure CELL may include a first region R1 and a second region R2 .

[0047] The first region R1 of the memory cell structure CELL may be configured as a region in which the memory cell array 20 is disposed. The second region R2 of the memory cell structure CELL may correspond to a region for electrically connecting the memory cells of the memory cell array 20 to the peripheral circuit 30. The second region R2 may be disposed on at least one end of the first region R1 in at least one direction (e.g., a first direction (X direction)).

[0048] Figure 1A and Figure 1B The plurality of pumping capacitors CAP1 included in the charge pump circuits 56 and 56a in the peripheral circuit structure PERI may be provided in the peripheral circuit structure PERI. For example, the plurality of pumping capacitors CAP1 may be provided below the second region R2 of the memory cell structure CELL in the peripheral circuit structure PERI, but some example embodiments are not limited thereto. In some example embodiments, the plurality of pumping capacitors CAP1 may be provided below the first region R1 of the memory cell structure CELL.

[0049] Figure 2A is a perspective view illustrating a capacitor structure of a semiconductor device according to some example embodiments. Figure 2B is a description of some example embodiments Figure 2A A plan view of a first lower electrode structure and a second lower electrode structure of a capacitor structure in FIG. Figure 2C is a description of some example embodiments Figure 2A A plan view of a first electrode structure and a second electrode structure of a capacitor structure. Figure 3 is a description Figure 2B and Figure 2C A cross-sectional view of the capacitor structure in FIG. 1 taken along line II′.

[0050] Reference Figures 2A to 3 The capacitor structure 200 may include a first lower electrode structure 210B and a second lower electrode structure 220B, a first electrode structure 210 and a second electrode structure 220 disposed on the first lower electrode structure 210B and the second lower electrode structure 220B, a first insulating layer IL0 disposed between the first lower electrode structure 210B and the second lower electrode structure 220B, and a second insulating layer IL1 disposed between the first electrode structure 210 and the second electrode structure 220.

[0051] The capacitor structure 200 may be formed as shown above. Figures 1A to 1C The pumping capacitor CAP1 of the charge pump circuits 56 and 56a is depicted.

[0052] The first lower electrode structure 210B and the second lower electrode structure 220B may be disposed on the substrate 201. The first lower electrode structure 210B and the second lower electrode structure 220B may have different potentials.

[0053] The first lower electrode structure 210B may include a first lower connection portion BCP1 connecting the first lower electrodes ML0a to each other and extending in a first direction (X direction). The first lower electrode ML0a may have a linear shape protruding from the first lower connection portion BCP1 and extending in a second direction (Y direction). The first lower electrode ML0a may be included in a first finger portion FP1 branching from the first lower connection portion BCP1.

[0054] The second lower electrode structure 220B may include a second lower connection portion BCP2 that connects the second lower electrodes ML0b to each other and extends in the first direction (X direction). The second lower electrode ML0b may have a linear shape that protrudes and extends from the second lower connection portion BCP2 in the second direction (Y direction). The second lower electrode ML0b may be included in a second finger portion FP2 that branches from the second lower connection portion BCP2.

[0055] The second lower electrodes ML0b may be alternately disposed with the first lower electrodes ML0a. The second lower connection portion BCP2 may be spaced apart from the first lower connection portion BCP1 in the second direction (Y direction). In some example embodiments, a blocking conductive film MB0 may be disposed between the first lower electrode ML0a and the first insulating layer IL0, and between the second lower electrode ML0b and the first insulating layer IL0. For example, the blocking conductive film MB0 may cover the side surface and bottom surface of the first lower electrode ML0a, and may cover the side surface and bottom surface of the second lower electrode ML0b.

[0056] The first lower electrode ML0a, the second lower electrode ML0b, and the first insulating layer IL0 disposed therebetween may constitute or form a capacitor. The capacitor formed by the first lower electrode ML0a, the second lower electrode ML0b, and the first insulating layer IL0 may have a capacitance C0.

[0057] The first electrode structure 210 and the second electrode structure 220 may be disposed on the first lower electrode structure 210B and the second lower electrode structure 220B. The first electrode structure 210 and the second electrode structure 220 may have different potentials. In some example embodiments, the first electrode structure 210 may be referred to as a first intermediate electrode structure, and the second electrode structure 220 may be referred to as a second intermediate electrode structure.

[0058] The first electrode structure 210 may include first electrodes MC1a and ML1a, and a first connection portion CP1 connecting the first electrodes MC1a and ML1a to each other and extending in a first direction (X direction). The first electrodes MC1a and ML1a may have a linear shape that protrudes from and extends from the first connection portion CP1 in a second direction (Y direction). The first electrodes MC1a and ML1a may be included in a first finger portion FP1 branching from the first connection portion CP1. In some example embodiments, the first electrodes MC1a and ML1a may overlap with the first lower electrode ML0a of the first lower electrode structure 210B in a vertical direction (Z direction). The first connection portion CP1 may overlap with the second lower connection portion BCP2 of the second lower electrode structure 220B in a vertical direction (Z direction).

[0059] The second electrode structure 220 may include second electrodes MC1b and ML1b, and a second connection portion CP2 connecting the second electrodes MC1b and ML1b to each other and extending in the first direction (X direction). The second electrodes MC1b and ML1b may have a linear shape that protrudes and extends from the second connection portion CP2 in the second direction (Y direction). The second electrodes MC1b and ML1b may form a second finger portion FP2 branching from the second connection portion CP2. The second electrodes MC1b and ML1b may overlap with the second lower electrode ML0b of the second lower electrode structure 220B in the vertical direction (Z direction). The second connection portion CP2 may overlap with the first lower connection portion BCP1 of the first lower electrode structure 210B in the vertical direction (Z direction).

[0060] The second electrodes MC1b and ML1b may be alternately arranged with the first electrodes MC1a and ML1a in the first direction (X direction). The second connection portion CP2 may be spaced apart from the first connection portion CP1 in the second direction (Y direction). The first electrodes MC1a and ML1a and the second electrodes MC1b and ML1b may include a conductive material, for example, a metal such as tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), and aluminum (Al), but some example embodiments thereof are not limited thereto.

[0061] The first electrodes MC1a and ML1a and the second electrodes MC1b and ML1b may include first wall patterns MC1a and MC1b and second wall patterns ML1a and ML1b extending from the first wall patterns MC1a and MC1b, respectively. In some example embodiments, the first wall patterns MC1a and MC1b may include a 1-1 wall pattern MC1a disposed on the first lower electrode ML0a and a 1-2 wall pattern MC1b disposed on the second lower electrode ML0b.

[0062] The first wall patterns MC1a and MC1b may include a first side surface MCS, and the second wall patterns ML1a and ML1b may include a second side surface MLS extending from the first side surface MCS. The first wall patterns MC1a and MC1b may have a width in a first direction (X direction) that increases linearly in a vertical direction (Z direction). The first side surface MCS may have a linear shape in the vertical direction (Z direction). The second wall patterns ML1a and ML1b may have a width in the first direction (X direction), the second side surface MLS extending from the first side surface MCS and the width widening nonlinearly in the vertical direction (Z direction). The second side surface MLS may have a curved shape. In some example embodiments, the side surface profile at the boundary point P1 between the first side surface MCS and the second side surface MLS may change nonlinearly.

[0063] The first wall patterns MC1a and MC1b and the second wall patterns ML1a and ML1b may have a line shape extending in the second direction (Y direction) and may be formed through a dual damascene process.

[0064] The bottom surfaces and first side surfaces MCS of the first wall patterns MC1a and MC1b, and the second side surfaces MLS of the second wall patterns ML1a and ML1b may be covered by the first barrier conductive films MBa and MBb. The 1-1 barrier conductive film MBa may extend along the bottom surface of the 1-1 wall pattern MC1a, the first side surface MCS of the 1-1 wall pattern MC1a, and the second side surface MLS of the 2-1 wall pattern ML1a. The 1-2 barrier conductive film MBb may extend along the bottom surface of the 1-2 wall pattern MC1b, the first side surface MCS of the 1-2 wall pattern MC1b, and the second side surface MLS of the 2-2 wall pattern ML1b.

[0065] The first wall patterns MC1a and MC1b may be integrated with the second wall patterns ML1a and ML1b.

[0066] The insulating layers IL0 and IL1 may be configured as insulating layers including an insulating material (eg, silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride).

[0067] The blocking conductive films MB0, MBa and MBb may include at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tantalum carbonitride (TaCN), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN) and combinations thereof, but some example embodiments thereof are not limited thereto.

[0068] The capacitor formed by the 1-1 wall pattern MC1a and the 1-2 wall pattern MC1b and the second insulating layer IL1 may have a first capacitance C1. The capacitor formed by the 2-1 wall pattern ML1a, the 2-2 wall pattern ML1b and the second insulating layer IL1 may have a second capacitance C2. The second capacitance C2 may be greater than the first capacitance C1.

[0069] The height of the first connection portion CP1 and the second connection portion CP2 in the vertical direction (Z direction) may be less than the height of the first electrodes MC1a and ML1a and the second electrodes MC1b and ML1b in the vertical direction (Z direction). In some example embodiments, the lower surface of the first connection portion CP1 and the lower surface of the second connection portion CP2 may be disposed at a level higher than the level of the lower surface of the first wall patterns MC1a and MC1b. The lower surface of the first connection portion CP1 and the lower surface of the second connection portion CP2 may be disposed at a level higher than the level of a boundary point P1 where the first side surface MCS of the first wall patterns MC1a and MC1b meets the second side surface MLS of the second wall patterns ML1a and ML1b, but some example embodiments are not limited thereto. The lower surface of the first connection portion CP1 and the lower surface of the second connection portion CP2 may be disposed and / or formed at the same level as the level of the boundary point P1. The upper surface of the first connection portion CP1 and the upper surface of the second connection portion CP2 may be at the same level as the upper surface of the second wall patterns ML1a and ML1b.

[0070] A semiconductor device according to some example embodiments may include a capacitor structure 200 including first electrodes MC1a and ML1a and second electrodes MC1b and ML1b. The first electrodes MC1a and ML1a and the second electrodes MC1b and ML1b may include first wall patterns MC1a and MC1b and second wall patterns ML1a and ML1b on the first wall patterns MC1a and MC1b. Since the first wall patterns MC1a and MC1b and the second wall patterns ML1a and ML1b are formed by a dual damascene process, the line width roughness (LWR) of the first electrodes MC1a and ML1a and the second electrodes MC1b and ML1b may be improved.

[0071] Figure 4A is a perspective view illustrating a lower interconnection structure of a semiconductor device according to some example embodiments. Figure 4B is a description of some example embodiments Figure 4A Plan view of the lower interconnect structure in .

[0072] Figure 5 is a description of some example embodiments Figure 4B sectional view of the lower interconnect structure taken along line II-II'.

[0073] Reference Figure 4A 、 Figure 4B and Figure 5 , the lower interconnect structure 250 can be referred to above Figure 1C The lower interconnection structure 250 may be spaced apart from the capacitor structure 200 disposed under the second region R2 of the memory cell structure CELL in the peripheral circuit structure PERI in the first direction (X direction).

[0074] The lower interconnection structure 250 may include a first interconnection structure 250A and a second interconnection structure 250B. The first interconnection structure 250A may be alternately arranged with the second interconnection structure 250B in the first direction (X direction).

[0075] The first interconnection structure 250A may include a first lower interconnection 251 extending in the second direction (Y direction), a first peripheral contact plug 253 disposed on the first lower interconnection 251 , and a first peripheral interconnection 255 disposed on the first peripheral contact plug 253 and extending in the second direction (Y direction).

[0076] The second interconnect structure 250B may include a second lower interconnect 252 extending in the second direction (Y direction), second peripheral contact plugs 254a and 254b disposed on the second lower interconnect 252, and a second peripheral interconnect 256 disposed on the second peripheral contact plugs 254a and 254b and extending in the second direction (Y direction).

[0077] The second lower interconnection 252 may be disposed at the same level as that of the first lower interconnection 251. Bottom and side surfaces of the first lower interconnection 251 and bottom and side surfaces of the second lower interconnection 252 may be covered by the barrier conductive film BLa.

[0078] The first peripheral contact plug 253 may be disposed at the same level as that of the second peripheral contact plugs 254 a and 254 b .

[0079] The first lower interconnect 251 and the second lower interconnect 252 may have a linear shape extending in the second direction (Y direction). The first peripheral contact plug 253 and the second peripheral contact plugs 254a and 254b may have a cylindrical shape as a contact structure. The first peripheral contact plug 253 and the second peripheral contact plugs 254a and 254b may have a via hole shape. The first peripheral interconnect 255 and the second peripheral interconnect 256 may have a linear shape extending in the second direction (Y direction).

[0080] The first peripheral contact plug 253 may be disposed in a central region on the first lower interconnect 251 between the first lower interconnect 251 and the first peripheral interconnect 255. However, some example embodiments are not limited thereto, and the first peripheral contact plug 253 may be disposed to intersect with the second peripheral contact plugs 254a and 254b disposed at the same level. In some example embodiments, the second peripheral contact plugs 254a and 254b may include a 2-1 contact plug 254a and a 2-2 contact plug 254b spaced apart from each other in the second direction (Y direction) on the second lower interconnect 252.

[0081] The heights of the first and second peripheral interconnections 255 and 256 in the vertical direction (Z direction) may be higher than the heights of the first and second lower interconnections 251 and 252 in the vertical direction (Z direction).

[0082] The width of the first peripheral contact plug 253 may linearly increase in a vertical direction (Z direction).The first peripheral contact plug 253 may have a third side surface CS and may have a cylindrical shape.

[0083] The first peripheral interconnect 255 may be in contact with the upper surface of the first peripheral contact plug 253 and may have a fourth side surface LS extending from the third side surface CS of the first peripheral contact plug 253. In some example embodiments, the second peripheral contact plugs 254a and 254b may have a third side surface CS similar to the first peripheral contact plug 253, and the second peripheral interconnect 256 may be in contact with the upper surface of the second peripheral contact plugs 254a and 254b and may have a fourth side surface LS extending from the third side surface CS of the second peripheral contact plugs 254a and 254b. The widths of the first and second peripheral interconnects 255 and 256 in the first direction (X direction) may be smaller than the widths of the second wall patterns ML1a and ML1b in the first direction (X direction).

[0084] The side surface profile may change nonlinearly at a boundary point P2 where the third side surface CS of the first peripheral contact plug 253 meets the fourth side surface LS of the first peripheral interconnect 255. Similarly, the side surface profile may change nonlinearly at a boundary point P2 where the third side surface CS of the second peripheral contact plugs 254a and 254b meets the fourth side surface LS of the second peripheral interconnect 256.

[0085] The first peripheral contact plug 253 and the first peripheral interconnect 255 may be provided and / or formed by a dual damascene process. The second peripheral contact plugs 254a and 254b and the second peripheral interconnect 256 may also be provided and / or formed by a dual damascene process.

[0086] The upper surface of the first peripheral interconnection 255 and the upper surface of the second peripheral interconnection 256 may be disposed on the same Figure 3 In some example embodiments, the depth from the upper surface of the first peripheral interconnect 255 and the upper surface of the second peripheral interconnect 256 to the boundary point P2 where the third side surface CS meets the fourth side surface LS may be less than the depth from the upper surface of the first peripheral interconnect 255 and the upper surface of the second peripheral interconnect 256 to the boundary point P2 where the third side surface CS meets the fourth side surface LS. Figure 3 The depth is from the upper surface of the second wall patterns ML1 a and ML1 b to a boundary point P1 where the first side surface MCS meets the second side surface MLS.

[0087] According to some example embodiments, a semiconductor device may include a capacitor structure 200 and a lower interconnect structure 250 spaced apart in a first direction (X direction). The lower interconnect structure 250 may include peripheral contact plugs 253, 254a, and 254b, and a first peripheral interconnect 255 and a second peripheral interconnect 256 on the peripheral contact plugs 253, 254a, and 254b. The first peripheral contact plug 253, the first peripheral interconnect 255, the second peripheral contact plugs 254a and 254b, and the second peripheral interconnect 256 may be formed by a dual damascene process. Therefore, by reducing misalignment between the first peripheral interconnect 255 and the second peripheral interconnect 256, the lower interconnect structure 250 may be provided with improved reliability.

[0088] Figure 6A is a perspective view illustrating a capacitor structure of a semiconductor device according to some example embodiments. Figure 6B is a description of some example embodiments Figure 6A A plan view of a first upper electrode structure and a second upper electrode structure of a capacitor structure in FIG. Figure 7 is a description of some example embodiments Figure 6B sectional view of the capacitor structure taken along line III-III'.

[0089] Reference Figure 6A , the components of the capacitor structure 200' except the first upper electrode structure 210U and the second upper electrode structure 220U can be connected to Figure 2A The components of the capacitor structure 200 in FIG. 1 are the same or similar.

[0090] Reference Figures 6A to 7The capacitor structure 200' may include a first lower electrode structure 210B and a second lower electrode structure 220B, a first intermediate electrode structure 210L and a second intermediate electrode structure 220L disposed on the first lower electrode structure 210B and the second lower electrode structure 220B, a first upper electrode structure 210U and a second upper electrode structure 220U disposed on the first intermediate electrode structure 210L and the second intermediate electrode structure 220L, a first insulating layer IL0 disposed between the first lower electrode structure 210B and the second lower electrode structure 220B, a second insulating layer IL1 disposed between the first intermediate electrode structure 210L and the second intermediate electrode structure 220L, and a third insulating layer IL2 disposed between the first upper electrode structure 210U and the second upper electrode structure 220U.

[0091] The first lower electrode structure 210B and the second lower electrode structure 220B may correspond to Figure 2B The first lower electrode structure 210B and the second lower electrode structure 220B of the capacitor structure 200 in FIG. The first intermediate electrode structure 210L and the second intermediate electrode structure 220L may correspond to Figure 2C The first electrode structure 210 and the second electrode structure 220 of the capacitor structure 200 are shown in FIG.

[0092] The first upper electrode structure 210U and the second upper electrode structure 220U may be disposed on the first and second intermediate electrode structures 210L and 220L. The first and second upper electrode structures 210U and 220U may have different potentials.

[0093] The first upper electrode structure 210U may include first upper electrodes MC2a and ML2a, and a first upper connection portion UCP1 connecting the first upper electrodes MC2a and ML2a and extending in a first direction (X direction). The first upper electrodes MC2a and ML2a may have a linear shape that protrudes and extends from the first upper connection portion UCP1 in a second direction (Y direction). The first upper electrodes MC2a and ML2a may form first finger portions FP1 branching from the first upper connection portion UCP1. In some example embodiments, the first upper electrodes MC2a and ML2a may overlap with the first electrodes MC1a and ML1a of the first intermediate electrode structure 210L and the first lower electrode ML0a of the first lower electrode structure 210B in a vertical direction (Z direction). The first upper connection portion UCP1 may overlap with the second connection portion CP2 of the second intermediate electrode structure 220L and the first lower connection portion BCP1 of the first lower electrode structure 210B in a vertical direction (Z direction).

[0094] The second upper electrode structure 220U may include second upper electrodes MC2b and ML2b and a second upper connection portion UCP2 connecting the second upper electrodes MC2b and ML2b and extending in the first direction (X direction). The second upper electrodes MC2b and ML2b may have a linear shape protruding and extending from the second upper connection portion UCP2 in the second direction (Y direction). The second upper electrodes MC2b and ML2b may form second finger portions FP2 branching from the second upper connection portion UCP2. In some example embodiments, the second upper electrodes MC2b and ML2b may overlap with the second electrodes MC1b and ML1b of the second intermediate electrode structure 220L and the second lower electrode ML0b of the second lower electrode structure 220B in the vertical direction (Z direction). The second upper connection portion UCP2 may overlap with the first connection portion CP1 of the first intermediate electrode structure 210L and the second lower connection portion BCP2 of the second lower electrode structure 220B in the vertical direction (Z direction). The lower surface of the first lower connection portion BCP1 may be at the same level as the lower surface of the first lower electrode ML0a.

[0095] The first upper electrodes MC2a and ML2a and the second upper electrodes MC2b and ML2b may be alternately arranged in the first direction (X direction). The first upper connection portion UCP1 may be spaced apart from the second upper connection portion UCP2 in the second direction (Y direction). The first upper electrodes MC2a and ML2a and the second upper electrodes MC2b and ML2b may include a conductive material.

[0096] The first upper electrodes MC2a and ML2a and the second upper electrodes MC2b and ML2b may include third wall patterns MC2a and MC2b and fourth wall patterns ML2a and ML2b extending from the third wall patterns MC2a and MC2b. In some example embodiments, the third wall patterns MC2a and MC2b may contact the second wall patterns ML1a and ML1b. The third wall patterns MC2a and MC2b may include a 3-1 wall pattern MC2a disposed on the 2-1 wall pattern ML1a and a 3-2 wall pattern MC2b disposed on the 2-2 wall pattern ML1b.

[0097] The first wall patterns MC1a and MC1b may include a 1-1 side surface MCS1, and the second wall patterns ML1a and ML1b may include a 2-1 side surface MLS1 extending from the 1-1 side surface MCS1.

[0098] The third wall patterns MC2a and MC2b may include a 1-2 side surface MCS2, and the fourth wall patterns ML2a and ML2b may include a 2-2 side surface MLS2 extending from the 1-2 side surface MCS2.

[0099] The first wall patterns MC1a and MC1b and the third wall patterns MC2a and MC2b may have a width in the first direction (X direction) that linearly increases in the vertical direction (Z direction). The 1-1 side surface MCS1 and the 1-2 side surface MCS2 may have a linear shape. The second wall patterns ML1a and ML1b and the fourth wall patterns ML2a and ML2b may have a width in the first direction (X direction) that nonlinearly increases in the vertical direction (Z direction). The 2-1 side surface MLS1 and the 2-2 side surface MLS2 may have a curved shape.

[0100] The side surface profile may nonlinearly change at a boundary point P1 of the 1-1 side surface MCS1 and the 2-1 side surface MLS1 and a boundary point P1 ′ of the 1-2 side surface MCS2 and the 2-2 side surface MLS2 .

[0101] The height of the third wall patterns MC2a and MC2b in the vertical direction (Z direction) may be greater than the height of the first wall patterns MC1a and MC1b in the vertical direction (Z direction). However, some example embodiments are not limited thereto, and the height of the third wall patterns MC2a and MC2b in the vertical direction (Z direction) may be substantially the same as the height of the first wall patterns MC1a and MC1b in the vertical direction (Z direction).

[0102] The height of the fourth wall patterns ML2a and ML2b in the vertical direction (Z direction) may be greater than the height of the second wall patterns ML1a and ML1b in the vertical direction (Z direction). In some example embodiments, the width of the second wall patterns ML1a and ML1b in the first direction (X direction) at the upper surfaces may be substantially the same as the width of the fourth wall patterns ML2a and ML2b in the first direction (X direction) at the upper surfaces.

[0103] The third wall patterns MC2a and MC2b and the fourth wall patterns ML2a and ML2b may have a line shape extending in the second direction (Y direction) and may be formed through a dual damascene process.

[0104] The bottom surfaces of the third wall patterns MC2a and MC2b, the 1-2 side surfaces MCS2 of the third wall patterns MC2a and MC2b, and the 2-2 side surfaces MLS2 of the fourth wall patterns ML2a and ML2b may be covered by the second blocking conductive films MB2a and MB2b. In some example embodiments, the 2-1 blocking conductive film MB2a may extend along the bottom surface of the 3-1 wall pattern MC2a, the 1-2 side surfaces MCS2 of the 3-1 wall pattern MC2a, and the 2-2 side surfaces MLS2 of the 4-1 wall pattern ML2a. In some example embodiments, the second blocking conductive films MB2a and MB2b may include the same material as the first blocking conductive films MBa and MBb.

[0105] The capacitor formed by the 3-1 wall pattern MC2a, 3-2 wall pattern MC2b and the third insulating layer IL2 may have a third capacitance C3. The capacitor formed by the 4-1 wall pattern ML2a, 4-2 wall pattern ML2b and the third insulating layer IL2 may have a fourth capacitance C4. The fourth capacitance C4 may be greater than the third capacitance C3.

[0106] Figure 8A is a perspective view illustrating a lower interconnection structure of a semiconductor device according to some example embodiments. Figure 8B is a description of some example embodiments Figure 8A Plan view of the lower interconnect structure in . Figure 9 is a description of some example embodiments Figure 8B 4 is a cross-sectional view of the lower interconnect structure taken along line IV-IV'.

[0107] Reference Figure 8A 、 Figure 8B and Figure 9 , the lower interconnect structure 250' can be referenced Figure 1C The lower interconnection structure 250' may be spaced apart from the capacitor structure 200' disposed under the second region R2 of the memory cell structure CELL in the peripheral circuit structure PERI in the first direction (X direction).

[0108] The lower interconnection structure 250' may include a first interconnection structure 250A' and a second interconnection structure 250B'. The first interconnection structure 250A' may be alternately disposed with the second interconnection structure 250B' in the first direction (X direction).

[0109] The first interconnect structure 250A' may include a first lower interconnect 251 extending in the second direction (Y direction), a first peripheral contact plug 253 arranged on the first lower interconnect 251, a first peripheral interconnect 255 arranged on the first peripheral contact plug 253 and extending in the second direction (Y direction), third peripheral contact plugs 257a and 257b on the first peripheral interconnect 255, and a third peripheral interconnect 259 arranged on the third peripheral contact plugs 257a and 257b and extending in the second direction (Y direction).

[0110] The first interconnect structure 250A′ may be configured in which third peripheral contact plugs 257 a and 257 b and a third peripheral interconnect 259 are added to Figure 4A The interconnect structure of the first interconnect structure 250A.

[0111] The second interconnect structure 250B' may include a second lower interconnect 252 extending in the second direction (Y direction), second peripheral contact plugs 254a and 254b arranged on the second lower interconnect 252, a second peripheral interconnect 256 arranged on the second peripheral contact plugs 254a and 254b and extending in the second direction (Y direction), a fourth peripheral contact plug 258 on the second peripheral interconnect 256, and a fourth peripheral interconnect 260 on the fourth peripheral contact plug 258 and extending in the second direction (Y direction).

[0112] The second interconnect structure 250B′ may be configured in which a fourth peripheral contact plug 258 and a fourth peripheral interconnect 260 are added to Figure 4A The interconnect structure of the second interconnect structure 250B.

[0113] The third peripheral contact plugs 257a and 257b of the first interconnect structure 250A' may be disposed at the same level as the fourth peripheral contact plug 258 of the second interconnect structure 250B'. The third peripheral interconnect 259 and the fourth peripheral interconnect 260 may be disposed at the same level. The bottom surface and side surfaces of the third peripheral interconnect 259 may be covered with a blocking conductive film BLc.

[0114] The third peripheral contact plugs 257a and 257b and the fourth peripheral contact plug 258 may have a cylindrical shape as a contact structure. The third peripheral contact plugs 257a and 257b and the fourth peripheral contact plug 258 may have a via hole shape. The third peripheral interconnect 259 and the fourth peripheral interconnect 260 may have a linear shape extending in the second direction (Y direction).

[0115] The third peripheral contact plugs 257a and 257b and the third peripheral interconnection 259 may be provided and / or formed by a dual damascene process. The fourth peripheral contact plug 258 and the fourth peripheral interconnection 260 may also be provided and / or formed by a dual damascene process.

[0116] The third peripheral contact plugs 257a and 257b may include a 3-1 peripheral contact plug 257a and a 3-2 peripheral contact plug 257b spaced apart from each other in the second direction (Y direction) on the first peripheral interconnect 255 between the first peripheral interconnect 255 and the third peripheral interconnect 259. A fourth peripheral contact plug 258 may be disposed in a central region of the second peripheral interconnect 256 between the second peripheral interconnect 256 and the fourth peripheral interconnect 260. However, some example embodiments are not limited thereto, and the fourth peripheral contact plug 258 may intersect the third peripheral contact plugs 257a and 257b disposed at the same level.

[0117] The heights of the third and fourth peripheral interconnections 259 and 260 in the vertical direction (Z direction) may be higher than the heights of the first and second peripheral interconnections 255 and 256 in the vertical direction (Z direction).

[0118] The width of the first peripheral contact plug 253 may linearly increase in a vertical direction (Z direction) The first peripheral contact plug 253 may have a 3-1 side surface CS1 and may have a cylindrical shape.

[0119] The first peripheral interconnection 255 may be in contact with an upper surface of the first peripheral contact plug 253 and may have a 4-1 side surface LS1 extending from a 3-1 side surface CS1 of the first peripheral contact plug 253 .

[0120] The width of the fourth peripheral contact plug 258 may increase linearly in the vertical direction (Z direction). The fourth peripheral contact plug 258 may have a 3-2 side surface CS2 and may have a cylindrical shape. The third peripheral contact plugs 257a and 257b may have a 3-2 side surface CS2 similar to the fourth peripheral contact plug 258.

[0121] The fourth peripheral interconnection 260 may be in contact with an upper surface of the fourth peripheral contact plug 258 and may have a 4-2 side surface LS2 extending from the 3-2 side surface CS2 of the fourth peripheral contact plug 258 .

[0122] The side surface profile may change nonlinearly at a boundary point P2 where the 3-1 side surface CS1 of the first peripheral contact plug 253 meets the 4-1 side surface LS1 of the first peripheral interconnect 255, a boundary point P2' where the 3-2 side surface CS2 of the fourth peripheral contact plug 258 meets the 4-2 side surface LS2 of the fourth peripheral interconnect 260, and a boundary point P2' where the 3-2 side surface CS2 of the third peripheral contact plugs 257a and 257b meets the 4-2 side surface LS2 of the third peripheral interconnect 259.

[0123] The upper surface of the third peripheral interconnection 259 and the upper surface of the fourth peripheral interconnection 260 may be disposed on the same Figure 7 In some example embodiments, the depth from the upper surface of the third peripheral interconnect 259 and the upper surface of the fourth peripheral interconnect 260 to the boundary point P2′ where the 3-2 side surface CS2 meets the 4-2 side surface LS2 may be less than the depth from the upper surface of the third peripheral interconnect 259 and the upper surface of the fourth peripheral interconnect 260 to the boundary point P2′ where the 3-2 side surface CS2 meets the 4-2 side surface LS2. Figure 7 The depth is from the upper surface of the fourth wall patterns ML2a and ML2b to a boundary point P1′ where the 1-2 side surface MCS2 meets the 2-2 side surface MLS2.

[0124] Figure 10is a cross-sectional view illustrating a semiconductor device according to some example embodiments.

[0125] Reference Figure 10 , the semiconductor device 10 may include a peripheral circuit structure PERI including a substrate 201 and a memory cell structure CELL including a board layer 101 .

[0126] The peripheral circuit structure PERI may include a substrate 201 , an impurity region 205 and a device isolation region 209 in the substrate 201 , a circuit device 221 disposed on the substrate 201 , a peripheral region insulating layer IL, and a lower interconnection structure 250 .

[0127] The substrate 201 may have an upper surface extending in a first direction (X direction) and a second direction (Y direction). An active region may be defined on the substrate 201 by a device isolation region 209. An impurity region 205 including impurities may be provided in a portion of the active region. The substrate 201 may include a semiconductor material such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor. The substrate 201 may be provided as a bulk wafer or an epitaxial layer. For example, the substrate 201 may be bulk silicon or silicon-on-insulator (SOI).

[0128] The circuit devices 221 may include planar transistors. Each circuit device 221 may include a gate dielectric layer 222, a spacer layer 224, and a gate electrode 225. As source / drain regions, impurity regions 205 may be provided on both sides of the gate electrode 225 in the substrate 201.

[0129] The peripheral region insulating layer IL may be provided on the circuit device 221 on the substrate 201. The peripheral region insulating layer IL may include a plurality of insulating layers formed in different processes. The peripheral region insulating layer IL may be formed of an insulating material.

[0130] The lower interconnect structure 250 may be electrically connected to the circuit device 221 and the impurity region 205. The lower interconnect structure 250 may include a lower interconnect (eg, Figure 4A The first lower interconnect 251 in the peripheral interconnect (eg, Figure 4A The first peripheral interconnect 255 in the lower interconnect and the contact plug between the lower interconnect and the peripheral interconnect (eg, Figure 4A The first peripheral contact plug 253 in the lower interconnect structure 250 is shown. The lower interconnect and the peripheral interconnect can have a line shape, and the contact plug can have a via hole shape. An electrical signal can be applied to the circuit device 221 through the lower interconnect structure 250. The lower interconnect structure 250 can also be connected to the circuit gate electrode 225 in an area not shown.

[0131] The capacitor structure 200 may be spaced apart from the lower interconnect structure 250 in the first direction (X direction) and may be disposed on the second region R2 of the peripheral circuit structure PERI. The capacitor structure 200 may be disposed on the device isolation region 209 of the substrate 201. The capacitor structure 200 may include a lower electrode formed in the same process as forming the lower interconnect, the peripheral interconnect, and the peripheral contact plug disposed between the lower interconnect and the peripheral interconnect of the lower interconnect structure 250, and a first electrode and a second electrode including a first wall pattern and a second wall pattern extending from the first wall pattern.

[0132] The memory cell structure CELL may include a first region R1 and a second region R2, a source structure SS, a gate electrode 130 stacked on the source structure SS, an interlayer insulating layer 140 alternately stacked with the gate electrodes 130, a channel structure CH provided as a stacked structure penetrating the gate electrodes 130, and a contact plug 170 connected to the gate electrode 130 and extending vertically. The memory cell structure CELL may further include a horizontal insulating layer 113 provided below the gate electrode 130, a substrate insulating layer 121 penetrating the plate layer 101, a pillar 185 on the contact plug 170, and a cell region insulating layer 190 covering the gate electrode 130.

[0133] In the memory cell structure CELL, the first region R1 may be configured as a region where gate electrodes 130 are vertically stacked and form a memory cell or connected to a contact plug 170. The second region R2 may be configured as an outer region of the plate layer 101.

[0134] The source structure SS may include a plate layer 101, a first horizontal conductive layer 102, and a second horizontal conductive layer 104 stacked in sequence. The plate layer 101 may have a plate shape and may serve as at least a portion of a common source line of the semiconductor device 10. The plate layer 101 may include a conductive material, such as a semiconductor material. The plate layer 101 may further include impurities. The plate layer 101 may be provided as a polycrystalline semiconductor layer, such as a polysilicon layer, or an epitaxial layer.

[0135] A first horizontal conductive layer 102 and a second horizontal conductive layer 104 may be sequentially stacked on the upper surface of the plate layer 101 in the region where the channel structure CH is provided. The first horizontal conductive layer 102 may function as part of a common source line of the semiconductor device 10, for example, may function together with the plate layer 101 as a common source line. The first horizontal conductive layer 102 may be directly connected to the channel layer in the channel structure CH. The first horizontal conductive layer 102 and the second horizontal conductive layer 104 may comprise a semiconductor material, such as polysilicon.

[0136] Horizontal insulating layer 113 may be provided on plate layer 101 at the same level as first horizontal conductive layer 102. Horizontal insulating layer 113 may include first horizontal insulating layers 111 and second horizontal insulating layers 112 alternately stacked on plate layer 101. Horizontal insulating layer 113 may be a layer that remains after a portion thereof is replaced by first horizontal conductive layer 102 during the manufacturing process of semiconductor device 10. Horizontal insulating layer 113 may include silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride. First horizontal insulating layer 111 and second horizontal insulating layer 112 may include different insulating materials.

[0137] The substrate insulating layer 121 may be provided to penetrate the board layer 101, the horizontal insulating layer 113, and the second horizontal conductive layer 104. The substrate insulating layer 121 may include an insulating material such as silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride.

[0138] The gate electrodes 130 may be vertically stacked and spaced apart from each other on the plate layer 101, and may form a stacked structure together with the interlayer insulating layer 140. The stacked structure may include a lower stacked structure and an upper stacked structure stacked vertically. The gate electrodes 130 may include upper gate electrodes 130U1 and 130U2 forming a string selection transistor, a memory gate electrode 130M forming a plurality of memory cells, and lower gate electrodes 130L1 and 130L2 forming a ground selection transistor. The number of memory gate electrodes 130M included in the memory cell may be determined depending on the capacity of the semiconductor device 10.

[0139] The gate electrodes 130 may be vertically stacked and spaced apart from each other on the first region R1, may extend to different lengths in the X direction, and may form a stepped structure in the form of a staircase. Due to the stepped structure, the gate electrodes 130 in the lower portion may extend longer than the gate electrodes 130 in the upper portion, and the gate electrodes 130 may each have a contact region 130P exposed upward from the interlayer insulating layer 140. The gate electrodes 130 may be connected to the contact plugs 170 in the contact regions 130P, which may be end regions.

[0140] The gate electrode 130 may include a metal material such as tungsten (W). In some example embodiments, the gate electrode 130 may include polysilicon or a metal silicide material. The gate electrode 130 may include the same material throughout. In some example embodiments, the gate electrode 130 may further include a diffusion barrier. For example, the diffusion barrier may include tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof.

[0141] Interlayer insulating layers 140 may be provided between gate electrodes 130. Similar to gate electrodes 130, interlayer insulating layers 140 may be spaced apart from each other in a direction perpendicular to the upper surface of plate layer 101 and may extend in a first direction (X direction). Interlayer insulating layers 140 may include an insulating material such as silicon oxide or silicon nitride.

[0142] The channel structure CH may penetrate the gate electrode 130, may extend in the vertical direction (Z direction), and may be connected to the plate layer 101. The channel structure CH may form a memory cell string and may be spaced apart from each other in rows and columns on the plate layer 101. The channel structure CH may be arranged to form a grid pattern on the XY plane or arranged in a zigzag pattern in one direction. The channel structure CH may have a pillar shape and may have an inclined side surface so that the channel structure CH has a width that decreases toward the plate layer 101.

[0143] The channel structure CH may include a lower channel structure CH1 and an upper channel structure CH2 stacked vertically. The channel structure CH may have a form in which the lower channel structure CH1 and the upper channel structure CH2 are connected to each other, and may have a curved portion in the connection area due to a width difference. However, in some example embodiments, the number of channel structures stacked in the vertical direction (Z direction) may vary. Each channel structure CH may include a channel layer disposed in a channel hole, a channel dielectric layer, a channel filling insulating layer, and a channel pad at the upper end.

[0144] Contact plugs 170 may be connected to contact regions 130P of gate electrode 130. Contact plugs 170 may penetrate at least a portion of cell region insulating layer 190 and may be respectively connected to upwardly exposed contact regions 130P of gate electrode 130. Contact plugs 170 may penetrate gate electrode 130 below contact regions 130P, may penetrate second horizontal conductive layer 104, horizontal insulating layer 113, and plate layer 101, and may be connected to lower interconnect structure 250 in peripheral circuit structure PERI.

[0145] The contact plug 170 may be spaced apart from the gate electrode 130 below the contact region 130P by the contact insulating layer 160 . The contact plug 170 may be spaced apart from the plate layer 101 , the horizontal insulating layer 113 , and the second horizontal conductive layer 104 by the substrate insulating layer 121 .

[0146] Each contact plug 170 may have a horizontally extended form in the contact region 130P. Contact plug 170 may include a vertical extension portion 170V extending in the vertical direction (Z direction) and a horizontal extension portion 170H extending horizontally from vertical extension portion 170V and contacting gate electrode 130. Horizontal extension portion 170H may be provided along the perimeter of vertical extension portion 170V, and its entire side surface may be surrounded by gate electrode 130. Contact plug 170 may be separated from gate electrode 130 below contact region 130P by contact insulating layer 160, that is, gate electrodes 130 are not electrically connected to each other.

[0147] The contact plug 170 may include at least one of conductive materials such as tungsten (W), copper (Cu), aluminum (Al), and alloys thereof. In some example embodiments, the contact plug 170 may include a barrier layer extending along side and bottom surfaces, or may have an air gap therein.

[0148] The contact insulating layer 160 may be provided to surround the side surfaces of the contact plugs 170 below the contact regions 130P. The contact insulating layers 160 may be spaced apart from each other in the vertical direction (Z direction) around each contact plug 170. The contact insulating layer 160 may be provided at a level substantially the same as that of the gate electrode 130. The contact insulating layer 160 may include an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0149] Pillar 185 may form a cell interconnect structure electrically connected to the memory cells in memory cell structure CELL. Pillar 185 may be connected to channel structure CH and contact plug 170, and may be electrically connected to channel structure CH and gate electrode 130. Pillar 185 may include a metal such as tungsten (W), copper (Cu), aluminum (Al), etc.

[0150] The cell region insulating layer 190 may be provided to cover the stack structure of the gate electrode 130 and the contact plug 170. The cell region insulating layer 190 may be formed of an insulating material and may include a plurality of insulating layers.

[0151] The through-plug 164 and the capacitor contact 165 may be respectively disposed in the first region R1 of the memory cell structure CELL and the second region R2 which may be the outer region of the plate layer 101, and may extend to the peripheral circuit structure PERI by penetrating the cell region insulating layer 190. The through-plug 164 and the capacitor contact 165 may be disposed to be connected to the pillar 185 of the memory cell structure CELL and to be connected to the lower interconnect structure 250 and the capacitor structure 200 of the peripheral circuit structure PERI, respectively. The through-plug 164 and the capacitor contact 165 may include a conductive material, for example, a metal material such as tungsten (W), copper (Cu), and aluminum (Al). The through-plug 164 and the capacitor contact 165 may be formed in the same process as the process for forming the contact plug 170, may include the same material, and may have the same internal structure.

[0152] The capacitor structure 200 may be disposed in the second region R2 of the peripheral circuit structure PERI. The capacitor structure 200 may perform a function of storing charge. The capacitor structure 200 may include a first electrode structure 210, a second electrode structure 220, and a peripheral region insulating layer IL (eg, see Figure 3 The capacitor structure 200 may be disposed on the device isolation region 209 and may vertically overlap the device isolation region 209 .

[0153] Figures 11A to 11G is a diagram illustrating a method of manufacturing a semiconductor device according to some example embodiments. Figures 11A to 11G , will describe Figure 10 1. The manufacturing process of the lower interconnect structure 250 and the capacitor structure 200 of the peripheral circuit structure PERI.

[0154] Reference Figure 11A , a first insulating layer IL0 on the substrate 201, a first lower interconnection 251 and a second lower interconnection 252 on the first region R1, a first lower electrode ML0a and a second lower electrode ML0b on the second region R2, a second insulating layer IL1 on the first insulating layer IL0, a conductive pad 301 on the second insulating layer IL1, and a first interlayer insulating film 302 on the conductive pad 301 can be formed in sequence.

[0155] The first insulating layer IL0 may be formed on the substrate 201. The first and second lower interconnections 251 and 252 and the first and second lower electrodes ML0a and ML0b may be buried in the first insulating layer IL0 on an upper surface of the first insulating layer IL0.

[0156] The first and second lower interconnects 251 and 252 on the first region R1 and the first and second lower electrodes ML0a and ML0b on the second region R2 may be formed at the same level. The first and second lower interconnects 251 and 252 and the first and second lower electrodes ML0a and ML0b may be formed by a damascene process. A blocking conductive film BLa may be formed between the first and second lower interconnects 251 and 252 and the first insulating layer IL0. A blocking conductive film MB0 may be formed between the first and second lower electrodes ML0a and ML0b and the first insulating layer IL0.

[0157] A second insulating layer IL1 , a conductive liner 301 , and a first interlayer insulating film 302 may be sequentially formed on the first insulating layer IL0 .

[0158] The conductive pad 301 may include a conductive material such as at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tantalum carbonitride (TaCN), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), and combinations thereof, but some example embodiments thereof are not limited thereto.

[0159] The first interlayer insulating film 302 may include at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), and combinations thereof, but some example embodiments thereof are not limited thereto.

[0160] Reference Figure 11B A first trench RT1 a exposing the second insulating layer IL1 in the first region R1 and a second trench RT2 a exposing the second insulating layer IL1 in the second region R2 may be formed by etching the conductive liner 301 and the first interlayer insulating film 302 .

[0161] The first trench RT1a may overlap the first and second lower interconnections 251 and 252 in the vertical direction (Z direction). The second trench RT2a may overlap the first and second lower electrodes ML0a and MLb0 in the vertical direction (Z direction).

[0162] Reference Figure 11C, a hard mask 303 and a second interlayer insulating film 304 may be sequentially formed on the first interlayer insulating film 302. The hard mask 303 may cover the first interlayer insulating film 302 and may fill the first trench RT1a and the second trench RT2a. The hard mask 303 may include a spin-on hard mask (SOH), but some example embodiments thereof are not limited thereto. The second interlayer insulating film 304 may be formed on the hard mask 303. In some example embodiments, the second interlayer insulating film 304 may include the same material as that of the first interlayer insulating film 302, but some example embodiments thereof are not limited thereto and may include at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), and combinations thereof.

[0163] Reference Figure 11D The second interlayer insulating film 304 , the hard mask 303 , the first interlayer insulating film 302 , and the conductive liner 301 may be sequentially etched to form first openings RT1 b in the first region R1 and second openings RT2 b in the second region R2 .

[0164] The first opening RT1 b may penetrate the second interlayer insulating film 304 , the hard mask 303 , the first interlayer insulating film 302 , and the conductive liner 301 , and may expose a region of the second insulating layer IL1 overlapping the first and second lower interconnections 251 and 252 .

[0165] The second opening RT2 b may penetrate the second interlayer insulating film 304 , the hard mask 303 , the first interlayer insulating film 302 , and the conductive liner 301 , and may expose regions of the second insulating layer IL1 overlapping the first and second lower electrodes ML0 a and MLb0 .

[0166] Reference Figure 11E , a via hole VPa penetrating the second insulating layer IL1 and exposing the first lower interconnect 251, and a third opening WPa penetrating the second insulating layer IL1 and exposing the first lower electrode ML0a and the second lower electrode ML0b can be formed by etching through the first opening RT1b and the second opening RT2b. The via hole VPa may have a cylindrical shape, and the third opening WPa may have a trench shape extending in the second direction (Y direction) and exposing the first lower electrode ML0a and the second lower electrode MLb0. In some example embodiments, the width Wa of the via hole VPa in the first direction (X direction) may be smaller than the width Wb of the third opening WPa in the first direction (X direction). After etching, the remaining portions of the second interlayer insulating film 304, the hard mask 303, and the first interlayer insulating film 302 may be removed.

[0167] Reference Figure 11F, a third trench VPb, a fourth trench VPc, and a fifth trench WPb may be formed in the second insulating layer IL1 using the conductive liner 301 as an etching mask.

[0168] Because the third trench VPb overlaps with the via hole VPa, the third trench VPb can be integrated with the via hole VPa. The third trench VPb can be formed on the via hole VPa and can have a curved side surface extending from the linear side surface of the via hole VPa. The third trench VPb can have a first height H1 from the upper surface of the conductive pad 301 to the lower end of the curved side surface in the third direction (Z direction).

[0169] The fourth trench VPc may be configured as a region overlapping with the second lower interconnection 252 and may be connected to the second lower interconnection 252 through a via hole (or a through plug) in an unillustrated region. The depth of the fourth trench VPc in the vertical direction (Z direction) may be smaller than the depth of the third trench VPb in the vertical direction (Z direction).

[0170] Because the fifth trench WPb overlaps with the third opening WPa, the fifth trench WPb can be integrated with the third opening WPa. The fifth trench WPb can be formed on the third opening WPa and can have a curved side surface extending from the linear side surface of the third opening WPa. The fifth trench WPb can have a second height H2 from the upper surface of the conductive pad 301 to the lower end of the curved side surface in the third direction (Z direction). The second height H2 of the fifth trench WPb can be greater than the first height H1 of the third trench VPb. The fifth trench WPb can be formed by etching to a greater depth from the upper surface of the conductive pad 301 than the third trench VPb.

[0171] Reference Figure 11G , a first peripheral contact plug 253 and a first peripheral interconnection 255 may be formed in the third trench VPb, a second peripheral interconnection 256 may be formed in the fourth trench VPc, and first wall patterns MC1a and MC1b and second wall patterns ML1a and ML1b may be formed in the fifth trench WPb.

[0172] Before forming the first wall patterns MC1 a and MC1 b and the second wall patterns ML1 a and ML1 b , the barrier conductive films MBa and MBb may be conformally formed along the bottom surface and the side surface of the fifth trench WPb.

[0173] Before forming the first peripheral contact plug 253 and the first peripheral interconnection 255, a blocking conductive film BLb may be formed along the bottom and side surfaces of the third trench VPb. Before forming the second peripheral interconnection 256, a conductive film may be formed along the bottom and side surfaces of the fourth trench VPc.

[0174] A method of manufacturing a semiconductor device according to some example embodiments may include forming the first electrode structure 210 and the second electrode structure 220 of the capacitor structure 200 in the same process as forming the lower interconnect structure 250, and forming the first wall patterns MC1a and MC1b and the second wall patterns ML1a and ML1b included in the first and second electrode structures 210 and 220 together with the first peripheral contact plugs 253 and the first peripheral interconnects 255 through a dual damascene process. Thus, by reducing the separation distance between the capacitor structure 200 and the lower interconnect structure 250, a semiconductor device with improved integration density may be provided.

[0175] Figure 12 is a diagram illustrating a data storage system including a semiconductor device according to some example embodiments.

[0176] Reference Figure 12 , the data storage system 1000 may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The data storage system 1000 may be implemented as a storage device including one or more semiconductor devices 1100 or an electronic device including a storage device. For example, the data storage system 1000 may be implemented as a solid-state drive device (SSD), a universal serial bus (USB), a computing system, a medical device, or a communication device including one or more semiconductor devices 1100.

[0177] The semiconductor device 1100 may be implemented as a nonvolatile memory device, such as, for example, referring to Figures 1A to 6B The NAND flash memory device described in the aforementioned example embodiments. The semiconductor device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. In some example embodiments, the first structure 1100F may be disposed next to the second structure 1100S. The first structure 1100F may be implemented as a peripheral circuit structure including a decoder 1110, a page buffer 1120, and a logic circuit 1130. For example, the first structure 1100F may include a pumping capacitor CAP1 and an output capacitor CAP2 of the charge pump circuit 56 or 56a included in the voltage generator 38 (e.g., see Figures 1A to 1C The second structure 1100S may be implemented as a memory cell structure including a bit line BL, a common source line CSL, a word line WL, first and second upper gate lines UL1 and UL2, first and second lower gate lines LL1 and LL2, and a memory cell string CSTR disposed between the bit line BL and the common source line CSL.

[0178] In the second structure 1100S, each memory cell string CSTR may include lower transistors LT1 and LT2 adjacent to a common source line CSL, upper transistors UT1 and UT2 adjacent to a bit line BL, and a plurality of memory cell transistors MCT disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. In some example embodiments, the number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 may vary.

[0179] In some example embodiments, the upper transistors UT1 and UT2 may include string selection transistors, and the lower transistors LT1 and LT2 may include ground selection transistors. The lower gate lines LL1 and LL2 may be configured as gate electrodes of the lower transistors LT1 and LT2, respectively. The word line WL may be configured as a gate electrode of the memory cell transistor MCT, and the upper gate lines UL1 and UL2 may be configured as gate electrodes of the upper transistors UT1 and UT2, respectively.

[0180] In some example embodiments, the lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground selection transistor LT2 connected in series. The upper transistors UT1 and UT2 may include a string selection transistor UT1 and an upper erase control transistor UT2 connected in series. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT2 may be used in an erase operation for erasing data stored in the memory cell transistor MCT using the GIDL phenomenon.

[0181] The common source line CSL, the first and second lower gate lines LL1 and LL2, the word lines WL, and the first and second upper gate lines UL1 and UL2 may be electrically connected to the decoder 1110 through a first connection interconnect 1115 extending from the first structure 1100F to the second structure 1100S. The bit line BL may be electrically connected to the page buffer 1120 through a second connection interconnect 1125 extending from the first structure 1100F to the second structure 1100S.

[0182] In the first structure 1100F, the decoder 1110 and the page buffer 1120 can perform a control operation on at least one selected memory cell transistor among the plurality of memory cell transistors MCT. The decoder 1110 and the page buffer 1120 can be controlled by a logic circuit 1130. The semiconductor device 1100 can communicate with the controller 1200 through an input / output pad 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 can be electrically connected to the logic circuit 1130 through an input / output connection line 1135 extending from the first structure 1100F to the second structure 1100S.

[0183] The controller 1200 may include a processor 1210 , a NAND controller 1220 , and a host interface 1230 . In some example embodiments, the data storage system 1000 may include a plurality of semiconductor devices 1100 , and in some example embodiments, the controller 1200 may control the plurality of semiconductor devices 1100 .

[0184] Processor 1210 can control the overall operation of data storage system 1000, including controller 1200. Processor 1210 can operate according to predetermined firmware and can access semiconductor device 1100 by controlling NAND controller 1220. NAND controller 1220 may include a controller interface 1221 for handling communication with semiconductor device 1100. Control commands for controlling semiconductor device 1100, data to be written to memory cell transistors MCT of semiconductor device 1100, and data to be read from memory cell transistors MCT of semiconductor device 1100 can be transmitted via controller interface 1221. Host interface 1230 can provide communication functionality between data storage system 1000 and an external host. When a control command from an external host is received via host interface 1230, processor 1210 can control semiconductor device 1100 in response to the control command.

[0185] According to the aforementioned example embodiments, a semiconductor device and a data storage system including the semiconductor device may include a capacitor structure and a lower interconnect structure disposed at the same level as the capacitor structure. Each of the first and second electrodes of the capacitor structure may include a first wall pattern having a first side surface and a second wall pattern having a second side surface extending from the first side surface, and the lower interconnect structure may include a peripheral contact plug and a peripheral interconnect having a line shape extending from the peripheral contact plug. Therefore, the line width roughness (LWR) of the first and second electrodes of the capacitor structure can be improved, and the interconnect alignment of the peripheral interconnect of the lower interconnect structure can be improved, thereby providing a semiconductor device with improved reliability and a data storage system including the semiconductor device.

[0186] One or more of the elements disclosed above may include or be implemented in a processing circuit, such as hardware including logic circuitry; a hardware / software combination, such as a processor running software; or a combination thereof. For example, the processing circuit may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), and the like.

[0187] While certain example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

[0188] This application claims the benefit of priority from Korean Patent Application No. 10-2024-0037165 filed on March 18, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device comprising: a first semiconductor structure comprising a substrate, a circuit device on the substrate, a lower interconnect structure electrically connected to the circuit device, and a capacitor structure spaced apart from the lower interconnect structure; as well as a second semiconductor structure comprising a plate layer on the first semiconductor structure, the second semiconductor structure comprising gate electrodes spaced apart from each other and stacked in sequence in a vertical direction perpendicular to an upper surface of the plate layer, and a channel structure penetrating the gate electrodes and extending in the vertical direction, Wherein, the capacitor structure includes a first electrode structure including first electrodes spaced apart from each other in a first direction parallel to an upper surface of the substrate, the first electrodes extending in the perpendicular direction and in a second direction intersecting the first direction, and a second electrode structure comprising second electrodes arranged alternately with the first electrodes along the first direction, the second electrodes extending in the second direction; wherein each of the first electrode and the second electrode includes a first wall pattern having a first side surface and a second wall pattern having a second side surface, the second side surface extending from the first side surface, and The side surface profiles of the first electrode and the second electrode change nonlinearly at a boundary between the first side surface and the second side surface.

2. The semiconductor device according to claim 1, in, The first side surface has a linear shape, a width of the first wall pattern in the first direction increases along an upwardly increasing height of the first wall pattern in the vertical direction, and The second side surface extends from the first side surface and has a curved shape.

3. The semiconductor device according to claim 1, wherein The capacitor structure further includes a blocking conductive film covering a bottom surface of the first wall pattern, the first side surface of the first wall pattern, and the second side surface of the second wall pattern.

4. The semiconductor device according to claim 1, in, The first electrode structure further includes a first connection portion connecting the first electrodes to each other, the first connection portion extending in the first direction, and The second electrode structure further includes a second connection portion connecting the second electrodes to each other, the second connection portion extending in the first direction and spaced apart from the first connection portion in the second direction.

5. The semiconductor device according to claim 4, wherein An upper surface of the first connection portion and an upper surface of the second connection portion are at the same level as an upper surface of the second wall pattern. The semiconductor device according to claim 4 , wherein: A lower surface of the first connection portion and a lower surface of the second connection portion are at a level higher than that of a lower surface of the first wall pattern.

7. The semiconductor device according to claim 4, wherein The capacitor structure further comprises: a first lower electrode structure between the substrate and the first electrode structure, the first lower electrode structure including a first lower electrode overlapping the first electrode and a first lower connection portion connecting the first lower electrodes to each other, the first lower connection portion extending in the first direction; and a second lower electrode structure between the substrate and the second electrode structure, the second lower electrode structure comprising a second lower electrode overlapping the second electrode and a second lower connecting portion connecting the second lower electrodes to each other, the second lower connecting portion extending in the first direction, wherein the first lower connecting portion overlaps with the second connecting portion, and Wherein, the second lower connecting portion overlaps with the first connecting portion.

8. The semiconductor device according to claim 4, wherein The capacitor structure further comprises: a first upper electrode structure on the first electrode structure, the first upper electrode structure including a first upper electrode overlapping the first electrode and a first upper connection portion connecting the first upper electrodes to each other, the first upper connection portion extending in the first direction; and a second upper electrode structure on the second electrode structure, the second upper electrode structure including a second upper electrode overlapping the second electrode and a second upper connection portion connecting the second upper electrodes to each other, the second upper connection portion extending in the first direction, wherein the first upper connecting portion overlaps with the second connecting portion, and Wherein, the second upper connecting portion overlaps with the first connecting portion.

9. The semiconductor device according to claim 8, wherein A height of the first upper electrode structure in the vertical direction is greater than a height of the first electrode structure in the vertical direction.

10. The semiconductor device according to claim 8, in, The first upper electrode and the second upper electrode each include a third wall pattern having a third side surface and a fourth wall pattern having a fourth side surface, the fourth wall pattern extending from the third wall pattern, and The side surface profile changes nonlinearly at a boundary between the third side surface and the fourth side surface.

11. The semiconductor device according to claim 1, in, The lower interconnect structure is spaced apart from the capacitor structure in the first direction, and The lower interconnect structure is at the same level as the first wall pattern, and includes a cylindrical contact plug and a peripheral interconnect on and in contact with an upper surface of the contact plug, the peripheral interconnect extending in the second direction.

12. The semiconductor device according to claim 11, in, an upper surface of the peripheral interconnection is at the same level as an upper surface of the second wall pattern, and Wherein, a height of the peripheral interconnection in the vertical direction is smaller than a height of the second wall pattern in the vertical direction.

13. The semiconductor device according to claim 11, wherein The lower interconnect structure further includes a peripheral barrier film covering a lower surface of the contact plug, a side surface of the contact plug, and a side surface of the peripheral interconnect.

14. The semiconductor device according to claim 11, wherein A width of the peripheral interconnection in the first direction is smaller than a width of the second wall pattern in the first direction.

15. A semiconductor device comprising: a first lower electrode structure on a substrate, the first lower electrode structure comprising first lower electrodes and a first lower connecting portion, the first lower electrodes being spaced apart from each other in a first direction parallel to an upper surface of the substrate and extending in a second direction intersecting the first direction, the first lower connecting portion connecting the first lower electrodes to each other and extending in the first direction; a second lower electrode structure comprising second lower electrodes and second lower connecting portions, the second lower electrodes being arranged alternately with the first lower electrodes along the first direction, the second lower connecting portions connecting the second lower electrodes to each other and extending in the first direction; a first insulating layer between the first lower electrode structure and the second lower electrode structure; a first intermediate electrode structure comprising a first intermediate electrode and a first intermediate connecting portion, wherein the first intermediate electrode is on the first lower electrode, the first intermediate connecting portion connects the first intermediate electrodes to each other and extends in the first direction, and the first intermediate connecting portion vertically overlaps the second lower connecting portion; a second intermediate electrode structure comprising a second intermediate electrode and a second intermediate connecting portion, wherein the second intermediate electrode is on the second lower electrode, the second intermediate connecting portion connects the second intermediate electrodes to each other and extends in the first direction, and the second intermediate connecting portion overlaps the first lower connecting portion in the vertical direction; as well as a second insulating layer between the first intermediate electrode structure and the second intermediate electrode structure, wherein each of the first intermediate electrode and the second intermediate electrode includes a first wall pattern having a first side surface and a second wall pattern having a second side surface, the second side surface extending from the first side surface, and The side surface profiles of the first intermediate electrode and the second intermediate electrode change nonlinearly at a boundary between the first side surface and the second side surface.

16. The semiconductor device according to claim 15, in, The first wall pattern includes a 1-1 wall pattern on the first lower electrode and a 1-2 wall pattern on the second lower electrode, and The second wall pattern includes a 2-1 wall pattern extending from the 1-1 wall pattern and a 2-2 wall pattern extending from the 1-2 wall pattern.

17. The semiconductor device according to claim 15, in, a lower surface of the first lower connection portion is at the same level as a lower surface of the first lower electrode, and The lower surface of the first intermediate connection portion is at a higher level than the lower surface of the first intermediate electrode.

18. The semiconductor device according to claim 15, further comprising: a first upper electrode structure comprising a first upper electrode and a first upper connecting portion, wherein the first upper electrode is on the first intermediate electrode, the first upper connecting portion connects the first upper electrodes to each other and extends in the first direction, and the first upper connecting portion overlaps the second intermediate connecting portion in the vertical direction; a second upper electrode structure comprising a second upper electrode and a second upper connecting portion, the second upper electrode being on the second intermediate electrode, the second upper connecting portion connecting the second upper electrodes to each other and extending in the first direction, the second upper connecting portion overlapping the first intermediate connecting portion in the vertical direction; as well as A third insulating layer is between the first upper electrode structure and the second upper electrode structure.

19. A data storage system comprising: A semiconductor memory device including a circuit device, a memory cell, a capacitor structure, and an input / output pad on a substrate; as well as a controller configured to control the semiconductor memory device, the controller being electrically connected to the semiconductor memory device through the input / output pad, Wherein, the capacitor structure includes a first electrode structure including first electrodes and a first connecting portion, the first electrodes being spaced apart from each other in a first direction parallel to the upper surface of the substrate and extending in a second direction intersecting the first direction, the first connecting portion connecting the first electrodes to each other and extending in the first direction; a second electrode structure including second electrodes and second connecting portions, the second electrodes being arranged alternately with the first electrodes along the first direction and extending in the second direction, the second connecting portions connecting the second electrodes to each other and extending in the first direction, and an insulating layer between the first electrode structure and the second electrode structure, wherein each of the first electrode and the second electrode includes a first wall pattern having a first side surface and a second wall pattern having a second side surface, the second side surface extending from the first side surface, and wherein a lower surface of the first connection portion and a lower surface of the second connection portion are at a level higher than a level of a lower surface of the first wall pattern.

20. The data storage system according to claim 19, wherein: The first connection portion and the second connection portion are spaced apart from each other in the second direction.

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