Semiconductor device and forming method thereof

Abstract

The embodiment of the invention provides a semiconductor device and a forming method thereof. The semiconductor device comprises a first semiconductor structure, a first bonding layer and a second semiconductor structure which are sequentially stacked along a first direction, wherein the first semiconductor structure comprises a transistor structure; the second semiconductor structure comprises a memristor structure; the first bonding layer comprises a first bonding structure and a second bonding structure which are arranged along a second direction; the memristor structure is connected with the transistor structure through the first bonding structure and the second bonding structure; the second direction is perpendicular to the first direction.

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, a semiconductor device and a method for forming the same. Background Art

[0002] The traditional von Neumann computing architecture suffers from both storage and power consumption issues. Storage and computing units are separated, and large amounts of data must be moved back and forth between them to perform various computational tasks. Furthermore, the read and write speeds of storage units are much slower than the computational speed of the computing units, limiting computational speed and resulting in high power consumption and latency in the computing system. As AI applications continue to increase their computing and storage demands, the problems caused by the separation of storage and computing will become increasingly prominent. One feasible approach to eliminating data movement between storage and computing units is to integrate storage and computing, enabling both data storage and in-situ computation. Memristors are two-terminal nanoscale electronic devices with advantages such as high switching speed, non-volatility, variable resistance states, low power consumption, and high scalability, making them suitable for a wide range of applications in logic operations and storage. Summary of the Invention

[0003] According to a first aspect of an embodiment of the present disclosure, a semiconductor device is provided, comprising: a first semiconductor structure, a first bonding layer, and a second semiconductor structure stacked in sequence along a first direction; wherein the first semiconductor structure comprises a transistor structure; the second semiconductor structure comprises a memristor structure; the first bonding layer comprises a first bonding structure and a second bonding structure arranged along a second direction; the memristor structure is connected to the transistor structure through the first bonding structure and the second bonding structure; and the second direction is perpendicular to the first direction.

[0004] In some embodiments, the first bonding layer includes a first sub-bonding layer and a second sub-bonding layer stacked along the first direction; the first sub-bonding layer is located between the second sub-bonding layer and the first semiconductor structure; the first sub-bonding layer includes a first dielectric layer, a first bonding contact of the first bonding structure located in the first dielectric layer, and a second bonding contact of the second bonding structure located in the first dielectric layer, and the second sub-bonding layer includes a second dielectric layer, a third bonding contact of the first bonding structure located in the second dielectric layer, and a fourth bonding contact of the second bonding structure located in the second dielectric layer; the first dielectric layer is bonded to the second dielectric layer, the first bonding contact is bonded to the third bonding contact, and the second bonding contact is bonded to the fourth bonding contact.

[0005] In some embodiments, the transistor structure includes a first transistor and a second transistor arranged along the second direction; the first semiconductor structure also includes: a first interconnect layer; the first interconnect layer is located between the transistor structure and the first bonding layer, the first interconnect layer includes a first interconnect structure and a second interconnect structure arranged along the second direction, the memristive structure is connected to the first transistor through the first bonding structure and the first interconnect structure, and the memristive structure is connected to the second transistor through the second bonding structure and the second interconnect structure.

[0006] In some embodiments, the memristive structure includes a first electrode layer, a resistive switching layer, and a second electrode layer stacked in sequence along the first direction.

[0007] In some embodiments, the second semiconductor structure also includes a first conductive line, a first contact structure and a second contact structure; the first contact structure, the second contact structure and the memristive structure are located between the first bonding layer and the first conductive line; one end of the first contact structure opposite to each other along the first direction is connected to the first conductive line, and the other end is connected to the first bonding structure; one end of the second contact structure opposite to each other along the first direction is connected to the first electrode layer of the memristive structure, and the other end is connected to the second bonding structure; the second electrode layer of the memristive structure is connected to the first conductive line.

[0008] In some embodiments, the material of the resistive switching layer includes at least one of the following: metal oxide, perovskite material, chalcogenide semiconductor, two-dimensional material, and organic material.

[0009] In some embodiments, the first semiconductor structure further includes a peripheral circuit; and the transistor structure and the memristor structure are coupled to the peripheral circuit.

[0010] According to a second aspect of an embodiment of the present disclosure, a method for forming a semiconductor device is provided, the formation method comprising: forming a first semiconductor structure on a first wafer, and forming a first sub-bonding layer on the first semiconductor structure; the first semiconductor structure comprises a transistor structure; forming a second sub-bonding layer on a second wafer, and forming a second semiconductor structure on the second sub-bonding layer; the second semiconductor structure comprises a memristive structure; removing the second wafer to expose the second sub-bonding layer; bonding the first sub-bonding layer to the second sub-bonding layer to form a first bonding layer; the first bonding layer comprises a first bonding structure and a second bonding structure; the memristive structure is connected to the transistor structure through the first bonding structure and the second bonding structure.

[0011] In some embodiments, the bonding temperature range of the first sub-bonding layer and the second sub-bonding layer is 200° C. to 400° C.

[0012] In some embodiments, the first sub-bonding layer includes a first dielectric layer, a first bonding contact of the first bonding structure located in the first dielectric layer, and a second bonding contact of the second bonding structure located in the first dielectric layer; the second sub-bonding layer includes a second dielectric layer, a third bonding contact of the first bonding structure located in the second dielectric layer, and a fourth bonding contact of the second bonding structure located in the second dielectric layer; bonding the first sub-bonding layer to the second sub-bonding layer includes: bonding the first dielectric layer to the second dielectric layer, bonding the first bonding contact to the third bonding contact, and bonding the second bonding contact to the fourth bonding contact.

[0013] In some embodiments, the first semiconductor structure is formed on the first wafer, including: forming the transistor structure and the peripheral circuit on the first wafer; the transistor structure includes a first transistor and a second transistor; the transistor structure and the memristive structure are coupled to the peripheral circuit; forming a first interconnect layer on the transistor structure; the first interconnect layer includes a first interconnect structure and a second interconnect structure, the memristive structure is connected to the first transistor through the first bonding structure and the first interconnect structure, and the memristive structure is connected to the second transistor through the second bonding structure and the second interconnect structure.

[0014] In some embodiments, forming the memristive structure includes: forming a first electrode layer, a resistive switching layer, and a second electrode layer stacked in sequence along a first direction; the first direction is the stacking direction of the first semiconductor structure, the first bonding layer, and the second semiconductor structure.

[0015] In some embodiments, the second semiconductor structure is formed on the second sub-bonding layer, including: forming a first conductive line, a first contact structure and a second contact structure on the second sub-bonding layer; the first contact structure, the second contact structure and the memristive structure are located between the second sub-bonding layer and the first conductive line; one end of the first contact structure opposite to each other along the first direction is connected to the first conductive line, and the other end is connected to the first bonding structure; one end of the second contact structure opposite to each other along the first direction is connected to the first electrode layer of the memristive structure, and the other end is connected to the second bonding structure; the second electrode layer of the memristive structure is connected to the first conductive line.

[0016] In some embodiments, the formation method further includes: forming a temporary bonding adhesive layer on the second semiconductor structure before removing the second wafer to expose the second sub-bonding layer, and bonding the temporary bonding adhesive layer to a carrier wafer; or, forming a temporary bonding adhesive layer on a carrier wafer before removing the second wafer to expose the second sub-bonding layer, and bonding the temporary bonding adhesive layer to the second semiconductor structure; after bonding the first sub-bonding layer to the second sub-bonding layer, removing the temporary bonding adhesive layer and the carrier wafer.

[0017] In some embodiments, a plurality of second semiconductor structures and a plurality of second sub-bonding layers are formed on the second wafer; the formation method further includes: before removing the second wafer to expose the second sub-bonding layer, forming a temporary bonding layer on the second semiconductor structure, and bonding the temporary bonding layer to a carrier wafer; or, before removing the second wafer to expose the second sub-bonding layer, forming a temporary bonding layer on the carrier wafer, and bonding the temporary bonding layer to the second semiconductor structure; after removing the second wafer to expose the second sub-bonding layer, cutting the carrier wafer, the temporary bonding layer on the carrier wafer, the second sub-bonding layer and the second semiconductor structure to form a plurality of chips; the chip includes the second semiconductor structure and the second sub-bonding layer; after bonding the first sub-bonding layer to the second sub-bonding layer, removing part of the temporary bonding layer on the chip and part of the carrier wafer on the chip.

[0018] In the disclosed embodiment, the semiconductor device includes a first semiconductor structure, a first bonding layer, and a second semiconductor structure stacked along a first direction, the first semiconductor structure includes a transistor structure, the second semiconductor structure includes a memristor structure, and the first semiconductor structure and the second semiconductor structure are bonded together via the first bonding layer. That is, the transistor structure and the memristor structure can be formed on different wafers and then bonded together. On the one hand, the separate preparation of the transistor structure and the memristor structure on different wafers can solve the problem of process incompatibility in the preparation of the transistor structure and the memristor structure, and can independently optimize the performance of the resistive layer in the memristor structure, thereby reducing the difficulty of the overall process; on the other hand, qualified wafers can be independently tested and screened before bonding, thereby reducing costs; on the other hand, defective wafers can be removed before bonding, thereby avoiding “all losses due to one loss” and improving the overall yield; on the other hand, the first wafer and the second wafer can use the same process or different processes, and the appropriate process can be selected according to actual needs, which can also reduce costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 Schematic diagram of the frame structure of a semiconductor device provided in one embodiment of the present disclosure Figure 1 ;

[0020] Figure 2 A schematic diagram of a cross-sectional structure of a semiconductor device provided in one embodiment of the present disclosure;

[0021] Figure 3 Schematic diagram of the frame structure of a semiconductor device provided in one embodiment of the present disclosure Figure 2 ;

[0022] Figure 4 A schematic flow chart of a method for forming a semiconductor device according to an embodiment of the present disclosure;

[0023] Figures 5 to 12 A schematic structural diagram of a semiconductor device formation process according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0024] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0025] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0026] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0027] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. However, when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part exists in the present disclosure.

[0028] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0029] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0030] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present disclosure, the implementation of the embodiments of the present disclosure is described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference only and are not intended to limit the embodiments of the present disclosure.

[0031] Modern computers are primarily based on the von Neumann architecture. In this architecture, data is retrieved from storage, transferred to a computing unit, and then returned to storage after computation is complete. Today, processors and memory have reached remarkably high speeds, but the bus connecting them has become a bottleneck to further speed increases. Frequent data transfers consume a significant portion of the time and energy required for data processing. With the advent of the big data era, computers face more computationally intensive tasks, exacerbating this bottleneck and limiting the development of modern computers, resulting in what is known as the memory wall. In-memory computing offers a promising solution. Similar to the human brain, in-memory computing aims to enable storage and computing to coexist within the same physical structure. This can significantly reduce energy consumption and clock cycles, enabling parallel computing and offers enormous potential for research and development and application.

[0032] As a new type of non-volatile memory device, memristor has become a strong candidate for in-memory computing architecture due to its ability to maintain its resistance state after power is removed.

[0033] A memristor, or memristor, is a circuit device that represents the relationship between magnetic flux and charge. A memristor unit has the dimension of conductance, but unlike conductance, the resistance of a memristor is determined by the charge flowing through it. Even when the memristor loses power, its conductance remains unchanged, indicating that it possesses a memory function. If the high-resistance state of a memristor is defined as "1" and the low-resistance state as "0," the memristor can store data through its own resistance. Currently, a one-transistor-one-memristor (1T1R) structure is commonly used. 1T1R can be referred to as a memristor unit.

[0034] In some embodiments, the integration of the non-volatile memristor structure in a 1T1R structure is completed within the CMOS back-end process, with the transistors and memristor structure formed on the same wafer. Firstly, this integration method requires completion of the transistors (CMOS process) and must be compatible with the CMOS process. Secondly, the memristor resistive layer is incompatible with the manufacturing temperature and chemical environment of the CMOS process, making integration difficult. Thirdly, the traditional monolithic integration process is highly complex, and a single wafer defect can render the entire wafer scrapped.

[0035] The present disclosure provides a semiconductor device, such as Figure 1 as well as Figure 2As shown, the semiconductor device includes: a first semiconductor structure 101, a first bonding layer 102, and a second semiconductor structure 103 stacked in sequence along a first direction; wherein, the first semiconductor structure 101 includes a transistor structure; the second semiconductor structure 103 includes a memristor structure 104; the first bonding layer 102 includes a first bonding structure 105 and a second bonding structure 106 arranged along a second direction; the memristor structure 104 is connected to the transistor structure through the first bonding structure 105 and the second bonding structure 106; the second direction is perpendicular to the first direction.

[0036] In the embodiment of the present disclosure, the first direction may be the Z-axis direction in the drawings, and the second direction may be the X-axis direction in the drawings.

[0037] In an embodiment of the present disclosure, a semiconductor device includes a first semiconductor structure 101, a first bonding layer 102, and a second semiconductor structure 103 stacked along a first direction. The first semiconductor structure 101 includes a transistor structure, and the second semiconductor structure 103 includes a memristor structure 104. The first semiconductor structure 101 and the second semiconductor structure 103 are bonded together via the first bonding layer 102. In other words, the transistor structure and the memristor structure 104 can be formed on different wafers and then bonded together. First, separately preparing the transistor structure and the memristor structure 104 on different wafers can solve the process incompatibility problem in the preparation of the transistor structure and the memristor structure 104, and can independently optimize the performance of the resistive switching layer in the memristor structure, reducing the overall process difficulty; second, qualified wafers can be independently tested and screened before bonding, reducing costs; third, defective wafers can be removed before bonding to avoid "one loss, all losses" and improve the overall yield; fourth, the first wafer and the second wafer can use the same process or different processes, and the appropriate process can be selected according to actual needs, which can also reduce costs.

[0038] In some embodiments, the first semiconductor structure 101 and the second semiconductor structure 103 are bonded together via the first bonding layer 102. The bonding connection includes a hybrid bonding connection (also referred to as a "metal / dielectric hybrid bonding connection"), which is a direct bonding technology. For example, a bond is formed between surfaces without using an intermediate layer such as solder or adhesive, and metal-metal bonding and dielectric-dielectric bonding can be obtained simultaneously. It should be noted that the "bonding" referred to in the present disclosure may be any appropriate bonding technology, such as the hybrid bonding, anodic bonding, fusion bonding, transfer bonding, adhesive bonding, and eutectic bonding mentioned above. The hybrid bonding connection is taken as an example for exemplary description below.

[0039] In some embodiments, as Figure 2As shown, the first bonding layer 102 includes a first sub-bonding layer 108 and a second sub-bonding layer 109 stacked along the first direction; the first sub-bonding layer 108 is located between the second sub-bonding layer 109 and the first semiconductor structure 101; the first sub-bonding layer 108 includes a first dielectric layer 110, a first bonding contact 111 of the first bonding structure 105 located in the first dielectric layer 110, and a second bonding contact 112 of the second bonding structure 106 located in the first dielectric layer 110. Point 112, the second sub-bonding layer 109 includes a second dielectric layer 113, a third bonding contact 114 of the first bonding structure 105 located in the second dielectric layer 113, and a fourth bonding contact 115 of the second bonding structure 106 located in the second dielectric layer 113; the first dielectric layer 110 is bonded to the second dielectric layer 113, the first bonding contact 111 is bonded to the third bonding contact 114, and the second bonding contact 112 is bonded to the fourth bonding contact 115.

[0040] In the disclosed embodiment, the materials of the first dielectric layer 110 and the second dielectric layer 113 include, but are not limited to, silicon oxide, silicon nitride, silicon carbonitride, and polymers. The materials of the first bonding contact 111, the second bonding contact 112, the third bonding contact 114, and the fourth bonding contact 115 include conductive materials, such as at least one of conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.) and metal materials (e.g., aluminum, copper, tungsten, titanium, tantalum, etc.).

[0041] In the disclosed embodiments, hybrid bonding decouples the resistive switching layer of the memristive structure from the CMOS logic layer, the resistive switching layer material can be independently optimized (such as using low-temperature PEALD to deposit a dense superlattice-like resistive switching layer), and high-performance memristor units can be prepared separately. The hybrid bonding method can solve the problem of incompatibility between the memristive structure and the CMOS logic circuit process.

[0042] In some embodiments, as Figure 2 As shown, the transistor structure includes a first transistor 116 and a second transistor 117 arranged along the second direction; the first semiconductor structure 101 also includes: a first interconnection layer 118; the first interconnection layer 118 is located between the transistor structure and the first bonding layer 102, and the first interconnection layer 118 includes a first interconnection structure 119 and a second interconnection structure 120 arranged along the second direction, the memristive structure 104 is connected to the first transistor 116 through the first bonding structure 105 and the first interconnection structure 119, and the memristive structure 104 is connected to the second transistor 117 through the second bonding structure 106 and the second interconnection structure 120.

[0043] like Figure 2As shown, the first transistor 116 and the second transistor 117 both include a source doping region 133, a drain doping region 134, and a gate structure 135. It should be noted that, Figure 2 The first transistor 116 and the second transistor 117 are planar transistors, but Figure 2 The first transistor 116 and the second transistor 117 are merely examples and are not intended to limit the types of the first transistor 116 and the second transistor 117 in the embodiment of the present disclosure. The first transistor 116 and the second transistor 117 in the embodiment of the present disclosure may also be, for example, vertical transistors.

[0044] In the embodiment of the present disclosure, the material of the first interconnect structure 119 , the second interconnect structure 120 and other interconnect structures described below includes at least one of the conductive metal materials aluminum, copper, tungsten and cobalt.

[0045] In the embodiment of the present disclosure, Figure 2 As shown, the first interconnect structure 119 includes three layers of second conductive wires 128 and four layers of third contact structures 130, and the second interconnect structure 120 includes three layers of third conductive wires 129 and four layers of fourth contact structures 131, but the present disclosure is not limited to this. The number of layers of corresponding contact structures and conductive wires in the first interconnect structure 119 and the second interconnect structure 120 can be set accordingly according to actual conditions.

[0046] In some embodiments, the material of the second conductive lines 128 and the third conductive lines 129 includes a conductive material. The second conductive lines 128 and the third conductive lines 129 can both extend along a third direction, which is perpendicular to both the first and second directions. The materials of different third conductive lines 129 in multiple layers of third conductive lines 129 can be the same or different; the materials of different second conductive lines 128 in multiple layers of second conductive lines 128 can be the same or different; and the materials of the third conductive lines 129 can be the same or different from those of the second conductive lines 128.

[0047] In some embodiments, the materials of the third contact structure 130 and the fourth contact structure 131 include a conductive material. Both the third contact structure 130 and the fourth contact structure 131 extend along the first direction. The portion of the third contact structure 130 near the first transistor 116, along the second direction, is smaller than the portion of the third contact structure 130 far from the first transistor 116. The portion of the fourth contact structure 131 near the second transistor 117, along the second direction, is smaller than the portion of the fourth contact structure 131 far from the second transistor 117. The materials of different third contact structures 130 can be the same or different; the materials of different fourth contact structures 131 can be the same or different; and the materials of the third contact structures 130 and the fourth contact structures 131 can be the same or different.

[0048] In the embodiment of the present disclosure, the third contact structure 130 among the multiple third contact structures 130 of the first interconnect structure 119 that is closest to the first transistor 116 is connected to the drain doping region 134 of the first transistor 116, and the fourth contact structure 131 among the multiple fourth contact structures 131 of the second interconnect structure 120 that is closest to the second transistor 117 is connected to the source doping region 133 of the second transistor 117.

[0049] In some embodiments, as Figure 2 As shown, corresponding interconnect structures are also provided on the gate structure 135 of the first transistor 116 and the source doping region 133, and corresponding interconnect structures are also provided on the gate structure 135 of the second transistor 117 and the drain doping region 134. Figure 2 As shown, the source doping region 133 and the drain doping region 134 of the first transistor 116 and the second transistor 117 can be formed in a first wafer 136. The first wafer 136 includes a substrate, and the material of the substrate includes but is not limited to a single-element semiconductor material (for example, silicon (Si) or germanium (Ge), etc.), a III-V compound semiconductor material (for example, gallium nitride (GaN), gallium arsenide (GaAs) or indium phosphide (InP), etc.), a II-VI compound semiconductor material (for example, zinc sulfide (ZnS), cadmium sulfide (CdS) or cadmium telluride (CdTe), etc.), an organic semiconductor material or other semiconductor materials known in the art.

[0050] In some embodiments, as Figure 2 As shown, a shallow trench isolation structure 132 (STI) is further formed in the first wafer 136 . The material of the shallow trench isolation structure 132 includes an insulating material, which includes but is not limited to silicon oxide and silicon nitride.

[0051] In some embodiments, as Figure 2 As shown, the memristive structure 104 includes a first electrode layer 121 , a resistive switching layer 122 , and a second electrode layer 123 stacked in sequence along the first direction.

[0052] In some embodiments, the material of the first electrode layer 121 includes at least one of a metal material (e.g., Ag, Cu, Ti, Pb, Au, etc.), an alloy material (e.g., Cu-Te alloy, Ag-Cu alloy, etc.), a silicon-based material (e.g., n-Si, p-Si, etc.), or a nitride-based material (e.g., TiN, TaN, etc.); the material of the second electrode layer 123 includes at least one of a metal material (e.g., Ag, Cu, Ti, Pb, Au, etc.), an alloy material (e.g., Cu-Te alloy, Ag-Cu alloy, etc.), a silicon-based material (e.g., n-Si, p-Si, etc.), or a nitride-based material (e.g., TiN, TaN, etc.). The material of the first electrode layer 121 and the material of the second electrode layer 123 may be the same or different.

[0053] In some embodiments, as Figure 2 As shown, the second semiconductor structure 103 also includes a first conductive wire 125, a first contact structure 126 and a second contact structure 127; the first contact structure 126, the second contact structure 127 and the memristive structure 104 are all located between the first bonding layer 102 and the first conductive wire 125; one end of the first contact structure 126 at two opposite ends along the first direction is connected to the first conductive wire 125, and the other end is connected to the first bonding structure 105; one end of the second contact structure 127 at two opposite ends along the first direction is connected to the first electrode layer 121 of the memristive structure 104, and the other end is connected to the second bonding structure 106; the second electrode layer 123 of the memristive structure 104 is connected to the first conductive wire 125.

[0054] In some embodiments, the material of the resistive layer 122 includes metal oxides, perovskite materials, chalcogenide semiconductors, two-dimensional materials, and organic materials.

[0055] In some embodiments, the material of the resistive layer 122 includes oxides of one or more metals selected from the group consisting of Hf, Al, Ti, Ta, Au, W, Ni, Zr, Zn, Fe, Mn, and Nb. In some embodiments, the material of the resistive layer 122 may also include perovskite materials, chalcogenide semiconductors, two-dimensional materials, organic materials, and the like.

[0056] In the embodiments of the present disclosure, semiconductor devices include but are not limited to resistive random access memory (RRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), magnetoresistive random access memory (MRAM), and other non-volatile memory devices with a metal-insulator-metal (MIM) sandwich structure.

[0057] In some embodiments, as Figure 2 As shown, the second semiconductor structure 103 includes a multi-layer first diffusion barrier layer 142. The material of the first diffusion barrier layer 142 includes but is not limited to silicon nitride. The first diffusion barrier layer 142 can be used to improve the diffusion problem of metal elements. In addition, the first diffusion barrier layer 142 can also serve as an etching stop layer to prevent over-etching.

[0058] In some embodiments, as Figure 2 as well as Figure 3 As shown, the semiconductor device further includes a third semiconductor structure 150, which includes a third dielectric layer 147 and a pad structure 146 located in the third dielectric layer 147. The pad structure 146 includes a second diffusion barrier layer 143, an adhesion layer 144, and a conductive layer 145. The material of the third dielectric layer 147 includes, but is not limited to, silicon oxide made of TEOS. The portion of the third dielectric layer 147 located above the pad structure 146 can protect the pad structure 146. The material of the second diffusion barrier layer 143 includes, but is not limited to, tantalum nitride. The second diffusion barrier layer 143 can be used to block the diffusion of metal elements. The material of the adhesion layer 144 includes, but is not limited to, titanium or titanium nitride. The adhesion layer 144 can enhance the adhesion between the conductive layer 145 and the second diffusion barrier layer 143. The material of the conductive layer 145 includes a conductive material, including, but not limited to, aluminum.

[0059] In some embodiments, the first semiconductor structure 101 further includes a peripheral circuit; the transistor structure and the memristor structure 104 are coupled to the peripheral circuit.

[0060] The peripheral circuit may include any suitable digital, analog, and / or mixed signal circuits for facilitating the operation of the semiconductor device. For example, the peripheral circuit may include control logic, a data buffer, a decoder (a decoder may also be referred to as a decoder), a driver, and a read / write circuit. When the control logic receives a read / write operation command and address data, the decoder, under the action of the control logic, may apply the corresponding voltage generated by the driver to the corresponding word line (WL) and bit line (BL) based on the decoded address to implement data read or write operations, and exchange data with the outside through the data buffer.

[0061] Based on a concept similar to the above-mentioned semiconductor device, the present disclosure also provides a method for forming a semiconductor device, such as Figure 4 As shown, the following steps are included: Step S1001: forming a first semiconductor structure on a first wafer, and forming a first sub-bonding layer on the first semiconductor structure; the first semiconductor structure includes a transistor structure and a peripheral circuit; Step S1002: forming a second sub-bonding layer on a second wafer, and forming a second semiconductor structure on the second sub-bonding layer; the second semiconductor structure includes a memristor structure; Step S1003: removing the second wafer to expose the second sub-bonding layer; Step S1004: bonding the first sub-bonding layer to the second sub-bonding layer to form a first bonding layer; the first bonding layer includes a first bonding structure and a second bonding structure; the memristor structure is connected to the transistor structure through the first bonding structure and the second bonding structure.

[0062] In the embodiment of the present disclosure, after forming the memristor structure and the transistor structure on different wafers, the two are bonded together. First, the separate preparation of the transistor structure and the memristor structure on different wafers can solve the process incompatibility problem in the preparation of the transistor structure and the memristor structure, so that the performance of the resistive layer in the memristor structure can be independently optimized, reducing the difficulty of the overall process; second, qualified wafers can be independently tested and screened before bonding, reducing costs; third, defective wafers can be removed before bonding to avoid "one loss for all" and improve the overall yield; fourth, the first wafer and the second wafer can use the same process (for example: both are 55nm process) or different processes (for example: the first wafer is 55nm process, the second wafer is 40nm process), and the appropriate process can be selected according to actual needs, which can also reduce costs.

[0063] It should be understood that Figure 4 The steps shown in the operation are not exclusive, and other steps may be performed before, after, or between any steps in the operation shown; Figure 4The steps shown in the figure can be adjusted in order according to actual needs. In the embodiment of the present disclosure, step S1001 and step S1002 can be performed simultaneously. Step S1003, which removes the second wafer, needs to be performed after step S1002. Step S1004 needs to be performed after completing step S1003 and step S1001 and removing the first protective layer mentioned later.

[0064] Figures 5 to 12 The process diagram of the method for forming a semiconductor device provided by the embodiment of the present disclosure is as follows. Figures 4 to 12 The method for forming a semiconductor device is further introduced.

[0065] In step S1001 , a first semiconductor structure is mainly formed on a first wafer, and a first sub-bonding layer is formed on the first semiconductor structure.

[0066] like Figure 5 As shown, a first wafer 136 is provided, and the first wafer 136 includes a first side and a second side opposite to each other along the thickness direction (i.e., the Z-axis direction) of the first wafer 136. A first semiconductor structure 101 is formed on the first wafer 136 from the first side of the first wafer 136, and then a first sub-bonding layer 108 is formed on the first semiconductor structure 101 from the first side of the first wafer 136.

[0067] The method for forming the first semiconductor structure 101 and the first sub-bonding layer 108 includes a deposition process and an etching process. The deposition process includes, but is not limited to, chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). The etching process includes, but is not limited to, plasma etching (PE), sputtering etching (SE), ion beam etching (IBE), and reactive ion etching (RIE).

[0068] In some embodiments, as Figure 5As shown, the first semiconductor structure 101 is formed on the first wafer 136, including: forming the transistor structure and the peripheral circuit on the first wafer 136; the transistor structure includes a first transistor 116 and a second transistor 117; the transistor structure is coupled to the peripheral circuit.

[0069] In some embodiments, as Figure 5 As shown, the method for forming a semiconductor device further includes forming a first semiconductor structure 101 and a first sub-bonding layer 108 on a first wafer 136, and then forming a first protective layer 138 on the first sub-bonding layer 108 from a first side of the first wafer 136. The material of the first protective layer 138 includes, but is not limited to, silicon oxide and silicon nitride.

[0070] It is understandable that after the first semiconductor structure 101 and the first sub-bonding layer 108 are formed, it may take some time before the first sub-bonding layer 108 is bonded to the second sub-bonding layer. The first protective layer 138 can protect the first sub-bonding layer 108 and prevent the first bonding contact 111 and the second bonding contact 112 in the first sub-bonding layer 108 from being oxidized, resulting in defects in subsequent bonding and other problems.

[0071] In some embodiments, the bonding temperature range of the first sub-bonding layer 108 and the second sub-bonding layer 109 is 200° C. to 400° C.

[0072] In the embodiment of the present disclosure, a lower temperature can be used to bond the first sub-bonding layer 108 to the second sub-bonding layer 109, thereby avoiding affecting the performance of the memristive structure. It should be noted that the bonding temperature range for the first sub-bonding layer 108 and the second sub-bonding layer 109 given in the above embodiment is only an example and is not intended to limit the bonding temperature range for the first sub-bonding layer 108 and the second sub-bonding layer 109 in the embodiment of the present disclosure.

[0073] In some embodiments, as Figure 5 As shown, the first sub-bonding layer 108 includes a first dielectric layer 110 , a first bonding contact 111 of the first bonding structure located in the first dielectric layer 110 , and a second bonding contact 112 of the second bonding structure located in the first dielectric layer 110 .

[0074] In some embodiments, as Figure 5 As shown, the first semiconductor structure 101 is formed on the first wafer 136 , including: forming a first interconnect layer 118 on the transistor structure; the first interconnect layer 118 includes a first interconnect structure 119 and a second interconnect structure 120 .

[0075] In the disclosed embodiment, diffusion barrier layers are formed around the peripheries of the corresponding conductive lines and contact structures in the first interconnect structure 119 and the second interconnect structure 120 to prevent the diffusion of metal elements in the corresponding conductive lines and contact structures. The material of the diffusion barrier layer can be selected based on the material of the corresponding conductive lines and contact structures. For example, when the corresponding conductive lines and contact structures are made of copper, the material of the diffusion barrier layer can be tantalum nitride; alternatively, when the corresponding conductive lines and contact structures are made of cobalt, the material of the diffusion barrier layer can be tantalum or titanium.

[0076] In step S1002 , a second sub-bonding layer is mainly formed on the second wafer, and a second semiconductor structure is formed on the second sub-bonding layer, where the second semiconductor structure includes a memristive structure.

[0077] like Figure 6 As shown, a second wafer 137 is provided, and the second wafer 137 includes a first side and a second side opposite to each other along the thickness direction of the second wafer 137. A second sub-bonding layer 109 is formed on the second wafer 137 from the first side of the second wafer 137, and then a second semiconductor structure 103 is formed on the second sub-bonding layer 109 from the first side of the second wafer 137.

[0078] In the embodiment of the present disclosure, the first wafer 136 and the second wafer 137 may both include a substrate, the material of the substrate including but not limited to a single-element semiconductor material (e.g., silicon (Si) or germanium (Ge), etc.), a III-V compound semiconductor material (e.g., gallium nitride (GaN), gallium arsenide (GaAs), or indium phosphide (InP), etc.), a II-VI compound semiconductor material (e.g., zinc sulfide (ZnS), cadmium sulfide (CdS), or cadmium telluride (CdTe), etc.), an organic semiconductor material, or other semiconductor materials known in the art. The materials of the first wafer 136 and the second wafer 137 may be the same or different.

[0079] In some embodiments, as Figure 6 As shown, the formation method further includes: after providing a second wafer 137, forming a fourth dielectric layer 148 on the second wafer 137 from the first side of the second wafer 137, forming a third diffusion barrier layer 149 on the fourth dielectric layer 148, and forming a second sub-bonding layer 109 on the third diffusion barrier layer 149. The material of the fourth dielectric layer 148 includes, but is not limited to, silicon oxide. The fourth dielectric layer 148 can regulate the stress of the second wafer 137 and reduce the risk of breakage of the second wafer 137. The material of the third diffusion barrier layer 149 includes, but is not limited to, silicon nitride. The third diffusion barrier layer 149 can be used to improve the diffusion of metal elements. In addition, the third diffusion barrier layer 149 can also serve as an etch stop layer to prevent over-etching. In addition, the third diffusion barrier layer 149 can also serve as a grinding stop layer when removing the second wafer.

[0080] In some embodiments, as Figure 6 As shown, forming the memristive structure includes: forming a first electrode layer, a resistive switching layer, and a second electrode layer stacked in sequence along a first direction; the first direction is the stacking direction of the first semiconductor structure 101, the first bonding layer 102, and the second semiconductor structure 103.

[0081] In some embodiments, as Figure 6 As shown, the second sub-bonding layer 109 includes a second dielectric layer 113 , a third bonding contact 114 of the first bonding structure located in the second dielectric layer 113 , and a fourth bonding contact 115 of the second bonding structure located in the second dielectric layer 113 .

[0082] In some embodiments, as Figure 6 As shown, a second semiconductor structure 103 is formed on the second sub-bonding layer 109, including: a first conductive line 125, a first contact structure 126 and a second contact structure 127 are formed on the second sub-bonding layer 109; the first contact structure 126, the second contact structure 127 and the memristive structure 104 are located between the second sub-bonding layer 109 and the first conductive line 125; one end of the first contact structure 126 opposite to each other along the first direction is connected to the first conductive line 125, and the other end is connected to the third bonding contact 114 of the first bonding structure; one end of the second contact structure 127 opposite to each other along the first direction is connected to the first electrode layer of the memristive structure 104, and the other end is connected to the fourth bonding contact 115 of the second bonding structure; the second electrode layer of the memristive structure 104 is connected to the first conductive line 125.

[0083] In some embodiments, as Figure 6 As shown, forming the second semiconductor structure further includes forming a second protective layer 139 on the first conductive line 125 from the first side of the second wafer 137. The material of the second protective layer 139 includes silicon oxide and silicon nitride. The second protective layer 139 can prevent damage to the first conductive line 125 and the second semiconductor structure 103 during the subsequent formation of the temporary bonding layer and bonding with the carrier wafer.

[0084] In some embodiments, as Figure 7As shown, the formation method also includes: before removing the second wafer 137 to expose the second sub-bonding layer, forming a temporary bonding adhesive layer 140 on the second semiconductor structure 103, and bonding the temporary bonding adhesive layer 140 to the carrier wafer 141; or, before removing the second wafer 137 to expose the second sub-bonding layer, forming a temporary bonding adhesive layer 140 on the carrier wafer 141, and bonding the temporary bonding adhesive layer 140 to the second semiconductor structure 103.

[0085] It is understandable that the temporary bonding layer 140 in the embodiment of the present disclosure can be formed on the carrier wafer 141 or on the second semiconductor structure 103. The embodiment of the present disclosure does not limit this. The specific method can be determined according to the debonding method.

[0086] In some embodiments, as Figure 7 As shown, the forming method further includes: forming a temporary bonding adhesive layer 140 on the second protective layer 139 from the first side of the second wafer 137 , and bonding the temporary bonding adhesive layer 140 to the carrier wafer 141 .

[0087] In some embodiments, as Figure 7 As shown, the forming method further includes: forming a temporary bonding adhesive layer 140 on the carrier wafer 141 , and bonding the temporary bonding adhesive layer 140 to the second protective layer 139 .

[0088] In step S1003 , the second wafer is mainly removed to expose the second sub-bonding layer.

[0089] like Figure 7 as well as Figure 8 As shown, the second wafer 137 is removed from the second side of the second wafer 137 to expose the second sub-bonding layer 109 .

[0090] In some embodiments, a method of removing the second wafer 137 includes but is not limited to chemical mechanical polishing (CMP).

[0091] In some embodiments, when the fourth dielectric layer 148 and the third diffusion barrier layer 149 are formed, the forming method further includes: Figure 7 as well as Figure 8 As shown, the fourth dielectric layer 148 and the third diffusion barrier layer 149 are removed to expose the second sub-bonding layer 109 .

[0092] In some embodiments, as Figure 9As shown, before bonding the first sub-bonding layer 108 to the second sub-bonding layer 109 , the forming method further includes removing the first protection layer 138 from the first side of the first wafer 136 to expose the first sub-bonding layer 108 .

[0093] In some embodiments, the method of removing the first protection layer 138 includes, but is not limited to, chemical mechanical polishing.

[0094] In the embodiment of the present disclosure, before the first sub-bonding layer 108 is bonded to the second sub-bonding layer 109 , the process steps on the first wafer 136 and the second wafer 137 can be performed simultaneously, thereby saving process time.

[0095] In step S1004, Figure 10 As shown, the first sub-bonding layer 108 is mainly bonded to the second sub-bonding layer 109 to form a first bonding layer 102; the first bonding layer 102 includes a first bonding structure 105 and a second bonding structure 106; the memristive structure is connected to the transistor structure through the first bonding structure 105 and the second bonding structure 106.

[0096] In some embodiments, the memristor structure is connected to the first transistor 116 through the first bonding structure 105 and the first interconnect structure 119 , and the memristor structure is connected to the second transistor 117 through the second bonding structure 106 and the second interconnect structure 120 .

[0097] In some embodiments, bonding the first sub-bonding layer 108 to the second sub-bonding layer 109 includes: bonding the first dielectric layer to the second dielectric layer, bonding the first bonding contact to the third bonding contact, and bonding the second bonding contact to the fourth bonding contact.

[0098] In some embodiments, as Figure 11 As shown, the forming method further includes: after bonding the first sub-bonding layer 108 and the second sub-bonding layer 109 , removing the temporary bonding adhesive layer 140 and the carrier wafer 141 .

[0099] In some embodiments, as Figure 11 as well as Figure 12 As shown, the formation method further includes forming a third semiconductor structure 150 on the second protective layer 139 after bonding the first sub-bonding layer 108 to the second sub-bonding layer 109. The third semiconductor structure 150 includes a third dielectric layer 147 and a pad structure 146 located in the third dielectric layer 147. The pad structure 146 includes a second diffusion barrier layer 143, an adhesion layer 144, and a conductive layer 145.

[0100] It should be noted that the above embodiments and the accompanying drawings are described using the example of forming the third semiconductor structure 150 after the first sub-bonding layer 108 and the second sub-bonding layer 109 are bonded, but the embodiments of the present disclosure are not limited to this. In the embodiments of the present disclosure, the third semiconductor structure 150 can also be formed from the first side of the second wafer 137 before the first sub-bonding layer 108 and the second sub-bonding layer 109 are bonded.

[0101] In some embodiments, a plurality of second semiconductor structures and a plurality of second sub-bonding layers are formed on the second wafer; the formation method further includes: before removing the second wafer to expose the second sub-bonding layer, forming a temporary bonding layer on the second semiconductor structure, and bonding the temporary bonding layer to a carrier wafer; or, before removing the second wafer to expose the second sub-bonding layer, forming a temporary bonding layer on the carrier wafer, and bonding the temporary bonding layer to the second semiconductor structure; after removing the second wafer to expose the second sub-bonding layer, cutting the carrier wafer, the temporary bonding layer on the carrier wafer, the second sub-bonding layer and the second semiconductor structure to form a plurality of chips; the chip includes the second semiconductor structure and the second sub-bonding layer; after bonding the first sub-bonding layer to the second sub-bonding layer, removing part of the temporary bonding layer on the chip and part of the carrier wafer on the chip.

[0102] It is understood that in the embodiment of the present disclosure, the first semiconductor structure and the second semiconductor structure can be wafer-to-wafer bonding or chip-to-wafer bonding. In the chip-to-wafer bonding method, before the first sub-bonding layer is bonded to the second sub-bonding layer, the second sub-bonding layer and the second semiconductor structure on the carrier wafer can be cut into multiple chips, so that the multiple chips on the same wafer can be screened accordingly, and the multiple screened known good chips (KGD) can be further bonded to the first sub-bonding layer 108 on the first wafer.

[0103] For other details about the method of forming the semiconductor device, please refer to the above-mentioned introduction on the semiconductor device side. For the sake of brevity, it will not be repeated here.

[0104] It should be understood that “one embodiment” or “an embodiment” mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, “in one embodiment” or “in an embodiment” appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0105] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0106] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the present disclosure, and they should all be covered by the protection scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: include: A first semiconductor structure, a first bonding layer, and a second semiconductor structure are sequentially stacked along a first direction; wherein, The first semiconductor structure includes a transistor structure; the second semiconductor structure includes a memristor structure; the first bonding layer includes a first bonding structure and a second bonding structure arranged along a second direction; the memristor structure is connected to the transistor structure through the first bonding structure and the second bonding structure; the second direction is perpendicular to the first direction.

2. The semiconductor device according to claim 1, wherein The first bonding layer includes a first sub-bonding layer and a second sub-bonding layer stacked along the first direction; the first sub-bonding layer is located between the second sub-bonding layer and the first semiconductor structure; the first sub-bonding layer includes a first dielectric layer, a first bonding contact of the first bonding structure located in the first dielectric layer, and a second bonding contact of the second bonding structure located in the first dielectric layer; the second sub-bonding layer includes a second dielectric layer, a third bonding contact of the first bonding structure located in the second dielectric layer, and a fourth bonding contact of the second bonding structure located in the second dielectric layer; the first dielectric layer is bonded to the second dielectric layer, the first bonding contact is bonded to the third bonding contact, and the second bonding contact is bonded to the fourth bonding contact.

3. The semiconductor device according to claim 1, wherein The transistor structure includes a first transistor and a second transistor arranged along the second direction; The first semiconductor structure further includes: a first interconnection layer; the first interconnection layer is located between the transistor structure and the first bonding layer, the first interconnection layer includes a first interconnection structure and a second interconnection structure arranged along the second direction, the memristive structure is connected to the first transistor through the first bonding structure and the first interconnection structure, and the memristive structure is connected to the second transistor through the second bonding structure and the second interconnection structure.

4. The semiconductor device according to claim 1, wherein The memristive structure includes a first electrode layer, a resistive switching layer, and a second electrode layer sequentially stacked along the first direction.

5. The semiconductor device according to claim 4, wherein The second semiconductor structure further includes a first conductive line, a first contact structure, and a second contact structure; the first contact structure, the second contact structure, and the memristive structure are located between the first bonding layer and the first conductive line; One end of the first contact structure's two opposite ends along the first direction is connected to the first conductive line, and the other end is connected to the first bonding structure; one end of the second contact structure's two opposite ends along the first direction is connected to the first electrode layer of the memristive structure, and the other end is connected to the second bonding structure; the second electrode layer of the memristive structure is connected to the first conductive line.

6. The semiconductor device according to claim 4, wherein The material of the resistive switching layer includes at least one of the following: metal oxide, perovskite material, chalcogenide semiconductor, two-dimensional material, and organic material.

7. The semiconductor device according to claim 1, wherein The first semiconductor structure further includes a peripheral circuit; the transistor structure and the memristor structure are coupled to the peripheral circuit.

8. A method for forming a semiconductor device, characterized in that: The forming method comprises: forming a first semiconductor structure on a first wafer and forming a first sub-bonding layer on the first semiconductor structure; the first semiconductor structure includes a transistor structure; forming a second sub-bonding layer on the second wafer, and forming a second semiconductor structure on the second sub-bonding layer; the second semiconductor structure includes a memristive structure; removing the second wafer to expose the second sub-bonding layer; The first sub-bonding layer is bonded to the second sub-bonding layer to form a first bonding layer; the first bonding layer includes a first bonding structure and a second bonding structure; the memristive structure is connected to the transistor structure through the first bonding structure and the second bonding structure.

9. The forming method according to claim 8, wherein: The bonding temperature range of the first sub-bonding layer and the second sub-bonding layer is 200° C. to 400° C.

10. The forming method according to claim 8, wherein: The first sub-bonding layer includes a first dielectric layer, a first bonding contact of the first bonding structure located in the first dielectric layer, and a second bonding contact of the second bonding structure located in the first dielectric layer; the second sub-bonding layer includes a second dielectric layer, a third bonding contact of the first bonding structure located in the second dielectric layer, and a fourth bonding contact of the second bonding structure located in the second dielectric layer; Bonding the first sub-bonding layer to the second sub-bonding layer includes: The first dielectric layer is bonded to the second dielectric layer, the first bonding contact is bonded to the third bonding contact, and the second bonding contact is bonded to the fourth bonding contact.

11. The forming method according to claim 8, wherein: The forming of the first semiconductor structure on the first wafer includes: forming the transistor structure and the peripheral circuit on the first wafer; the transistor structure comprising a first transistor and a second transistor; the transistor structure and the memristor structure being coupled to the peripheral circuit; A first interconnect layer is formed on the transistor structure; the first interconnect layer includes a first interconnect structure and a second interconnect structure, the memristive structure is connected to the first transistor through the first bonding structure and the first interconnect structure, and the memristive structure is connected to the second transistor through the second bonding structure and the second interconnect structure.

12. The forming method according to claim 8, wherein: Forming the memristive structure includes forming a first electrode layer, a resistive switching layer, and a second electrode layer stacked in sequence along a first direction; the first direction is the stacking direction of the first semiconductor structure, the first bonding layer, and the second semiconductor structure.

13. The forming method according to claim 12, wherein: The step of forming a second semiconductor structure on the second sub-bonding layer includes: A first conductive line, a first contact structure and a second contact structure are formed on the second sub-bonding layer; the first contact structure, the second contact structure and the memristive structure are located between the second sub-bonding layer and the first conductive line; one end of the first contact structure opposite to each other along the first direction is connected to the first conductive line, and the other end is connected to the first bonding structure; one end of the second contact structure opposite to each other along the first direction is connected to the first electrode layer of the memristive structure, and the other end is connected to the second bonding structure; the second electrode layer of the memristive structure is connected to the first conductive line.

14. The forming method according to claim 8, wherein: The forming method further comprises: Before removing the second wafer to expose the second sub-bonding layer, forming a temporary bonding layer on the second semiconductor structure, and bonding the temporary bonding layer to a carrier wafer; or, before removing the second wafer to expose the second sub-bonding layer, forming a temporary bonding layer on a carrier wafer, and bonding the temporary bonding layer to the second semiconductor structure; After bonding the first sub-bonding layer and the second sub-bonding layer, removing the temporary bonding adhesive layer and the carrier wafer.

15. The forming method according to claim 8, wherein: A plurality of second semiconductor structures and a plurality of second sub-bonding layers are formed on the second wafer; the forming method further includes: Before removing the second wafer to expose the second sub-bonding layer, forming a temporary bonding layer on the second semiconductor structure, and bonding the temporary bonding layer to a carrier wafer; or, before removing the second wafer to expose the second sub-bonding layer, forming a temporary bonding layer on a carrier wafer, and bonding the temporary bonding layer to the second semiconductor structure; After removing the second wafer to expose the second sub-bonding layer, cutting the carrier wafer, the temporary bonding layer on the carrier wafer, the second sub-bonding layer, and the second semiconductor structure to form a plurality of chips; the chips include the second semiconductor structure and the second sub-bonding layer; After bonding the first sub-bonding layer to the second sub-bonding layer, a portion of the temporary bonding layer on the chip and a portion of the carrier wafer on the chip are removed.

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