Cell structure forming method of groove-type SiC MOSFET device, cell structure of groove-type SiC MOSFET device, groove-type SiC MOSFET device and electronic equipment

Abstract

The invention relates to a cell structure forming method of a groove-type SiC MOSFET device, a cell structure of the groove-type SiC MOSFET device, the groove-type SiC MOSFET device and electronic equipment. According to the embodiment of the invention, a bottom P + injection structure at the bottom of a gate groove structure is connected with a source metal structure through a conductive communication structure, so that the gate-oxide electric field intensity of the bottom and corners of a groove can be greatly reduced; and the dielectric layer ILD is arranged between the gate trench structure and the source metal structure, so that isolation of the gate trench structure and the source metal structure can be realized, the stability of electrical performance in the device is ensured, and the service life of the device can be prolonged through the method so as to ensure long-term reliability. Moreover, according to the embodiment of the invention, the conductive communication structure is formed by opening the grid trench structure, and the cell size does not need to be greatly increased, so that the influence on the conduction characteristic is relatively small. In the process, mega-electron volt high-energy or large-dose ion implantation is not needed, silicon carbide deep groove etching is not needed, and the number of conducting channels is not sacrificed.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a method for forming a cellular structure of a trench SiC MOSFET device, a cellular structure thereof, a trench SiC MOSFET device, and an electronic device. Background Art

[0002] In recent years, SiC power devices have become an indispensable part of the new energy industry chain and have rapidly captured the market share of power devices in the fields of electric vehicles, solar power generation, wind power generation, medical equipment, etc. One of the most important components of SiC power devices is the switching element, namely the high-power MOSFET. SiC MOSFET is mainly divided into two structures, planar and trench types. The process flow of planar MOSFET is relatively simple, but the cell size is relatively large and the on-resistance is also large. The integration of trench MOSFET is nearly twice as high as that of planar type, but the device design and process are relatively complex. The present invention focuses on solving one of the most important design problems of trench MOSFET, the gate oxide protection at the bottom of the trench.

[0003] Figure 1 (a) shows a basic trench SiC MOSFET structure diagram, which does not include the gate oxide protection at the bottom of the trench. Figure 1 (b) shows the schematic diagram of P+ implantation at the bottom of the trench as gate oxide protection. Figure 1 (c) shows a schematic diagram of the electric field distribution inside silicon carbide along the center tangent of the device. The dotted line represents the case without gate oxide protection, and the solid line represents the case with P+ gate oxide protection. Figure 1 In (a), the dielectric layer (gate oxide) in the trench separates the polysilicon gate electrode (poly-Si) from the SiC. In the off state, the source electrode at the top of the device is grounded, the drain electrode at the bottom is connected to a positive high voltage, and the gate electrode gate poly is grounded. Under this bias condition, the electric field in the N-epilayer is trapezoidal, as shown in the figure below. Figure 1 As shown by the dotted line in (c), the highest point of the electric field is located at the SiC at the bottom of the trench. The excellent properties of silicon carbide material allow this electric field to be as high as 2 to 3 MV / cm. Given the difference in dielectric constants between SiC and SiO2 (εSiC = 9.7, εSiO2 = 3.9), Gauss's law causes the maximum electric field of SiO2 at the bottom of the trench to reach 2.5 times that of the adjacent SiC (i.e., 5.0 to 7.5 MV / cm), which greatly exceeds the maximum electric field that the gate oxide reliability allows (3.5 to 4.0 MV / cm). To solve this problem, a P+ implantation region can be introduced at the bottom of the trench so that the electric field can drop rapidly in the P+ region. Figure 1 As shown by the solid line in (c), the electric field in the adjacent SiO2 is reduced.

[0004] The P+ injection at the bottom of the trench theoretically solves the one-dimensional electric field problem, but in practice, the two-dimensional gathering effect of the electric field lines is more noteworthy. Specifically, because the gate oxide corner at the bottom of the trench is close to 90 degrees, the two-dimensional geometric effect makes the local electric field at the corner much higher than the electric field at the flat part of the trench bottom. Figure 1 (b)) under the shutdown condition with V ds =650V voltage, the electric field in the gate oxide layer is about 1.45MV / cm in the flat part and as high as 5.70MV / cm in the corner, which is a serious reliability risk! ( Figure 2 The middle left illustration and red curve represent the case where the P+ at the bottom of the trench is not grounded, and the right illustration and green curve represent the case where the P+ at the bottom of the trench is grounded).

[0005] by Figure 1 In the trench SiC MOSFET structure shown in (b), the P+ implanted region at the bottom of the trench will be at a floating potential if no special treatment is done. In this case, when the device is in the off state (source and gate are grounded, and the drain is at a positive high voltage), the gate oxide electric field at the bottom corner of the trench will reach 5.70 MV / cm, as shown in Figure 1. Figure 2 As shown in the left illustration and red curve, the industry consensus in SiC MOSFET design is that the gate oxide electric field strength should not exceed 3.5-4.0 MV / cm. If the P+ at the bottom of the trench is grounded, the maximum electric field in the gate oxide is only 1.70 MV / cm (a 70% decrease) under the same bias conditions. Figure 2 Shown in the right inset and green curve.

[0006] To protect the gate oxide at the bottom of the trench of trench SiC MOSFET from breakdown, the industry currently has the following designs:

[0007] The first design uses a source deep trench structure, such as Figure 3 As shown. This structure etches two deeper source trenches on both sides of the gate trench, performs high-energy P-type ion implantation inside the source trench, and forms an ohmic contact at the bottom of the trench. This design ensures that the source deep trench P region is grounded in the off state, forcing most of the electric field lines to terminate in these two P regions instead of the bottom of the trench, thereby alleviating the electric field strength at the bottom of the gate and protecting the gate oxide at the bottom of the trench. This design requires SiC trench etching with a large aspect ratio, as well as ion implantation and ohmic contact inside the deep trench, which poses great challenges to process capabilities. Due to the addition of two source trenches, the cell size will inevitably increase, with a certain sacrifice in the conduction characteristics of the device. At the same time, a JFET region is formed between the two source P regions, which will introduce additional resistance.

[0008] The second design uses an asymmetric cell structure, that is, only one of the two sidewalls of the gate trench is used to conduct current, and the SiC implanted adjacent to the other sidewall is P-type (P+), such as Figure 4 As shown. This P+ region is deeper than the trench and semi-encloses the right half of the trench. The P+ implant region on the left side of the cell has the same depth and is connected to the P-body. Both P+ regions are grounded through the top ohmic contact. This design uses P+ to ensure that the right corner of the trench is grounded. At the same time, because the bottom of the P+ on both sides is lower than the bottom of the trench on the left, the electric field is shielded, thereby protecting the bottom of the trench and the corner gate oxide layer. This design requires a large dose of high-energy P-type implant, which is a challenge for equipment and yield. In addition, half of the conduction channel is closed, which greatly sacrifices the conduction capability. At the same time, a JFET region is formed between the two P+ regions, which will introduce additional resistance.

[0009] The third design is somewhat similar to the dual source trench design, such as Figure 5 The difference is that this design uses high-energy, high-dose P-type implantation to form two deep P+ regions at the source on both sides of the gate trench. The lower ends of these two P+ regions are lower than the bottom of the gate trench, resulting in most electric field lines terminating at the P+ rather than the bottom of the trench, thus protecting the bottom of the trench. The high-energy implantation used in this design requires a mask with a large aspect ratio and high-energy, high-beam implantation equipment of at least 2MeV, and inevitably increases the size of the cell. A JFET region is also formed between the two P+ regions, which increases the on-resistance.

[0010] The above three trench SiC MOSFET structures use different methods to protect the gate oxide at the bottom of the trench, but all of them come at a considerable cost, including difficult (large aspect ratio) deep trench etching, high-dose high-energy ion implantation, challenges in cell size and complexity, and even sacrificing part of the conduction channel. Summary of the Invention

[0011] According to one aspect of the present disclosure, a method for forming a cell structure of a trench SiC MOSFET device is provided, the method comprising:

[0012] Growing a substrate epitaxial layer on the substrate to form a cellular main structure;

[0013] Performing ion implantation on the epitaxial layer of the substrate to form a P+ implantation structure, an N+ implantation structure, and a P-Body structure;

[0014] forming a gate trench, performing P+ ion implantation on the bottom of the gate trench to form a bottom P+ implantation structure at the bottom of the gate trench structure, and depositing gate polysilicon after forming a gate oxide layer in the gate trench to form a gate trench structure;

[0015] forming a dielectric layer ILD on the cell main structure, wherein the dielectric layer ILD covers the gate trench structure, and a boundary of the dielectric layer ILD exceeds a boundary of the gate trench structure;

[0016] Etching the gate trench structure to obtain a channel with a depth reaching the surface of the P+ implantation structure, wherein the channel passes through the dielectric layer ILD, the gate polysilicon, and the gate oxide layer;

[0017] forming ohmic metal on the surfaces of the N+ structure and the P+ structure, and on the surface of the P+ injection structure, and filling the channel with a conductive material to obtain the conductive connection structure;

[0018] Depositing a surface metal layer on the top area of ​​the cell main structure to form a source metal structure, wherein the source metal structure is electrically connected to the bottom P+ injection structure;

[0019] A back metal layer is deposited on the bottom area of ​​the cell main structure to form a drain metal structure.

[0020] In a possible implementation, ion implantation is performed on the substrate epitaxial layer to form a P+ implantation structure, an N+ implantation structure, and a P-Body structure, including:

[0021] Performing P-type ion implantation on the epitaxial layer of the substrate to form a P-body structure;

[0022] Performing N-type ion implantation on the epitaxial layer of the substrate to form an N+ implantation structure;

[0023] A photolithography mask is formed on both sides of the epitaxial layer of the substrate, and P-type ion implantation is performed to form a P+ implantation structure.

[0024] The P-Body structure is below the P+ injection structure and the N+ injection structure.

[0025] In a possible embodiment, the doping concentration of the substrate epitaxial layer is 2.0×10 14 cm -3 ~1.5x10 16 cm -3 The doping concentration of the P-Body structure is 10 16 cm -3 ~10 18 cm -3 , the doping concentration of N+ implantation structure is 10 19 cm -3 ~10 20 cm -3 , the doping concentration of the P+ injection structure is 10 20 cm -3 ~1021 cm -3 The trench depth of the gate trench structure is 1.0 to 1.5 μm, and the width of the conductive connection structure is less than or equal to 1.5 μm.

[0026] In a possible implementation, the forming of the gate trench and the implantation of P+ ions into the bottom of the gate trench include:

[0027] Depositing a mask on the surface of the cell main structure, performing photolithography and RIE etching to obtain the gate trench;

[0028] P+ ion implantation is performed directly on the bottom of the gate trench while retaining the mask.

[0029] In one possible implementation, a channel having a depth reaching the surface of the P+ injection structure is obtained by etching the gate trench structure, an ohmic metal is formed on the surfaces of the N+ structure and the P+ structure, and the surface of the P+ injection structure, and the channel is filled with a conductive material to obtain the conductive connection structure, including:

[0030] Etching the channel using photolithography and RIE etching techniques;

[0031] After removing the photoresist and cleaning, performing a low-temperature thermal oxidation operation on the gate trench to form a bottom oxide layer on the surface of the polysilicon;

[0032] Removing the oxide layer on the source metal structure and the oxide layer at the bottom of the gate trench by using RIE technology, depositing ohmic metal on the surfaces of the N+ structure and the P+ structure not covered by the dielectric layer ILD and the surface of the P+ implantation structure, and performing an ohmic annealing process;

[0033] The channel is filled with a metal filling process, and the filled conductive material is directly connected to the source metal structure.

[0034] In one possible implementation, if the trench SiC MOSFET device is an N-channel MOSFET type, two N+ implant structures are respectively adjacent to both sides of the gate trench structure, and two P+ implant structures are respectively located on both sides of the cell main structure and adjacent to the corresponding N+ implant structures, wherein the dielectric layer ILD covers portions of the gate trench structure and the two N+ implant structures;

[0035] In one possible embodiment, if the trench SiC MOSFET device is a P-channel MOSFET type, two P+ injection structures are respectively adjacent to both sides of the gate trench structure, and two N+ injection structures are respectively located on both sides of the cell main structure and adjacent to the corresponding P+ injection structures, wherein the dielectric layer ILD covers portions of the gate trench structure and the two P+ injection structures.

[0036] According to one aspect of the present disclosure, a cellular structure of a trench SiC MOSFET device is provided, wherein the cellular structure is obtained by the method described, wherein the cellular structure comprises:

[0037] The main structure of the cell includes a substrate and a substrate epitaxial layer;

[0038] A source metal structure is provided in the top region of the cell main structure;

[0039] A drain metal structure is provided in the bottom area of ​​the cell main structure;

[0040] A gate trench structure is provided in the cell main body structure, wherein the gate trench structure is filled with polysilicon;

[0041] A bottom P+ implantation structure is provided at the bottom of the gate trench structure;

[0042] A conductive connection structure, penetrating the gate trench structure, to achieve electrical connection between the source metal structure and the bottom P+ implantation structure; and

[0043] A P+ injection structure, an N+ injection structure, a P-Body structure, and an ohmic metal structure disposed on both sides of the gate trench structure, between the P+ injection structure, the N+ injection structure, and the source metal structure;

[0044] A dielectric layer ILD covers the gate trench structure, and a boundary of the dielectric layer ILD exceeds a boundary of the gate trench structure. The boundaries of the dielectric layer ILD are respectively adjacent to boundaries of the two ohmic metal structures.

[0045] In a possible implementation, a current diffusion layer is provided below the P-Body structure.

[0046] An N-pillar structure is provided below the current diffusion layer.

[0047] A P-pillar structure is provided below the bottom P+ injection structure.

[0048] The depth of the N-pillar structure and the P-pillar structure is less than or equal to the depth between the current diffusion layer and the substrate.

[0049] According to one aspect of the present disclosure, a trench SiC MOSFET device is provided, comprising the cell structure of the trench SiC MOSFET device.

[0050] According to one aspect of the present disclosure, an electronic device is provided, comprising the SiCMOSFET device.

[0051] The embodiment of the present disclosure connects the bottom P+ injection structure at the bottom of the gate trench structure to the source metal structure through a conductive connection structure, which can significantly reduce the gate oxide electric field strength at the bottom of the trench and the corners, and by providing a dielectric layer ILD between the gate trench structure and the source metal structure, the two can be isolated to ensure the stability of the internal electrical performance of the device. The above method can extend the life of the SiC MOSFET device to ensure long-term reliability. In addition, the embodiment of the present disclosure forms a conductive connection structure by opening a hole in the gate trench structure, without significantly increasing the cell size, and therefore has little effect on the conduction characteristics. In terms of process, no mega-electron-volt high-energy or high-dose ion implantation is required, no silicon carbide deep trench etching is required, and the number of conduction channels is not sacrificed.

[0052] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, rather than limiting the present disclosure. Other features and aspects of the present disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] The accompanying drawings herein are incorporated into and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and, together with the specification, are used to explain the technical solutions of the present disclosure.

[0054] Figure 1 A schematic diagram of a trench SiC MOSFET structure according to an embodiment of the present disclosure is shown.

[0055] Figure 2 A schematic diagram of the electric field distribution of a trench-type 650V SiC MOSFET according to an embodiment of the present disclosure is shown.

[0056] Figure 3 FIG. 1 is a schematic diagram showing a related art SiC trench MOSFET using a source trench to protect the gate oxide at the bottom of the trench.

[0057] Figure 4 A schematic diagram of the structure of a SiC trench MOSFET in the related art using a P+ deep implantation semi-encircling structure to protect the gate oxide at the bottom of the trench is shown.

[0058] Figure 5 A schematic diagram of the structure of a SiC trench MOSFET using deep source P+ implantation on both sides to protect the gate oxide at the bottom of the trench is shown in the related art.

[0059] Figure 6a A flow chart of a method for forming a cell structure of a trench SiC MOSFET device according to an embodiment of the present disclosure is shown.

[0060] Figure 6b A schematic diagram of a trench SiC MOSFET structure according to an embodiment of the present disclosure is shown.

[0061] Figure 7a 、 Figure 7b 、 Figure 7c 、 Figure 7d 、 Figure 7e 、 Figure 7f 、 Figure 7g 、 Figure 7h A schematic diagram illustrating a method for forming a cell structure of a trench SiC MOSFET device according to an embodiment of the present disclosure is shown.

[0062] Figure 8 Another schematic diagram of a trench SiC MOSFET structure according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0063] Various exemplary embodiments, features, and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise indicated.

[0064] In the description of the present disclosure, it should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0065] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the present disclosure, "plurality" means two or more, unless otherwise specifically defined.

[0066] In this disclosure, unless otherwise expressly specified or limited, terms such as "mounted," "connected," "connect," and "fixed" should be understood broadly. For example, they may refer to fixed connections, detachable connections, or integration; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and internal connections between two components or interactions between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure based on specific circumstances.

[0067] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0068] The term "and / or" herein simply describes an association relationship between associated objects, indicating that three relationships can exist. For example, "A and / or B" can represent the existence of three situations: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" herein refers to any combination of at least two of any one or more of a plurality of items. For example, "at least one of A, B, and C" can represent any one or more elements selected from the set consisting of A, B, and C.

[0069] In addition, numerous specific details are provided in the following detailed description to better illustrate the present disclosure. Those skilled in the art will appreciate that the present disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art are not described in detail in order to highlight the main points of the present disclosure.

[0070] See also Figure 6a , Figure 6a A flow chart of a method for forming a cell structure of a trench SiC MOSFET device according to an embodiment of the present disclosure is shown.

[0071] like Figure 6a As shown, the method includes:

[0072] Step S11, growing a substrate epitaxial layer on the substrate to form a cell main structure;

[0073] Step S12, performing ion implantation on the epitaxial layer of the substrate to form a P+ implantation structure, an N+ implantation structure, and a P-Body structure;

[0074] Step S13, forming a gate trench, performing P+ ion implantation on the bottom of the gate trench to form a bottom P+ implantation structure at the bottom of the gate trench structure, and depositing gate polysilicon after forming a gate oxide layer in the gate trench to form a gate trench structure;

[0075] Step S14, forming a dielectric layer ILD on the cell main structure, wherein the dielectric layer ILD covers the gate trench structure, and a boundary of the dielectric layer ILD exceeds a boundary of the gate trench structure;

[0076] Step S15, etching the gate trench structure to obtain a channel with a depth reaching the surface of the P+ implantation structure, wherein the channel passes through the dielectric layer ILD, the gate polysilicon, and the gate oxide layer;

[0077] Step S16, forming ohmic metal on the surface of the N+ structure and the P+ structure, and the surface of the P+ injection structure, and filling the channel with a conductive material to obtain the conductive connection structure;

[0078] Step S17, depositing a surface metal layer on the top area of ​​the cell main structure to form a source metal structure, wherein the source metal structure is electrically connected to the bottom P+ injection structure;

[0079] Step S18: depositing a back metal layer on the bottom area of ​​the cell main structure to form a drain metal structure.

[0080] The embodiment of the present disclosure connects the bottom P+ injection structure at the bottom of the gate trench structure to the source metal structure through a conductive connection structure, which can significantly reduce the gate oxide electric field strength at the bottom of the trench and the corners, and by providing a dielectric layer ILD between the gate trench structure and the source metal structure, the two can be isolated to ensure the stability of the internal electrical performance of the device. The above method can extend the life of the SiC MOSFET device to ensure long-term reliability. In addition, the embodiment of the present disclosure forms a conductive connection structure by opening a hole in the gate trench structure, without significantly increasing the cell size, and therefore has little effect on the conduction characteristics. In terms of process, no mega-electron-volt high-energy or high-dose ion implantation is required, no silicon carbide deep trench etching is required, and the number of conduction channels is not sacrificed.

[0081] See also Figure 6b , Figure 6b A schematic diagram of a trench SiC MOSFET structure according to an embodiment of the present disclosure is shown.

[0082] pass Figure 6a The various steps of the cell structure formation method of the trench SiC MOSFET device shown in FIG. Figure 6b The cell structure of the trench SiC MOSFET device is shown in Figure 6b As shown, the cellular structure includes:

[0083] The main cell structure 100 includes a substrate (N+substrate) and a substrate epitaxial layer (N-epilayer);

[0084] A source metal structure 110 is provided in the top region of the cell main structure 100;

[0085] The drain metal structure 120 is provided at the bottom area of ​​the cell main structure 100;

[0086] A gate trench structure 130 is provided in the cell main structure 100 , and the gate trench structure 130 is filled with polysilicon (Poly-Si);

[0087] A bottom P+ implantation structure 140 is provided at the bottom of the gate trench structure 130 ;

[0088] A conductive connection structure 150 passes through the gate trench structure 130 to achieve electrical connection between the source metal structure 110 and the bottom P+ implantation structure 140; and

[0089] A P+ implant structure 160 , an N+ implant structure 170 , a P-Body structure 180 disposed on both sides of the gate trench structure 130 , and an ohmic metal structure (OMC) between the P+ implant structure 160 , the N+ implant structure 170 and the source metal structure 110 ;

[0090] A dielectric layer ILD 190 covers the gate trench structure, and a boundary of the dielectric layer ILD 190 exceeds a boundary of the gate trench structure. The boundaries of the dielectric layer ILD 190 are adjacent to boundaries of the two ohmic metal structures.

[0091] The embodiment of the present disclosure does not limit the types of the substrate, substrate epitaxial layer, etc. in the cell main structure 100, and the positions of the P+ injection structure 160 and the N+ injection structure 170. Those skilled in the art can determine them according to the type of the trench SiC MOSFET device. For example, if the trench SiC MOSFET device is an N-channel MOSFET, the substrate can be an N-type substrate, the substrate epitaxial layer can be an N-type epitaxial layer, and the positions of the P+ injection structure 160 and the N+ injection structure 170 of the N-channel MOSFET are as follows: Figure 6b As shown (the N+ implantation structure 170 is close to the gate trench structure 130). Accordingly, if the trench SiCMOSFET device is a P-channel MOSFET, the substrate can be a P-type substrate, the substrate epitaxial layer can be a P-type epitaxial layer, the implantation structure 160 is changed to N+ doping, and the implantation structure 170 is changed to P+ doping.

[0092] For example, if the trench SiC MOSFET device is an N-channel MOSFET type, then Figure 6bAs shown, two N+ implantation structures 170 are respectively adjacent to the two sides of the gate trench structure 130, and two P+ implantation structures 160 are respectively located on both sides of the cell main structure and adjacent to the corresponding N+ implantation structures, wherein the dielectric layer ILD 190 covers portions of the gate trench structure 130 and the two N+ implantation structures 170.

[0093] Exemplarily, if the trench SiC MOSFET device is a P-channel MOSFET type (not shown in the drawings), the two P+ injection structures are respectively adjacent to the two sides of the gate trench structure, and the two N+ injection structures are respectively located on both sides of the cell main structure and adjacent to the corresponding P+ injection structures, wherein the dielectric layer ILD covers the gate trench structure and parts of the two P+ injection structures.

[0094] The present disclosure does not limit the specific values ​​of the doping concentration of the substrate epitaxial layer, the doping concentration of the P-Body structure 180, the doping concentration of the N+ injection structure 170, and the doping concentration of the P+ injection structure 160. Those skilled in the art can set them according to actual conditions and needs. For example, in one possible embodiment, the doping concentration of the substrate epitaxial layer is 2.0x10 14 cm -3 ~1.5x10 16 cm -3 The doping concentration of the P-Body structure 180 is 10 16 cm -3 ~10 18 cm -3 , the doping concentration of N+ implantation structure 170 is 10 19 cm -3 ~10 20 cm -3 , the doping concentration of the P+ implantation structure 160 is 10 20 cm -3 ~10 21 cm -3 .

[0095] The embodiment of the present disclosure does not limit the trench depth of the gate trench structure 130 . For example, in one possible implementation, the trench depth of the gate trench structure 130 is 1.0 to 1.5 μm, for example, 1.5 μm.

[0096] The embodiment of the present disclosure does not limit the shape and size of the conductive interconnection structure 150, nor does it limit the specific type of conductive material of the conductive interconnection structure 150. For example, in one possible embodiment, the conductive interconnection structure 150 can be a rectangular parallelepiped or a structure similar to a rectangular parallelepiped. The length, width, and height of the rectangular parallelepiped can be adaptively set. For example, the width of the conductive interconnection structure 150 (the width between the two Poly-Si layers) can be less than or equal to 1.5μm, and the height of the conductive interconnection structure 150 can be, for example, the trench depth of the gate trench structure 130. The length of the conductive interconnection structure 150 can be set as needed, wherein the conductive material can be metal. Preferably, in the embodiment of the present disclosure, the width of the conductive interconnection structure 150 is less than or equal to 1μm; more preferably, in the embodiment of the present disclosure, the width of the conductive interconnection structure 150 is 0.5μm.

[0097] The embodiments of the present disclosure do not limit the specific process for forming the cell structure of the trench SiC MOSFET device. Those skilled in the art may adopt a suitable process according to actual conditions and needs.

[0098] The disclosed embodiments do not limit the metal material of the ohmic metal structure (OMC) between the N+ implant structure 170 and the source metal structure 110, and those skilled in the art may configure it based on actual circumstances and needs. In one example, the disclosed embodiments can form a conductive channel (e.g., a rectangular or rectangular-like slot-shaped hole) at the center of the gate trench structure (starting from a corresponding position in the dielectric layer ILD), passing through the dielectric layer ILD and the gate polysilicon (poly-Si) oxide directly to the P+ region at the bottom of the trench. An ohmic contact is then formed at the bottom of the trench to connect to the P+ region. Finally, the conductive channel is filled with a conductive material (e.g., metal) and connected to the source metal structure 110 at the top. Before metal filling (filling the conductive channel with a conductive material and connecting it to the source metal structure 110 at the top), the poly-Si can be oxidized to prevent short circuits between the source and gate. This design ensures that the P+ region at the bottom of each cell trench is directly grounded to the source, thereby achieving maximum gate oxide protection.

[0099] The embodiment of the present disclosure can achieve low-resistance electrical connection between the upper metal layer (source metal structure 110) and the lower semiconductor region (P+ injection structure 160, N+ injection structure 170) through the ohmic metal structure, ensuring smooth transmission of current between different layers, improving the overall electrical performance of the device, and reducing power loss caused by contact resistance.

[0100] Of course, the cell structure of the trench SiC MOSFET device of the embodiment of the present disclosure may also include other structures, which are not limited to the embodiment of the present disclosure. Those skilled in the art may configure the structure according to actual conditions and needs, which is exemplarily introduced below.

[0101] The embodiments of the present disclosure do not limit the specific implementation of each step. Those skilled in the art can configure it according to actual conditions and needs. An exemplary introduction is given below.

[0102] See also Figure 7a 、 Figure 7b 、 Figure 7c 、 Figure 7d 、 Figure 7e 、 Figure 7f 、 Figure 7g 、 Figure 7h , Figure 7a 、 Figure 7b 、 Figure 7c 、 Figure 7d 、 Figure 7e 、 Figure 7f 、 Figure 7g 、 Figure 7h A schematic diagram illustrating a method for forming a cell structure of a trench SiC MOSFET device according to an embodiment of the present disclosure is shown.

[0103] For example, Figure 7a As shown, the embodiment of the present disclosure can grow an N-epilayer on an N+ substrate, wherein the epitaxial doping concentration can be 2.0x10 14 cm -3 ~1.5x10 16 cm -3 .

[0104] In a possible implementation, step S12 performs ion implantation on the epitaxial layer of the substrate to form a P+ implantation structure, an N+ implantation structure, and a P-Body structure, which may include:

[0105] Performing P-type ion implantation on the epitaxial layer of the substrate to form a P-body structure;

[0106] Performing N-type ion implantation on the epitaxial layer of the substrate to form an N+ implantation structure;

[0107] A photolithography mask is formed on both sides of the epitaxial layer of the substrate, and P-type ion implantation is performed to form a P+ implantation structure.

[0108] The P-Body structure is below the P+ injection structure and the N+ injection structure.

[0109] For example, Figure 7b As shown, the embodiment of the present disclosure can use P-type ion implantation to form a P-body structure (the doping concentration can be 10 16 cm -3 ~10 18 cm-3 ), use high dose N-type ion implantation to form N+ implantation structure, namely N+ source region (doping concentration can be 10 19 cm -3 ~10 20 cm -3 ). Use photolithography mask and ion implantation to form P+ implantation structure or P+ region on both sides of the cell (doping concentration can be 10 20 cm -3 ~10 21 cm -3 ).

[0110] In a possible implementation, step S13 of forming a gate trench and performing P+ ion implantation on the bottom of the gate trench may include:

[0111] Depositing a mask on the surface of the cell main structure, performing photolithography and RIE etching to obtain the gate trench;

[0112] P+ ion implantation is performed directly on the bottom of the gate trench while retaining the mask.

[0113] For example, Figure 7c As shown, a mask material (such as SiO2) can be deposited on the wafer surface (surface of the main cell structure), and the mask and SiC gate trench can be etched by photolithography and RIE. The trench depth can be 1.0 to 1.5um, and then P+ ion implantation can be performed directly at the bottom of the trench while retaining the mask. The self-aligned implantation method used in the disclosed embodiment eliminates one photolithography step and ensures that P-type ions will not be mistakenly implanted on the sidewalls of the trench. The disclosed embodiment does not limit the doping concentration of the bottom P+ implantation structure, and those skilled in the art can set it according to actual conditions and needs.

[0114] For example, Figure 7d As shown, the embodiment of the present disclosure can remove the photoresist and surface mask material, perform a gate pre-oxidation cleaning process, and deposit a gate oxide layer (which can be SiO2 or a high-k dielectric layer such as Al2O3) at the bottom of the gate trench. Then, the embodiment of the present disclosure can deposit and dope a polysilicon gate electrode, etch back the polysilicon to the SiC surface, deposit a dielectric layer ILD, and use photolithography and RIE etching to define the ILD boundary, as shown in FIG. Figure 7dAs shown, for an N-channel MOSFET, the dielectric layer ILD covers the gate trench structure, and the left and right sides of the dielectric layer ILD are respectively in the N+ injection structure adjacent to the gate trench structure. The embodiments disclosed herein do not limit the specific method of depositing the dielectric layer ILD. Those skilled in the art can adopt appropriate means to achieve it according to actual conditions and needs. For example, chemical vapor deposition (CVD) technology, such as plasma enhanced chemical vapor deposition (PECVD), can be used. This method forms a uniform and dense insulating dielectric layer on the surface of the gate trench through gas chemical reaction, ensuring good coverage of the trench. Photoresist is coated on the surface of the dielectric layer, and a precise photoresist mask is formed through steps such as exposure and development to define the dielectric layer ILD area that needs to be retained. Reactive ion etching (RIE) technology is used to etch the dielectric layer not protected by the photoresist mask through active ions in the plasma, removing the excess part, thereby accurately defining the boundary of the dielectric layer ILD. In the embodiments disclosed herein, the dielectric layer ILD acts as an insulating layer to isolate the gate from other conductive structures (such as the source and drain), prevent current leakage, and ensure normal operation of the device. By precisely defining the position of the dielectric layer ILD through photolithography and etching, the dielectric layer can be prevented from covering non-target areas, ensuring the accuracy of subsequent processes and improving the consistency and reliability of the device structure.

[0115] In one possible implementation, steps S15 and S16 may include etching the gate trench structure to obtain a channel with a depth reaching the surface of the P+ injection structure, forming an ohmic metal on the surfaces of the N+ structure and the P+ structure, and the surface of the P+ injection structure, and filling the channel with a conductive material to obtain the conductive connection structure. The steps may include:

[0116] Etching the channel using photolithography and RIE etching techniques;

[0117] After removing the photoresist and cleaning, performing a low-temperature thermal oxidation operation on the gate trench to form a bottom oxide layer on the surface of the polysilicon;

[0118] Removing the oxide layer on the source metal structure and the oxide layer at the bottom of the gate trench by using RIE technology, depositing ohmic metal on the surface of the N+ structure and the P+ structure, and the surface of the P+ implantation structure, and performing an ohmic annealing process;

[0119] The channel is filled with a metal hole filling process, and the filled conductive material is directly connected to the source metal structure.

[0120] For example, Figure 7e As shown, the embodiment of the present disclosure can use photolithography ( Figure 7eA small hole (the channel) is opened in the center of the gate trench by coating photoresist PR in the middle and RIE etching is performed, passing through the photoresist PR, dielectric layer ILD, and polysilicon Poly-Si. The hole depth reaches the bottom of the polycrystalline gate, and the gate oxide layer at the bottom of the trench is etched away to reach the surface of the bottom P+ implanted structure. After removing the photoresist, cleaning is performed, and then low-temperature thermal oxidation (for example, 900°C) is performed to form a SiO2 insulating layer on the surface of the polysilicon in the trench.

[0121] For example, Figure 7f As shown, RIE can be used to remove the oxide layer on the source metal structure and the oxide layer at the bottom of the gate trench, and ohmic metal can be deposited and an ohmic annealing process can be performed, so that ohmic contacts are formed on the source P+ and N+ surfaces and the P+ surface at the bottom of the trench (ohmic metal OMC is deposited on the surfaces of the N+ structure and the P+ structure, and on the surface of the P+ injection structure).

[0122] For example, Figure 7g As shown, a metal filling process (or other processes) can be used to fill the central hole of the gate trench structure, and a thick source metal layer is deposited on the surface to form a source metal structure. The metal filled in the hole is directly connected to the source metal layer.

[0123] For example, Figure 7h As shown, the embodiment of the present disclosure can use relevant processes to protect the front side of the wafer, thin the back side of the wafer and deposit ohmic metal, perform laser ohmic annealing, and finally deposit back gold on the back side to form a drain metal structure.

[0124] In the disclosed embodiments, the final device structure increases the cell size only by the width of the central gate aperture (which can be as small as 0.5 μm). The P+ region at the bottom of the trench, which protects the gate oxide, is directly shorted to the source metal for optimal grounding. The entire process follows a standard trench SiC MOSFET flow, without high-energy (>1 MeV) ion implantation or etching deep SiC trenches (>1.5 μm).

[0125] According to another aspect of the present disclosure, a cell structure of a trench SiC MOSFET device is proposed, such as Figure 6b As shown, the cellular structure includes:

[0126] The cell main body structure 100 includes a substrate (N+substrate) and a substrate epitaxial layer (N-epilayer);

[0127] A source metal structure 110 is provided in the top region of the cell main structure 100;

[0128] The drain metal structure 120 is provided at the bottom area of ​​the cell main structure 100;

[0129] A gate trench structure 130 is provided in the cell main structure 100 , and the gate trench structure 130 is filled with polysilicon (Poly-Si);

[0130] A bottom P+ implantation structure 140 is provided at the bottom of the gate trench structure 130 ;

[0131] A conductive connection structure 150 passes through the gate trench structure 130 to achieve electrical connection between the source metal structure 110 and the bottom P+ implantation structure 140; and

[0132] A P+ implant structure 160 , an N+ implant structure 170 , a P-Body structure 180 disposed on both sides of the gate trench structure 130 , and an ohmic metal structure (OMC) between the P+ implant structure 160 , the N+ implant structure 170 and the source metal structure 110 ;

[0133] A dielectric layer ILD 190 covers the gate trench structure, and a boundary of the dielectric layer ILD 190 exceeds a boundary of the gate trench structure. The boundaries of the dielectric layer ILD 190 are adjacent to boundaries of the two ohmic metal structures.

[0134] The embodiment of the present disclosure connects the bottom P+ injection structure at the bottom of the gate trench structure to the source metal structure through a conductive connection structure, which can significantly reduce the gate oxide electric field strength at the bottom of the trench and the corners, and by providing a dielectric layer ILD between the gate trench structure and the source metal structure, the two can be isolated to ensure the stability of the internal electrical performance of the device. The above method can extend the life of the SiC MOSFET device to ensure long-term reliability. In addition, the embodiment of the present disclosure forms a conductive connection structure by opening a hole in the gate trench structure, without significantly increasing the cell size, and therefore has little effect on the conduction characteristics. In terms of process, no mega-electron-volt high-energy or high-dose ion implantation is required, no silicon carbide deep trench etching is required, and the number of conduction channels is not sacrificed.

[0135] See also Figure 8 , Figure 8 Another schematic diagram of a trench SiC MOSFET structure according to an embodiment of the present disclosure is shown.

[0136] In one possible implementation, Figure 8 As shown, a current spreading layer (CSL) may be provided under the P-Body structure.

[0137] The embodiments of the present disclosure do not limit the specific method for forming the current diffusion layer CSL, and those skilled in the art may configure the method according to actual conditions and needs. For example, the current diffusion layer CSL may be a highly doped N-type conductive layer.

[0138] The disclosed embodiments, by providing a current diffusion layer (CSL) beneath the P-Body structure, can reduce resistance, allow current to spread more evenly within the device, reduce energy loss during internal device transmission, improve current conduction efficiency, reduce hotspot issues caused by excessive local current density, and enhance device operational stability and reliability. Furthermore, the current diffusion layer of the disclosed embodiments connects adjacent gate trench structures, increasing the device's forward current conduction capability. The higher the doping concentration and the deeper the injection region, the more pronounced the current diffusion effect during conduction, effectively enhancing the device's current-carrying capacity.

[0139] Furthermore, in a possible implementation, as Figure 8 As shown, an N-pillar structure is provided below the current diffusion layer, and a P-pillar structure is provided below the bottom P+ injection structure, wherein the depths of the N-pillar structure and the P-pillar structure are less than or equal to the depth between the current diffusion layer and the substrate.

[0140] For example, the N-pillar and P-pillar structures are typically highly doped regions that further reduce the resistance of the current conduction path. They work in conjunction with the current diffusion layer (CSL) to optimize current distribution, ensuring even current diffusion over a wider area, reducing the problem of excessive local current density, and improving the device's high-current carrying capacity. For example, the N-pillar can influence the storage and release of carriers, improving the device's switching speed and switching losses. Furthermore, during long-term operation, by uniformly distributing current and heat, it enhances the device's thermal stability and reliability, reducing performance degradation caused by heat accumulation or current concentration.

[0141] The presently disclosed embodiments do not limit the depth of the N-pillar and P-pillar structures. Those skilled in the art can adjust the depth based on practical needs. The maximum depth can be the depth between the current diffusion layer and the substrate. Increasing the depth of the N-pillar and P-pillar structures in the presently disclosed embodiments improves the current-carrying capacity of the cell structure of the trench SiC MOSFET device.

[0142] In one possible implementation, Figure 8As shown, a dielectric layer (ILD) is provided between the gate trench structure and the source metal structure. In the disclosed embodiment, the dielectric layer ILD is provided between the gate trench structure and the source metal structure to provide insulation, isolating different conductive layers and ensuring the stability of the device's internal electrical performance.

[0143] The above describes various possible implementation methods of the cell of the trench SiC MOSFET. It should be understood that the introduction of each structure above should not be regarded as an exhaustive list of the cell structure of the trench SiC MOSFET. In other embodiments, the cell structure of the trench SiC MOSFET can also be changed according to actual conditions and needs. The embodiment of the present disclosure is applicable to the cell structure of various types of trench SiC MOSFET. A conductive connection structure is set in the gate trench structure in the form of an opening, and the P+ region set under the gate trench structure is electrically connected to the source metal structure to achieve gate oxide protection at the bottom of the trench SiC MOSFET and improve the reliability of the gate oxide at the bottom of the trench. There is no need to lose the number of channels, basically no increase in the cell size, no need for mega-electron-volt high-energy injection, and no need for deep trench etching. Each cell in the embodiment of the present disclosure can be directly grounded individually to ensure the dynamic characteristics of the device under high-frequency conditions.

[0144] According to one aspect of the present disclosure, a trench SiC MOSFET device is provided, comprising the cell structure of the trench SiC MOSFET device.

[0145] According to one aspect of the present disclosure, an electronic device is provided, comprising the SiCMOSFET device.

[0146] While various embodiments of the present disclosure have been described above, the above descriptions are illustrative, non-exhaustive, and not intended to be limiting of the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, their practical applications, or improvements to existing technologies, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A method for forming a cell structure of a trench SiC MOSFET device, characterized in that: The method comprises: Growing a substrate epitaxial layer on the substrate to form a cellular main structure; Performing ion implantation on the epitaxial layer of the substrate to form a P+ implantation structure, an N+ implantation structure, and a P-Body structure; forming a gate trench, performing P+ ion implantation on the bottom of the gate trench to form a bottom P+ implantation structure at the bottom of the gate trench structure, and depositing gate polysilicon after forming a gate oxide layer in the gate trench to form a gate trench structure; forming a dielectric layer ILD on the cell main structure, wherein the dielectric layer ILD covers the gate trench structure, and a boundary of the dielectric layer ILD exceeds a boundary of the gate trench structure; Etching the gate trench structure to obtain a channel with a depth reaching the surface of the P+ implantation structure, wherein the channel passes through the dielectric layer ILD, the gate polysilicon, and the gate oxide layer; forming ohmic metal on the surfaces of the N+ structure and the P+ structure, and on the surface of the P+ injection structure, and filling the channel with a conductive material to obtain the conductive connection structure; Depositing a surface metal layer on the top area of ​​the cell main structure to form a source metal structure, wherein the source metal structure is electrically connected to the bottom P+ injection structure; A back metal layer is deposited on the bottom area of ​​the cell main structure to form a drain metal structure.

2. The method according to claim 1, characterized in that Ion implantation is performed on the epitaxial layer of the substrate to form a P+ implantation structure, an N+ implantation structure, and a P-Body structure, including: Performing P-type ion implantation on the epitaxial layer of the substrate to form a P-body structure; Performing N-type ion implantation on the epitaxial layer of the substrate to form an N+ implantation structure; A photolithography mask is formed on both sides of the epitaxial layer of the substrate, and P-type ion implantation is performed to form a P+ implantation structure. The P-Body structure is below the P+ injection structure and the N+ injection structure.

3. The method according to claim 2, characterized in that The doping concentration of the substrate epitaxial layer is 2.0x10 14 cm -3 ~1.5x10 16 cm -3 , The doping concentration of the P-Body structure is 10 16 cm -3 ~10 18 cm -3 , The doping concentration of the N+ implant structure is 10 19 cm -3 ~10 20 cm -3 , The doping concentration of the P+ implant structure is 10 20 cm -3 ~10 21 cm -3 , The trench depth of the gate trench structure is 1.0 to 1.5 μm. The width of the conductive connection structure is less than or equal to 1.5 μm.

4. The method according to claim 1, wherein The forming of the gate trench and performing P+ ion implantation on the bottom of the gate trench include: Depositing a mask on the surface of the cell main structure, performing photolithography and RIE etching to obtain the gate trench; P+ ion implantation is performed directly on the bottom of the gate trench while retaining the mask.

5. The method according to claim 1, wherein Etching the gate trench structure to obtain a channel with a depth reaching the surface of the P+ injection structure, forming ohmic metal on the surfaces of the N+ structure and the P+ structure, and the surface of the P+ injection structure, and filling the channel with a conductive material to obtain the conductive connection structure, including: Etching the channel using photolithography and RIE etching techniques; After removing the photoresist and cleaning, performing a low-temperature thermal oxidation operation on the gate trench to form a bottom oxide layer on the surface of the polysilicon; Removing the oxide layer on the source metal structure and the oxide layer at the bottom of the gate trench by using RIE technology, depositing ohmic metal on the surfaces of the N+ structure and the P+ structure not covered by the dielectric layer ILD and the surface of the P+ implantation structure, and performing an ohmic annealing process; The channel is filled with a metal filling process, and the filled conductive material is directly connected to the source metal structure.

6. The method according to claim 1, characterized in that If the trench SiC MOSFET device is an N-channel MOSFET type, two N+ implantation structures are respectively adjacent to both sides of the gate trench structure, and two P+ implantation structures are respectively located on both sides of the cell body structure and adjacent to the corresponding N+ implantation structures, wherein the dielectric layer ILD covers portions of the gate trench structure and the two N+ implantation structures; If the trench SiC MOSFET device is a P-channel MOSFET type, the two P+ injection structures are respectively adjacent to the two sides of the gate trench structure, and the two N+ injection structures are respectively located on both sides of the cell body structure and adjacent to the corresponding P+ injection structures, wherein the dielectric layer ILD covers the gate trench structure and parts of the two P+ injection structures.

7. A cell structure of a trench SiC MOSFET device, characterized in that: The cellular structure is obtained by the method according to any one of claims 1 to 6, wherein the cellular structure comprises: The main structure of the cell includes a substrate and a substrate epitaxial layer; A source metal structure is provided in the top region of the cell main structure; A drain metal structure is provided in the bottom region of the cell main structure; A gate trench structure is provided in the cell main body structure, wherein the gate trench structure is filled with polysilicon; A bottom P+ implantation structure is provided at the bottom of the gate trench structure; A conductive connection structure, penetrating the gate trench structure, to achieve electrical connection between the source metal structure and the bottom P+ implantation structure; and A P+ injection structure, an N+ injection structure, a P-Body structure, and an ohmic metal structure disposed on both sides of the gate trench structure, between the P+ injection structure, the N+ injection structure, and the source metal structure; A dielectric layer ILD covers the gate trench structure, and a boundary of the dielectric layer ILD exceeds a boundary of the gate trench structure. The boundaries of the dielectric layer ILD are respectively adjacent to boundaries of the two ohmic metal structures.

8. The cellular structure according to claim 7, characterized in that A current diffusion layer is provided below the P-Body structure. An N-pillar structure is provided below the current diffusion layer. A P-pillar structure is provided below the bottom P+ injection structure. The depth of the N-pillar structure and the P-pillar structure is less than or equal to the depth between the current diffusion layer and the substrate.

9. A trench SiC MOSFET device, characterized in that: The trench SiC MOSFET device comprises the cell structure of the trench SiC MOSFET device according to claim 7 or 8.

10. An electronic device, characterized in that: The electronic device includes the SiC MOSFET device according to claim 9.

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