Semiconductor device and preparation method thereof

Abstract

The invention discloses a semiconductor device and a preparation method thereof, and the semiconductor device comprises a substrate; a channel layer; a barrier layer; the first gate structure and the second gate structure are located on the side, away from the substrate, of the barrier layer at intervals; the first passivation layer comprises a first opening, the first opening is located between the first gate structure and the second gate structure, and the first opening exposes the barrier layer; the surface of one surface, far away from the substrate, of the barrier layer exposed by the first opening is doped with electronegative atoms, and the electronegativity of the electronegative atoms is greater than or equal to the electronegativity of oxygen atoms; the second passivation layer is located on the side, away from the substrate, of the first passivation layer and fills the first opening; the first electrode is positioned on one side, away from the first opening, of the first gate structure; the second electrode is located on the side, away from the first opening, of the second gate structure. According to the invention, the leakage current of the gate structure is low, and the concentration and mobility of the two-dimensional electron gas of the device are improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for preparing the same. Background Art

[0002] For existing gallium nitride (GaN) high electron mobility transistors (HEMTs), the surface of the barrier layer and the surface of the gate structure are covered with the same passivation layer. That is, the side of the drift region of the GaN HEMT device away from the substrate and the surface of the gate structure are covered with the same passivation layer. The configuration of the same passivation layer cannot simultaneously meet the requirements of high concentration and high mobility of the two-dimensional electron gas and effective protection of the gate structure. Summary of the Invention

[0003] The present invention provides a semiconductor device and a method for preparing the same, so as to solve the problem that the current passivation layer cannot simultaneously meet the requirements of high concentration and high mobility of two-dimensional electron gas and effective protection of gate structure.

[0004] In a first aspect, the present invention provides a semiconductor device, wherein the semiconductor device comprises:

[0005] substrate;

[0006] A channel layer, wherein the channel layer is located on one side of the substrate;

[0007] a barrier layer, the barrier layer being located on a side of the channel layer away from the substrate;

[0008] a first gate structure and a second gate structure, wherein the first gate structure and the second gate structure are spaced apart and located on a side of the barrier layer away from the substrate;

[0009] a first passivation layer, located on a side of the first gate structure, the second gate structure, and the barrier layer away from the substrate; the first passivation layer includes a first sub-passivation layer and a second sub-passivation layer, the first passivation layer includes a first opening, the first opening is located between the first gate structure and the second gate structure, and the first opening exposes the barrier layer; a surface of the barrier layer exposed by the first opening away from the substrate is doped with electronegative atoms, and the electronegativity of the electronegative atoms is greater than or equal to the electronegativity of oxygen atoms;

[0010] a second passivation layer, located on a side of the first passivation layer away from the substrate and filling the first opening, the second passivation layer comprising a third sub-passivation layer and a fourth sub-passivation layer;

[0011] a first electrode located on a side of the first gate structure away from the first opening;

[0012] The second electrode is located on a side of the second gate structure away from the first opening.

[0013] Optionally, the first passivation layer further includes a second opening and a third opening; the second opening is located on a side of the first gate structure away from the first opening, and the third opening is located on a side of the second gate structure away from the first opening; the second opening and the third opening expose the barrier layer, and a surface of the barrier layer exposed by the second opening and the third opening, away from the substrate, is doped with electronegative atoms, and the electronegativity of the electronegative atoms is greater than or equal to the electronegativity of oxygen atoms;

[0014] The second passivation layer fills the second opening and the third opening.

[0015] Optionally, the first sub-passivation layer is located on the side of the first gate structure, the second gate structure and the barrier layer away from the substrate; the second sub-passivation layer is located on the side of the first sub-passivation layer away from the substrate; the third sub-passivation layer is located on the side of the first passivation layer away from the substrate, and the third sub-passivation layer fills the first opening; the fourth sub-passivation layer is located on the side of the third sub-passivation layer away from the substrate; the thickness of the third sub-passivation layer is less than the thickness of the first sub-passivation layer.

[0016] Optionally, the thickness of the first sub-passivation layer is 5 nm-100 nm, and the thickness of the third sub-passivation layer is 0.5 nm-5 nm.

[0017] Optionally, the first sub-passivation layer includes a first aluminum nitride layer, and the third sub-passivation layer includes a second aluminum nitride layer.

[0018] Optionally, the material of the second sub-passivation layer and the fourth sub-passivation layer includes at least one of silicon nitride, silicon oxide and silicon oxynitride.

[0019] Optionally, the electronegative atom includes at least one of an oxygen atom and a fluorine atom.

[0020] Optionally, a cross-sectional shape of the first opening is a symmetrical shape along a center line of the semiconductor device, a distance between a vertical projection of the first gate structure on the substrate and a vertical projection of the first opening on the substrate is equal to a distance between a vertical projection of the second gate structure on the substrate and a vertical projection of the first opening on the substrate; and the first gate structure and the second gate structure are identical gate structures.

[0021] The distance between the vertical projection of the first electrode on the substrate and the vertical projection of the first gate structure on the substrate is the same as the distance between the vertical projection of the second electrode on the substrate and the vertical projection of the second gate structure on the substrate; both the first electrode and the second electrode are in contact with the barrier layer.

[0022] Optionally, the opening size of the second opening is the same as the opening size of the third opening; the distance between the vertical projection of the second opening on the substrate and the vertical projection of the first electrode on the substrate is equal to the distance between the vertical projection of the third opening on the substrate and the vertical projection of the second electrode on the substrate; the distance between the vertical projection of the second opening on the substrate and the vertical projection of the first gate structure on the substrate is equal to the distance between the vertical projection of the third opening on the substrate and the vertical projection of the second gate structure on the substrate.

[0023] In a second aspect, the present invention provides a method for manufacturing a semiconductor device, wherein the manufacturing method comprises:

[0024] providing a substrate;

[0025] forming a channel layer on one side of the substrate;

[0026] forming a barrier layer on a side of the channel layer away from the substrate;

[0027] forming a first gate structure and a second gate structure on a side of the barrier layer away from the substrate;

[0028] forming a first passivation layer on the first gate structure, the second gate structure, and the barrier layer on a side away from the substrate, wherein the first passivation layer includes a first sub-passivation layer and a second sub-passivation layer;

[0029] Etching the first sub-passivation layer and the second sub-passivation layer between the first gate structure and the second gate structure to form a first opening, wherein the first opening exposes the barrier layer;

[0030] doping electronegative atoms on a surface of the barrier layer exposed by the first opening away from the substrate through a plasma surface treatment process, wherein the electronegativity of the electronegative atoms is greater than or equal to that of oxygen atoms;

[0031] forming a second passivation layer on a side of the first passivation layer away from the substrate and in the first opening, wherein the second passivation layer includes a third sub-passivation layer and a fourth sub-passivation layer;

[0032] forming a first electrode on a side of the first gate structure away from the first opening;

[0033] A second electrode is formed on a side of the second gate structure away from the first opening.

[0034] Optionally, after etching the first sub-passivation layer and the second sub-passivation layer between the first gate structure and the second gate structure to form the first opening, the method further includes:

[0035] Etching the first sub-passivation layer and the second sub-passivation layer on a side of the first gate structure away from the first opening to form a second opening, wherein the second opening exposes the barrier layer;

[0036] Etching the first sub-passivation layer and the second sub-passivation layer on a side of the second gate structure away from the first opening to form a third opening, wherein the third opening exposes the barrier layer;

[0037] After doping electronegative atoms on the surface of the barrier layer exposed by the first opening and away from the substrate by a plasma surface treatment process, the method further includes:

[0038] doping electronegative atoms on a surface of the barrier layer exposed at the second opening, away from the substrate, through a plasma surface treatment process, wherein the electronegativity of the electronegative atoms is greater than or equal to that of oxygen atoms;

[0039] doping electronegative atoms on the surface of the barrier layer exposed by the third opening and away from the substrate through a plasma surface treatment process, wherein the electronegativity of the electronegative atoms is greater than or equal to that of oxygen atoms;

[0040] forming a second passivation layer on a side of the first passivation layer away from the substrate and in the first opening, comprising:

[0041] A second passivation layer is formed on a side of the first passivation layer away from the substrate and in the first opening, the second opening, and the third opening.

[0042] Optionally, the plasma surface treatment process includes placing the surfaces of the barrier layer exposed by the first opening, the second opening, and the third opening, which are away from the substrate, in an oxygen and / or fluorine plasma atmosphere.

[0043] Optionally, forming a first passivation layer on a side of the first gate structure, the second gate structure, and the barrier layer away from the substrate includes:

[0044] forming a first sub-passivation layer on the entire surface of the first gate structure, the second gate structure, and the barrier layer on a side away from the substrate;

[0045] forming a second sub-passivation layer on a side of the first sub-passivation layer away from the substrate;

[0046] forming a second passivation layer on a side of the first passivation layer away from the substrate and in the first opening, comprising:

[0047] forming a third sub-passivation layer on a side of the first passivation layer away from the substrate and in the first opening;

[0048] A fourth sub-passivation layer is formed on a side of the third sub-passivation layer away from the substrate.

[0049] Optionally, forming a first electrode on a side of the first gate structure away from the first opening includes:

[0050] Etching the second passivation layer on a side of the first gate structure away from the first opening to form a sixth opening;

[0051] etching the first passivation layer in a region corresponding to the sixth opening to form a fourth opening; wherein a vertical projection of the fourth opening on the substrate coincides with a vertical projection of the sixth opening on the substrate;

[0052] forming a first electrode in the fourth opening and the sixth opening;

[0053] forming a second electrode on a side of the second gate structure away from the first opening, comprising:

[0054] Etching the second passivation layer on a side of the second gate structure away from the first opening to form a seventh opening;

[0055] etching the first passivation layer in a region corresponding to the seventh opening to form a fifth opening; wherein a vertical projection of the fifth opening on the substrate coincides with a vertical projection of the seventh opening on the substrate;

[0056] A second electrode is formed in the fifth opening and the seventh opening.

[0057] According to the technical solution of the embodiment of the present invention, the first passivation layer can be located on the side of the first gate structure and the second gate structure away from the substrate, the thickness of the first sub-passivation layer can be relatively thick, and the electric field shielding ability is better, so that the first passivation layer composed of the first sub-passivation layer and the second sub-passivation layer has a better passivation protection effect on the first gate structure and the second gate structure, thereby reducing the leakage of the first gate structure and the second gate structure; in addition, the first sub-passivation layer and the second sub-passivation layer cover the entire first gate structure and the entire second gate structure, thereby avoiding the damage of plasma such as oxygen or fluorine to the first gate structure and the second gate structure region when doping electronegative atoms on the surface of the barrier layer at the first opening away from the substrate. The first passivation layer may include a first opening. When electronegative atoms are doped on the surface of the barrier layer exposed by the first opening, which is away from the substrate, the electronegativity of the doped electronegative atoms is greater than or equal to that of oxygen atoms, i.e., the doped electronegative atoms have strong oxidizing properties. During doping of the barrier layer with the electronegative atoms, the surface is oxidized and the interface is improved. This improves the surface state of the barrier layer in the drift region, increases the concentration of the two-dimensional electron gas in the drift region, and thereby enhances the performance of the power device. A second passivation layer is located on the side of the first passivation layer away from the substrate and fills the first opening. The second passivation layer, which is in direct contact with the barrier layer within the first opening, effectively stress-enhances the drift region of the GaN HEMT device, thereby increasing the concentration and mobility of the two-dimensional electron gas, reducing the on-resistance of the GaN HEMT device, and improving the dynamic performance of the GaN HEMT device. The technical solution of the embodiment of the present invention can realize separate modulation of the first gate structure, the second gate structure and the device drift region through the first passivation layer and the second passivation layer, while achieving lower leakage current of the first gate structure and the second gate structure, while improving the concentration and mobility of the two-dimensional electron gas of the device, thereby effectively improving the performance of the device.

[0058] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0060] Figure 1 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention;

[0061] Figure 2 is a flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0062] Figure 3-Figure 9 It is a structural schematic diagram corresponding to some steps in the method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0063] Figure 10 is a flow chart of another method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0064] Figure 11-12 It is a structural schematic diagram corresponding to some steps in another method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0065] Figure 13 is a flow chart of another method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0066] Figure 14 This is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0067] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0068] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0069] Figure 1 Schematic diagram of a semiconductor device according to an embodiment of the present invention. Figure 1 As shown, the semiconductor device includes: a substrate 1; a channel layer 2, the channel layer 2 being located on one side of the substrate 1; and a barrier layer 3, the barrier layer 3 being located on the side of the channel layer 2 away from the substrate 1. A first gate structure 4 and a second gate structure 5 are provided, the first gate structure 4 and the second gate structure 5 being spaced apart and located on the side of the barrier layer 3 away from the substrate 1. A first passivation layer 6 includes a first sub-passivation layer 61 and a second sub-passivation layer 62. The first sub-passivation layer 61 is located on the side of the first gate structure 4, the second gate structure 5, and the barrier layer 3 away from the substrate 1, and the second sub-passivation layer 62 is located on the side of the first sub-passivation layer 61 away from the substrate 1. The first passivation layer 6 includes a first opening 63, the first opening 63 being located between the first gate structure 4 and the second gate structure 5, and exposing the barrier layer 3. The surface of the barrier layer 3 exposed by the first opening 63, away from the substrate 1, is doped with electronegative atoms, the electronegativity of which is greater than or equal to that of oxygen atoms. The second passivation layer 7 includes a third sub-passivation layer 71 and a fourth sub-passivation layer 72. The third sub-passivation layer 71 is located on the side of the first passivation layer 6 away from the substrate 1 and fills the first opening 63. The fourth sub-passivation layer 72 is located on the side of the third sub-passivation layer 71 away from the substrate 1. The first electrode 81 is located on the side of the first gate structure 4 away from the first opening 63. The second electrode 82 is located on the side of the second gate structure 5 away from the first opening 63.

[0070] Specifically, substrate 1 can be a Si substrate, a sapphire substrate, or a GaN substrate. Channel layer 2 can be made of intrinsic GaN, and barrier layer 3 can be made of AlGaN. First gate structure 4 can be located on the side of barrier layer 3 away from substrate 1, and second gate structure 5 can also be located on the side of barrier layer 3 away from substrate 1. First gate structure 4 and second gate structure 5 are spaced apart, and can be completely symmetrical along the centerline of the GaN HEMT device, that is, they can be spaced symmetrically along the centerline of the GaN HEMT device. First gate structure 4 can include a first doped III-V semiconductor layer 41 and a first gate 42. First doped III-V semiconductor layer 41 can be located on the side of barrier layer 3 away from substrate 1, and first gate 42 can be located on the side of first doped III-V semiconductor layer 41 away from substrate 1. The second gate structure 5 may include a second doped Group III-V semiconductor layer 51 and a second gate 52. The second doped Group III-V semiconductor layer 51 may be located on a side of the barrier layer 3 away from the substrate 1, and the second gate 52 may be located on a side of the second doped Group III-V semiconductor layer 51 away from the substrate 1. The first doped Group III-V semiconductor layer 41 and the second doped Group III-V semiconductor layer 51 may each include a P-GaN layer, and the first gate 42 and the second gate 52 may each include a titanium nitride metal layer.

[0071] The first passivation layer 6 may include a first sub-passivation layer 61 and a second sub-passivation layer 62. The first sub-passivation layer 61 may be located on the side of the first gate structure 4 and the second gate structure 5 away from the substrate 1. The first sub-passivation layer 61 may also be located on the side of a portion of the barrier layer 3 away from the substrate 1. The second sub-passivation layer 62 may be located on the side of the first sub-passivation layer 61 away from the substrate 1. The first passivation layer 6 may completely surround the first gate structure 4 and the second gate structure 5. The first passivation layer 6 is primarily used to passivate and protect the first gate structure 4 and the second gate structure 5. The first sub-passivation layer 61 can be relatively thick, providing better electric field shielding capabilities. This allows the first passivation layer 6, composed of the first sub-passivation layer 61 and the second sub-passivation layer 62, to provide better passivation protection for the first gate structure 4 and the second gate structure 5, thereby reducing leakage current in the first gate structure 4 and the second gate structure 5. Furthermore, the first sub-passivation layer 61 and the second sub-passivation layer 62 cover the entire first gate structure 4 and the entire second gate structure 5. This prevents plasma, such as oxygen or fluorine, from damaging the first gate structure 4 and the second gate structure 5 when electronegative atoms are doped onto the surface of the barrier layer 3 at the first opening 63 away from the substrate 1. The size of the first opening 63 can be adjusted based on actual conditions. A certain distance can be set between the edge of the first opening 63 near the first gate structure 4 and the first gate structure 4, and a certain distance can also be set between the edge of the first opening 63 near the second gate structure 5 and the second gate structure 5. This ensures that the first passivation layer 6 between the edge of the first opening 63 near the first gate structure 4 and the first gate structure 4 completely surrounds the first gate structure 4, effectively passivating and protecting the first gate structure 4. And ensure that the first passivation layer 6 between the edge of the first opening 63 close to the second gate structure 5 and the second gate structure 5 can completely surround the second gate structure 5, thereby effectively passivating and protecting the second gate structure 5.

[0072] Experiments have shown that when electronegative atoms are doped on the surface of the barrier layer 3 exposed by the first opening 63, which is away from the substrate 1, the electronegativity of the doped electronegative atoms is greater than or equal to that of oxygen atoms, i.e., the doped electronegative atoms have strong oxidizing properties. During this process, the surface of the barrier layer 3 is oxidized and the interface is improved. This improves the surface state of the barrier layer 3 in the drift region, increases the concentration of the two-dimensional electron gas in the drift region, and thus enhances the performance of the power device. The larger the opening size of the first opening 63, the greater the effect of increasing the concentration and mobility of the two-dimensional electron gas in the drift region.

[0073] The second passivation layer 7 may include a third sub-passivation layer 71 and a fourth sub-passivation layer 72. The third sub-passivation layer 71 may be located on the side of the second sub-passivation layer 62 away from the substrate 1 and may fill the first opening 63. The third sub-passivation layer 71 may cover the barrier layer 3 exposed by the first opening 63. The fourth sub-passivation layer 72 may be located on the side of the third sub-passivation layer 71 away from the substrate 1. The thickness of the third sub-passivation layer 71 may be less than that of the first sub-passivation layer 61. The second passivation layer 7, which is in direct contact with the barrier layer 3 within the first opening 63, can effectively stress-enhance the drift region of the GaN HEMT device, thereby increasing the concentration and mobility of the two-dimensional electron gas (2DEG) of the GaN HEMT device, reducing the on-resistance of the GaN HEMT device, and improving the dynamic performance of the GaN HEMT device. The larger the opening size of the first opening 63, the larger the contact area between the second passivation layer 7 and the barrier layer 3, which can further improve the concentration and mobility of the two-dimensional electron gas of the GaN HEMT device.

[0074] The GaN HEMT device provided in the embodiment of the present invention may have a completely symmetrical structure. The first electrode 81 may serve as a source or a drain, and the second electrode 82 may serve as a drain or a source.

[0075] According to the technical solution of the embodiment of the present invention, the first passivation layer 6 can be located on the side of the first gate structure 4 and the second gate structure 5 away from the substrate 1, and the thickness of the first sub-passivation layer 61 can be relatively thick, with better electric field shielding ability, so that the first passivation layer 6 composed of the first sub-passivation layer 61 and the second sub-passivation layer 62 has a better passivation protection effect on the first gate structure 4 and the second gate structure 5, thereby reducing the leakage of the first gate structure 4 and the second gate structure 5; in addition, the first sub-passivation layer 61 and the second sub-passivation layer 62 cover the entire first gate structure 4 and the entire second gate structure 5, thereby avoiding the damage of plasma such as oxygen or fluorine to the first gate structure 4 and the second gate structure 5 when doping electronegative atoms on the surface of the barrier layer 3 at the first opening 63 away from the substrate 1. The first passivation layer 6 may include a first opening 63. When electronegative atoms are doped on the surface of the barrier layer 3 exposed by the first opening 63 and facing away from the substrate 1, the electronegativity of the doped electronegative atoms is greater than or equal to that of oxygen atoms, i.e., the doped electronegative atoms have strong oxidizing properties. During the doping process, the surface of the barrier layer 3 is oxidized and the interface is improved. This improves the surface state of the barrier layer 3 in the drift region, increases the concentration of the two-dimensional electron gas in the drift region, and thereby enhances the performance of the power device. A second passivation layer 7 is located on the side of the first passivation layer 6 facing away from the substrate 1 and fills the first opening 63. The second passivation layer 6 in direct contact with the barrier layer 3 within the first opening 63 effectively stress-enhances the drift region of the GaN HEMT device, thereby increasing the concentration and mobility of the two-dimensional electron gas, reducing the on-resistance of the GaN HEMT device, and improving the dynamic performance of the GaN HEMT device. The technical solution of the embodiment of the present invention can achieve separate modulation of the first gate structure 4, the second gate structure 5 and the device drift region through the first passivation layer 6 and the second passivation layer 7, while achieving lower leakage current of the first gate structure 4 and the second gate structure 5, while improving the concentration and mobility of the two-dimensional electron gas of the device, thereby effectively improving the performance of the device.

[0076] Optionally, based on the above embodiments, continue to refer to Figure 1 The first passivation layer 6 further includes a second opening 64 and a third opening 65. The second opening 64 is located on the side of the first gate structure 4 away from the first opening 63, and the third opening 65 is located on the side of the second gate structure 5 away from the first opening 63. The second opening 64 and the third opening 65 expose the barrier layer 3. The surface of the barrier layer 3 exposed by the second opening 64 and the third opening 65, which is away from the substrate 1, is doped with electronegative atoms, the electronegativity of which is greater than or equal to that of oxygen atoms. The second passivation layer 7 fills the second opening 64 and the third opening 65.

[0077] Specifically, a certain distance can be set between the edge of the second opening 64 near the first gate structure 4 and the first gate structure 4 to ensure that the first passivation layer 6 between the edge of the second opening 64 near the first gate structure 4 and the first gate structure 4 can completely surround the first gate structure 4, effectively passivating and protecting the first gate structure 4. The edge of the second opening 64 away from the first gate structure 4 can be located between the first gate structure 4 and the first electrode 81. The second opening 64 can further extend away from the edge of the first gate structure 4. The second opening 64 can extend to the region of the first electrode 81 or to the region of the first electrode 81 away from the first gate structure 4.

[0078] A certain distance can be set between the edge of the third opening 65 near the second gate structure 5 and the second gate structure 5 to ensure that the first passivation layer 6 between the edge of the third opening 65 near the second gate structure 5 and the second gate structure 5 can completely surround the second gate structure 5, effectively passivating and protecting the second gate structure 5. The edge of the third opening 65 away from the second gate structure 5 can be located between the second gate structure 5 and the second electrode 82. The third opening 65 can further extend away from the edge of the second gate structure 5, extending to the region of the second electrode 82, or further extending to the region of the second electrode 82 away from the second gate structure 5.

[0079] When electronegative atoms are doped on the surface of the barrier layer 3 exposed by the second opening 64 and the third opening 65, which is away from the substrate 1, the electronegativity of the doped electronegative atoms is greater than or equal to that of oxygen atoms, i.e., the doped electronegative atoms have strong oxidizing properties. During the doping process, the surface of the barrier layer 3 is oxidized and the interface is improved. This can improve the surface state of the barrier layer 3 in the drift region, increase the concentration of the two-dimensional electron gas in the drift region, and thus enhance the performance of the power device. The larger the opening size of the second opening 64 and the third opening 65, the greater the effect of increasing the concentration and mobility of the two-dimensional electron gas in the drift region.

[0080] The third sub-passivation layer 71 can be located on the side of the second sub-passivation layer 62 away from the substrate 1. The third sub-passivation layer 71 can fill the first opening 63, the second opening 64, and the third opening 65. The third sub-passivation layer 71 can cover the barrier layer 3 exposed by the first opening 63, the second opening 64, and the third opening 65. The fourth sub-passivation layer 72 can be located on the side of the third sub-passivation layer 71 away from the substrate 1. The thickness of the third sub-passivation layer 71 can be less than that of the first sub-passivation layer 61. The second passivation layer 7 in direct contact with the barrier layer 3 within the first opening 63, the second opening 64, and the third opening 65 can effectively stress-enhance the drift region of the GaN HEMT device, thereby increasing the concentration and mobility of the two-dimensional electron gas in the GaN HEMT device, reducing the on-resistance of the GaN HEMT device, and improving the dynamic performance of the GaN HEMT device. The larger the opening sizes of the first opening 63 , the second opening 64 and the third opening 65 , the larger the contact area between the second passivation layer 7 and the barrier layer 3 , and the concentration and mobility of the two-dimensional electron gas of the GaN HEMT device can be further improved.

[0081] Optionally, based on the above embodiments, continue to refer to Figure 1 , the thickness of the third sub-passivation layer 71 is less than the thickness of the first sub-passivation layer 61 .

[0082] Specifically, the thickness of the first sub-passivation layer 61 can be thicker and the electric field shielding ability is better, so that the first passivation layer 6 composed of the first sub-passivation layer 61 and the second sub-passivation layer 62 has a better passivation protection effect on the first gate structure 4 and the second gate structure 5, thereby reducing the leakage of the first gate structure 4 and the second gate structure 5; in addition, the first sub-passivation layer 61 and the second sub-passivation layer 62 cover the entire first gate structure 4 and the entire second gate structure 5, thereby avoiding the damage of plasma such as oxygen or fluorine to the first gate structure 4 and the second gate structure 5 when the surface of the barrier layer 3 at the first opening 63, the second opening 64 and the third opening 65 away from the substrate 1 is doped with electronegative atoms. The thickness of the third sub-passivation layer 71 can be less than the thickness of the first sub-passivation layer 61. The second passivation layer 7 in direct contact with the barrier layer 3 within the first opening 63, the second opening 64, and the third opening 65 can effectively stress-enhance the drift region of the GaN HEMT device, thereby increasing the concentration and mobility of the two-dimensional electron gas of the GaN HEMT device, reducing the on-resistance of the GaN HEMT device, and improving the dynamic performance of the GaN HEMT device.

[0083] In the embodiment of the present invention, the thickness and other parameters of the first sub-passivation layer 61 and the third sub-passivation layer 71 are set to be different, which is mainly achieved by adjusting the process temperature, gas ratio and pretreatment of forming the first sub-passivation layer 61 and the third sub-passivation layer 71.

[0084] Optionally, based on the above embodiments, continue to refer to Figure 1 , the first sub-passivation layer 61 includes a first aluminum nitride layer, and the second sub-passivation layer 71 includes a second aluminum nitride layer.

[0085] Specifically, the materials of the first sub-passivation layer 61 and the third sub-passivation layer 71 can both be aluminum nitride. In some embodiments of the present invention, the materials of the first passivation layer 61 and the second passivation layer 71 can also be aluminum oxide or the like.

[0086] Optionally, based on the above embodiments, continue to refer to Figure 1 The material of the second sub-passivation layer 62 and the fourth sub-passivation layer 72 can be set to at least one of silicon nitride, silicon oxide and silicon oxynitride.

[0087] Optionally, based on the above embodiments, continue to refer to Figure 1 , the electronegative atoms include at least one of oxygen atoms and fluorine atoms.

[0088] Specifically, after forming the first gate structure 4 and the second gate structure 5, the GaN HEMT device according to the embodiment of the present invention forms a first passivation layer 6 on the sides of the first and second gate structures 4 and 5 away from the substrate 1 and on the side of the barrier layer 3 away from the substrate 1. Then, photolithography and etching processes are used to selectively open the drift region of the GaN HEMT device, forming a first opening 63, a second opening 64, and a third opening 65. Oxygen and / or fluorine gas is then introduced into the surface of the barrier layer 3 in the drift region exposed by the first opening 63, the second opening 64, and the third opening 65. Interface enhancement treatment is then performed on the surface of the barrier layer 3 exposed by the first opening 63, the second opening 64, and the third opening 65. Specifically, electronegative atoms are doped on the surface of the barrier layer 3 away from the substrate 1, exposed by the first opening 63, the second opening 64, and the third opening 65. Due to the strong electronegativity of these electronegative atoms, the surface state of the barrier layer 3 is improved, the concentration and mobility of the two-dimensional electron gas in the drift region are increased, and thus the performance of the device is improved.

[0089] Optionally, based on the above embodiments, continue to refer to Figure 1The cross-sectional shape of the first opening 63 is symmetrical along the centerline of the semiconductor device. The distance between the vertical projection of the first gate structure 4 on the substrate 1 and the vertical projection of the first opening 63 on the substrate 1 is equal to the distance between the vertical projection of the second gate structure 5 on the substrate 1 and the vertical projection of the first opening 63 on the substrate 1. The first gate structure 4 and the second gate structure 5 are identical gate structures. The distance between the vertical projection of the first electrode 81 on the substrate 1 and the vertical projection of the first gate structure 4 on the substrate 1 is equal to the distance between the vertical projection of the second electrode 82 on the substrate 1 and the vertical projection of the second gate structure 5 on the substrate 1. Both the first electrode 81 and the second electrode 82 are in contact with the barrier layer.

[0090] Specifically, the cross-sectional shape of the first opening 63 is symmetrical along the centerline of the semiconductor device. The first gate structure 4 and the second gate structure 5 can be symmetrically spaced along the centerline of the GaN HEMT device. The first electrode 81 and the second electrode 82 can also be symmetrically disposed along the centerline of the GaN HEMT device. This allows the GaN HEMT device to have a completely symmetrical structure. The first electrode 81 can function as either a source or a drain, and the second electrode 82 can function as either a drain or a source.

[0091] Optionally, based on the above embodiments, continue to refer to Figure 1 The opening size of the second opening 64 is the same as the opening size of the third opening 65. The distance between the vertical projection of the second opening 64 on the substrate 1 and the vertical projection of the first electrode 81 on the substrate 1 is equal to the distance between the vertical projection of the third opening 65 on the substrate 1 and the vertical projection of the second electrode 82 on the substrate 1. The distance between the vertical projection of the second opening 64 on the substrate 1 and the vertical projection of the first gate structure 4 on the substrate 1 is equal to the distance between the vertical projection of the third opening 65 on the substrate 1 and the vertical projection of the second gate structure 5 on the substrate 1.

[0092] Specifically, when the first passivation layer 6 is provided with a second opening 64 and a third opening 65 in addition to the first opening 63, the cross-sectional shape of the first opening 63 is a symmetrical shape along the center line of the semiconductor device, the first gate structure 4 and the second gate structure 5 can be symmetrically spaced along the center line of the GaN HEMT device, the second opening 64 and the third opening 65 can also be symmetrically arranged along the center line of the GaN HEMT device, and the first electrode 81 and the second electrode 82 can also be symmetrically arranged along the center line of the GaN HEMT device. This allows the GaN HEMT device to have a completely symmetrical structure.

[0093] The first passivation layer 6 may further include a fourth opening 66 and a fifth opening 67, and the second passivation layer 7 may further include a sixth opening 73 and a seventh opening 74. The fourth opening 66 may be located on the side of the second opening 64 away from the first gate structure 4, and the vertical projection of the sixth opening 73 on the substrate 1 may overlap with the vertical projection of the fourth opening 66 on the substrate 1. The fifth opening 67 may be located on the side of the third opening 65 away from the second gate structure 5, and the vertical projection of the seventh opening 74 on the substrate 1 may overlap with the vertical projection of the fifth opening 67 on the substrate 1. The first electrode 81 is located within the fourth opening 66 and the sixth opening 73 and contacts the barrier layer 3. The second electrode 82 is located within the fifth opening 67 and the seventh opening 74 and contacts the barrier layer 3.

[0094] Optionally, based on the above embodiments, continue to refer to Figure 1 The thickness of the first sub-passivation layer 61 is 5 nm-100 nm, and the thickness of the third sub-passivation layer 71 is 0.5 nm-5 nm.

[0095] Specifically, the thickness of the third sub-passivation layer 71 can be less than that of the first sub-passivation layer 61. For example, the thickness of the first sub-passivation layer 61 can be 5 nm to 100 nm, and the thickness of the third sub-passivation layer 71 can be 0.5 nm to 5 nm. By forming the first sub-passivation layer 61 and the third sub-passivation layer 71 separately and having different thicknesses, the first passivation layer 6 can effectively passivate and protect the first gate structure 4 and the second gate structure 5. Furthermore, the second passivation layer 7 in direct contact with the barrier layer 3 within the first opening 63, the second opening 64, and the third opening 65 can effectively stress-enhance the drift region of the GaN HEMT device, thereby improving the concentration and mobility of the two-dimensional electron gas in the GaN HEMT device.

[0096] Optionally, based on the above embodiments, continue to refer to Figure 1The semiconductor device may further include a first gate field plate 91 and a second gate field plate 92. Both the first gate field plate 91 and the second gate field plate 92 may be located on a side of the fourth sub-passivation layer 72 away from the substrate 1. The centerline of the first gate field plate 91 may coincide with the centerline of the first gate structure 4. The vertical projection of the first gate field plate 91 on the substrate 1 may cover the vertical projection of the first gate structure 4 on the substrate 1. The vertical projection of the first gate field plate 91 on the substrate 1 may not overlap with the vertical projections of the first opening 63 and the second opening 64 on the substrate 1. The first gate field plate 91 may also extend in a direction from the first gate structure 4 toward the first opening 63, such that the vertical projection of the first gate field plate 91 on the substrate 1 at least partially overlaps with the vertical projection of the first opening 63 on the substrate 1. The first gate field plate 91 may also extend in a direction from the first gate structure 4 toward the second opening 64, such that the vertical projection of the first gate field plate 91 on the substrate 1 at least partially overlaps with the vertical projection of the second opening 64 on the substrate 1.

[0097] The centerline of the second gate field plate 92 may coincide with the centerline of the second gate structure 5, and the vertical projection of the second gate field plate 92 on the substrate 1 may cover the vertical projection of the second gate structure 5 on the substrate 1. The vertical projection of the second gate field plate 92 on the substrate 1 may not overlap with the vertical projections of the first opening 63 and the third opening 65 on the substrate 1. The second gate field plate 92 may also extend in the direction from the second gate structure 4 to the first opening 63, so that the vertical projection of the second gate field plate 92 on the substrate 1 may at least partially overlap with the vertical projection of the first opening 63 on the substrate 1. The second gate field plate 92 may also extend in the direction from the second gate structure 5 to the third opening 65, so that the vertical projection of the second gate field plate 92 on the substrate 1 may at least partially overlap with the vertical projection of the third opening 65 on the substrate 1.

[0098] The materials of the first gate field plate 91 and the second gate field plate 92 can both be metal materials. The first gate field plate 91 and the second gate field plate 92 can be used to control the electric field to avoid electric field concentration between the first gate structure 4 and the first electrode 81 or the second gate structure 5 and the second electrode 82, thereby improving the breakdown voltage of the device.

[0099] Figure 2 is a flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention. Figure 3-Figure 9 FIG. 1 is a schematic structural diagram corresponding to some steps in the method for manufacturing a semiconductor device provided by an embodiment of the present invention, such as Figure 2 As shown, the preparation method includes:

[0100] S100: providing a substrate.

[0101] Specifically, such as Figure 3As shown, a substrate 1 is first provided, and the substrate 1 can be a Si substrate, a sapphire substrate or a GaN substrate.

[0102] S110: forming a channel layer and a barrier layer in sequence on one side of the substrate.

[0103] Specifically, such as Figure 4 As shown, a channel layer 2 is first formed on one side of a substrate 1, and a barrier layer 3 is formed on the side of the channel layer 2 away from the substrate 1. The channel layer 2 can be made of intrinsic GaN, and the barrier layer 3 can be made of AlGaN material.

[0104] S120 : forming a first gate structure and a second gate structure on a side of the barrier layer away from the substrate.

[0105] Specifically, such as Figure 5 As shown, a first gate structure 4 and a second gate structure 5 are formed on a side of the barrier layer 3 away from the substrate 1. The first gate structure 4 and the second gate structure 5 can be completely symmetrical along the centerline of the GaN HEMT device, that is, the first gate structure 4 and the second gate structure 5 can be symmetrically spaced along the centerline of the GaN HEMT device. The first gate structure 4 can include a first doped III-V semiconductor layer 41 and a first gate 42. The first doped III-V semiconductor layer 41 can be located on the side of the barrier layer 3 away from the substrate 1, and the first gate 42 can be located on the side of the first doped III-V semiconductor layer 41 away from the substrate 1. The second gate structure 5 can include a second doped III-V semiconductor layer 51 and a second gate 52. The second doped III-V semiconductor layer 51 can be located on the side of the barrier layer 3 away from the substrate 1, and the second gate 52 can be located on the side of the second doped III-V semiconductor layer 51 away from the substrate 1. The first doped III-V semiconductor layer 41 and the second doped III-V semiconductor layer 51 may each include a P-GaN layer, and the first gate electrode 42 and the second gate electrode 52 may each include a titanium nitride metal layer.

[0106] For example, a doped III-V semiconductor layer can be formed on the entire surface of the barrier layer 3 away from the substrate 1, and a gate can be formed on the entire surface of the doped III-V semiconductor layer away from the substrate 1, and then a first gate structure 4 and a second gate structure 5 can be formed by processes such as photolithography and etching.

[0107] S130: forming a first passivation layer on the first gate structure, the second gate structure, and the barrier layer on a side away from the substrate, wherein the first passivation layer includes a first sub-passivation layer and a second sub-passivation layer.

[0108] Specifically, such as Figure 6As shown, a first passivation layer 6 is formed on the side of the first gate structure 4, the second gate structure 5 and the barrier layer 3 away from the substrate 1. The first passivation layer 6 can be formed on the entire side of the first gate structure 4, the second gate structure 5 and the barrier layer 3 away from the substrate 1.

[0109] S140 : etching the first sub-passivation layer and the second sub-passivation layer between the first gate structure and the second gate structure to form a first opening, wherein the first opening exposes the barrier layer.

[0110] Specifically, such as Figure 7 As shown, a mask is used to selectively open the drift region of the GaN HEMT device through processes such as photolithography and etching, thereby forming a first opening 63. A certain distance can be set between the edge of the first gate structure 4 and the first gate structure 4, and a certain distance can also be set between the edge of the first opening 63 and the second gate structure 5, to ensure that the first passivation layer 6 can completely surround the first gate structure 4 and the second gate structure 5. The first passivation layer 6 is mainly used to passivate and protect the first gate structure 4 and the second gate structure 5. The thickness of the first sub-passivation layer 61 can be relatively thick, with a stronger electric field shielding capability; so that the first passivation layer 6 composed of the first sub-passivation layer 61 and the second sub-passivation layer 62 has a better passivation protection effect on the first gate structure 4 and the second gate structure 5, thereby reducing the leakage of the first gate structure 4 and the second gate structure 5.

[0111] S150: doping electronegative atoms on the surface of the barrier layer exposed in the first opening away from the substrate through a plasma surface treatment process, wherein the electronegativity of the electronegative atoms is greater than or equal to that of oxygen atoms.

[0112] Specifically, such as Figure 7 As shown, when electronegative atoms are doped on the surface of the barrier layer 3 exposed by the first opening 63 away from the substrate 1 through a plasma surface treatment process, the specific process is to place the surface of the barrier layer 3 exposed by the first opening 63 away from the substrate 1 in an oxygen and / or fluorine plasma atmosphere. In this process, because the entire device is placed in the plasma atmosphere, the role of the second sub-passivation layer 62 is to isolate the first sub-passivation layer 61, the first gate structure 4, and the second gate structure 5 from the plasma atmosphere, thereby preventing damage by the plasma. In other words, without the second sub-passivation layer 62, the surface of the first sub-passivation layer 61 would be exposed to the plasma atmosphere, and the effect of reducing gate leakage current, etc. would not be achieved. The second sub-passivation layer 62 is used to protect the first sub-passivation layer 61, the first gate structure 4, and the second gate structure, and specifically, to prevent the adverse effects of doping electronegative atoms on the surface of the barrier layer 3 exposed by the first opening 63 away from the substrate 1.

[0113] During the process of doping the surface of barrier layer 3 with the electronegative atoms, the surface is oxidized and the interface is improved. This can improve the surface state of barrier layer 3 in the drift region, increase the concentration of the two-dimensional electron gas in the drift region, and thus enhance the performance of the power device. The larger the opening size of first opening 63, the greater the effect of increasing the concentration and mobility of the two-dimensional electron gas in the drift region.

[0114] S160 : forming a second passivation layer on a side of the first passivation layer away from the substrate and in the first opening, wherein the second passivation layer includes a third sub-passivation layer and a fourth sub-passivation layer.

[0115] Specifically, such as Figure 8 As shown, a second passivation layer 7 is formed within the first opening 63 on the side of the first passivation layer 6 away from the substrate 1. The thickness of the third sub-passivation layer 71 can be less than that of the first sub-passivation layer 61. The second passivation layer 7 in direct contact with the barrier layer 3 within the first opening 63 can effectively stress-enhance the drift region of the GaN HEMT device, thereby increasing the concentration and mobility of the two-dimensional electron gas of the GaN HEMT device, reducing the on-resistance of the GaN HEMT device, and improving the dynamic performance of the GaN HEMT device. The larger the opening size of the first opening 63, the larger the contact area between the second passivation layer 7 and the barrier layer 3, which can further improve the concentration and mobility of the two-dimensional electron gas of the GaN HEMT device.

[0116] S170 : forming a first electrode on a side of the first gate structure away from the first opening.

[0117] Specifically, such as Figure 9 As shown, the first passivation layer 6 may further be provided with a fourth opening 66, and the second passivation layer 7 may further be provided with a sixth opening 73. The fourth opening 66 may be located on a side of the first gate structure 4 away from the first opening 63, and the vertical projection of the sixth opening 73 on the substrate 1 may coincide with the vertical projection of the fourth opening 66 on the substrate 1. The first electrode 81 is located within the fourth opening 66 and the sixth opening 73 and contacts the barrier layer 3.

[0118] S180 : forming a second electrode on a side of the second gate structure away from the first opening.

[0119] Specifically, such as Figure 9 As shown, the first passivation layer 6 may further be provided with a fifth opening 67, and the second passivation layer 7 may further be provided with a seventh opening 74. The fifth opening 67 may be located on a side of the second gate structure 5 away from the first opening 63, and the vertical projection of the seventh opening 74 on the substrate 1 may coincide with the vertical projection of the fifth opening 67 on the substrate 1. The second electrode 82 is located within the fifth opening 67 and the seventh opening 74 and contacts the barrier layer 3.

[0120] Optionally, based on the above embodiments, Figure 10 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention, Figure 11-12 FIG. 1 is a schematic structural diagram corresponding to some steps in another method for preparing a semiconductor device provided by an embodiment of the present invention, such as Figure 10 As shown, the preparation method includes:

[0121] S200: providing a substrate.

[0122] S210: forming a channel layer and a barrier layer in sequence on one side of the substrate.

[0123] S220 : forming a first gate structure and a second gate structure on a side of the barrier layer away from the substrate.

[0124] S230: forming a first passivation layer on the first gate structure, the second gate structure, and the barrier layer on a side away from the substrate, wherein the first passivation layer includes a first sub-passivation layer and a second sub-passivation layer.

[0125] S240 : etching the first sub-passivation layer and the second sub-passivation layer between the first gate structure and the second gate structure to form a first opening, wherein the first opening exposes the barrier layer.

[0126] S250 : etching the first sub-passivation layer and the second sub-passivation layer on a side of the first gate structure away from the first opening to form a second opening, wherein the second opening exposes the barrier layer.

[0127] Specifically, such as Figure 11 As shown, the first sub-passivation layer 61 and the second sub-passivation layer 62 on the side of the first gate structure 4 away from the first opening 63 are etched to form a second opening 64. A certain distance can be set between the edge of the second opening 64 near the first gate structure 4 and the first gate structure 4 to ensure that the first passivation layer 6 between the edge of the second opening 64 near the first gate structure 4 and the first gate structure 4 can completely surround the first gate structure 4, effectively passivating and protecting the first gate structure 4. The edge of the second opening 64 away from the first gate structure 4 can be located between the first gate structure 4 and the first electrode 81. The second opening 64 can further extend away from the edge of the first gate structure 4. The second opening 64 can extend to the region of the first electrode 81 or to the region of the first electrode 81 away from the first gate structure 4.

[0128] S260 : etching the first sub-passivation layer and the second sub-passivation layer on a side of the second gate structure away from the first opening to form a third opening, wherein the third opening exposes the barrier layer.

[0129] Specifically, such as Figure 11As described above, the first sub-passivation layer 61 and the second sub-passivation layer 62 on the side of the second gate structure 5 away from the first opening 63 are etched to form a third opening 65. A certain distance can be set between the edge of the third opening 65 near the second gate structure 5 and the second gate structure 5 to ensure that the first passivation layer 6 between the edge of the third opening 65 near the second gate structure 5 and the second gate structure 5 can completely surround the second gate structure 5, effectively passivating and protecting the second gate structure 5. The edge of the third opening 65 away from the second gate structure 5 can be located between the second gate structure 5 and the second electrode 82. The third opening 65 can further extend away from the edge of the second gate structure 5, and can extend to the region of the second electrode 82 or to the region of the second electrode 82 away from the second gate structure 5.

[0130] S270: doping electronegative atoms on the surface of the barrier layer exposed at the first opening away from the substrate through a plasma surface treatment process, wherein the electronegativity of the electronegative atoms is greater than or equal to that of oxygen atoms.

[0131] S280: doping electronegative atoms on the surface of the barrier layer exposed in the second opening away from the substrate through a plasma surface treatment process, wherein the electronegativity of the electronegative atoms is greater than or equal to that of oxygen atoms.

[0132] Specifically, such as Figure 11 As shown, when electronegative atoms are doped on the surface of the barrier layer 3 exposed by the second opening 64 away from the substrate 1 through a plasma surface treatment process, the specific process is to place the surface of the barrier layer 3 exposed by the second opening 64 away from the substrate 1 in an oxygen and / or fluorine plasma atmosphere. In this process, because the entire device is placed in the plasma atmosphere, the role of the second sub-passivation layer 62 is to isolate the first sub-passivation layer 61, the first gate structure 4, and the second gate structure 5 from the plasma atmosphere, thereby preventing damage by the plasma. In other words, without the second sub-passivation layer 62, the surface of the first sub-passivation layer 61 would be exposed to the plasma atmosphere, and the effect of reducing gate leakage current, etc. would not be achieved. The second sub-passivation layer 62 is used to protect the first sub-passivation layer 61, the first gate structure 4, and the second gate structure 5. Specifically, it prevents the adverse effects of doping electronegative atoms on the surface of the barrier layer 3 exposed by the second opening 64 away from the substrate 1.

[0133] During the process of doping the surface of barrier layer 3 with these electronegative atoms, the surface is oxidized and the interface is improved. This improves the surface state of barrier layer 3 in the drift region, increases the concentration of the two-dimensional electron gas in the drift region, and thus enhances the performance of the power device. The larger the size of second opening 64, the greater the effect of increasing the concentration and mobility of the two-dimensional electron gas in the drift region.

[0134] S290: doping electronegative atoms on the surface of the barrier layer exposed at the third opening away from the substrate through a plasma surface treatment process, where the electronegativity of the electronegative atoms is greater than or equal to that of oxygen atoms.

[0135] Specifically, such as Figure 11 As shown, when electronegative atoms are doped on the surface of the barrier layer 3 exposed by the third opening 65 and facing away from the substrate 1 through a plasma surface treatment process, the specific process is to place the surface of the barrier layer 3 exposed by the third opening 65 and facing away from the substrate 1 in an oxygen and / or fluorine plasma atmosphere. In this process, because the entire device is placed in the plasma atmosphere, the role of the second sub-passivation layer 62 is to isolate the first sub-passivation layer 61, the first gate structure 4, and the second gate structure 5 from the plasma atmosphere, thereby preventing damage by the plasma. In other words, without the second sub-passivation layer 62, the surface of the first sub-passivation layer 61 would be exposed to the plasma atmosphere, and the effect of reducing gate leakage current, etc., would not be achieved. The second sub-passivation layer 62 is used to protect the first sub-passivation layer 61, the first gate structure 4, and the second gate structure 5. Specifically, it prevents the adverse effects of doping electronegative atoms on the surface of the barrier layer 3 exposed by the third opening 65 and facing away from the substrate 1.

[0136] During the process of doping the surface of barrier layer 3 with these electronegative atoms, the surface is oxidized and the interface is improved. This improves the surface state of barrier layer 3 in the drift region, increases the concentration of the two-dimensional electron gas in the drift region, and thus enhances the performance of the power device. The larger the opening size of third opening 65, the greater the effect of increasing the concentration and mobility of the two-dimensional electron gas in the drift region.

[0137] S291: forming a second passivation layer on a side of the first passivation layer away from the substrate and in the first opening, the second opening, and the third opening, wherein the second passivation layer includes a third sub-passivation layer and a fourth sub-passivation layer.

[0138] Specifically, such as Figure 12 As shown, a second passivation layer 7 is formed on a side of the first passivation layer 6 away from the substrate 1 and within the first opening 63, the second opening 64, and the third opening 65. The thickness of the third sub-passivation layer 71 can be less than the thickness of the first sub-passivation layer 61. The second passivation layer 7 in direct contact with the barrier layer 3 within the first opening 63, the second opening 64, and the third opening 65 can effectively stress enhance the drift region of the GaN HEMT device, thereby increasing the concentration and mobility of the two-dimensional electron gas of the GaN HEMT device, reducing the on-resistance of the GaN HEMT device, and improving the dynamic performance of the GaN HEMT device.

[0139] S292: forming a first electrode on a side of the first gate structure away from the first opening.

[0140] S293: forming a second electrode on a side of the second gate structure away from the first opening.

[0141] Optionally, based on the above embodiments, Figure 13 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention, such as Figure 13 As shown, the preparation method includes:

[0142] S300: providing a substrate.

[0143] S310: forming a channel layer and a barrier layer in sequence on one side of the substrate.

[0144] S320 : forming a first gate structure and a second gate structure on a side of the barrier layer away from the substrate.

[0145] S330 : forming a first sub-passivation layer on the entire surface of the first gate structure, the second gate structure, and the barrier layer on a side away from the substrate.

[0146] Specifically, such as Figure 6 As shown, a first sub-passivation layer 61 is formed on the entire surface of the first gate structure 4, the second gate structure 5 away from the substrate 1, and the barrier layer 3 away from the substrate 1. Exemplarily, the material of the first sub-passivation layer 61 can be aluminum nitride or aluminum oxide.

[0147] S340: forming a second sub-passivation layer on a side of the first sub-passivation layer away from the substrate.

[0148] Specifically, such as Figure 6 As shown, a second sub-passivation layer 62 is formed on a side of the first sub-passivation layer 61 away from the substrate 1 . For example, the material of the second sub-passivation layer 62 may be silicon nitride or silicon oxide.

[0149] S350 : etching the first sub-passivation layer and the second sub-passivation layer between the first gate structure and the second gate structure to form a first opening, wherein the first opening exposes the barrier layer.

[0150] S360: doping electronegative atoms on the surface of the barrier layer exposed at the first opening away from the substrate through a plasma surface treatment process, wherein the electronegativity of the electronegative atoms is greater than or equal to that of oxygen atoms.

[0151] S370: forming a third sub-passivation layer on a side of the first passivation layer away from the substrate and in the first opening.

[0152] Specifically, such as Figure 8 As shown, a third sub-passivation layer 71 is formed on a side of the second sub-passivation layer 62 away from the substrate 1 and is formed in the first opening 63 . For example, the material of the third sub-passivation layer 71 may include aluminum nitride or aluminum oxide.

[0153] S380: forming a fourth sub-passivation layer on a side of the third sub-passivation layer away from the substrate.

[0154] Specifically, such as Figure 8 As shown, a fourth sub-passivation layer 72 is formed on a side of the third sub-passivation layer 71 away from the substrate 1 . For example, the material of the fourth sub-passivation layer 72 may include silicon nitride or silicon oxide.

[0155] S390: forming a first electrode on a side of the first gate structure away from the first opening.

[0156] S391: forming a second electrode on a side of the second gate structure away from the first opening.

[0157] Optionally, based on the above embodiments, Figure 14 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention, such as Figure 14 As shown, the preparation method includes:

[0158] S400: providing a substrate.

[0159] S410: forming a channel layer and a barrier layer in sequence on one side of the substrate.

[0160] S420 : forming a first gate structure and a second gate structure on a side of the barrier layer away from the substrate.

[0161] S430: forming a first passivation layer on the first gate structure, the second gate structure, and the barrier layer on a side away from the substrate, wherein the first passivation layer includes a first sub-passivation layer and a second sub-passivation layer.

[0162] S440 : etching the first sub-passivation layer and the second sub-passivation layer between the first gate structure and the second gate structure to form a first opening, wherein the first opening exposes the barrier layer.

[0163] S450: doping electronegative atoms on the surface of the barrier layer exposed at the first opening away from the substrate through a plasma surface treatment process, wherein the electronegativity of the electronegative atoms is greater than or equal to that of oxygen atoms.

[0164] S460 : forming a second passivation layer on a side of the first passivation layer away from the substrate and in the first opening, wherein the second passivation layer includes a third sub-passivation layer and a fourth sub-passivation layer.

[0165] S470 : Etching the second passivation layer on a side of the first gate structure away from the first opening to form a sixth opening.

[0166] Specifically, such as Figure 1 As shown, a sixth opening 73 is formed on the second passivation layer 7 on a side of the first gate structure 4 away from the first opening 63 by photolithography and etching processes.

[0167] S480: etching the first passivation layer in a region corresponding to the sixth opening to form a fourth opening; a vertical projection of the fourth opening on the substrate coincides with a vertical projection of the sixth opening on the substrate.

[0168] Specifically, such as Figure 1 As shown, a fourth opening 66 is formed on the first passivation layer 6 in a region corresponding to the sixth opening 73 by photolithography and etching processes.

[0169] S490 : forming a first electrode in the fourth opening and the sixth opening.

[0170] Specifically, such as Figure 1 As shown, a first electrode 81 is formed in the fourth opening 66 and the sixth opening 73 . For example, the first electrode 81 may be a metal electrode.

[0171] S491: Etching the second passivation layer on a side of the second gate structure away from the first opening to form a seventh opening.

[0172] Specifically, such as Figure 1 As shown, a seventh opening 74 is formed on the second passivation layer 7 on a side of the second gate structure 5 away from the first opening 63 by photolithography and etching processes.

[0173] S492: etching the first passivation layer in a region corresponding to the seventh opening to form a fifth opening; a vertical projection of the fifth opening on the substrate coincides with a vertical projection of the seventh opening on the substrate.

[0174] Specifically, such as Figure 1 As shown, a fifth opening 67 is formed on the first passivation layer 6 in a region corresponding to the seventh opening 74 by photolithography and etching processes.

[0175] S493: forming a second electrode in the fifth opening and the seventh opening.

[0176] Specifically, such as Figure 1 As shown, a second electrode 82 is formed in the fifth opening 67 and the seventh opening 74 . For example, the second electrode 82 may be a metal electrode.

[0177] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0178] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A semiconductor device, characterized in that: include: substrate; a channel layer, located on one side of the substrate; a barrier layer, located on a side of the channel layer away from the substrate; a first gate structure and a second gate structure, wherein the first gate structure and the second gate structure are spaced apart and located on a side of the barrier layer away from the substrate; a first passivation layer, located on a side of the first gate structure, the second gate structure, and the barrier layer away from the substrate; the first passivation layer includes a first sub-passivation layer and a second sub-passivation layer, the first passivation layer includes a first opening, the first opening is located between the first gate structure and the second gate structure, and the first opening exposes the barrier layer; A surface of the barrier layer exposed by the first opening and away from the substrate is doped with electronegative atoms, and the electronegativity of the electronegative atoms is greater than or equal to the electronegativity of oxygen atoms; a second passivation layer, located on a side of the first passivation layer away from the substrate and filling the first opening, the second passivation layer comprising a third sub-passivation layer and a fourth sub-passivation layer; a first electrode, located on a side of the first gate structure away from the first opening; The second electrode is located on a side of the second gate structure away from the first opening.

2. The semiconductor device according to claim 1, wherein The first passivation layer further includes a second opening and a third opening; the second opening is located on a side of the first gate structure away from the first opening, and the third opening is located on a side of the second gate structure away from the first opening; the second opening and the third opening expose the barrier layer, and a surface of the barrier layer exposed by the second opening and the third opening away from the substrate is doped with electronegative atoms, and the electronegativity of the electronegative atoms is greater than or equal to the electronegativity of oxygen atoms; The second passivation layer fills the second opening and the third opening.

3. The semiconductor device according to claim 1, wherein The first sub-passivation layer is located on a side of the first gate structure, the second gate structure and the barrier layer away from the substrate; the second sub-passivation layer is located on a side of the first sub-passivation layer away from the substrate; the third sub-passivation layer is located on a side of the first passivation layer away from the substrate, and the third sub-passivation layer fills the first opening; the fourth sub-passivation layer is located on a side of the third sub-passivation layer away from the substrate; the thickness of the third sub-passivation layer is less than the thickness of the first sub-passivation layer.

4. The semiconductor device according to claim 3, wherein The thickness of the first sub-passivation layer is 5 nm to 100 nm, and the thickness of the third sub-passivation layer is 0.5 nm to 5 nm.

5. The semiconductor device according to claim 1, wherein The first sub-passivation layer includes a first aluminum nitride layer, and the third sub-passivation layer includes a second aluminum nitride layer. The semiconductor device according to claim 1 , wherein: Materials of the second sub-passivation layer and the fourth sub-passivation layer include at least one of silicon nitride, silicon oxide, and silicon oxynitride.

7. The semiconductor device according to claim 1 or 2, wherein: The electronegative atom includes at least one of an oxygen atom and a fluorine atom.

8. The semiconductor device according to claim 1, wherein The cross-sectional shape of the first opening is a symmetrical shape along the center line of the semiconductor device, and the distance between the vertical projection of the first gate structure on the substrate and the vertical projection of the first opening on the substrate is equal to the distance between the vertical projection of the second gate structure on the substrate and the vertical projection of the first opening on the substrate; The first gate structure and the second gate structure are the same gate structure; The distance between the vertical projection of the first electrode on the substrate and the vertical projection of the first gate structure on the substrate is the same as the distance between the vertical projection of the second electrode on the substrate and the vertical projection of the second gate structure on the substrate; both the first electrode and the second electrode are in contact with the barrier layer.

9. The semiconductor device according to claim 2, wherein: The opening size of the second opening is the same as the opening size of the third opening; the distance between the vertical projection of the second opening on the substrate and the vertical projection of the first electrode on the substrate is equal to the distance between the vertical projection of the third opening on the substrate and the vertical projection of the second electrode on the substrate; the distance between the vertical projection of the second opening on the substrate and the vertical projection of the first gate structure on the substrate is equal to the distance between the vertical projection of the third opening on the substrate and the vertical projection of the second gate structure on the substrate.

10. A method for preparing a semiconductor device, characterized in that: include: providing a substrate; forming a channel layer on one side of the substrate; forming a barrier layer on a side of the channel layer away from the substrate; forming a first gate structure and a second gate structure at intervals on a side of the barrier layer away from the substrate; forming a first passivation layer on the first gate structure, the second gate structure, and a side of the barrier layer away from the substrate, wherein the first passivation layer includes a first sub-passivation layer and a second sub-passivation layer; Etching the first sub-passivation layer and the second sub-passivation layer between the first gate structure and the second gate structure to form a first opening, wherein the first opening exposes the barrier layer; doping electronegative atoms on a surface of the barrier layer exposed at the first opening and away from the substrate through a plasma surface treatment process, wherein the electronegativity of the electronegative atoms is greater than or equal to that of oxygen atoms; forming a second passivation layer on a side of the first passivation layer away from the substrate and in the first opening, wherein the second passivation layer includes a third sub-passivation layer and a fourth sub-passivation layer; forming a first electrode on a side of the first gate structure away from the first opening; A second electrode is formed on a side of the second gate structure away from the first opening.

11. The method for manufacturing a semiconductor device according to claim 10, wherein: After etching the first sub-passivation layer and the second sub-passivation layer between the first gate structure and the second gate structure to form a first opening, the method further includes: Etching the first sub-passivation layer and the second sub-passivation layer on a side of the first gate structure away from the first opening to form a second opening, wherein the second opening exposes the barrier layer; Etching the first sub-passivation layer and the second sub-passivation layer on a side of the second gate structure away from the first opening to form a third opening, wherein the third opening exposes the barrier layer; After doping electronegative atoms on the surface of the barrier layer exposed by the first opening and away from the substrate by a plasma surface treatment process, the method further includes: doping electronegative atoms on the surface of the barrier layer exposed at the second opening and away from the substrate through a plasma surface treatment process, wherein the electronegativity of the electronegative atoms is greater than or equal to that of oxygen atoms; doping electronegative atoms on a surface of the barrier layer exposed at the third opening away from the substrate through a plasma surface treatment process, wherein the electronegativity of the electronegative atoms is greater than or equal to that of oxygen atoms; forming a second passivation layer on a side of the first passivation layer away from the substrate and in the first opening, comprising: A second passivation layer is formed on a side of the first passivation layer away from the substrate and in the first opening, the second opening, and the third opening.

12. The method for preparing a semiconductor device according to claim 11, wherein: The plasma surface treatment process includes placing the surface of the barrier layer exposed by the first opening, the second opening, and the third opening, away from the substrate, in an oxygen and / or fluorine plasma atmosphere.

13. The method for preparing a semiconductor device according to claim 10, wherein: forming a first passivation layer on the first gate structure, the second gate structure, and a side of the barrier layer away from the substrate, comprising: forming a first sub-passivation layer on the entire surface of the first gate structure, the second gate structure, and the barrier layer on a side away from the substrate; forming the second sub-passivation layer on a side of the first sub-passivation layer away from the substrate; forming a second passivation layer on a side of the first passivation layer away from the substrate and in the first opening, comprising: forming a third sub-passivation layer on a side of the first passivation layer away from the substrate and in the first opening; The fourth sub-passivation layer is formed on a side of the third sub-passivation layer away from the substrate.

14. The method for manufacturing a semiconductor device according to claim 10, wherein: forming a first electrode on a side of the first gate structure away from the first opening, comprising: Etching the second passivation layer on a side of the first gate structure away from the first opening to form a sixth opening; etching the first passivation layer in a region corresponding to the sixth opening to form a fourth opening; wherein a vertical projection of the fourth opening on the substrate coincides with a vertical projection of the sixth opening on the substrate; forming the first electrode in the fourth opening and the sixth opening; forming a second electrode on a side of the second gate structure away from the first opening, comprising: Etching the second passivation layer on a side of the second gate structure away from the first opening to form a seventh opening; etching the first passivation layer in a region corresponding to the seventh opening to form a fifth opening; wherein a vertical projection of the fifth opening on the substrate coincides with a vertical projection of the seventh opening on the substrate; The second electrode is formed in the fifth opening and the seventh opening.

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