Power device and preparation method thereof

Abstract

The invention discloses a power device and a preparation method thereof, and the power device comprises a gate structure which comprises a doped nitride semiconductor layer and a gate; the doped nitride semiconductor layer covers part of the barrier layer; the grid electrode covers part of the doped nitride semiconductor layer; the first strained layer is located at one side, far away from the substrate, of the gate and covers the side surface of the gate, the surface, far away from the substrate, of the gate and the surface, far away from the substrate, of the partially doped nitride semiconductor layer; the spacing layer covers the first strain layer; the second strain layer covers the surface, away from the substrate, of the spacing layer, the side surface of the spacing layer, the side surface of the first strain layer, the side surface of the doped nitride semiconductor layer and the surface, away from the substrate, of part of the barrier layer; in the first direction, the thickness of the first strained layer is larger than that of the second strained layer, and / or the dielectric constant of the first strained layer is larger than that of the second strained layer. According to the invention, the dynamic performance of the device can be improved while the gate electric leakage is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a power device and a preparation method thereof. Background Art

[0002] Figure 1 This is a schematic diagram of the structure of a power device in the prior art. Figure 1 The power device in the circuit is directly in contact with the gate through a strained layer, which limits the adjustable space of the strained layer on the device and cannot simultaneously meet the requirements of reducing gate leakage and improving the dynamic performance of the device. Summary of the Invention

[0003] The present invention provides a power device and a preparation method thereof, which can reduce gate leakage and improve the dynamic performance of the device.

[0004] According to one aspect of the present invention, there is provided a power device, comprising:

[0005] substrate;

[0006] a channel layer, the channel layer being located on one side of the substrate;

[0007] a barrier layer, the barrier layer being located on a side of the channel layer away from the substrate;

[0008] A gate structure comprising a doped nitride semiconductor layer and a gate; the doped nitride semiconductor layer is located on a side of the barrier layer away from the substrate, and the doped nitride semiconductor layer covers a portion of the barrier layer; the gate is located on a side of the doped nitride semiconductor layer away from the substrate, and the gate covers a portion of the doped nitride semiconductor layer;

[0009] a first strained layer, the first strained layer being located on a side of the gate away from the substrate, the first strained layer covering a side surface of the gate away from the substrate, a surface of the gate away from the substrate, and a surface of a portion of the doped nitride semiconductor layer away from the substrate;

[0010] a spacer layer, the spacer layer being located on a side of the first strained layer away from the substrate; the spacer layer covering the first strained layer;

[0011] a second strained layer, the second strained layer being located on a side of the spacer layer away from the substrate, the second strained layer covering a surface of the spacer layer away from the substrate, a side surface of the spacer layer, a side surface of the first strained layer, a side surface of the doped nitride semiconductor layer, and a portion of a surface of the barrier layer away from the substrate; wherein, along a first direction, a thickness of the first strained layer is greater than a thickness of the second strained layer, and / or a dielectric constant of the first strained layer is greater than a dielectric constant of the second strained layer; and the first direction is a direction from the substrate to the channel layer;

[0012] The source and drain are located on the side of the barrier layer away from the substrate; the drain is located on the side of the barrier layer away from the substrate, and the drain is located on the side of the gate away from the source.

[0013] Based on the above embodiment, optionally, the first strained layer and the second strained layer are made of the same material;

[0014] The material of the first strained layer and the material of the second strained layer include any one of aluminum nitride and aluminum oxide.

[0015] Based on the above embodiment, optionally, along the first direction, the thickness of the first strained layer is 5 nm-100 nm;

[0016] Along the first direction, the thickness of the second strained layer is 0.5 nm-5 nm.

[0017] Based on the above embodiment, optionally, the power device further includes:

[0018] The passivation structure is located on a side of the second strained layer away from the substrate; the passivation structure covers the second strained layer.

[0019] Based on the above embodiment, optionally, the material of the spacer layer includes silicon nitride or silicon oxynitride.

[0020] According to one aspect of the present invention, there is provided a method for preparing a power device, comprising:

[0021] forming a channel layer on one side of the substrate;

[0022] forming a barrier layer on a side of the channel layer away from the substrate;

[0023] forming a doped nitride semiconductor material layer on a side of the barrier layer away from the substrate; the doped nitride semiconductor material layer covers the barrier layer;

[0024] forming a gate on a side of the doped nitride semiconductor material layer away from the substrate;

[0025] A first strained layer and a spacer layer are formed simultaneously; the first strained layer is located on a side of the gate away from the substrate, and covers a side of the gate, a surface of the gate away from the substrate, and a surface of the partially doped nitride semiconductor material layer away from the substrate; the spacer layer is located on a side of the first strained layer away from the substrate; and the spacer layer covers the first strained layer;

[0026] Etching the doped nitride semiconductor material layer to form a doped nitride semiconductor layer; the doped nitride semiconductor layer covers a portion of the barrier layer; the gate structure includes the doped nitride semiconductor layer and the gate;

[0027] A second strained layer is formed on a side of the spacer layer away from the substrate; the second strained layer covers a surface of the spacer layer away from the substrate, a side surface of the spacer layer, a side surface of the first strained layer, a side surface of the doped nitride semiconductor layer, and a portion of a surface of the barrier layer away from the substrate; wherein, along a first direction, a thickness of the first strained layer is greater than a thickness of the second strained layer, and / or a dielectric constant of the first strained layer is greater than a dielectric constant of the second strained layer; and the first direction is a direction from the substrate to the channel layer;

[0028] A source and a drain are formed; the source is located on the side of the barrier layer away from the substrate; the drain is located on the side of the barrier layer away from the substrate, and the drain is located on the side of the gate away from the source.

[0029] Based on the above embodiment, optionally, forming the first strained layer and the spacer layer simultaneously includes:

[0030] forming a first strained material layer on a side of the gate away from the substrate; the first strained material layer covers a surface of the gate away from the substrate, a side of the gate, and a surface of the doped nitride semiconductor material layer away from the substrate that is not covered by the gate;

[0031] forming a spacer material layer on a side of the first strained material layer away from the substrate; the spacer material layer covers the first strained material layer;

[0032] The spacer material layer and the first strained material layer are etched to form a first strained layer and a spacer layer.

[0033] Based on the above embodiment, optionally, forming a first strained material layer on a side of the gate away from the substrate includes:

[0034] forming a first strained material layer on a side of the gate away from the substrate at a temperature of 300° C. to 600° C.;

[0035] forming a second strained layer on a side of the spacer layer away from the substrate, comprising:

[0036] At a temperature of 150° C. to 300° C., a second strained layer is formed on a side of the spacer layer away from the substrate. The first strained material layer and the second strained layer are made of the same material, and the thickness of the first strained material layer is greater than that of the second strained layer. The material of the first strained material layer and the material of the second strained layer include any one of aluminum nitride and aluminum oxide.

[0037] Based on the above embodiment, optionally, etching the doped nitride semiconductor material layer to form a doped nitride semiconductor layer includes:

[0038] The doped nitride semiconductor material layer is etched using the first strained layer and the spacer layer as masks to form a doped nitride semiconductor layer.

[0039] Based on the above embodiment, optionally, after forming the second strained layer on a side of the spacer layer away from the substrate, the method includes:

[0040] A passivation structure is formed on a side of the second strained layer away from the substrate; the passivation structure covers the second strained layer.

[0041] In the power device provided by the technical solution of the embodiment of the present invention, the gate structure includes a doped nitride semiconductor layer and a gate; the doped nitride semiconductor layer covers a portion of the barrier layer; the gate covers a portion of the doped nitride semiconductor layer; a first strained layer covers the side of the gate, the surface of the gate away from the substrate, and the surface of the partially doped nitride semiconductor layer away from the substrate; a spacer layer, the spacer layer is located on the side of the first strained layer away from the substrate; the spacer layer covers the first strained layer; the second strained layer covers the surface of the spacer layer away from the substrate, the side of the spacer layer, the side of the first strained layer, the side of the doped nitride semiconductor layer, and the surface of the partially doped nitride semiconductor layer away from the substrate; along the first direction, the thickness of the first strained layer is greater than the thickness of the second strained layer, and / or the dielectric constant of the first strained layer is greater than the dielectric constant of the second strained layer; the thicker thickness of the first strained layer or the larger dielectric constant of the first strained layer can enable the first strained layer to protect the gate structure and reduce gate leakage; the thinner thickness of the second strained layer or the smaller dielectric constant of the second strained layer, the second strained layer covers the drift region, and can be used to increase the stress of the device, improve the concentration and mobility of the two-dimensional electron gas, and effectively improve the dynamic performance of the device. The spacer layer can further provide protection for the gate, and the film layers covering the gate are the first strain layer and the spacer layer in sequence, which increases the number of protection layers on the surface and sides of the gate away from the substrate, thereby further avoiding gate leakage and reducing the leakage current at the gate.

[0042] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0044] Figure 1 This is a structural diagram of a power device in the prior art.

[0045] Figure 2 It is a schematic structural diagram of a power device provided by an embodiment of the present invention.

[0046] Figure 3 This is a schematic structural diagram of another power device provided by an embodiment of the present invention.

[0047] Figure 4 This is a flow chart of a method for preparing a power device provided by an embodiment of the present invention.

[0048] Figure 5-Figure 9 It is a schematic diagram of the intermediate structure of a power device provided by an embodiment of the present invention.

[0049] Figure 10 yes Figure 4 Detailed flow chart of S150.

[0050] Figure 11 This is a flow chart of a method for preparing a power device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0051] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0052] It should be noted that the terms "first," "second," and the like in the present invention are used to distinguish similar objects and are not necessarily used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to these processes, methods, products, or apparatuses.

[0053] As described in the background art, existing power devices cannot simultaneously meet the requirements of a high concentration of two-dimensional electron gas in the drift region and the need to reduce gate leakage current in the gate structure through a single strained layer. Figure 1As shown, the stress layer 101 covers the drift region, which is the area between the gate structure 40 and the drain 91, and between the gate 40 and the source 92. To reduce gate leakage current, the stress layer 101 needs to be very thick. However, to increase the two-dimensional electron gas in the drift region, a very thick stress layer 101 is not necessary. Therefore, the stress layer 101 covering the gate structure 40 and the drift region cannot simultaneously meet the requirements of a high concentration of two-dimensional electron gas in the drift region and the need to reduce gate leakage current in the gate structure, limiting the adjustable range of the stress layer 101 in the device.

[0054] In order to solve the above problems, an embodiment of the present invention provides a power device, Figure 2 is a schematic structural diagram of a power device provided by an embodiment of the present invention, Figure 3 This is a schematic diagram of the structure of another power device provided by an embodiment of the present invention, referring to Figure 2 and Figure 3 The power device includes: a substrate 10 ; a channel layer 20 , which is located on one side of the substrate 10 ; and a barrier layer 30 , which is located on a side of the channel layer 20 away from the substrate 10 .

[0055] The gate structure 40 includes a doped nitride semiconductor layer 41 and a gate 42; the doped nitride semiconductor layer 41 is located on the side of the barrier layer 30 away from the substrate 10, and the doped nitride semiconductor layer 41 covers a portion of the barrier layer 30; the gate 42 is located on the side of the doped nitride semiconductor layer 41 away from the substrate 10, and the gate 42 covers a portion of the doped nitride semiconductor layer 41.

[0056] A first strained layer 50 is located on a side of the gate 42 away from the substrate 10 , and covers the side surface of the gate 42 , the surface of the gate 42 away from the substrate 10 , and the surface of the partially doped nitride semiconductor layer 41 away from the substrate 10 ; a spacer layer 60 is located on a side of the first strained layer 50 away from the substrate 10 ; and the spacer layer 60 covers the first strained layer 50 .

[0057] a second strained layer 70, the second strained layer 70 being located on a side of the spacer layer 60 away from the substrate 10, and covering a surface of the spacer layer 60 away from the substrate, a side surface of the spacer layer 60, a side surface of the first strained layer 50, a side surface of the doped nitride semiconductor layer 41, and a portion of a surface of the barrier layer 30 away from the substrate 10; wherein, along a first direction X, the thickness of the first strained layer 50 is greater than the thickness of the second strained layer 70, and / or the dielectric constant of the first strained layer 50 is greater than the dielectric constant of the second strained layer 70; and the first direction X is the direction from the substrate 10 toward the channel layer 20;

[0058] The source 92 and the drain 91 are located on the side of the barrier layer 30 away from the substrate 10 ; the drain 91 is located on the side of the barrier layer 30 away from the substrate 10 ; and the drain 91 is located on the side of the gate 42 away from the source 92 .

[0059] Among them, the substrate 10 can be a silicon substrate or a silicon carbide substrate; the material of the channel layer 20 can be a gallium nitride material; the material of the barrier layer 30 can be AlGaN. The doped nitride semiconductor layer 41 can be a P-type gallium nitride layer. The portion of the doped nitride semiconductor layer 41 covered by the first strained layer 50 is away from the surface of the substrate 10, that is, the portion of the doped nitride semiconductor layer 41 not covered by the gate 42 is away from the surface of the substrate 10. The source 92 and the drain 91 can be formed of the same material, which is simple in process and can further reduce the control of thin film deposition materials and reduce costs. The materials of the first strained layer 50 and the second strained layer 70 can include dielectric materials with high dielectric constants such as aluminum nitride and aluminum oxide, or other suitable stress materials. Along the first direction X, the thickness of the first strained layer 50 is greater than the thickness of the second strained layer 70, or the dielectric constant of the first strained layer 50 is greater than the dielectric constant of the second strained layer 70. Alternatively, along the first direction X, the thickness of the first strained layer 50 is greater than the thickness of the second strained layer 70, and the dielectric constant of the first strained layer 50 is greater than the dielectric constant of the second strained layer 70.

[0060] When the first strained layer 50 and the second strained layer 70 are made of the same material, the thickness of the first strained layer 50 is greater than that of the second strained layer 70. The thicker thickness of the first strained layer 50 allows the first strained layer 50 to protect the gate structure 40 and reduce gate leakage. The thinner thickness of the second strained layer 70 covers the drift region and can be used to increase the stress of the device, increase the concentration and mobility of the two-dimensional electron gas, and effectively improve the dynamic performance of the device.

[0061] When the first strained layer 50 and the second strained layer 70 are made of the same material, the formation process conditions can also be controlled. For example, by controlling the deposition process temperature, gas ratio conditions, and pre-treatment, different lattice structures of the first strained layer 50 and the second strained layer 70 can be achieved, thereby achieving an effect in which the dielectric constant of the first strained layer 50 is greater than that of the second strained layer 70.

[0062] When the first strained layer 50 and the second strained layer 70 are made of different materials, the dielectric constant of the first strained layer 50 can be selected to be greater than the dielectric constant of the second strained layer 70. The higher dielectric constant of the first strained layer 50 provides stronger electric field shielding capability, allowing the first strained layer 50 to protect the gate structure 40 and reduce gate leakage. The lower dielectric constant of the second strained layer 70 can reduce the parasitic capacitance of the device. The second strained layer 70 covers the drift region and can be used to increase the stress of the device, improve the concentration and mobility of the two-dimensional electron gas, and effectively improve the dynamic performance of the device. The spacer layer 60 can further provide protection for the gate 42. The film layers covering the gate 42 are the first strained layer 50 and the spacer layer 60 in sequence. This increases the number of protective layers on the surface and sides of the gate 42 away from the substrate, thereby preventing leakage of the gate 42 and reducing the leakage current at the gate 42.

[0063] In the power device provided by the technical solution of the embodiment of the present invention, the gate structure 40 includes a doped nitride semiconductor layer 41 and a gate 42; the doped nitride semiconductor layer 41 covers a portion of the barrier layer 30; the gate 42 covers a portion of the doped nitride semiconductor layer 41; the first strained layer 50 covers the side of the gate 42, the surface of the gate 42 away from the substrate 10, and the surface of the partially doped nitride semiconductor layer 41 away from the substrate 10; the spacer layer 60 is located on the side of the first strained layer 50 away from the substrate 10; the spacer layer 60 covers the first strained layer 50; the second strained layer 70 covers the surface of the spacer layer 60 away from the substrate, the side of the spacer layer 60, the side of the first strained layer 50, the doped The side surfaces of the nitride semiconductor layer 41 and a portion of the barrier layer 30 are away from the surface of the substrate 10; along the first direction X, the thickness of the first strained layer 50 is greater than the thickness of the second strained layer 70, and / or the dielectric constant of the first strained layer 50 is greater than the dielectric constant of the second strained layer 70; the thicker thickness of the first strained layer 50 or the larger dielectric constant of the first strained layer 50 can enable the first strained layer 50 to protect the gate structure 40 and reduce gate leakage; the thinner thickness of the second strained layer 70 or the smaller dielectric constant of the second strained layer 70, which covers the drift region, can be used to increase the stress of the device, increase the concentration and mobility of the two-dimensional electron gas, and effectively improve the dynamic performance of the device. The spacer layer 60 can further provide protection for the gate 42, and the film layers covering the gate 42 are the first strained layer 50 and the spacer layer 60 in sequence, increasing the number of protective layers on the surface and sides of the gate 42 away from the substrate, thereby further preventing gate 42 leakage and reducing the leakage current at the gate 42.

[0064] Based on the above embodiment, optionally, refer to Figure 2 The first strained layer 50 and the second strained layer 70 are made of the same material; the material of the first strained layer 50 and the material of the second strained layer 70 include any one of aluminum nitride and aluminum oxide.

[0065] The first strained layer 50 and the second strained layer 70 are made of the same material. By controlling the growth time, the thickness of the first strained layer 50 is greater than that of the second strained layer 70, and / or by controlling the growth temperature, the first strained layer 50 and the second strained layer 70 have different lattice structures. This results in a dielectric constant of the first strained layer 50 greater than that of the second strained layer 70. This allows the first strained layer 50 to protect the gate structure 40 and reduce gate leakage. The second strained layer 70 can be used to increase device stress, enhance two-dimensional electron gas concentration and mobility, and effectively improve the device's dynamic performance. The materials for the first strained layer 50 and the second strained layer 70 include either aluminum nitride or aluminum oxide, both of which are mature and simple to prepare. Other high-k dielectric materials or suitable stress materials can also be used for the first strained layer 50 and the second strained layer 70.

[0066] Based on the above embodiment, optionally, refer to Figure 2 Along the first direction X, the thickness of the first strained layer 50 is 5 nm-100 nm; along the first direction X, the thickness of the second strained layer 70 is 0.5 nm-5 nm.

[0067] The thickness of the first strained layer 50 is set to 5 nm to 100 nm. Setting the thickness of the first strained layer 50 relatively thick allows the first strained layer 50 to protect the gate structure 40 and reduce gate leakage. The thickness of the second strained layer 70 is set to 0.5 nm to 5 nm, ensuring that the thickness of the first strained layer 50 is greater than that of the second strained layer 70. The second strained layer 70 can be used to increase device stress, increase the two-dimensional electron gas concentration and mobility, and effectively improve the dynamic performance of the device.

[0068] Optional, reference Figure 3 The power device further includes: a passivation structure 80 , which is located on a side of the second strained layer 70 away from the substrate 10 ; the passivation structure 80 covers the second strained layer 70 .

[0069] The material of the passivation structure 80 includes silicon nitride or silicon oxynitride, which can play a role of insulating passivation and facilitate the subsequent preparation of structures such as field plates.

[0070] Optional, reference Figure 2 and Figure 3 The material of the spacer layer 60 includes silicon nitride or silicon oxynitride.

[0071] The spacer layer 60 is made of silicon nitride or silicon oxynitride, both of which are well-developed materials and processes. The spacer layer 60 further protects the gate 42. The first strained layer 50 and the spacer layer 60 cover the gate 42, increasing the number of protective layers on the surface and sides of the gate 42 away from the substrate. This further prevents leakage from the gate 42 and reduces leakage current at the gate 42.

[0072] An embodiment of the present invention provides a method for preparing a power device based on the above embodiment, which is used to prepare the power device described in any embodiment of the present invention. Figure 4 is a flow chart of a method for preparing a power device provided by an embodiment of the present invention, Figure 5-Figure 9 This is a schematic diagram of the intermediate structure of a power device provided by an embodiment of the present invention, with reference to Figure 4-Figure 9 , the preparation method comprises:

[0073] S110 , forming a channel layer on one side of the substrate.

[0074] Among them, reference Figure 5 A channel layer 20 may be epitaxially grown on one side of the substrate 10; the channel layer 20 covers the substrate 10. The substrate 10 may be made of silicon or silicon carbide; the channel layer 20 may be made of gallium nitride.

[0075] S120 , forming a barrier layer on a side of the channel layer away from the substrate.

[0076] Among them, reference Figure 5 The material of the barrier layer 30 may be AlGaN. The barrier layer 30 may be epitaxially grown on a side of the channel layer 20 away from the substrate 10 , and the barrier layer 30 covers the channel layer 20 .

[0077] S130 , forming a doped nitride semiconductor material layer on a side of the barrier layer away from the channel layer; the doped nitride semiconductor material layer covers the barrier layer.

[0078] Among them, reference Figure 5 The doped nitride semiconductor material layer 411 may be a P-type gallium nitride layer.

[0079] S140 , forming a gate on a side of the doped nitride semiconductor material layer away from the substrate.

[0080] Among them, reference Figure 5 A whole layer of gate may be formed in advance on the doped nitride semiconductor material layer 411 , the whole layer of gate covering the doped nitride semiconductor material layer 411 , and then the whole layer of gate is etched by a photolithography and etching process to form a gate 42 .

[0081] S150. A first strained layer and a spacer layer are formed simultaneously; the first strained layer is located on a side of the gate away from the substrate, and the first strained layer covers a side of the gate, a surface of the gate away from the substrate, and a surface of a partially doped nitride semiconductor material layer away from the substrate; the spacer layer is located on a side of the first strained layer away from the substrate; and the spacer layer covers the first strained layer.

[0082] Among them, reference Figure 6-8 First, a first strained material layer 501 is formed, and then a spacer material layer 601 is formed. Then, the first strained material layer 501 and the spacer material layer 601 are etched simultaneously by a spacer etching process to form a first strained layer 50 and a spacer layer 60. The material of the spacer layer 60 includes silicon nitride or silicon oxynitride.

[0083] S160, etching the doped nitride semiconductor material layer to form a doped nitride semiconductor layer; the doped nitride semiconductor layer covers a portion of the barrier layer; the gate structure includes the doped nitride semiconductor layer and the gate.

[0084] Among them, reference Figure 8 and Figure 9 The doped nitride semiconductor material layer 411 can be etched using the first strained layer 50 and the spacer layer 60 as masks to form a doped nitride semiconductor layer 41 .

[0085] S170. Form a second strained layer on a side of the spacer layer away from the substrate; the second strained layer covers a surface of the spacer layer away from the substrate, a side surface of the spacer layer, a side surface of the first strained layer, a side surface of the doped nitride semiconductor layer, and a portion of the surface of the barrier layer away from the substrate; wherein, along a first direction, a thickness of the first strained layer is greater than a thickness of the second strained layer, and / or a dielectric constant of the first strained layer is greater than a dielectric constant of the second strained layer; the first direction is a direction from the substrate to the channel layer.

[0086] Among them, reference Figure 2 The second strain layer 70 can be formed by a deposition process. Along the first direction X, the thickness of the second strain layer 70 is 0.5 nm-5 nm.

[0087] S180, forming a source and a drain; the source is located on the side of the barrier layer away from the substrate; the drain is located on the side of the barrier layer away from the substrate, and the drain is located on the side of the gate away from the source.

[0088] In a method for fabricating a power device provided by the technical solution of an embodiment of the present invention, the thickness of the first strained layer is greater than the thickness of the second strained layer along a first direction, and / or the dielectric constant of the first strained layer is greater than the dielectric constant of the second strained layer. The thicker thickness or the larger dielectric constant of the first strained layer can enable the first strained layer to protect the gate structure and reduce gate leakage. The thinner thickness or the smaller dielectric constant of the second strained layer, which covers the drift region, can be used to increase the stress of the device, improve the concentration and mobility of the two-dimensional electron gas, and effectively improve the dynamic performance of the device. The spacer layer can further provide protection for the gate, and the film layers covering the gate are the first strained layer and the spacer layer in sequence, increasing the number of protective layers on the surface and sides of the gate away from the substrate, thereby further preventing gate leakage and reducing leakage current at the gate. The strained layer is deposited in two steps to form the first strained layer and the second strained layer. The first strained layer is mainly used to passivate and protect the gate and reduce gate leakage; the second strained layer is mainly used to enhance the stress in the drift region, increase the concentration and mobility of the two-dimensional electron gas, and improve the dynamic performance of the device. The first strained layer and the second strained layer are grown separately, which is conducive to adjusting the thickness and composition of each strained layer separately, thereby achieving the adjustment of device performance.

[0089] Based on the above embodiment, optionally, Figure 10 yes Figure 4 The detailed flow chart of S150, S150, simultaneously forming the first strained layer and the spacer layer, specifically includes:

[0090] S151, forming a first strained material layer on a side of the gate away from the substrate; the first strained material layer covers a surface of the gate away from the substrate, a side surface of the gate, and a surface of the doped nitride semiconductor material layer away from the substrate that is not covered by the gate.

[0091] Among them, reference Figure 6 The first strained material layer 501 is formed by a deposition process. The material of the first strained material layer 501 includes any one of aluminum nitride and aluminum oxide.

[0092] S152 , forming a spacer material layer on a side of the first strained material layer away from the substrate; the spacer material layer covers the first strained material layer.

[0093] Among them, reference Figure 7 , a spacer material layer 601 is formed by a deposition process. Along the first direction X, the thickness of the first strained material layer 501 covering the gate 42 is greater than the thickness of the first strained material layer 501 covering the doped nitride semiconductor material layer on both sides of the gate 42, so that the first strained layer and the spacer layer can be directly formed by a spacer process.

[0094] S153 , etching the spacer material layer and the first strained material layer to form a first strained layer and a spacer layer.

[0095] Among them, reference Figure 7 and Figure 8 The spacer material layer 601 and the first strained material layer 501 are etched by a spacer process to form a first strained layer 50 and a spacer layer 60. The thickness of the first strained layer 50 can be 5 nm to 100 nm.

[0096] Based on the above embodiment, optionally, forming a first strained material layer on a side of the gate away from the substrate includes:

[0097] A first strained material layer is formed on a side of the gate away from the substrate at a temperature of 300° C.-600° C.

[0098] forming a second strained layer on a side of the spacer layer away from the substrate, comprising:

[0099] At a temperature of 150° C. to 300° C., a second strained layer is formed on a side of the spacer layer away from the substrate. The first strained material layer and the second strained layer are made of the same material, and the thickness of the first strained material layer is greater than that of the second strained layer. The material of the first strained material layer and the material of the second strained layer include any one of aluminum nitride and aluminum oxide.

[0100] Based on the above embodiment, optionally, etching the doped nitride semiconductor material layer to form a doped nitride semiconductor layer includes:

[0101] The doped nitride semiconductor material layer is etched using the first strained layer and the spacer layer as masks to form a doped nitride semiconductor layer.

[0102] The doped nitride semiconductor material layer is etched using the first strained layer and the spacer layer as masks to form a doped nitride semiconductor layer, thereby simplifying the process steps.

[0103] Based on the above embodiment, optionally, Figure 11 This is a flow chart of a method for preparing a power device provided by an embodiment of the present invention, with reference to Figure 11 , a preparation method comprising:

[0104] S110 , forming a channel layer on one side of the substrate.

[0105] S120 , forming a barrier layer on a side of the channel layer away from the substrate.

[0106] S130 , forming a doped nitride semiconductor material layer on a side of the barrier layer away from the channel layer; the doped nitride semiconductor material layer covers the barrier layer.

[0107] S140 , forming a gate on a side of the doped nitride semiconductor material layer away from the substrate.

[0108] S150. A first strained layer and a spacer layer are formed simultaneously; the first strained layer is located on a side of the gate away from the substrate, and the first strained layer covers a side of the gate, a surface of the gate away from the substrate, and a surface of a partially doped nitride semiconductor material layer away from the substrate; the spacer layer is located on a side of the first strained layer away from the substrate; and the spacer layer covers the first strained layer.

[0109] S160, etching the doped nitride semiconductor material layer to form a doped nitride semiconductor layer; the doped nitride semiconductor layer covers a portion of the barrier layer; the gate structure includes the doped nitride semiconductor layer and the gate.

[0110] S170. Form a second strained layer on a side of the spacer layer away from the substrate; the second strained layer covers a surface of the spacer layer away from the substrate, a side surface of the spacer layer, a side surface of the first strained layer, a side surface of the doped nitride semiconductor layer, and a portion of the surface of the barrier layer away from the substrate; wherein, along a first direction, a thickness of the first strained layer is greater than a thickness of the second strained layer, and / or a dielectric constant of the first strained layer is greater than a dielectric constant of the second strained layer; the first direction is a direction from the substrate to the channel layer.

[0111] S190 , forming a passivation structure on a side of the second strained layer away from the substrate; the passivation structure covers the second strained layer.

[0112] Among them, reference Figure 3 , a passivation structure 80 can be formed by a deposition process. The material of the passivation structure 80 includes silicon nitride or silicon oxynitride, which can play the role of insulating passivation and facilitate the subsequent preparation of structures such as field plates.

[0113] S180, forming a source and a drain; the source is located on the side of the barrier layer away from the substrate; the drain is located on the side of the barrier layer away from the substrate, and the drain is located on the side of the gate away from the source.

[0114] The method for preparing the power device provided by the embodiment of the present invention has the same beneficial effects as the power device provided by any embodiment of the present invention.

[0115] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0116] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A power device, characterized in that: include: substrate; a channel layer, the channel layer being located on one side of the substrate; a barrier layer, the barrier layer being located on a side of the channel layer away from the substrate; A gate structure, the gate structure comprising a doped nitride semiconductor layer and a gate; the doped nitride semiconductor layer is located on a side of the barrier layer away from the substrate, and the doped nitride semiconductor layer covers a portion of the barrier layer; the gate is located on a side of the doped nitride semiconductor layer away from the substrate, and the gate covers a portion of the doped nitride semiconductor layer; a first strained layer, the first strained layer being located on a side of the gate away from the substrate, the first strained layer covering a side surface of the gate, a surface of the gate away from the substrate, and a portion of a surface of the doped nitride semiconductor layer away from the substrate; a spacer layer, the spacer layer being located on a side of the first strained layer away from the substrate; The spacer layer covers the first strained layer; a second strained layer, the second strained layer being located on a side of the spacer layer away from the substrate, the second strained layer covering a surface of the spacer layer away from the substrate, a side surface of the spacer layer, a side surface of the first strained layer, a side surface of the doped nitride semiconductor layer, and a portion of a surface of the barrier layer away from the substrate; wherein, along a first direction, a thickness of the first strained layer is greater than a thickness of the second strained layer, and / or a dielectric constant of the first strained layer is greater than a dielectric constant of the second strained layer; and the first direction is a direction from the substrate to the channel layer; A source and a drain, the source is located on a side of the barrier layer away from the substrate; the drain is located on a side of the barrier layer away from the substrate, and the drain is located on a side of the gate away from the source.

2. The power device according to claim 1, wherein: The first strained layer and the second strained layer are made of the same material; The material of the first strained layer and the material of the second strained layer include any one of aluminum nitride and aluminum oxide.

3. The power device according to claim 1, wherein: Along the first direction, the thickness of the first strained layer is 5 nm-100 nm; Along the first direction, the thickness of the second strained layer is 0.5 nm-5 nm.

4. The power device according to claim 1, wherein: Also includes: A passivation structure is located on a side of the second strained layer away from the substrate; the passivation structure covers the second strained layer.

5. The power device according to claim 1, wherein: The material of the spacer layer includes silicon nitride or silicon oxynitride.

6. A method for preparing a power device, characterized in that: include: forming a channel layer on one side of the substrate; forming a barrier layer on a side of the channel layer away from the substrate; forming a doped nitride semiconductor material layer on a side of the barrier layer away from the substrate; the doped nitride semiconductor material layer covers the barrier layer; forming a gate on a side of the doped nitride semiconductor material layer away from the substrate; forming a first strained layer and a spacer layer simultaneously; the first strained layer is located on a side of the gate away from the substrate, and the first strained layer covers a side surface of the gate, a surface of the gate away from the substrate, and a portion of a surface of the doped nitride semiconductor material layer away from the substrate; The spacer layer is located on a side of the first strained layer away from the substrate; The spacer layer covers the first strained layer; Etching the doped nitride semiconductor material layer to form a doped nitride semiconductor layer; the doped nitride semiconductor layer covers a portion of the barrier layer; The gate structure includes a doped nitride semiconductor layer and a gate; A second strained layer is formed on a side of the spacer layer away from the substrate; the second strained layer covers a surface of the spacer layer away from the substrate, a side surface of the spacer layer, a side surface of the first strained layer, a side surface of the doped nitride semiconductor layer, and a portion of a surface of the barrier layer away from the substrate; wherein, along a first direction, a thickness of the first strained layer is greater than a thickness of the second strained layer, and / or a dielectric constant of the first strained layer is greater than a dielectric constant of the second strained layer; and the first direction is a direction from the substrate to the channel layer; A source and a drain are formed; the source is located on a side of the barrier layer away from the substrate; the drain is located on a side of the barrier layer away from the substrate, and the drain is located on a side of the gate away from the source.

7. The method for preparing a power device according to claim 6, wherein: The method simultaneously forms a first strained layer and a spacer layer, comprising: forming a first strained material layer on a side of the gate away from the substrate; the first strained material layer covers a surface of the gate away from the substrate, a side surface of the gate, and a surface of the doped nitride semiconductor material layer away from the substrate that is not covered by the gate; forming a spacer material layer on a side of the first strained material layer away from the substrate; the spacer material layer covers the first strained material layer; The spacer material layer and the first strained material layer are etched to form a first strained layer and a spacer layer.

8. The method for preparing a power device according to claim 7, wherein: forming a first strained material layer on a side of the gate away from the substrate, comprising: forming a first strained material layer on a side of the gate away from the substrate at a temperature of 300° C.-600° C.; Forming a second strained layer on a side of the spacer layer away from the substrate, comprising: At a temperature of 150° C. to 300° C., a second strained layer is formed on a side of the spacer layer away from the substrate; wherein the first strained material layer and the second strained layer are made of the same material, the first strained material layer is thicker than the second strained layer, and the material of the first strained material layer and the second strained layer include any one of aluminum nitride and aluminum oxide.

9. The method for preparing a power device according to claim 7, wherein: Etching the doped nitride semiconductor material layer to form a doped nitride semiconductor layer comprises: The doped nitride semiconductor material layer is etched using the first strained layer and the spacer layer as masks to form a doped nitride semiconductor layer.

10. The method for preparing a power device according to claim 7, wherein: After forming a second strained layer on a side of the spacer layer away from the substrate, the method includes: A passivation structure is formed on a side of the second strained layer away from the substrate; the passivation structure covers the second strained layer.

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