Semiconductor device and preparation method thereof, power module, power conversion circuit and vehicle

Abstract

The invention discloses a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle, and relates to the technical field of semiconductors, a semiconductor body of the semiconductor device comprises a first surface and a second surface which are oppositely arranged, the first surface is provided with a groove, and the groove extends into the semiconductor body from the first surface. The first structure is located in the trench. The first barrier layer is located between the first structure and the bottom and part of the side wall of the groove, the second barrier layer covers the side, away from the second surface, of the first structure, the second barrier layer comprises a protruding part located between the first structure and the inner wall of the groove, and the protruding part makes contact with the first barrier layer. Through the arrangement of the second barrier layer, a gap which is allowed to be formed when the first barrier layer is over-etched and removed is filled, a gap in the semiconductor device is avoided, an erosion defect is avoided, and the reliability of the device is improved.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular relates to a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle. Background Art

[0002] In silicon carbide double-trench devices, due to the difference in etching rate between the material of the insulating dielectric layer and polysilicon, the etching process during the preparation of semiconductor devices will cause a gap between the trench wall and the polysilicon. In the subsequent process of forming ohmic contact, this gap will cause the ohmic contact metal to react with polysilicon to form corrosion defects, affecting device reliability. Summary of the Invention

[0003] The embodiments of the present application provide a semiconductor device and preparation method, a power module, a power conversion circuit and a vehicle, which are intended to avoid the existence of gaps in semiconductor devices, avoid the formation of corrosion defects, and improve device reliability.

[0004] In a first aspect, the present application provides a semiconductor device comprising a semiconductor body, a first structure, a source, a drain, a first barrier layer, and a second barrier layer. The semiconductor body is configured as a first conductivity type, and includes a first surface and a second surface disposed opposite each other. The first surface is provided with a trench, the trench extending from the first surface into the semiconductor body, and the first structure is located within the trench. The first barrier layer is located between the first structure and the bottom and a portion of the sidewall of the trench. The second barrier layer covers the side of the first structure away from the second surface. The second barrier layer includes a protrusion located between the first structure and the inner wall of the trench, the protrusion contacting the first barrier layer. The source is located on the first surface, and the drain is located on the second surface.

[0005] In some embodiments, the trench comprises a gate trench, and the first structure comprises a gate structure. Alternatively, the trench comprises a source trench, and the first structure comprises a source trench structure.

[0006] In some embodiments, the first barrier layer includes a concave gap at a contact portion with the protrusion, and the protrusion at least partially fills the gap.

[0007] In some embodiments, the first barrier layer and the second barrier layer are made of the same material, both comprising silicon oxide.

[0008] In a second aspect, the present application further provides a method for preparing a semiconductor device, comprising the following steps S01 to S04: Step S01 : forming a trench on a semiconductor body, wherein the semiconductor body is set to a first conductivity type, the semiconductor body includes a first surface and a second surface opposite to each other, and the trench extends from the first surface into the semiconductor body.

[0009] Step S02: forming a first structure in the trench, and forming a first barrier layer and a second barrier layer, wherein the first barrier layer is located between the first structure and the bottom and part of the side wall of the trench, and the second barrier layer covers the side of the first structure away from the second surface, and the second barrier layer includes a protrusion located between the first structure and the inner wall of the trench, and the protrusion is in contact with the first barrier layer.

[0010] Step S03: forming a source electrode on the first surface.

[0011] Step S04: forming a drain on the second surface.

[0012] In some embodiments, forming the second barrier layer includes performing a thermal oxidation process on a portion of the first structure away from the second surface to form the second barrier layer.

[0013] In some embodiments, forming the second barrier layer includes: forming the second barrier layer on a side of the first barrier layer away from the second surface and a side of the first structure away from the second surface by using a deposition process.

[0014] On the other hand, an embodiment of the present application further provides a power module, which includes a substrate and a semiconductor device as described in any of the above embodiments, wherein the substrate is used to support the semiconductor device.

[0015] In yet another aspect, embodiments of the present application further provide a power conversion circuit configured for one or more of current conversion, voltage conversion, and power factor correction. The power conversion circuit includes a circuit board and a semiconductor device according to any of the above embodiments, the semiconductor device being electrically connected to the circuit board.

[0016] On the other hand, an embodiment of the present application also provides a vehicle, which includes a load and a power conversion circuit as described in the above embodiment, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0017] In the embodiments provided in the present application, the semiconductor body includes a first surface and a second surface arranged opposite to each other, the first surface is provided with a groove, the groove extends from the first surface into the semiconductor body, and the first structure is located in the groove. The first barrier layer is located between the first structure and the bottom and part of the side wall of the groove, the second barrier layer covers the side of the first structure away from the second surface, and the second barrier layer includes a protrusion located between the first structure and the inner wall of the groove, and the protrusion is in contact with the first barrier layer. In some embodiments, the first barrier layer here is an insulating dielectric layer. Due to the difference in etching rate during the process, the first barrier layer between the first structure and part of the side wall of the groove is over-etched and removed. In the present application, the protrusion of the second barrier layer is in contact with the first barrier layer, filling the gap formed by the over-etching and removal of the first barrier layer, avoiding the existence of gaps inside the semiconductor device, which is beneficial to avoiding corrosion defects and improving device reliability.

[0018] The above-mentioned power module, power conversion circuit and vehicle have the same structure and beneficial technical effects as the semiconductor devices provided in some of the above-mentioned embodiments, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which: Figure 1 Schematic diagram of the gap at the source trench in the related art; Figure 2 A schematic structural diagram of a semiconductor device provided in an embodiment of the present application; Figure 3 A flow chart of a method for preparing a semiconductor device provided in an embodiment of the present application; Figures 4 to 12 A diagram of the steps for preparing a semiconductor device according to an embodiment of the present application; Figure 13 A structural diagram of a power module provided in an embodiment of the present application; Figure 14 A structural diagram of a power conversion circuit provided in an embodiment of the present application; Figure 15 A structural diagram of a vehicle provided in an embodiment of the present application. DETAILED DESCRIPTION

[0020] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the embodiments described are only some embodiments of the present application, not all embodiments. Based on the embodiments provided in this application, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of this application.

[0021] Unless the context requires otherwise, throughout the specification and claims, the term "comprising" is to be construed in an open, inclusive sense, that is, meaning "including, but not limited to."

[0022] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of this application, unless otherwise specified, "plurality" means two or more.

[0023] When describing some embodiments, the word "connected" and its derivatives may be used. The term "connected" should be understood broadly. For example, "connected" can mean fixed connection, detachable connection, or integration; it can be directly connected or indirectly connected through an intermediate medium. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other.

[0024] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0025] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0026] Example embodiments are described herein with reference to cross-sectional illustrations that are idealized example drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the example embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the example embodiments.

[0027] Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and are not to be construed as limiting the present application.

[0028] As mentioned in the background technology, in the silicon carbide double trench device, due to the difference in etching rate between the insulating dielectric layer and the polysilicon, the relevant etching process will cause the insulating dielectric layer in the trench to be over-etched. Taking the source trench as an example, the insulating dielectric layer is over-etched, resulting in a gap between the trench wall of the source trench and the polysilicon, such as Figure 1 As shown in the dotted box, Figure 1 This is a schematic diagram of the gap in the source trench in the related art. In the subsequent process of forming the ohmic contact, this gap will cause the ohmic contact metal to react with the polysilicon to form corrosion defects, affecting the device reliability.

[0029] Based on this, the present application provides a semiconductor device, such as Figure 2 As shown, Figure 2 A schematic structural diagram of a semiconductor device provided in an embodiment of the present application.

[0030] The semiconductor device 10 includes a semiconductor body 11, a first structure 20, a source 14, a drain 15, a first barrier layer 16, and a second barrier layer 17. The semiconductor body 11 is configured as a first conductivity type and includes a first surface P1 and a second surface P2 disposed opposite each other. A trench T0 is provided on the first surface P1, extending from the first surface P1 into the semiconductor body 11. The first structure 20 is located within the trench T0. The first barrier layer 16 is located between the first structure 20 and the bottom and a portion of the sidewalls of the trench T0. The second barrier layer 17 covers a side of the first structure 20 away from the second surface P2. The second barrier layer 17 includes a protrusion 171 located between the first structure 20 and the inner wall of the trench T0, and the protrusion 171 contacts the first barrier layer 16.

[0031] The source 14 is located on the first surface P1 , and the drain 15 is located on the second surface P2 .

[0032] In some embodiments, as Figure 2 As shown, the trench T0 includes a source trench T1, and the first structure 20 includes a source trench structure 12. Alternatively, the trench T0 includes a gate trench T2, and the first structure includes a gate structure 13.

[0033] For example, Figure 2 As shown, in some embodiments, the semiconductor body 11 further includes a well region 101 set to the second conductivity type, a first region 102 set to the first conductivity type, and a second region 103 set to the second conductivity type. The first conductivity type may be N-type, and correspondingly, the second conductivity type is P-type, that is, the semiconductor device is an N-type semiconductor device. Accordingly, the well region 101 may also be referred to as a "P-type well region (P-well)", and the first region 102 may also be referred to as an "N-type semiconductor device". + The second region 103 may also be referred to as "P +The semiconductor device 10 further includes an ohmic contact layer 18, which is located between the first surface P1 and the source 14 to form a good electrical contact. The ohmic contact metal of the ohmic contact layer 18 may include at least one of nickel (Ni), titanium (Ti), or a nickel-titanium alloy (NiTi alloy metal). Alternatively, in other embodiments, the first conductivity type may be P-type, and the second conductivity type may be N-type. Accordingly, the semiconductor device is a P-type semiconductor device.

[0034] Taking an N-type semiconductor device as an example, by transmitting a turn-on voltage to the gate structure 13, when the semiconductor device 10 is forward conducting and the operating current is low, the operating current flows from the drain 15 through the semiconductor body 11, the well region 101, the first region 102, the ohmic contact layer 18, and finally reaches the source 14. Because the P-type ion concentration in the second region 103 is higher than that in the well region 101, the second region 103 can form more PN junctions with the semiconductor body 11. When the operating current is high, the operating current flows from the drain 15 through the semiconductor body 11, the second region 103 ohmic contact layer 18, and finally reaches the source 14, preventing the high operating current from flowing through the well region 101 and thus protecting the channel in the well region 101.

[0035] It can be understood that in some embodiments, the semiconductor device may not be provided with the source trench T1 and the source trench structure 12. For example, during the preparation process, the source trench T1 is no longer formed synchronously during the formation of the gate trench T2, and only the second region 103 is formed at the corresponding position, which will not be repeated here.

[0036] Alternatively, in other embodiments, a source trench T1 is provided on the first surface P1, but the source trench structure 12 is not provided in the source trench T1. For example, during the manufacturing process, after the gate trench T2 and the gate structure 13 are formed, the source trench T1 is formed, and then the second region 103 is formed at the corresponding position. The source trench T1 is no longer filled with polysilicon, but the subsequent process is directly carried out. In this case, in the finally formed semiconductor device, the source trench T1 may include the material of the source 14, or may also include a cavity. This will not be repeated here.

[0037] In the embodiment of the present application, the first barrier layer 16 is an insulating dielectric layer, which can be used to provide good electrical insulation performance and prevent current leakage.

[0038] Taking the example of trench T0 including source trench T1 and first structure 20 including source trench structure 12, in the related art, an etching process is required before forming the ohmic contact layer 18 to form a patterned source trench structure 12. The material of the source trench structure 12 includes polysilicon. Due to the inconsistent etching rates of the material of the insulating dielectric layer and polysilicon, after the patterned etching of the source trench structure 12 is completed, the first barrier layer 16 is usually over-etched, that is, a gap is formed between the trench wall of the source trench T1 and the source trench structure 12. Subsequently, the patterned etching process of the gate insulating layer 104 may further worsen the gap. In the subsequent process of forming the ohmic contact layer 18, the ohmic contact metal included in the ohmic contact layer 18 will be deposited in the gap and react with the exposed polysilicon in the source trench structure 12 to form corrosion defects, affecting the reliability of the device.

[0039] In the embodiment of the present application, the protruding portion 171 of the second barrier layer 17 is located between the source trench structure 12 and the inner wall of the source trench T1, and the protruding portion 171 contacts the first barrier layer 16. Compared to the related art, the second barrier layer 17 is formed after the patterned source trench structure 12 and gate structure 13 are formed and before the ohmic contact layer 18 is formed. The protruding portion 171 of the second barrier layer 17 fills the gap between the trench wall of the source trench T1 and the source trench structure 12, preventing the source trench structure 12 from being exposed in the gap and preventing corrosion defects in the subsequent ohmic contact process, thereby improving device reliability.

[0040] Moreover, in the embodiment of the present application, the second barrier layer 17 also covers a side of the first structure 20 away from the second surface P2 .

[0041] Taking the first structure 20 including the source trench structure 12 as an example, generally, the material of the semiconductor body 11 includes silicon carbide, the first region 102 is formed by ion doping of the silicon carbide material, and the material of the source trench structure 12 includes polycrystalline silicon. The process required to form metal silicide on the surface of silicon carbide is quite different from the process required to form metal silicide on the surface of polycrystalline silicon. Exposing part of the source trench structure 12 on the first surface of the semiconductor body 11 will increase the difficulty of forming an ohmic contact.

[0042] For example, in the related art, after the ohmic contact layer 18 is formed on the first surface P1 of the semiconductor body 11, a high-temperature annealing process is required to form an ohmic contact between the ohmic contact layer 18 and the first region 102. Since the temperature required to form metal silicide on the silicon carbide surface is relatively high, at this temperature, the polysilicon of the source trench structure 12 reacts too violently with the ohmic contact metal, easily forming corrosion defects, which in turn affects the stability of the device.

[0043] Based on this, in an embodiment of the present application, a second barrier layer 17 is provided on the side of the source trench structure 12 away from the second surface P2. This not only can modify the surface of the source trench structure 12 and make it flat, facilitating the subsequent formation of the ohmic contact layer 18, but also can prevent the polysilicon material of the source trench structure 12 from directly contacting the subsequently formed ohmic contact layer 18, thereby avoiding the formation of corrosion defects due to the reaction between the ohmic contact metal and the polysilicon in the subsequent process of forming the ohmic contact. That is, the second barrier layer 17 covers the side of the source trench structure 12 away from the second surface P2, which is beneficial to improving device reliability.

[0044] In some embodiments, the source trench T1 and the gate trench T2 are formed simultaneously in the same process, and the source trench structure 12 and the gate structure 13 are formed simultaneously in the same process. In addition, in some embodiments, the second barrier layer 17 is formed by a thermal oxidation process.

[0045] In related technologies, such as the patterned etching process of the first structure 20 mentioned above, after etching, the surface edge of the gate structure 13 away from the second surface P2 will have a sharp corner, which will cause electric field concentration and thus cause gate-source leakage.

[0046] In the embodiment provided herein, during the thermal oxidation process to form the second barrier layer 17, the sharp corners of the gate structure 13 are oxidized and removed, that is, the edges of the gate structure 13 are flattened. This can reduce the risk of gate-source leakage in the semiconductor device 10 and improve device reliability.

[0047] In some embodiments, as Figure 2 As shown, the first barrier layer 16 includes a concave gap K1 at the contact portion with the protrusion 171 , and the protrusion 171 at least partially fills the gap K1 .

[0048] like Figure 2 As shown, during the etching process, the first barrier layer 16 is affected by the first structure 20 and the sidewall of the trench T0, and is etched less near the first structure 20 or the sidewall of the trench T0, and is etched more at the middle position, so that the first barrier layer 16 forms the following Figure 2 The gap K1 is indicated by the dotted line.

[0049] The protrusion 171 at least partially fills the gap K1 to prevent a cavity from being formed in the gap K1 after subsequent processes are completed, thereby preventing corrosion defects and improving the stability of the semiconductor device.

[0050] In some embodiments, the first barrier layer 16 and the second barrier layer 17 are made of the same material, silicon oxide. Based on the silicon carbide material of the semiconductor body 11 and the polysilicon material of the first structure 20 (the source trench structure 12 and the gate structure 13), both the first barrier layer 16 and the second barrier layer 17 can be formed through an oxidation process. Silicon oxide has high insulation stability, which can be used to reduce leakage current and prevent corrosion defects caused by the reaction between the ohmic contact metal and the polysilicon during high-temperature annealing processes, thereby improving the stability of the semiconductor device 10.

[0051] In a second aspect, the present application also provides a method for preparing a semiconductor device, such as Figure 3 As shown, Figure 3 A flow chart of a method for preparing a semiconductor device provided in an embodiment of the present application, Figures 4 to 12 A diagram of the steps for preparing a semiconductor device provided in an embodiment of the present application.

[0052] like Figure 3 As shown, the preparation method includes the following steps S01 to S04: Step S01: Figure 4~Figure 5 As shown, a trench T0 is formed on a semiconductor body 11 , wherein the semiconductor body 11 is set to a first conductivity type, the semiconductor body 11 includes a first surface P1 and a second surface P2 opposite to each other, and the trench T0 extends from the first surface P1 into the semiconductor body 11 .

[0053] The first conductivity type may be N-type, for example, Figure 4 As shown, the conductivity type of the semiconductor body 11 is N-type. On the first surface P1 of the semiconductor body 11, a mask is formed by a photolithography process to define an ion implantation area and perform P + Ion implantation is performed to form a well region 101. After removing the mask, a new mask is formed by photolithography to define the ion implantation area and perform N + Ion implantation is performed to form the first region 102. The implantation energy is controlled to thereby control the implantation depth, so that the first region 102 is located on the first surface P1, and the well region 101 is located on a side of the first region 102 away from the first surface P1.

[0054] Afterwards, if Figure 5 As shown, a trench T0 is formed by an etching process, and the trench T0 extends from the first surface P1 into the semiconductor body 11. Figure 5 As shown, the trench T0 may include a source trench T1 and a gate trench T2, both of which are formed in the same process. After forming the source trench T1 and the gate trench T2, a second region 103 is formed on the surface of the source trench T1. The second region 103 may also be referred to as "P +Contact area". After that, a carbon film is deposited on the surface of the device and activated by high-temperature annealing. After the annealing activation is completed, the carbon film is removed. This process helps to activate the doped ions and repair the lattice defects caused by processes such as ion implantation, which is beneficial to improving the yield and reliability of the device.

[0055] Step S02: Figures 6 to 11 As shown, a first structure 20 is formed in the trench T0, and a first barrier layer 16 and a second barrier layer 17 are formed. The first barrier layer 16 is located between the first structure 20 and the bottom and part of the sidewall of the trench T0. The second barrier layer 17 covers the side of the first structure 20 away from the second surface P2. The second barrier layer 17 includes a protrusion 171 located between the first structure 20 and the inner wall of the trench T0, and the protrusion 171 is in contact with the first barrier layer 16.

[0056] For example, Figure 6 As shown, a high-temperature gate oxide process is used to thermally oxidize and grow an insulating dielectric layer on the sidewalls and bottom of the trenches, thereby forming a first barrier layer 16 on the inner wall of the source trench T1 and a first barrier layer 16 on the inner wall of the gate trench T2. The first barrier layer 16 can be used to provide good electrical insulation and prevent current leakage. In addition, the first barrier layer 16 formed on the inner wall of the gate trench T2 can also protect the gate structure 13.

[0057] Then, if Figure 7-Figure 8 As shown, polysilicon is deposited and etched, and finally, a source trench structure 12 is formed in the source trench T1 , and a gate structure 13 is formed in the gate trench T2 .

[0058] like Figure 8 As shown in the dashed box, due to the difference in etching rates between the insulating dielectric layer and the polysilicon, the first barrier layer 16 is overetched during the polysilicon etching process, resulting in a concave gap K1 formed in the first barrier layer 16. For example, a gap exists between the trench wall of the source trench T1 and the source trench structure 12.

[0059] To avoid the gap from causing corrosion defects in the subsequent ohmic contact process, such as Figure 9 As shown, the second barrier layer 17 may be formed first.

[0060] Illustratively, in some embodiments, forming the second barrier layer 17 includes: performing a thermal oxidation process on a portion of the first structure 20 away from the second surface P2 to form the second barrier layer 17. In some embodiments, the portion of the first structure 20 (the source trench structure 12 and the gate structure 13) away from the second surface P2 and the exposed portion of the first surface P1 of the semiconductor body 11 are both thermally oxidized simultaneously, that is, the formed second barrier layer 17 also covers the portion of the first structure 20 (the source trench structure 12 and the gate structure 13) away from the second surface P2 and the first surface P1 of the semiconductor body 11.

[0061] Thermal oxidation can modify the polysilicon surface, making the surface of the first structure 20 (source trench structure 12 and gate structure 13) away from the second surface P2 smoother. For the gate structure 13, thermal oxidation can remove sharp corners, reduce the risk of gate-source leakage in the semiconductor device, and improve device reliability.

[0062] Thermal oxidation treatment includes, but is not limited to, high-temperature dry oxygen oxidation, high-temperature wet oxygen oxidation, and rapid thermal oxidation. For example, oxygen, hydrogen chloride, nitrogen, or other gases may be introduced at a temperature of 800° C. to 1200° C. to form a second barrier layer 17 having a thickness ranging from 100 angstroms to 1000 angstroms.

[0063] Alternatively, in some embodiments, forming the second barrier layer 17 includes: forming the second barrier layer 17 on a side of the first barrier layer 16 away from the second surface P2 and a side of the first structure 20 away from the second surface P2 by a deposition process.

[0064] The purpose of thermal oxidation treatment or deposition process is to form the second barrier layer 17. The protrusion 171 of the second barrier layer 17 is located between the source trench structure 12 and the inner wall of the source trench T1, and the protrusion 171 contacts the first barrier layer 16, thereby avoiding corrosion defects caused by the gap.

[0065] The second barrier layer 17 also covers the side of the first structure 20 away from the second surface P2 , which is beneficial to the subsequent ohmic contact process and prevents the polysilicon of the source trench structure 12 from directly contacting and violently reacting with the ohmic contact metal to cause corrosion defects.

[0066] Afterwards, if Figure 10 As shown, a gate insulating layer 104 is formed, and the gate insulating layer 104 covers the gate structure 13 to isolate and protect the gate structure 13. In some embodiments, the gate insulating layer 104 and the first barrier layer 16 and the second barrier layer 17 are made of the same material, both comprising silicon oxide. Figure 10As shown, during the process of patterning the gate insulating layer 104 , the second barrier layer 17 can be patterned simultaneously to remove unnecessary portions of the second barrier layer 17 without adding an additional etching process.

[0067] Then, if Figure 11 As shown, an ohmic contact layer 18 is formed on the first surface P1. Due to the presence of the second barrier layer 17, during the process of forming the ohmic contact, the source trench structure 12 will not form corrosion defects due to reaction with the ohmic contact metal.

[0068] Step S03: Figure 12 As shown, a source electrode 14 is formed on the first surface P1. For example, aluminum is deposited to form a thick metal by sputtering or evaporation.

[0069] Step S04: Figure 12 As shown, a drain 15 is formed on the second surface P2.

[0070] At this point, the semiconductor device 10 is completed.

[0071] In the above-mentioned preparation method, after forming the patterned first structure 20 and before forming the ohmic contact layer 18, a second barrier layer 17 is formed by adding a process, so that the protrusion 171 of the second barrier layer 17 fills the space between the first structure 20 and the inner wall of the trench T0, and fills the gap formed by over-etching the first barrier layer 16, thereby avoiding the existence of gaps or cavities inside the semiconductor device, which is beneficial to avoiding corrosion defects and thus improving device reliability.

[0072] This additional process can be either a thermal oxidation process or a deposition process. Both processes are mature, simple, and easy to operate, and do not require an additional etching process. The patterning of the second barrier layer 17 can be performed simultaneously with the subsequent patterning of the gate insulating layer 104. Therefore, by adding a single process, device reliability can be significantly improved at a lower cost.

[0073] On the other hand, an embodiment of the present application further provides a power module, Figure 13 This is a structural diagram of the power module provided in an embodiment of the present application.

[0074] like Figure 13 As shown, the power module 200 includes a substrate 201 and the semiconductor device 10 in any of the above embodiments. The substrate 201 is used to support the semiconductor device 10 .

[0075] Illustratively, the power module 200 can function as a power amplifier, a power converter, a power controller, a power management module, or a power regulator. A power amplifier is used to amplify the power of an electrical signal. A power converter is used to convert electrical energy from one form to another. For example, a power converter can be an AC / DC converter or a DC / DC converter. A power controller is used to control the flow of power. A power management module is used to manage the power supply, ensuring stable and efficient distribution of power to different parts of an electronic device. A power regulator is used to adjust the power output to meet the needs of a specific application.

[0076] On the other hand, an embodiment of the present application further provides a power conversion circuit, Figure 14 This is a structural diagram of the power conversion circuit provided in an embodiment of the present application.

[0077] like Figure 14 As shown, the power conversion circuit 300 includes a circuit board 301 and the semiconductor device 10 in any of the above embodiments. The semiconductor device 10 is electrically connected to the circuit board 301. The power conversion circuit 300 can be used for current conversion, voltage conversion or power factor correction.

[0078] Exemplarily, the power conversion circuit 300 can be used as one of an AC / DC converter, an AC / AC converter, a DC / DC converter, a DC / AC inverter, or a power factor correction (PFC) circuit, wherein the AC / DC converter is used to convert alternating current (AC) into direct current (DC), the AC / AC converter is used to convert AC into AC, the DC / DC converter is used to convert DC into DC, the DC / AC inverter is used to convert DC into AC, and the power factor correction circuit is used to improve the power factor of the power supply and reduce harmonic pollution in the power grid.

[0079] On the other hand, an embodiment of the present application further provides a vehicle, Figure 15 A structural diagram of a vehicle provided in an embodiment of the present application.

[0080] like Figure 15 As shown, the vehicle 400 includes a load 401 and the power conversion circuit 300 in the above embodiment. The power conversion circuit 300 is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power, and then input it into the load 401 to power the load 401.

[0081] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in this application should be included within the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A semiconductor device, characterized in that: include: a semiconductor body, the semiconductor body being of a first conductivity type and comprising a first surface and a second surface opposite to each other, the first surface being provided with a trench, the trench extending from the first surface into the semiconductor body; a first structure located in the groove; a first barrier layer and a second barrier layer, wherein the first barrier layer is located between the first structure and the bottom and a portion of the sidewall of the trench, the second barrier layer covers a side of the first structure away from the second surface, and the second barrier layer includes a protrusion located between the first structure and the inner wall of the trench, the protrusion being in contact with the first barrier layer; a source electrode, located on the first surface; The drain is located on the second surface.

2. The semiconductor device according to claim 1, wherein The trench comprises a gate trench, and the first structure comprises a gate structure; or the trench comprises a source trench, and the first structure comprises a source trench structure.

3. The semiconductor device according to claim 1, wherein The first barrier layer includes a concave gap at a contact point with the protrusion, and the protrusion at least partially fills the gap.

4. The semiconductor device according to claim 1, wherein The first barrier layer and the second barrier layer are made of the same material, both comprising silicon oxide.

5. A method for preparing a semiconductor device, characterized in that: include: forming a trench on a semiconductor body, wherein the semiconductor body is configured to be of a first conductivity type, the semiconductor body comprises a first surface and a second surface opposite to each other, and the trench extends from the first surface into the semiconductor body; forming a first structure in the trench, and forming a first barrier layer and a second barrier layer, wherein the first barrier layer is located between the first structure and the bottom and a portion of the sidewall of the trench, and the second barrier layer covers a side of the first structure away from the second surface, and the second barrier layer includes a protrusion located between the first structure and the inner wall of the trench, and the protrusion is in contact with the first barrier layer; forming a source electrode on the first surface; A drain electrode is formed on the second surface.

6. The preparation method according to claim 5, characterized in that forming the second barrier layer, comprising: A thermal oxidation process is performed on a portion of the first structure away from the second surface to form the second barrier layer.

7. The preparation method according to claim 5, characterized in that Forming the second barrier layer comprises: The second barrier layer is formed on a side of the first barrier layer away from the second surface and a side of the first structure away from the second surface by using a deposition process.

8. A power module, characterized in that: include: At least one semiconductor device according to any one of claims 1 to 4; A substrate is used to support the semiconductor device.

9. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device according to any one of claims 1 to 4, wherein the semiconductor device is electrically connected to the circuit board.

10. A vehicle, characterized in that: include: A load and a power conversion circuit as claimed in claim 9, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

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