Cell structure of groove type SiC MOSFET device, device and electronic equipment

Abstract

The invention relates to a cell structure of a groove type SiC MOSFET device, the device and electronic equipment, and the cell structure comprises a cell main body structure which comprises a substrate and a substrate epitaxial layer; the source electrode metal structure is arranged in the top area of the cellular main body structure; the drain electrode metal structure is arranged in the bottom area of the cellular main body structure; the gate trench structure is arranged in the cellular main body structure, and the gate trench structure is filled with polycrystalline silicon; the bottom P + injection structure is arranged at the bottom of the gate trench structure; the conductive communication structure penetrates through the gate trench structure to realize electrical connection between the source metal structure and the bottom P + injection structure; the P + injection structure, the N + injection structure and the P-Body structure are arranged on the two sides of the gate trench structure, and the ohmic metal structures are arranged among the P + injection structure, the N + injection structure and the source metal structure. According to the embodiment of the invention, the gate oxide protection of the cellular structure is enhanced, and the method has the characteristics of low cost and high efficiency.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a cell structure of a trench SiC MOSFET device, a device, and an electronic device. Background Art

[0002] In recent years, SiC power devices have become an indispensable part of the new energy industry chain and have rapidly captured the market share of power devices in the fields of electric vehicles, solar power generation, wind power generation, medical equipment, etc. One of the most important components of SiC power devices is the switching element, namely the high-power MOSFET. SiC MOSFET is mainly divided into two structures, planar and trench types. The process flow of planar MOSFET is relatively simple, but the cell size is relatively large and the on-resistance is also large. The integration of trench MOSFET is nearly twice as high as that of planar type, but the device design and process are relatively complex. The present invention focuses on solving one of the most important design problems of trench MOSFET, the gate oxide protection at the bottom of the trench.

[0003] Figure 1 (a) shows a basic trench SiC MOSFET structure diagram, which does not include the gate oxide protection at the bottom of the trench. Figure 1 (b) shows the schematic diagram of P+ implantation at the bottom of the trench as gate oxide protection. Figure 1 (c) shows a schematic diagram of the electric field distribution inside silicon carbide along the center tangent of the device. The dotted line represents the case without gate oxide protection, and the solid line represents the case with P+ gate oxide protection. Figure 1 In (a), the dielectric layer (gate oxide) in the trench separates the polysilicon gate electrode (poly-Si) from the SiC. In the off state, the source electrode at the top of the device is grounded, the drain electrode at the bottom is connected to a positive high voltage, and the gate electrode gate poly is grounded. Under this bias condition, the electric field in the N-epilayer is trapezoidal, as shown in the figure below. Figure 1 As shown by the dotted line in (c), the highest point of the electric field is located at the SiC at the bottom of the trench. The excellent properties of silicon carbide material allow this electric field to be as high as 2 to 3 MV / cm. Given the difference in dielectric constants between SiC and SiO2 (εSiC = 9.7, εSiO2 = 3.9), Gauss's law causes the maximum electric field of SiO2 at the bottom of the trench to reach 2.5 times that of the adjacent SiC (i.e., 5.0 to 7.5 MV / cm), which greatly exceeds the maximum electric field that the gate oxide reliability allows (3.5 to 4.0 MV / cm). To solve this problem, a P+ implantation region can be introduced at the bottom of the trench so that the electric field can drop rapidly in the P+ region. Figure 1 As shown by the solid line in (c), the electric field in the adjacent SiO2 is reduced.

[0004] The P+ injection at the bottom of the trench theoretically solves the one-dimensional electric field problem, but in practice, the two-dimensional gathering effect of the electric field lines is more noteworthy. Specifically, because the gate oxide corner at the bottom of the trench is close to 90 degrees, the two-dimensional geometric effect makes the local electric field at the corner much higher than the electric field at the flat part of the trench bottom. Figure 1 (b)) under the shutdown condition with V ds =650V voltage, the electric field in the gate oxide layer is about 1.45MV / cm in the flat part and as high as 5.70MV / cm in the corner, which is a serious reliability risk! ( Figure 2 The middle left illustration and red curve represent the case where the P+ at the bottom of the trench is not grounded, and the right illustration and green curve represent the case where the P+ at the bottom of the trench is grounded).

[0005] by Figure 1 In the trench SiC MOSFET structure shown in (b), the P+ implanted region at the bottom of the trench will be at a floating potential if no special treatment is done. In this case, when the device is in the off state (source and gate are grounded, and the drain is at a positive high voltage), the gate oxide electric field at the bottom corner of the trench will reach 5.70 MV / cm, as shown in Figure 1. Figure 2 As shown in the left illustration and red curve, the industry consensus in SiC MOSFET design is that the gate oxide electric field strength should not exceed 3.5-4.0 MV / cm. If the P+ at the bottom of the trench is grounded, the maximum electric field in the gate oxide is only 1.70 MV / cm (a 70% decrease) under the same bias conditions. Figure 2 Shown in the right inset and green curve.

[0006] To protect the gate oxide at the bottom of the trench of trench SiC MOSFET from breakdown, the industry currently has the following designs:

[0007] The first design uses a source deep trench structure, such as Figure 3 As shown. This structure etches two deeper source trenches on both sides of the gate trench, performs high-energy P-type ion implantation inside the source trench, and forms an ohmic contact at the bottom of the trench. This design ensures that the source deep trench P region is grounded in the off state, forcing most of the electric field lines to terminate in these two P regions instead of the bottom of the trench, thereby alleviating the electric field strength at the bottom of the gate and protecting the gate oxide at the bottom of the trench. This design requires SiC trench etching with a large aspect ratio, as well as ion implantation and ohmic contact inside the deep trench, which poses great challenges to process capabilities. Due to the addition of two source trenches, the cell size will inevitably increase, with a certain sacrifice in the conduction characteristics of the device. At the same time, a JFET region is formed between the two source P regions, which will introduce additional resistance.

[0008] The second design uses an asymmetric cell structure, that is, only one of the two sidewalls of the gate trench is used to conduct current, and the SiC implanted adjacent to the other sidewall is P-type (P+), such as Figure 4 As shown. This P+ region is deeper than the trench and semi-encloses the right half of the trench. The P+ implant region on the left side of the cell has the same depth and is connected to the P-body. Both P+ regions are grounded through the top ohmic contact. This design uses P+ to ensure that the right corner of the trench is grounded. At the same time, because the bottom of the P+ on both sides is lower than the bottom of the trench on the left, the electric field is shielded, thereby protecting the bottom of the trench and the corner gate oxide layer. This design requires a large dose of high-energy P-type implant, which is a challenge for equipment and yield. In addition, half of the conduction channel is closed, which greatly sacrifices the conduction capability. At the same time, a JFET region is formed between the two P+ regions, which will introduce additional resistance.

[0009] The third design is somewhat similar to the dual source trench design, such as Figure 5 The difference is that this design uses high-energy, high-dose P-type implantation to form two deep P+ regions at the source on both sides of the gate trench. The lower ends of these two P+ regions are lower than the bottom of the gate trench, resulting in most electric field lines terminating at the P+ rather than the bottom of the trench, thus protecting the bottom of the trench. The high-energy implantation used in this design requires a mask with a large aspect ratio and high-energy, high-beam implantation equipment of at least 2MeV, and inevitably increases the size of the cell. A JFET region is also formed between the two P+ regions, which increases the on-resistance.

[0010] The above three trench SiC MOSFET structures use different methods to protect the gate oxide at the bottom of the trench, but all of them come at a considerable cost, including difficult (large aspect ratio) deep trench etching, high-dose high-energy ion implantation, challenges in cell size and complexity, and even sacrificing part of the conduction channel. Summary of the Invention

[0011] According to one aspect of the present disclosure, a cell structure of a trench SiC MOSFET device is provided, the cell structure comprising:

[0012] The main structure of the cell includes a substrate and a substrate epitaxial layer;

[0013] A source metal structure is provided in the top region of the cell main structure;

[0014] A drain metal structure is provided in the bottom area of ​​the cell main structure;

[0015] A gate trench structure is provided in the cell main body structure, wherein the gate trench structure is filled with polysilicon;

[0016] A bottom P+ implantation structure is provided at the bottom of the gate trench structure;

[0017] A conductive connection structure, penetrating the gate trench structure, to achieve electrical connection between the source metal structure and the bottom P+ implantation structure; and

[0018] A P+ injection structure, an N+ injection structure, a P-Body structure are arranged on both sides of the gate trench structure, and an ohmic metal structure is arranged between the P+ injection structure, the N+ injection structure and the source metal structure.

[0019] In a possible implementation manner, a current diffusion layer is provided under the P-Body structure.

[0020] In a possible implementation, an N-pillar structure is provided below the current diffusion layer, and a P-pillar structure is provided below the bottom P+ injection structure.

[0021] The depth of the N-pillar structure and the P-pillar structure is less than or equal to the depth between the current diffusion layer and the substrate.

[0022] In a possible implementation manner, an N-pillar structure is provided below the P-Body structure, and a P-pillar structure is provided below the bottom P+ implantation structure.

[0023] In a possible implementation manner, a dielectric layer ILD is disposed between the gate trench structure and the source metal structure.

[0024] In a possible implementation, a dielectric layer ILD is disposed between the conductive connection structure and the polysilicon in the gate trench structure.

[0025] In a possible embodiment, the doping concentration of the substrate epitaxial layer is 2.0×10 14 cm -3 ~1.5x10 16 cm -3 The doping concentration of the P-Body structure is 10 16 cm -3 ~10 18 cm -3 , the doping concentration of N+ implantation structure is 10 19 cm -3 ~10 20 cm -3 , the doping concentration of the P+ injection structure is 10 20 cm -3 ~10 21 cm -3The trench depth of the gate trench structure is 1.0 to 1.5 um.

[0026] In a possible implementation, the width of the conductive connection structure is less than or equal to 1.5 μm.

[0027] According to one aspect of the present disclosure, a trench SiC MOSFET device is provided, comprising the cell structure of the trench SiC MOSFET device.

[0028] According to one aspect of the present disclosure, an electronic device is provided, comprising the SiCMOSFET device.

[0029] The disclosed embodiments enhance gate oxide protection within the cell structure of trench SiC MOSFET devices by forming a bottom P+ implant structure at the bottom of the gate polysilicon and then opening a hole with conductive material to connect the bottom P+ implant structure to the source metal structure. Furthermore, this approach eliminates the need for complex (high aspect ratio) deep trench etching, high-dose high-energy ion implantation, or a significant increase in cell size and complexity, resulting in low cost and high efficiency.

[0030] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, rather than limiting the present disclosure. Other features and aspects of the present disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings herein are incorporated into and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and, together with the specification, are used to explain the technical solutions of the present disclosure.

[0032] Figure 1 A schematic diagram of a trench SiC MOSFET structure according to an embodiment of the present disclosure is shown.

[0033] Figure 2 A schematic diagram of the electric field distribution of a trench-type 650V SiC MOSFET according to an embodiment of the present disclosure is shown.

[0034] Figure 3 FIG. 1 is a schematic diagram showing a related art SiC trench MOSFET using a source trench to protect the gate oxide at the bottom of the trench.

[0035] Figure 4 A schematic diagram of the structure of a SiC trench MOSFET in the related art using a P+ deep implantation semi-encircling structure to protect the gate oxide at the bottom of the trench is shown.

[0036] Figure 5A schematic diagram of the structure of a SiC trench MOSFET using deep source P+ implantation on both sides to protect the gate oxide at the bottom of the trench is shown in the related art.

[0037] Figure 6 A schematic diagram of a cell structure of a trench SiC MOSFET device according to an embodiment of the present disclosure is shown.

[0038] Figure 7 A schematic diagram of a cell structure of a trench SiC MOSFET device according to an embodiment of the present disclosure is shown.

[0039] Figure 8 A schematic diagram of a cell structure of a trench SiC MOSFET device according to an embodiment of the present disclosure is shown.

[0040] Figure 9 A schematic diagram of a cell structure of a trench SiC MOSFET device according to an embodiment of the present disclosure is shown.

[0041] Figure 10 、 Figure 11 A schematic diagram showing a cell structure of a trench SiC MOSFET device according to an embodiment of the present disclosure is shown.

[0042] Figure 12 A schematic diagram of a cell structure of a trench SiC MOSFET device according to an embodiment of the present disclosure is shown.

[0043] Figure 13 Schematic diagrams of simulations of a trench SiC MOSFET of the related art and a trench SiC MOSFET of an embodiment of the present disclosure are shown. DETAILED DESCRIPTION

[0044] Various exemplary embodiments, features, and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise indicated.

[0045] In the description of the present disclosure, it should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0046] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the present disclosure, "plurality" means two or more, unless otherwise specifically defined.

[0047] In this disclosure, unless otherwise expressly specified or limited, terms such as "mounted," "connected," "connect," and "fixed" should be understood broadly. For example, they may refer to fixed connections, detachable connections, or integration; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and internal connections between two components or interactions between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure based on specific circumstances.

[0048] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0049] The term "and / or" herein simply describes an association relationship between associated objects, indicating that three relationships can exist. For example, "A and / or B" can represent the existence of three situations: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" herein refers to any combination of at least two of any one or more of a plurality of items. For example, "at least one of A, B, and C" can represent any one or more elements selected from the set consisting of A, B, and C.

[0050] In addition, numerous specific details are provided in the following detailed description to better illustrate the present disclosure. Those skilled in the art will appreciate that the present disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art are not described in detail in order to highlight the main points of the present disclosure.

[0051] In view of the defects of the various technical solutions mentioned above, the embodiments of the present disclosure propose a new cellular structure of a trench SiC MOSFET device, which strengthens the gate oxide protection of the cellular structure of the trench SiC MOSFET device. By forming a bottom P+ injection structure at the bottom of the gate polysilicon and opening a hole to connect the bottom P+ injection structure with the source metal structure using a conductive material, it does not require high-difficulty (large aspect ratio) deep trench etching, does not require high-dose high-energy ion implantation, and does not require a significant increase in the cell size and complexity, and has the characteristics of low cost and high efficiency.

[0052] See also Figure 6 , Figure 6 A schematic diagram of a cell structure of a trench SiC MOSFET device according to an embodiment of the present disclosure is shown.

[0053] like Figure 6 As shown, the cellular structure includes:

[0054] The main cell structure 100 includes a substrate (N+substrate) and a substrate epitaxial layer (N-epilayer);

[0055] A source metal structure 110 is provided in the top region of the cell main structure 100;

[0056] The drain metal structure 120 is provided at the bottom area of ​​the cell main structure 100;

[0057] A gate trench structure 130 is provided in the cell main structure 100 , and the gate trench structure 130 is filled with polysilicon (Poly-Si);

[0058] A bottom P+ implantation structure 140 is provided at the bottom of the gate trench structure 130 ;

[0059] A conductive connection structure 150 passes through the gate trench structure 130 to achieve electrical connection between the source metal structure 110 and the bottom P+ implantation structure 140; and

[0060] The P+ implant structure 160 , the N+ implant structure 170 , the P-Body structure 180 are disposed on both sides of the gate trench structure 130 , and an ohmic metal structure (OMC) is disposed between the P+ implant structure 160 , the N+ implant structure 170 and the source metal structure 110 .

[0061] The disclosed embodiment connects the bottom P+ injection structure 140 at the bottom of the gate trench structure 130 to the source metal structure 110 through a conductive connection structure 150, significantly reducing the gate oxide electric field strength at the bottom and corners of the trench, extending the device life, and ensuring long-term reliability.

[0062] Furthermore, the disclosed embodiment forms the conductive connection structure 150 by opening a hole in the gate trench structure 130, without significantly increasing the cell size, thus minimally impacting the conduction characteristics. The process does not require high-energy or high-dose ion implantation at megaelectron volts, deep trench etching at silicon carbide, or sacrifice the number of conductive channels.

[0063] The embodiment of the present disclosure does not limit the types of the substrate, substrate epitaxial layer, etc. in the cell main structure 100, and the positions of the P+ injection structure 160 and the N+ injection structure 170. Those skilled in the art can determine them according to the type of the trench SiC MOSFET device. For example, if the trench SiC MOSFET device is an N-channel MOSFET, the substrate can be an N-type substrate, the substrate epitaxial layer can be an N-type epitaxial layer, and the positions of the P+ injection structure 160 and the N+ injection structure 170 of the N-channel MOSFET are as follows: Figure 6 As shown (the N+ implantation structure 170 is close to the gate trench structure 130). Accordingly, if the trench SiCMOSFET device is a P-channel MOSFET, the substrate can be a P-type substrate, the substrate epitaxial layer can be a P-type epitaxial layer, the implantation structure 160 is changed to N+ doping, and the implantation structure 170 is changed to P+ doping.

[0064] The present disclosure does not limit the specific values ​​of the doping concentration of the substrate epitaxial layer, the doping concentration of the P-Body structure 180, the doping concentration of the N+ injection structure 170, and the doping concentration of the P+ injection structure 160. Those skilled in the art can set them according to actual conditions and needs. For example, in one possible embodiment, the doping concentration of the substrate epitaxial layer is 2.0x10 14 cm -3 ~1.5x10 16 cm -3 The doping concentration of the P-Body structure 180 is 10 16 cm -3 ~10 18 cm -3 , the doping concentration of N+ implantation structure 170 is 10 19 cm -3 ~10 20 cm -3 , the doping concentration of the P+ implantation structure 160 is 10 20 cm -3 ~10 21 cm -3 .

[0065] The embodiment of the present disclosure does not limit the trench depth of the gate trench structure 130 . For example, in one possible implementation, the trench depth of the gate trench structure 130 is 1.0 to 1.5 μm, for example, 1.5 μm.

[0066] The embodiment of the present disclosure does not limit the shape and size of the conductive interconnection structure 150, nor does it limit the specific type of conductive material of the conductive interconnection structure 150. For example, in one possible embodiment, the conductive interconnection structure 150 can be a rectangular parallelepiped or a structure similar to a rectangular parallelepiped. The length, width, and height of the rectangular parallelepiped can be adaptively set. For example, the width of the conductive interconnection structure 150 (the width between the two Poly-Si layers) can be less than or equal to 1.5μm, and the height of the conductive interconnection structure 150 can be, for example, the trench depth of the gate trench structure 130. The length of the conductive interconnection structure 150 can be set as needed, wherein the conductive material can be metal. Preferably, in the embodiment of the present disclosure, the width of the conductive interconnection structure 150 is less than or equal to 1μm; more preferably, in the embodiment of the present disclosure, the width of the conductive interconnection structure 150 is 0.5μm.

[0067] The embodiments of the present disclosure do not limit the specific process for forming the cell structure of the trench SiC MOSFET device. Those skilled in the art may adopt a suitable process according to actual conditions and needs.

[0068] The present embodiment of the present disclosure does not limit the metal material of the Ohmic Metal Structure (OMC) between the N+ implant structure 170 and the source metal structure 110. Those skilled in the art may configure the structure based on actual circumstances and needs. In one example, the present embodiment of the present disclosure may form a conductive channel (e.g., a rectangular or rectangular-like slot-shaped hole) in the center of the gate trench structure (or, if covered by a dielectric layer ILD, from a corresponding position in the dielectric layer ILD) that passes through the gate polysilicon (poly-Si) oxide (and the dielectric layer ILD, if present) and directly connects to the P+ region at the bottom of the trench. An ohmic contact is then formed at the bottom of the trench to the P+ region. Finally, the conductive channel is filled with a conductive material (e.g., metal) and connected to the source metal structure 110 at the top. Before metal filling (filling the conductive channel with a conductive material and connecting it to the source metal structure 110 at the top), the poly-Si may be oxidized to prevent short circuits between the source and gate. This design ensures that the P+ region at the bottom of each cell trench is directly grounded to the source, thereby achieving maximum gate oxide protection.

[0069] The embodiment of the present disclosure can achieve low-resistance electrical connection between the upper metal layer (source metal structure 110) and the lower semiconductor region (P+ injection structure 160, N+ injection structure 170) through the ohmic metal structure, ensuring smooth transmission of current between different layers, improving the overall electrical performance of the device, and reducing power loss caused by contact resistance.

[0070] Of course, the cell structure of the trench SiC MOSFET device of the embodiment of the present disclosure may also include other structures, which are not limited to the embodiment of the present disclosure. Those skilled in the art may configure the structure according to actual conditions and needs, which is exemplarily introduced below.

[0071] See also Figure 7 , Figure 7 A schematic diagram of a cell structure of a trench SiC MOSFET device according to an embodiment of the present disclosure is shown.

[0072] In one possible implementation, Figure 7 As shown, a dielectric layer (ILD) is provided between the gate trench structure 130 and the source metal structure 110. In the disclosed embodiment, the dielectric layer ILD is provided between the gate trench structure 130 and the source metal structure 110 to provide insulation, isolate different conductive layers, and ensure the stability of the internal electrical performance of the device.

[0073] See also Figure 8 , Figure 8 A schematic diagram of a cell structure of a trench SiC MOSFET device according to an embodiment of the present disclosure is shown.

[0074] In one possible implementation, Figure 8 As shown, in the embodiment of the present disclosure, a current spreading layer (CSL) may be provided below the P-Body structure 180 .

[0075] The embodiments of the present disclosure do not limit the specific method for forming the current diffusion layer CSL, and those skilled in the art may configure the method according to actual conditions and needs. For example, the current diffusion layer CSL may be a highly doped N-type conductive layer.

[0076] By providing a current diffusion layer (CSL) beneath the P-Body structure 180, the disclosed embodiments can reduce resistance, allowing current to spread more evenly within the device, reducing energy losses during internal device transmission, improving current conduction efficiency, and reducing hot spots caused by excessive local current density, thereby enhancing device operational stability and reliability. Furthermore, the current diffusion layer of the disclosed embodiments can increase the device's forward current conduction capability. The higher the doping concentration and the deeper the injection region, the more pronounced the current diffusion effect during conduction, effectively improving the device's current-carrying capacity.

[0077] See also Figure 9 , Figure 9 A schematic diagram of a cell structure of a trench SiC MOSFET device according to an embodiment of the present disclosure is shown.

[0078] In one possible implementation, Figure 9 As shown, an N-pillar structure is provided below the P-Body structure 180 , and a P-pillar structure is provided below the bottom P+ implant structure 140 .

[0079] The disclosed embodiment of the present invention provides an N-pillar structure below the P-Body structure 180 and a P-pillar structure below the bottom P+ injection structure 140, forming a superjunction-like structure with the surrounding P-type and N-type regions. This promotes lateral expansion of the depletion region when subjected to reverse voltage, making the vertical distribution of the electric field more uniform, avoiding local electric field concentration, improving the device's breakdown voltage and withstand voltage, and reducing the risk of device damage caused by excessive local electric fields. During forward conduction, the N-pillar doping concentration can be increased several times, reducing current crowding and ensuring smoother current conduction, which helps reduce on-resistance and improve the device's conductivity.

[0080] See also Figure 10 、 Figure 11 , Figure 10 、 Figure 11 A schematic diagram showing a cell structure of a trench SiC MOSFET device according to an embodiment of the present disclosure is shown.

[0081] In one possible implementation, Figure 10 、 Figure 11 As shown, in the embodiment of the present disclosure, an N-pillar structure may be provided below the current diffusion layer, and a P-pillar structure may be provided below the bottom P+ injection structure 140.

[0082] The depth of the N-pillar structure and the P-pillar structure is less than or equal to the depth between the current diffusion layer and the substrate.

[0083] For example, the N-pillar and P-pillar structures are typically highly doped regions that further reduce the resistance of the current conduction path. They work in conjunction with the current diffusion layer (CSL) to optimize current distribution, ensuring even current diffusion over a wider area, reducing the problem of excessive local current density, and improving the device's high-current carrying capacity. For example, the N-pillar can influence the storage and release of carriers, improving the device's switching speed and switching losses. Furthermore, during long-term operation, by uniformly distributing current and heat, it enhances the device's thermal stability and reliability, reducing performance degradation caused by heat accumulation or current concentration.

[0084] The presently disclosed embodiments do not limit the depth of the N-pillar and P-pillar structures. Those skilled in the art can adjust the depth based on practical needs. The maximum depth can be the depth between the current diffusion layer and the substrate. Increasing the depth of the N-pillar and P-pillar structures in the presently disclosed embodiments improves the current-carrying capacity of the cell structure of the trench SiC MOSFET device.

[0085] See also Figure 12 , Figure 12 A schematic diagram of a cell structure of a trench SiC MOSFET device according to an embodiment of the present disclosure is shown.

[0086] In one possible implementation, Figure 12 As shown, a dielectric layer ILD is provided between the conductive connection structure 150 and the polysilicon in the gate trench structure 130 .

[0087] The embodiment of the present disclosure utilizes the polysilicon and conductive interconnect structure in the dielectric layer ILD isolation gate trench structure 130 to ensure the stability of the internal electrical performance of the device.

[0088] Of course, the embodiment of the present disclosure does not limit the thickness of the dielectric layer ILD between the conductive connection structure 150 and the polysilicon in the gate trench structure 130, nor does it limit the specific formation method thereof. Those skilled in the art can adopt appropriate processes according to actual conditions and needs.

[0089] The above describes various possible implementation methods of the cell of the trench SiC MOSFET. It should be understood that the introduction of each structure above should not be regarded as an exhaustive list of the cell structure of the trench SiC MOSFET. In other embodiments, the cell structure of the trench SiC MOSFET can also be changed according to actual conditions and needs. The embodiment of the present disclosure is applicable to the cell structure of various types of trench SiC MOSFET. A conductive connection structure is set in the gate trench structure in the form of an opening, and the P+ region set under the gate trench structure is electrically connected to the source metal structure to achieve gate oxide protection at the bottom of the trench SiC MOSFET and improve the reliability of the gate oxide at the bottom of the trench. There is no need to lose the number of channels, basically no increase in the cell size, no need for mega-electron-volt high-energy injection, and no need for deep trench etching. Each cell in the embodiment of the present disclosure can be directly grounded individually to ensure the dynamic characteristics of the device under high-frequency conditions.

[0090] See also Figure 13 , Figure 13 Schematic diagrams of simulations of a trench SiC MOSFET of the related art and a trench SiC MOSFET of an embodiment of the present disclosure are shown.

[0091] like Figure 13 The middle left figure is a simulation diagram of a related art trench SiC MOSFET, in which the bottom P+ region is not grounded. Figure 13 The middle right figure is a simulation diagram of a trench SiC MOSFET according to an embodiment of the present disclosure. The bottom P+ injection structure 140 is electrically connected to the source metal structure 110 via the conductive connection structure 150, so that the bottom P+ injection structure 140 can be directly grounded.

[0092] like Figure 13 As shown, the electric field distribution in trench SiC MOSFETs of related art may be uneven, which can easily lead to localized electric field concentration, affecting the device's withstand voltage performance, reducing breakdown voltage, and potentially affecting long-term operational reliability. Furthermore, the current distribution is not optimized, resulting in current crowding, which increases on-resistance, increases conduction losses, and reduces efficiency.

[0093] like Figure 13 As shown, in the trench SiC MOSFET of the embodiment of the present disclosure, after the P+ structure at the bottom of the trench is grounded through the W-plug, the electric field distribution can be effectively improved, making the electric field more uniform, improving the breakdown voltage and withstand voltage capability of the device, enhancing reliability, optimizing the carrier movement path, reducing current crowding, reducing on-resistance, improving conduction efficiency, reducing conduction loss, and improving switching characteristics. The more uniform electric field and current distribution helps to accelerate switching speed, reduce switching loss, and is beneficial to high-frequency applications.

[0094] According to one aspect of the present disclosure, a trench SiC MOSFET device is provided, comprising the cell structure of the trench SiC MOSFET device.

[0095] According to one aspect of the present disclosure, an electronic device is provided, comprising the SiCMOSFET device.

[0096] While various embodiments of the present disclosure have been described above, the above descriptions are illustrative, non-exhaustive, and not intended to be limiting of the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, their practical applications, or improvements to existing technologies, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A cell structure of a trench SiC MOSFET device, characterized in that: The cellular structure comprises: The main structure of the cell includes a substrate and a substrate epitaxial layer; A source metal structure is provided in the top region of the cell main structure; A drain metal structure is provided in the bottom area of ​​the cell main structure; A gate trench structure is provided in the cell main body structure, wherein the gate trench structure is filled with polysilicon; A bottom P+ implantation structure is provided at the bottom of the gate trench structure; A conductive connection structure, penetrating the gate trench structure, to achieve electrical connection between the source metal structure and the bottom P+ implantation structure; and A P+ injection structure, an N+ injection structure, a P-Body structure are arranged on both sides of the gate trench structure, and an ohmic metal structure is arranged between the P+ injection structure, the N+ injection structure and the source metal structure.

2. The cellular structure according to claim 1, characterized in that A current diffusion layer is provided below the P-Body structure.

3. The cellular structure according to claim 2, characterized in that An N-pillar structure is provided below the current diffusion layer, and a P-pillar structure is provided below the bottom P+ injection structure. The depth of the N-pillar structure and the P-pillar structure is less than or equal to the depth between the current diffusion layer and the substrate.

4. The cellular structure according to claim 1, characterized in that An N-pillar structure is provided below the P-Body structure, and a P-pillar structure is provided below the bottom P+ implantation structure.

5. The cellular structure according to any one of claims 1 to 4, characterized in that A dielectric layer ILD is disposed between the gate trench structure and the source metal structure.

6. The cellular structure according to claim 5, characterized in that A dielectric layer ILD is provided between the conductive connection structure and the polysilicon in the gate trench structure.

7. The cellular structure according to claim 1, characterized in that The doping concentration of the substrate epitaxial layer is 2.0x10 14 cm -3 ~1.5x10 16 cm -3 , the doping concentration of the P-Body structure is 10 16 cm -3 ~10 18 cm -3 , the doping concentration of N+ implantation structure is 10 19 cm -3 ~10 20 cm -3 , the doping concentration of the P+ injection structure is 10 20 cm -3 ~10 21 cm -3 The trench depth of the gate trench structure is 1.0 to 1.5 um.

8. The cellular structure according to claim 1, characterized in that The width of the conductive connection structure is less than or equal to 1.5 μm.

9. A trench SiC MOSFET device, characterized in that: The trench SiC MOSFET device comprises the cell structure of the trench SiC MOSFET device according to any one of claims 1 to 8.

10. An electronic device, characterized in that: The electronic device includes the SiC MOSFET device according to claim 9.

Images