Separation gate trench MOSFET structure and preparation method thereof

Abstract

The invention provides a separation gate trench MOSFET structure and a preparation method thereof, and relates to the technical field of semiconductors, and the preparation method comprises the steps: selecting an N + type silicon substrate, sequentially depositing a first N-type epitaxial layer and a second N-type epitaxial layer on the N + type silicon substrate, forming an injection window by adopting photoetching and etching processes, and injecting P-type doping to form a P-type doping region in the second epitaxial layer; a third N-type epitaxial layer is deposited, and the P-type doped region, the first N-type epitaxial layer, the second N-type epitaxial layer and the third N-type epitaxial layer form a floating junction structure for bearing high electric field intensity; taking the first N-type epitaxial layer, the second N-type epitaxial layer and the third N-type epitaxial layer as an N-type drift region, and carrying out photoetching and etching processes on the N-type drift region to form a groove structure; on the basis of the trench structure, the preparation of the separated gate trench MOSFET structure is completed, and on the premise of not increasing the thickness of the oxide layer at the bottom of the trench, the size of the device is reduced and the on-resistance of the chip is reduced through the floating junction structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a separated-gate trench MOSFET structure and a preparation method thereof. Background Art

[0002] Power field-effect transistors (MOSFETs) are widely used in power systems requiring high efficiency due to their high input impedance, low switching power consumption, and high switching speed. The split-gate trench MOSFET (SGT MOS) is a trench-gate MOSFET (Trench MOS) with a split-gate structure connected to the source. By optimizing the electric field distribution in the drift region, the MOS device achieves both high breakdown voltage and low on-resistance.

[0003] Currently, by introducing a three-layer epitaxial structure and an electric field spike in the drift region of an SGT MOSFET, the device's breakdown voltage can be increased without increasing on-resistance. However, since the electric field spike introduced by the low-resistivity middle epitaxial layer in the three-layer epitaxial structure can also cause the outermost trench of the terminal structure to experience voltage breakdown due to the electric field strength exceeding the maximum breakdown field strength in the middle low-resistivity layer. Therefore, it is necessary to increase the thickness of the trench bottom oxide layer to reduce the excessive electric field strength and avoid a decrease in the maximum off-state voltage of the MOS device due to the low withstand voltage of the terminal structure.

[0004] However, a thicker trench bottom oxide layer not only increases the unit cell size of the SGT MOSFET device, but also requires a larger terminal structure size to withstand the lateral voltage at the chip edge due to the reduction of the electric field strength in the low-resistivity layer area in the middle of the terminal structure trench, resulting in a larger chip area or increased on-resistance. Summary of the Invention

[0005] The present invention provides a split-gate trench MOSFET structure and a preparation method thereof, which are used to solve the defect in the prior art that the trench bottom oxide layer reduces the high electric field strength by increasing the thickness, resulting in an increase in device size and chip on-resistance.

[0006] In a first aspect, the present invention provides a split-gate trench MOSFET structure, comprising:

[0007] substrate;

[0008] a first N-type epitaxial layer and a second N-type epitaxial layer sequentially deposited on the substrate;

[0009] a P-type doped region, wherein the P-type doped region is formed on the second N-type epitaxial layer;

[0010] a third N-type epitaxial layer, the third N-type epitaxial layer being deposited on the second N-type epitaxial layer forming the P-type doping region;

[0011] A floating junction structure, wherein the floating junction structure is composed of the P-type doped region, the first N-type epitaxial layer, the second N-type epitaxial layer, and the third N-type epitaxial layer; a space charge region formed by the P-type impurity doped region and the second N-type epitaxial layer in the floating junction structure is used to withstand high electric field strength;

[0012] a trench structure formed on an N-type drift region composed of the first N-type epitaxial layer, the second N-type epitaxial layer, and the third N-type epitaxial layer;

[0013] The peripheral structure is used to integrate the substrate, the first N-type epitaxial layer, the second N-type epitaxial layer, the P-type doped region, the third N-type epitaxial layer, the floating junction structure and the trench structure into one.

[0014] According to a split-gate trench MOSFET structure provided by the present invention, the trench structure includes a plurality of active region trenches and a plurality of terminal region trenches;

[0015] A center line of each of the termination region trenches coincides with a center line of the corresponding floating junction structure, and the floating junction structure surrounds a portion of the termination region trench located in the second N-type epitaxial layer.

[0016] According to a split-gate trench MOSFET structure provided by the present invention, the peripheral structure includes:

[0017] A bottom oxide layer, an active area polycrystalline structure, and a terminal area polycrystalline structure are sequentially formed in the active area trench and the terminal area trench;

[0018] an intermediate oxide layer formed on the active area polycrystalline structure;

[0019] Gate polysilicon is formed on the active area trench;

[0020] a shielding oxide layer formed on the gate polysilicon;

[0021] The front metal electrode is formed on the wafer in the N+ source region;

[0022] A back metal electrode is formed on the lower surface of the substrate.

[0023] In a second aspect, the present invention provides a method for preparing a split-gate trench MOSFET, comprising:

[0024] Selecting an N+ type silicon substrate, and sequentially depositing a first N-type epitaxial layer and a second N-type epitaxial layer on the N+ type silicon substrate, wherein the resistivity of the first N-type epitaxial layer is greater than the resistivity of the second N-type epitaxial layer;

[0025] forming an implantation window on the second N-type epitaxial layer by photolithography and etching processes, and implanting P-type dopants through the implantation window to form a P-type doped region in the second epitaxial layer;

[0026] Depositing a third N-type epitaxial layer on the second N-type epitaxial layer forming the P-type doped region, wherein the P-type doped region forms a floating junction structure with the first N-type epitaxial layer, the second N-type epitaxial layer, and the third N-type epitaxial layer; the resistivity of the third N-type epitaxial layer is greater than the resistivity of the second N-type epitaxial layer; using the first N-type epitaxial layer, the second N-type epitaxial layer, and the third N-type epitaxial layer as an N-type drift region, performing photolithography and etching processes on the N-type drift region to form a trench structure;

[0027] The trench structure includes a plurality of active area trenches and a plurality of terminal area trenches;

[0028] The center line of each of the terminal region trenches coincides with the center line of the corresponding floating junction structure, and the floating junction structure surrounds the portion of the terminal region trench located in the second N-type epitaxial layer; the space charge region formed by the P-type impurity doped region in the floating junction structure and the second N-type epitaxial layer is used to withstand high electric field strength;

[0029] Based on the trench structure, the preparation of the split-gate trench MOSFET structure is completed.

[0030] According to a method for preparing a split-gate trench MOSFET provided by the present invention, the method for preparing the split-gate trench MOSFET structure based on the trench structure includes:

[0031] forming a bottom oxide layer, an active area polycrystalline structure and a terminal area polycrystalline structure in the active area trench and the terminal area trench in sequence;

[0032] forming an intermediate oxide layer on the active area polycrystalline structure;

[0033] forming a gate polycrystalline structure and a shielding oxide layer in the active area trench;

[0034] Performing global P-base implantation on the silicon surface to form an N+ type source region;

[0035] forming a front metal electrode on the wafer forming the N+ type source region;

[0036] A back metal electrode is formed on the lower surface of the silicon substrate to complete the preparation of the separated gate trench MOSFET structure.

[0037] According to a method for preparing a split-gate trench MOSFET provided by the present invention, the method sequentially forming a bottom oxide layer, an active area polycrystalline structure, and a terminal area polycrystalline structure in the active area trench and the terminal area trench comprises:

[0038] forming a bottom oxide layer in the active area trench and the terminal area trench by sequentially performing thermal growth and deposition processes;

[0039] Polysilicon is deposited on the surface of the wafer where the bottom oxide layer is formed to fill the trench structure, and the polysilicon in the trench structure is subjected to photolithography and etching processes to form an active area polycrystalline structure and a terminal area polycrystalline structure respectively.

[0040] According to a method for preparing a split-gate trench MOSFET provided by the present invention, forming an intermediate oxide layer on the active area polycrystalline structure includes:

[0041] The trench structure is filled again by using an oxide layer deposition process to remove excess oxide layer on the silicon surface, and the deposited oxide layer in the active area trench is photolithography and etching processes are used to form an intermediate oxide layer on the active area polycrystalline structure.

[0042] According to a method for preparing a split-gate trench MOSFET provided by the present invention, forming a gate polycrystalline structure and a shielding oxide layer in the active area trench includes:

[0043] thermally growing an oxide layer on the sidewalls of the active area trench using a dry oxygen oxidation process to form a gate oxide layer structure;

[0044] Filling the active area trench by a polysilicon deposition process to form a gate polycrystalline structure;

[0045] A dry oxygen oxidation process is performed to form a shielding oxide layer on top of the gate polycrystalline structure.

[0046] According to a method for preparing a split-gate trench MOSFET provided by the present invention, the method of performing a global P-base implantation on a silicon surface to form an N+ type source region comprises:

[0047] Perform P-base global implantation on the silicon surface. After the ion implantation of the P-base region is completed, the base region implantation is annealed.

[0048] An N+ type source region arsenic ion implantation is performed on the active region, and annealing is performed after the source region arsenic ion implantation is completed to form an N+ type source region.

[0049] According to a method for preparing a split-gate trench MOSFET provided by the present invention, forming a front metal electrode on a wafer forming the N+ type source region comprises:

[0050] Depositing a dielectric oxide layer on the wafer forming the N+ type source region, and forming a metal electrode contact hole on the dielectric oxide layer by a photolithography process;

[0051] Performing a BF2 injection process on the source electrode contact region through the metal electrode contact hole, and performing annealing after the injection;

[0052] A metal layer is deposited on the upper surface of the wafer where the metal electrode contact hole is formed, and a front metal electrode is formed through photolithography and etching processes.

[0053] According to a method for preparing a split-gate trench MOSFET provided by the present invention, forming a back metal electrode on the lower surface of a silicon substrate comprises:

[0054] A passivation layer is deposited on the electrode structure, and a passivation structure is formed through photolithography and etching processes; a Ti / Ni / Ag metal layer is evaporated on the lower surface of the silicon substrate to form a back metal electrode, completing the preparation of the separated gate trench MOSFET structure.

[0055] The present invention provides a split-gate trench MOSFET structure and a preparation method thereof. A floating junction structure is formed in a local region of a second N-type epitaxial layer; a trench structure is then formed in an N-type drift region. When the terminal structure is subjected to a blocking voltage, a space charge region formed by a P-type impurity-doped region and the second N-type epitaxial layer is subjected to a high electric field strength. This prevents an oxide layer at the bottom of the terminal trench from being subjected to an excessively high electric field strength in the second N-type epitaxial layer, causing breakdown. This allows the device to withstand a higher blocking voltage, eliminates the need to increase the thickness of the oxide layer at the bottom of the trench, and guarantees the size of the MOS cell. This effectively reduces the on-resistance and chip area of ​​the device, thereby achieving lower conduction and switching losses. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] In order to more clearly illustrate the technical solutions in the present invention or the prior art, a brief introduction is given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0057] Figure 1 This is one of the partial structural diagrams of the split-gate trench MOSFET provided in this embodiment;

[0058] Figure 2 This is the second schematic diagram of the partial structure of the split-gate trench MOSFET provided in this embodiment;

[0059] Figure 3 This is the third schematic diagram of the partial structure of the split-gate trench MOSFET provided in this embodiment;

[0060] Figure 4 This is the fourth schematic diagram of the partial structure of the split-gate trench MOSFET provided in this embodiment;

[0061] Figure 5 This is the fifth partial structural diagram of the split-gate trench MOSFET provided in this embodiment;

[0062] Figure 6 This is the sixth schematic diagram of the partial structure of the split-gate trench MOSFET provided in this embodiment;

[0063] Figure 7 This is the seventh schematic diagram of the partial structure of the split-gate trench MOSFET provided in this embodiment;

[0064] Figure 8 This is the eighth partial structural diagram of the split-gate trench MOSFET provided in this embodiment;

[0065] Figure 9 This is the ninth partial structural diagram of the split-gate trench MOSFET provided in this embodiment;

[0066] Figure 10 This is the tenth schematic diagram of the partial structure of the split-gate trench MOSFET provided in this embodiment;

[0067] Figure 11 This is the eleventh partial structural diagram of the split-gate trench MOSFET provided in this embodiment;

[0068] Figure 12 It is a complete schematic diagram of the local structure of the split-gate trench MOSFET provided in this embodiment.

[0069] Reference numerals:

[0070] 1-substrate, 2-first N-type epitaxial layer, 3-second N-type epitaxial layer, 41-P-type doped region, 42-floating junction structure, 5-third N-type epitaxial layer, 61-active area trench, 62-terminal area trench, 7-bottom oxide layer, 8-active area polycrystalline structure, 9-terminal area polycrystalline structure, 10-intermediate oxide layer, 11-gate oxide layer, 12-gate polysilicon, 13-shielding oxide layer, 14-base region, 15-source region, 16-front metal electrode, 17, passivation structure, 18-back metal electrode. DETAILED DESCRIPTION

[0071] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0072] like Figure 12 As shown, an embodiment of the present invention provides a split-gate trench MOSFET structure, comprising:

[0073] Substrate 1;

[0074] A first N-type epitaxial layer 2 and a second N-type epitaxial layer 3 sequentially deposited on a substrate;

[0075] A P-type doped region 41, formed on the second N-type epitaxial layer 3;

[0076] A third N-type epitaxial layer 5, the third N-type epitaxial layer being deposited on the second N-type epitaxial layer forming the P-type doping region;

[0077] A floating junction structure 42, which is composed of a P-type doped region 41, a first N-type epitaxial layer 2, a second N-type epitaxial layer 3 and a third N-type epitaxial layer 5;

[0078] A trench structure is formed on an N-type drift region formed by a first N-type epitaxial layer 2, a second N-type epitaxial layer 3, and a third N-type epitaxial layer 5. The trench structure includes a plurality of active region trenches 61 and a plurality of terminal region trenches 62. The centerline of each terminal region trench 62 coincides with the centerline of the corresponding floating junction structure 42, and the floating junction structure 42 surrounds the portion of the terminal region trench 62 located in the second N-type epitaxial layer 3. The space charge region formed by the P-type impurity doped region 41 in the floating junction structure 42 and the second N-type epitaxial layer 3 is configured to withstand high electric field strength.

[0079] A bottom oxide layer 7, an active region polycrystalline structure 8, and a terminal region polycrystalline structure 9 are sequentially formed in the active region trench 61 and the terminal region trench 62;

[0080] An intermediate oxide layer 10 is formed on the active area polycrystalline structure;

[0081] Gate polysilicon 12, formed on the active area trench;

[0082] A shielding oxide layer 13 is formed on the gate polysilicon;

[0083] A front metal electrode 16 is formed on the wafer in the N+ type source region;

[0084] The back metal electrode 17 is formed on the bottom surface of the substrate.

[0085] In the split-gate trench MOSFET structure of this embodiment, the floating junction structure is located in the second low-resistivity N-type epitaxial layer in the middle of the three-layer epitaxial structure. The geometric centerline of the trench etching pattern of the terminal structure is aligned with the geometric centerline of the P-type doped impurity region locally implanted in the second N-type epitaxial layer, so that the area in the middle of the terminal trench that originally contacted the middle low-resistivity epitaxial layer is surrounded by the P-type doped impurity region and has symmetrical dimensions on the left and right.

[0086] When the MOS device is in the off state and subjected to a high drain-source voltage, the space charge region formed by the P-type impurity-doped region and the second low-resistivity epitaxial layer is subjected to a high electric field strength, thereby preventing the oxide layer at the bottom of the terminal structure trench from being subjected to an excessively high electric field strength in the second low-resistivity epitaxial layer and causing breakdown. This enables the terminal structure trench of the MOS device to withstand a higher blocking voltage at the same oxide layer thickness, reducing the size of the MOS cell, thereby reducing the chip area or achieving a lower on-resistance at the same chip area.

[0087] At the same time, since the introduction of the P-type floating junction structure expands the electric field distribution of the space charge region between the terminal trenches, the voltage resistance of the MOS device can be met at a smaller terminal structure size, reducing the chip area occupied by the terminal structure, thereby reducing the chip area or achieving lower on-resistance at the same chip area.

[0088] Based on the same general inventive concept, an embodiment of the present invention provides a method for preparing the split-gate trench MOSFET structure of the above embodiment, which mainly includes the following steps:

[0089] 101. Figure 1 As shown. An N+ silicon substrate 1 is selected, and a first N-type epitaxial layer 2 and a second N-type epitaxial layer 3 are sequentially deposited on the N+ silicon substrate 1, wherein the first N-type epitaxial layer has a higher resistivity and the second N-type epitaxial layer has a lower resistivity. The resistivity of the first N-type epitaxial layer 2 is greater than the resistivity of the second N-type epitaxial layer 3.

[0090] 102. Figure 2 On the second N-type epitaxial layer 3 with a relatively low resistivity, an implantation window is formed by photolithography and etching, and P-type dopants are implanted through the implantation window to form a P-type doped region 41 in the second epitaxial layer 3 .

[0091] 103. Figure 3 As shown. On the second N-type epitaxial layer 3 partially implanted with a P-type doped region, a third N-type epitaxial layer 5 with an intermediate resistivity value is continuously deposited. The P-type doped region 41 forms a floating junction structure 42 with the first N-type epitaxial layer 2, the second N-type epitaxial layer 3, and the third N-type epitaxial layer 5. The resistivity of the third N-type epitaxial layer is greater than that of the second N-type epitaxial layer.

[0092] By introducing a three-layer epitaxial layer structure with different resistivities and introducing an electric field spike in the drift region of the SGT MOS, the breakdown voltage of the device can be improved without increasing the on-resistance.

[0093] 104. Figure 4 As shown in the figure, the first N-type epitaxial layer 2, the second N-type epitaxial layer 3, and the third N-type epitaxial layer 5 serve as the N-type drift region. The N-type drift region is subjected to photolithography and etching processes to form a trench structure with a depth of 3mm-7mm and a width of 0.5mm-2.0mm. The trench structure includes multiple active area trenches 61 and multiple termination area trenches 62. The centerline of each termination area trench 62 coincides with the centerline of the corresponding floating junction structure 42 in the second N-type epitaxial layer 3, and the floating junction structure uniformly surrounds the portion of the termination area trench located in the second N-type epitaxial layer.

[0094] 105. Figure 5 A bottom oxide layer 7 with a thickness of 0.3 mm to 0.6 mm is formed in the active area trench 61 and the terminal area trench 62 by sequentially performing thermal growth and deposition processes, so that the floating junction structure 42 surrounds the bottom oxide layer 7 in the middle of the trench.

[0095] When the MOS device is in the off state and is subjected to a high drain-source voltage, the space charge region formed by the P-type floating junction structure 42 and the second low-resistivity epitaxial layer is subjected to a high electric field strength, which reduces the electric field strength borne by the bottom oxide layer 7 in the middle of the trench, thereby avoiding the breakdown of the bottom oxide layer of the terminal structure trench due to excessive electric field strength in the second low-resistivity epitaxial layer, so that the terminal structure trench of the MOS device can withstand a higher blocking voltage under the same oxide layer thickness.

[0096] 106. Figure 6 Polysilicon is deposited on the wafer surface where the bottom oxide layer 7 is formed to fill the trench structure, and the polysilicon in the trench structure is subjected to photolithography and etching processes to form an active area polycrystalline structure 8 and a terminal area polycrystalline structure 9 respectively.

[0097] 107. Figure 7 The trench structure is filled again with an oxide layer deposition process to remove excess oxide layer on the silicon surface, and the deposited oxide layer in the active area trench is photolithographically and etched to form an intermediate oxide layer 10 with a thickness of 0.3-0.6 mm on the active area polycrystalline structure 8.

[0098] 108. Figure 8As shown, a dry oxygen oxidation process is used to thermally grow an oxide layer on the sidewalls of the active area trench 61 to form a gate oxide layer structure 11 with a thickness of 0.04mm-0.09mm. Then, a polysilicon deposition process is used to fill the active area trench 61 to form a gate polycrystalline structure 12. A dry oxygen oxidation process is performed again to form a shield oxide layer 13 with a thickness of 0.05-0.1mm on top of the gate polycrystalline structure 12.

[0099] 109. Figure 9 As shown, a global P-base implant is performed on the silicon surface, with an implantation energy of 60KeV-150KeV and an implantation dose IMP1 of 0.6E13-1.5E13. After the ion implantation of the P-base region 14 is completed, the base region is annealed at a temperature of 1000°C-1150°C for 30-120 minutes.

[0100] Arsenic ions are implanted into the active region as an N+ source region. After the implantation of arsenic ions into the source region, annealing is performed at a temperature of 950-1000° C. for 90-120 minutes to form an N+ source region 15 .

[0101] 110. Figure 10 A dielectric oxide layer with a thickness of 1.0 mm to 1.5 mm is deposited on the wafer where the N+ type source region 15 is formed, and then a metal electrode contact hole is formed on the dielectric oxide layer by photolithography.

[0102] The BF2 injection process is carried out in the source electrode contact area through the metal electrode contact hole, and annealing is performed after the injection; the injection energy is 60-80KeV, the injection dose is 3E14-5E14, the annealing temperature is 900-1000℃, and the annealing time is 20-30min.

[0103] Then, an AlSiCu metal layer with a thickness of 4-6 μm is deposited on the upper surface of the wafer where the metal electrode contact hole is formed, and a front metal electrode 16 is formed by photolithography and etching processes.

[0104] 111. Figure 11 As shown. A passivation layer is deposited on the electrode structure, and a passivation structure 17 is formed by photolithography and etching processes; a Ti / Ni / Ag metal layer is evaporated on the lower surface of the silicon substrate 1 to form a back metal electrode 18, completing the preparation of the split-gate trench MOSFET structure, as shown. Figure 12 , which is a schematic diagram of the structure of the prepared split-gate trench MOSFET.

[0105] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., they may be located in one location or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of the present embodiment. Persons of ordinary skill in the art will be able to understand and implement the present invention without inventive effort.

[0106] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, or of course, by hardware. Based on this understanding, the essence of the above technical solution or the part that contributes to the existing technology can be embodied in the form of a software product. The computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or certain parts of the embodiments.

[0107] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A split-gate trench MOSFET structure, characterized in that: include: substrate; a first N-type epitaxial layer and a second N-type epitaxial layer sequentially deposited on the substrate; a P-type doped region, wherein the P-type doped region is formed on the second N-type epitaxial layer; a third N-type epitaxial layer, the third N-type epitaxial layer being deposited on the second N-type epitaxial layer forming the P-type doping region; A floating junction structure, wherein the floating junction structure is composed of the P-type doped region, the first N-type epitaxial layer, the second N-type epitaxial layer, and the third N-type epitaxial layer; a space charge region formed by the P-type impurity doped region and the second N-type epitaxial layer in the floating junction structure is used to withstand high electric field strength; a trench structure formed on an N-type drift region composed of the first N-type epitaxial layer, the second N-type epitaxial layer, and the third N-type epitaxial layer; The peripheral structure is used to integrate the substrate, the first N-type epitaxial layer, the second N-type epitaxial layer, the P-type doped region, the third N-type epitaxial layer, the floating junction structure and the trench structure into one.

2. The split-gate trench MOSFET structure according to claim 1, wherein: The trench structure includes a plurality of active area trenches and a plurality of terminal area trenches; A center line of each of the termination region trenches coincides with a center line of the corresponding floating junction structure, and the floating junction structure surrounds a portion of the termination region trench located in the second N-type epitaxial layer.

3. The split-gate trench MOSFET structure according to claim 2, wherein: The peripheral structure includes: A bottom oxide layer, an active area polycrystalline structure, and a terminal area polycrystalline structure are sequentially formed in the active area trench and the terminal area trench; an intermediate oxide layer formed on the active area polycrystalline structure; Gate polysilicon is formed on the active area trench; a shielding oxide layer formed on the gate polysilicon; The front metal electrode is formed on the wafer in the N+ source region; A back metal electrode is formed on the lower surface of the substrate.

4. A method for preparing a split-gate trench MOSFET structure according to any one of claims 1 to 3, characterized in that: include: Selecting an N+ type silicon substrate, and sequentially depositing a first N-type epitaxial layer and a second N-type epitaxial layer on the N+ type silicon substrate, wherein the resistivity of the first N-type epitaxial layer is greater than the resistivity of the second N-type epitaxial layer; forming an implantation window on the second N-type epitaxial layer by photolithography and etching processes, and implanting P-type dopants through the implantation window to form a P-type doped region in the second epitaxial layer; Depositing a third N-type epitaxial layer on the second N-type epitaxial layer forming the P-type doped region, wherein the P-type doped region forms a floating junction structure with the first N-type epitaxial layer, the second N-type epitaxial layer, and the third N-type epitaxial layer; the resistivity of the third N-type epitaxial layer is greater than the resistivity of the second N-type epitaxial layer; using the first N-type epitaxial layer, the second N-type epitaxial layer, and the third N-type epitaxial layer as an N-type drift region, performing photolithography and etching processes on the N-type drift region to form a trench structure; The trench structure includes a plurality of active area trenches and a plurality of terminal area trenches; The center line of each of the terminal region trenches coincides with the center line of the corresponding floating junction structure, and the floating junction structure surrounds the portion of the terminal region trench located in the second N-type epitaxial layer; the space charge region formed by the P-type impurity doped region in the floating junction structure and the second N-type epitaxial layer is used to withstand high electric field strength; Based on the trench structure, the preparation of the split-gate trench MOSFET structure is completed.

5. The method for preparing a split-gate trench MOSFET according to claim 4, wherein: The method of preparing a split-gate trench MOSFET structure based on the trench structure includes: forming a bottom oxide layer, an active area polycrystalline structure and a terminal area polycrystalline structure in the active area trench and the terminal area trench in sequence; forming an intermediate oxide layer on the active area polycrystalline structure; forming a gate polycrystalline structure and a shielding oxide layer in the active area trench; Performing global P-base implantation on the silicon surface to form an N+ type source region; forming a front metal electrode on the wafer forming the N+ type source region; A back metal electrode is formed on the lower surface of the silicon substrate to complete the preparation of the separated gate trench MOSFET structure.

6. The method for preparing a split-gate trench MOSFET according to claim 5, wherein: The step of sequentially forming a bottom oxide layer, an active area polycrystalline structure, and a terminal area polycrystalline structure in the active area trench and the terminal area trench comprises: forming a bottom oxide layer in the active area trench and the terminal area trench by sequentially performing thermal growth and deposition processes; Polysilicon is deposited on the surface of the wafer where the bottom oxide layer is formed to fill the trench structure, and the polysilicon in the trench structure is subjected to photolithography and etching processes to form an active area polycrystalline structure and a terminal area polycrystalline structure respectively.

7. The method for preparing a split-gate trench MOSFET according to claim 6, wherein: The step of forming an intermediate oxide layer on the active area polycrystalline structure comprises: The trench structure is filled again by using an oxide layer deposition process to remove excess oxide layer on the silicon surface, and the deposited oxide layer in the active area trench is photolithography and etching processes are used to form an intermediate oxide layer on the active area polycrystalline structure.

8. The method for preparing a split-gate trench MOSFET according to claim 7, wherein: The step of forming a gate polycrystalline structure and a shielding oxide layer in the active area trench comprises: thermally growing an oxide layer on the sidewalls of the active area trench using a dry oxygen oxidation process to form a gate oxide layer structure; Filling the active area trench by a polysilicon deposition process to form a gate polycrystalline structure; A dry oxygen oxidation process is performed to form a shielding oxide layer on top of the gate polycrystalline structure.

9. The method for preparing a split-gate trench MOSFET according to claim 8, wherein: The method of performing a global P-base implantation on the silicon surface to form an N+ type source region includes: Perform P-base global implantation on the silicon surface. After the ion implantation of the P-base region is completed, the base region implantation is annealed. An N+ type source region arsenic ion implantation is performed on the active region, and annealing is performed after the source region arsenic ion implantation is completed to form an N+ type source region.

10. The method for preparing a split-gate trench MOSFET according to claim 4, wherein: The forming of a front metal electrode on the wafer forming the N+ type source region comprises: Depositing a dielectric oxide layer on the wafer forming the N+ type source region, and forming a metal electrode contact hole on the dielectric oxide layer by a photolithography process; Performing a BF2 injection process on the source electrode contact region through the metal electrode contact hole, and performing annealing after the injection; Depositing a metal layer on the upper surface of the wafer where the metal electrode contact hole is formed, and forming a front metal electrode by photolithography and etching processes; A passivation layer is deposited on the electrode structure, and a passivation structure is formed through photolithography and etching processes; a Ti / Ni / Ag metal layer is evaporated on the lower surface of the silicon substrate to form a back metal electrode, completing the preparation of the separated gate trench MOSFET structure.

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