Semiconductor structure and preparation method thereof

Abstract

The embodiment of the invention relates to the field of semiconductors, and provides a semiconductor structure and a preparation method thereof, and the preparation method comprises the steps: providing a substrate, and forming a doped polycrystalline silicon electrode layer on the substrate; a first side wall, a second side wall and a protection side wall are formed on the side surface of the doped polycrystalline silicon electrode layer; an ion implantation process is carried out on the substrate, a first doped region and a second doped region are formed, and the first doped region and the second doped region are located on the two sides of the doped polycrystalline silicon electrode layer respectively; patterning the second side wall with partial height to expose the side surface of the first side wall with partial height; removing the protection side wall and the exposed first side wall with partial height, and exposing the side surface of the doped polycrystalline silicon electrode layer with partial height; a first metal silicide layer is formed in the doped polycrystalline silicon electrode layer, a second metal silicide layer is formed in the first doped region and the second doped region, and the thickness of the first metal silicide layer is larger than that of the second metal silicide layer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] A MOSFET is a metal-oxide-semiconductor field-effect transistor (MOSFET). It is a voltage-controlled current-mode device and a fundamental element in switching circuits. Its gate (G) has extremely high internal resistance. Taking the N-channel enhancement type as an example, its structure consists of two high-concentration N-type regions diffused on a piece of low-concentration P-type silicon, serving as the drain and source. The semiconductor surface is covered with a silicon dioxide insulating layer, and an electrode is introduced as the gate.

[0003] MOSFETs are one of the smallest electronic components in integrated circuits, and their primary function is to control the flow of current. A transistor can be thought of as a switch, opening or closing the path for current. Current integrated circuits require a high level of integration, as well as fast switching speeds and responsiveness. Switching speed depends on the response speed of each device, and more specifically, on the resistance and contact resistance of each device. The mechanism is as follows: the presence of contact resistance causes signal attenuation and distortion during transmission. When contact resistance is high, a large voltage drop occurs when the signal passes through the contact interface, weakening the signal strength and affecting the sensitivity and accuracy of the device. For example, in high-speed signal transmission lines, high contact resistance can cause signal delays and distortion, reducing the data transmission rate. Summary of the Invention

[0004] The embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, which are at least beneficial for improving the switching speed of the semiconductor structure.

[0005] According to some embodiments of the present disclosure, on the one hand, an embodiment of the present disclosure provides a method for preparing a semiconductor structure, including: providing a substrate, on which a doped polysilicon electrode layer is formed; a first side wall is formed on the side of the doped polysilicon electrode layer, a second side wall is formed on the surface of the substrate, the top surface of the doped polysilicon electrode layer, and the top and side surfaces of the first side wall, and a protective side wall is formed on the side of the second side wall; performing an ion implantation process on the substrate, and forming a first doping region and a second doping region, respectively, the first doping region and the second doping region are respectively located on both sides of the doped polysilicon electrode layer; patterning the second side wall of a partial height to expose the side of the first side wall of a partial height; removing the protective side wall and the exposed partial height of the first side wall, and exposing the side of the doped polysilicon electrode layer of a partial height; forming a first metal silicide layer in the doped polysilicon electrode layer, and forming a second metal silicide layer in the first doping region and the second doping region, the thickness of the first metal silicide layer being greater than the thickness of the second metal silicide layer.

[0006] In some embodiments, a wet etching process is used to pattern the second sidewall spacer of a partial height.

[0007] In some embodiments, the etchant of the wet etching process includes diluted hydrofluoric acid or a buffered oxide etchant.

[0008] In some embodiments, a fluorine-based plasma etching process is used to pattern the second sidewall spacer of a partial height.

[0009] In some embodiments, the material of the first sidewall spacer is silicon nitride, and the material of the second sidewall spacer is silicon oxide; or, the material of the first sidewall spacer is silicon carbide, and the material of the second sidewall spacer is silicon oxynitride.

[0010] In some embodiments, the proportion of oxygen in the etching gas for patterning the height of the second sidewall spacer is 5% to 20%.

[0011] In some embodiments, before the second side wall of the patterned portion height is formed, the process also includes: performing plasma treatment or ion implantation on the second side wall located on the surface of the substrate and the top surface of the doped polysilicon electrode layer away from the substrate, wherein, under the same etching process, the etching rate of the material of the modified second side wall is less than the etching rate of the material of the unmodified second side wall.

[0012] In some embodiments, the plasma of the plasma treatment includes N2 plasma, NH3 plasma, or argon plasma; and the ions of the ion implantation process include nitrogen, carbon, or fluorine ions.

[0013] In some embodiments, the substrate includes an array area and a peripheral area, and the doped polysilicon electrode layer is located in the peripheral area; when forming the second side wall, the second side wall is formed on the array area; a third side wall is formed, and the third side wall is located on the side of the second side wall, and when forming the third side wall, the third side wall is formed on the array area; after forming the third side wall, it also includes: forming a protective layer, and the protective layer is located in the array area.

[0014] According to some embodiments of the present disclosure, on the other hand, the embodiments of the present disclosure further provide a semiconductor structure, including: a substrate, having a first doped region and a second doped region in the substrate; a doped polysilicon electrode layer, the doped polysilicon electrode layer is located on the substrate; a first metal silicide layer, the first metal silicide layer is located on the surface of the doped polysilicon electrode layer; a second metal silicide layer, the second metal silicide layer is located in the first doped region and the second doped region, and the thickness of the first metal silicide layer is greater than the thickness of the second metal silicide layer; a first side wall, the first side wall is located on the substrate, and the first side wall is also located on the side of the doped polysilicon electrode layer and part of the side of the first metal silicide layer; a second side wall, the second side wall is located on the substrate, and the second side wall is located on the side of the first side wall; a third side wall, the third side wall is located on the substrate, and the third side wall is located on the side of the second side wall.

[0015] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0016] The method for preparing a semiconductor structure provided by the embodiment of the present disclosure patterns a portion of the height of the second sidewall to expose a portion of the height of the first sidewall; based on the exposed first sidewall, the side surface of the doped polysilicon electrode layer is exposed at a portion of the height. During this process, the first doped region and the second doped region in the substrate are not etched, leaving the exposed surface area of ​​the first doped region and the second doped region relatively small, thereby specifically increasing the area of ​​the exposed doped polysilicon electrode layer. A first metal silicide layer and a second metal silicide layer of different thicknesses are formed by the exposed doped polysilicon electrode layer, the first doped region, and the second doped region. In this way, the contact resistance distribution is optimized. The thick first metal silicide layer on the surface of the doped polysilicon electrode layer can reduce the gate / contact hole resistance, optimize the gate conductivity, and thus improve the switching speed of the semiconductor structure; the thin second metal silicide layer on the surface of the substrate prevents excessive consumption of the substrate, avoids junction punch-through or increases in leakage current, while still ensuring sufficient conductivity to ensure the off-state current IOFF. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1 A schematic structural diagram corresponding to a substrate provided in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0019] Figure 2 A schematic diagram of the structure corresponding to the second sidewall spacer of the patterned portion height in the method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0020] Figure 3 A schematic structural diagram corresponding to removing the protective sidewall in the method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0021] Figure 4 A schematic structural diagram corresponding to the formation of a third sidewall spacer in the method for preparing a semiconductor structure provided in one embodiment of the present disclosure;

[0022] Figure 5A schematic structural diagram corresponding to the formation of a protective layer in a method for preparing a semiconductor structure provided in one embodiment of the present disclosure;

[0023] Figure 6 A schematic structural diagram corresponding to removing a protective layer in a method for preparing a semiconductor structure provided in one embodiment of the present disclosure;

[0024] Figure 7 A schematic structural diagram corresponding to removing the first film layer in the method for preparing a semiconductor structure provided in one embodiment of the present disclosure;

[0025] Figure 8 A schematic structural diagram corresponding to the formation of a first metal silicide layer in a method for preparing a semiconductor structure provided in one embodiment of the present disclosure.

[0026] Description of reference numerals:

[0027] 100. Substrate; 11. Peripheral region; 12. Array region; 101. Shallow trench isolation structure; 102. First sidewall; 103. Second sidewall; 104. Protective sidewall; 105. Third sidewall; 115. First film layer; 125. Second film layer; 106. Protective layer; 111. Gate dielectric layer; 112. Doped polysilicon electrode layer; 121. First doped region; 122. Second doped region; 113. First metal silicide layer; 123. Second metal silicide layer. DETAILED DESCRIPTION

[0028] As known from the background art, the switching speed of current semiconductor structures is poor.

[0029] Analysis found that one of the reasons for the poor switching speed of the semiconductor structure is the large resistance of the gate.

[0030] Due to the structure of the MOSFET itself, a parasitic diode exists between the source and drain. Its direction is determined by the direction from source to drain for NMOS and vice versa for PMOS. The parasitic diode prevents breakdown of the MOSFET when VDD is too high (the parasitic diode will break down first, shorting the high voltage to ground) and also prevents reverse connection of DS. The parasitic capacitance of a MOSFET mainly includes gate-source capacitance (Cgs), gate-drain capacitance (Cgd), and drain-source capacitance (Cds). The parasitic capacitance Cgs between the gate and source affects switching speed. The MOSFET also has two resistors: the gate series resistor R1 and Rgs connected in parallel between the gate and source. Rgs is used to release the voltage between the gate and source. Due to the presence of Cgs, a small amount of static electricity can generate a huge voltage between the GS. To protect the MOSFET, Rgs is generally connected in parallel between the GS.

[0031] In addition to parasitic capacitance, parasitic inductance is also generated in actual applications due to PCB layout, routing, and internal factors of the MOSFET. This parasitic inductance and Cgs form an LC oscillation circuit, which can cause severe oscillations under the influence of the gate drive signal. Therefore, a series resistor is added to attenuate this oscillation. Parasitic capacitance and inductance store energy, and the series resistor prevents this energy from being dissipated internally and instead acts on the MOSFET. The gate resistance can affect the switching speed of the switch. If the gate resistance is too large, the switching speed will be reduced. If the gate resistance is too small, the rapid switching speed will result in a large current-voltage change rate, which means strong interference. Therefore, the size of the gate resistance is crucial to the switching speed of the semiconductor structure.

[0032] An embodiment of the present disclosure provides a method for preparing a semiconductor structure, by step-by-step etching of a first side wall, a protective side wall, and a second side wall, so that the side of a partially highly doped polysilicon electrode layer is exposed without excessive etching of the substrate, thereby forming a first metal silicide layer and a second metal silicide layer of different thicknesses to reduce the gate resistance and ensure the off-state current IOFF.

[0033] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the embodiments of the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular form is intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, they indicate the presence of features, steps, operations, devices, components and / or combinations thereof.

[0034] Unless otherwise specifically stated, the relative arrangement of the parts and steps, the numerical expressions and the numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure. At the same time, it should be understood that, for ease of description, the sizes of the various parts shown in the drawings are not drawn according to actual proportional relationships. The techniques, methods and equipment known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, the techniques, methods and equipment should be considered as part of the authorization specification. In all examples shown and discussed herein, any specific values ​​should be interpreted as being merely exemplary and not as limitations. Therefore, other examples of the exemplary embodiments may have different values. It should be noted that similar numbers and letters represent similar items in the following figures, and therefore, once an item is defined in one figure, it does not need to be further discussed in subsequent figures.

[0035] In the description of the embodiments of the present disclosure, it should be understood that the directions or positional relationships indicated by directional words such as "front, back, up, down, left, right", "horizontal, vertical, vertical, horizontal" and "top, bottom" are usually based on the directions or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present disclosure and simplifying the description. Unless otherwise specified, these directional words do not indicate or imply that the device or element referred to must have a specific direction or be constructed and operated in a specific direction. Therefore, they cannot be understood as limiting the scope of protection of the embodiments of the present disclosure; the directional words "inside and outside" refer to the inside and outside relative to the outline of each component itself.

[0036] For ease of description, spatially relative terms such as "above", "above", "on the upper surface of", "above", etc. may be used herein to describe the spatial positional relationship of a device or feature to other devices or features as shown in the figures. It should be understood that spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation described in the figures. For example, if the device in the drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Thus, the exemplary term "above" can include both "above" and "below". The device can also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatially relative descriptions used here are interpreted accordingly.

[0037] In addition, it should be noted that the use of words such as "first" and "second" to limit components is only for the convenience of distinguishing the corresponding components. Unless otherwise stated, the above words have no special meaning and therefore cannot be understood as limiting the scope of protection of this disclosure.

[0038] The following describes various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to facilitate a better understanding of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can still be implemented.

[0039] According to some embodiments of the present disclosure, on one hand, a method for preparing a semiconductor structure is provided.

[0040] Figure 1 A schematic structural diagram corresponding to a substrate is provided in a method for preparing a semiconductor structure provided in one embodiment of the present disclosure.

[0041] refer to Figure 1The preparation method includes: providing a substrate 100, on which a doped polysilicon electrode layer 112 is formed; forming a first sidewall 102 on the side of the doped polysilicon electrode layer 112, forming a second sidewall 103 on the surface of the substrate 100, the top surface of the doped polysilicon electrode layer 112, and the top and side surfaces of the first sidewall 102, and forming a protective sidewall 104 on the side of the second sidewall 103; performing an ion implantation process on the substrate 100, and forming a first doped region 121 and a second doped region 122 respectively, the first doped region 121 and the second doped region 122 are respectively located at the doped polysilicon electrode layer 112. Both sides of the crystalline silicon electrode layer 112; patterning the second side wall 103 of a partial height to expose the side of the first side wall 102 of a partial height; removing the protective side wall 104 and the exposed partial height of the first side wall 102, and exposing the side of the doped polysilicon electrode layer 112 of a partial height; forming a first metal silicide layer 113 in the doped polysilicon electrode layer 112, and forming a second metal silicide layer 123 in the first doping region 121 and the second doping region 122, the thickness of the first metal silicide layer 113 being greater than the thickness of the second metal silicide layer 123.

[0042] The method for preparing a semiconductor structure provided by an embodiment of the present disclosure patterns a partial height of the second sidewall 103 to expose a partial height of the first sidewall 102; based on the exposed first sidewall 102, the side surface of the doped polysilicon electrode layer 112 is exposed at a partial height. During this process, the first doped region 121 and the second doped region 122 in the substrate 100 are not etched, and the exposed surface area of ​​the first doped region 121 and the second doped region 122 is kept small, thereby specifically increasing the area of ​​the exposed doped polysilicon electrode layer 112. A first metal silicide layer 113 and a second metal silicide layer 123 of different thicknesses are formed through the exposed doped polysilicon electrode layer 112, the first doped region 121 and the second doped region 122. In this way, the contact resistance distribution is optimized. The thick first metal silicide layer 113 on the surface of the doped polysilicon electrode layer 112 can reduce the gate / contact hole resistance, optimize the gate conductivity, and thus improve the switching speed of the semiconductor structure; the thin second metal silicide layer 123 on the surface of the substrate 100 prevents excessive consumption of the silicon substrate, avoids junction punch-through or increased leakage current, while still ensuring sufficient conductivity to ensure the off-state current IOFF.

[0043] The following will describe in detail the method for preparing the semiconductor structure provided by the embodiment of the present disclosure in conjunction with the accompanying drawings.

[0044] refer to Figure 1 The preparation method includes: providing a substrate 100.

[0045] In some embodiments, the semiconductor structure can be a memory device. The semiconductor structure includes an array region 12 and a peripheral region 11. The array region 12 is the core region of the memory device, used for storing data; the peripheral region 11 is the control region of the memory device, used for controlling the writing and reading of data from the array region 12. The array region 12 includes storage capacitors and switches. The storage capacitors are used for storing data; the switches in the array region 12 are used to control the input and output of data from the storage capacitors. The peripheral region 11 also includes switches that form a control circuit to control the writing and reading of data from the array region 12.

[0046] In some embodiments, the substrate 100 includes an array region 12 and a peripheral region 11 . Figure 1 The array area 12 and the peripheral area 11 are actually the same substrate 100, divided by a dividing line in the middle. The array area 12 and the peripheral area 11 are only functional area divisions, and the film layers deposited thereon vary according to needs.

[0047] The substrate 100 may be made of a semiconductor material, which may include any one of silicon, germanium, silicon carbide, or silicon germanium. The substrate 100 may contain a doping element, which may be an N-type doping element or a P-type doping element. The N-type doping element may be a Group V element such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As). The P-type doping element may be a Group III element such as boron (B), aluminum (Al), gallium (Ga), or indium (In).

[0048] In some embodiments, a shallow trench isolation (STI) structure 101 is formed in the substrate 100 to isolate the pMOSFET and nMOSFET of the semiconductor structure to prevent mutual interference. The material of the shallow trench isolation structure 101 can be silicon oxide.

[0049] The process steps for forming the shallow trench isolation structure include: etching a shallow trench in the substrate 100, and then filling it with silicon oxide to form an electrical isolation layer.

[0050] The preparation method includes: forming a gate dielectric layer 111 , wherein the gate dielectric layer 111 is located on the surface of the substrate 100 and is located in the peripheral region 11 .

[0051] The gate dielectric layer 111 may be made of silicon oxide, silicon carbide, silicon nitride or other materials with a high dielectric constant, and is used to suppress short channel effects, thereby suppressing tunneling leakage current and the like.

[0052] The preparation method includes: forming a doped polysilicon electrode layer 112 on a substrate 100 , wherein the doped polysilicon electrode layer 112 is located on a surface of a gate dielectric layer 111 , and the doped polysilicon electrode layer 112 is located in a peripheral region 11 .

[0053] The doped polysilicon electrode layer 112 can serve as a conductive layer for the gate. Doped polysilicon is used as the conductive layer for the gate. The energy gap of polysilicon is similar to that of the material used for the channel portion, and the work function of polysilicon can be changed by controlling the doping concentration, which helps to reduce the threshold voltage between the gate and the channel portion. The doping element type of the doped polysilicon is the same as or different from the doping element type of the channel portion. The channel portion is a portion of the substrate 100, and the channel portion is located between the first doping region 121 and the second doping region 122 to be formed subsequently, with the gate facing the channel portion.

[0054] The preparation method includes: forming a first sidewall spacer 102 , wherein the first sidewall spacer 102 is located on a side of the doped polysilicon electrode layer 112 .

[0055] The second spacer 103 is formed on the surface of the substrate 100 , the top surface of the doped polysilicon electrode layer 112 away from the substrate 100 , and the top and side surfaces of the first spacer 102 . The second spacer 103 is also located in the array region 12 .

[0056] A protection spacer 104 is formed. The protection spacer 104 is located on the side of the second spacer 103 away from the first spacer 102 . The top surface of the protection spacer 104 away from the substrate 100 is lower than the top surface of the second spacer 103 .

[0057] First spacer 102: Formed on the side of the doped polysilicon electrode layer 112, the first spacer 102 serves as an isolation barrier for subsequent processes, preventing direct impact of ion implantation on the gate and defining the location of subsequent doped regions. Second spacer 103 and protective spacer 104: The second spacer 103 covers the surface of the substrate 100, the top surface of the doped polysilicon electrode layer 112, and the first spacer 102, and protective spacers 104 are formed on its side to provide multiple protections.

[0058] Under the same etching process, the etching rate of the material of the first sidewall spacer 102 is different from the etching rate of the material of the second sidewall spacer 103. Therefore, due to the different etching rates of the materials of the first sidewall spacer 102 and the second sidewall spacer 103, when removing the first sidewall spacer 102, the second sidewall spacer 103 will not be excessively etched. In other words, the second sidewall spacer 103 can still maintain its basic morphology. Conversely, when removing the second sidewall spacer 103, the morphology of the first sidewall spacer 102 can be maintained. Based on selective etching, a portion of the height of the first sidewall spacer 102 is removed before the height of the second sidewall spacer 103 is removed.

[0059] In some embodiments, the material of the first sidewall spacer 102 is silicon nitride, and the material of the second sidewall spacer 103 is silicon oxide. When silicon nitride is used as the first sidewall spacer 102, its structure is stable, which can prevent dopant ions from penetrating the sidewall into the gate polysilicon, thereby avoiding gate threshold voltage drift. It ensures a clear boundary between the doped region (source / drain) and the gate, reducing the risk of leakage; the silicon oxide sidewall serves as a thermal isolation layer, reducing heat diffusion to the substrate during high-temperature annealing and preventing junction degradation. The surface smoothness of silicon oxide helps to suppress metal residues in subsequent metal silicides and reduce the risk of short circuits.

[0060] Secondly, the strong isolation of silicon nitride prevents silicide from extending into the channel region, while silicon oxide blocks the lateral diffusion of source and drain silicide, ensuring device reliability.

[0061] The selectivity ratio of the wet etching of silicon oxide (the second sidewall spacer 103 ) to silicon nitride (the first sidewall spacer 102 ) can reach above 100:1, thus achieving lossless exposure, that is, maximizing the etching selectivity ratio.

[0062] In some embodiments, the first sidewall spacer 102 is made of silicon carbide (SiC), and the second sidewall spacer 103 is made of silicon oxynitride (SiON). The dry etch selectivity of SiC to SiON is greater than 20:1, allowing the first sidewall spacer 102 to be removed without damage during the removal of the second sidewall spacer 103. SiC has a higher density than SiON, providing enhanced barrier properties for implanted ions, reducing the risk of dopant ion penetration and preventing blurred gate doping profiles.

[0063] In some embodiments, the first sidewall 102, the second sidewall 103 and the subsequently formed third sidewall 105 serve together as gate sidewalls. The function of the gate sidewalls is to prevent large doses of source and drain from being injected too close to the channel during the subsequent ion implantation process, thereby causing the channel to be too short or even the source and drain to be connected.

[0064] An ion implantation process is performed on the substrate 100 to form a first doping region 121 and a second doping region 122 . The first doping region 121 and the second doping region 122 are respectively located on two sides of the doped polysilicon electrode layer 112 .

[0065] In some embodiments, n+ source / drain implantation is performed first. After the n-type transistor region is photolithographically defined, a medium-dose implantation is performed. The depth of the implantation is greater than the LDD junction depth, and the second spacer 103 prevents arsenic impurities from entering the narrow channel region. P+ source / drain implantation is performed next. After the p-type transistor region is photolithographically defined, a medium-dose implantation is also performed. The resulting junction depth is slightly greater than that of the LDD junction, and the second spacer 103 performs a similar barrier function. After implantation, the substrate 100 is annealed in a rapid annealing apparatus to form the first doped region 121 and the second doped region 122.

[0066] Figure 2 This is a schematic structural diagram corresponding to the second sidewall spacer 103 having a patterned portion height in the method for preparing a semiconductor structure provided by an embodiment of the present disclosure.

[0067] refer to Figure 2 , patterning a portion of the height of the second spacer 103 to expose a portion of the height of the side surface of the first spacer 102 .

[0068] In some embodiments, a wet etching process is used to pattern a portion of the second sidewall spacer 103 .

[0069] In some embodiments, the wet etching process includes an etchant comprising diluted hydrofluoric acid (DHF) or a buffered oxide etchant (BOE). The volume ratio of water to hydrofluoric acid in the DHF is 30:1. The buffered oxide etchant (BOE) is a mixture of a 49% hydrofluoric acid aqueous solution and an ammonium fluoride aqueous solution in a 1:6 volume ratio.

[0070] In some embodiments, a fluorine-based plasma etching process is used to pattern a portion of the height of the second sidewall spacer 103. Under the action of an RF electric field, a fluorine-containing gas (such as SF6, CF4, CHF3, or a C4F8 / O2 mixed gas) dissociates to form F free radicals. These neutral particles diffuse to the surface of the substrate 100 and selectively react with the material of the second sidewall spacer 103 to produce volatile products such as SiF4 and CO.

[0071] In some embodiments, the proportion of oxygen in the etching gas for patterning the height of the second sidewall spacer 103 is 5% to 20%. In this way, the etching rate of the second sidewall spacer 103 can be increased to shorten the etching time and reduce the etching time of other devices.

[0072] In some embodiments, before patterning a portion of the height of the second sidewall spacer 103, the method further includes: performing a plasma treatment or ion implantation process on the second sidewall spacer 103 located on the surface of the substrate 100 and the top surface of the doped polysilicon electrode layer 112 away from the substrate 100. Under the same etching process, the etching rate of the material of the modified second sidewall spacer 103 is lower than the etching rate of the material of the unmodified second sidewall spacer 103. In this way, when removing a portion of the height of the second sidewall spacer 103, the second sidewall spacer 103 located on the surface of the substrate 100 and the surface of the doped polysilicon electrode layer 112 can be partially etched and can serve as a protective layer, thereby improving the yield of the semiconductor structure.

[0073] In some embodiments, the plasma of the plasma treatment includes N2 plasma, NH3 plasma, or argon plasma; and the ions of the ion implantation process include nitrogen, carbon, or fluorine ions.

[0074] During the process of patterning a portion of the second sidewall spacer 103 , a portion of the second sidewall spacer 103 located on the top surface of the doped polysilicon electrode layer 112 and the second sidewall spacer 103 located on the first doped region 121 and the second doped region 122 is also removed.

[0075] Figure 3 This is a schematic structural diagram corresponding to removing the protective sidewall spacer 104 in the method for preparing a semiconductor structure provided by an embodiment of the present disclosure.

[0076] refer to Figure 3 , remove the protective sidewall spacer 104 and the exposed portion of the first sidewall spacer 102 , and expose the side surface of the doped polysilicon electrode layer 112 at a portion of the height.

[0077] During the patterning step, the second sidewall spacer 103 is partially removed to expose the side of the first sidewall spacer 102. The protective sidewall spacer 104 and a portion of the first sidewall spacer 102 are then removed through selective etching, precisely controlling the exposed area on the side of the doped polysilicon electrode layer 112. This step ensures that only the critical area of ​​the gate sidewall is exposed, providing space for the subsequent formation of a thick metal silicide layer.

[0078] Phosphoric acid is used to remove the protective side wall 104 and a portion of the height of the first side wall 102. Since the side of the first side wall 102 of a portion of its height is exposed, that is, the side and top surfaces of the first side wall 102 are exposed, this portion of the first side wall 102 is etched away under the isotropic etching of the etching solution, and the first side wall 102 located on the top surface of the doped polysilicon electrode layer 112 is not completely etched away, and thus serves as a protective layer in subsequent steps.

[0079] The volume fraction of phosphoric acid is 85% to 88%, and the phosphoric acid is heated to 155° C. to 165° C. to maintain a relatively high etching rate.

[0080] Figure 4 This is a structural schematic diagram corresponding to the formation of the third sidewall spacer 105 in the method for preparing the semiconductor structure provided in one embodiment of the present disclosure.

[0081] refer to Figure 4 , forming a third spacer 105 , the third spacer 105 is located on the side of the second spacer 103 . The third spacer 105 is also located in the array region 12 .

[0082] The third spacer 105 is formed by chemical vapor deposition process. The material of the third spacer 105 can be the same as that of the first spacer 102 .

[0083] The third sidewall spacer 105 includes a first film layer 115 and a second film layer 125 . The material of the first film layer 115 may be silicon oxide; the material of the second film layer 125 may be silicon nitride or silicon oxynitride.

[0084] Figure 5 A schematic structural diagram corresponding to the formation of a protective layer in the method for preparing a semiconductor structure provided in one embodiment of the present disclosure.

[0085] refer to Figure 5 , forming a protection layer, the protection layer is used to protect the second sidewall 103 and the third sidewall 105 located in the array area 12 when the second sidewall 103 is removed. The protection layer is located in the array area 12.

[0086] Figure 6 A schematic structural diagram corresponding to removing the protective layer in the method for preparing a semiconductor structure provided in one embodiment of the present disclosure.

[0087] refer to Figure 6 , remove the third sidewall spacer 105 on the substrate 100 and the surface of the doped polysilicon electrode layer 112 , and retain the third sidewall spacer 105 located on the side of the second sidewall spacer 103 .

[0088] refer to Figure 6 Removing the third sidewall spacer 105 on the substrate 100 and the surface of the doped polysilicon electrode layer 112 refers to removing the second film layer 125 on the substrate 100 and the surface of the doped polysilicon electrode layer 112 and retaining the first film layer 115 .

[0089] It should be noted that, Figure 6 As shown, the first film layer 115 located on the surface of the doped polysilicon electrode layer 112 is removed, or the first film layer 115 located on the surface of the doped polysilicon electrode layer 112 may be retained.

[0090] Continue to refer Figure 6 , remove the protective layer.

[0091] Figure 7 This is a structural schematic diagram corresponding to removing the first film layer 115 in the method for preparing a semiconductor structure provided by an embodiment of the present disclosure.

[0092] refer to Figure 7 , remove the first film layer 115 and other residual protective layers (if any) located on the surface of the doped polysilicon electrode layer 112 to expose the surface of the doped polysilicon electrode layer 112, and remove the first film layer 115 located on the substrate 100 to expose the first doped region 121 and the second doped region 122.

[0093] Figure 8 This is a schematic structural diagram corresponding to the formation of the first metal silicide layer 113 in the method for preparing the semiconductor structure provided in one embodiment of the present disclosure.

[0094] refer to Figure 8, forming a metal layer, the metal layer covers the surface of the substrate 100, the side of the doped polysilicon electrode layer 112 at a partial height, and the top surface of the doped polysilicon electrode layer 112 away from the substrate 100; performing heat treatment to convert the doped polysilicon electrode layer 112 at a partial height into a first metal silicide layer 113, and convert the partial thickness of the substrate 100 into a second metal silicide layer 123, the thickness of the first metal silicide layer 113 being greater than the thickness of the second metal silicide layer 123.

[0095] The method for preparing a semiconductor structure provided by an embodiment of the present disclosure patterns a partial height of the second sidewall 103 to expose a partial height of the first sidewall 102; based on the exposed first sidewall 102, the side surface of the doped polysilicon electrode layer 112 is exposed at a partial height. During this process, the first doped region 121 and the second doped region 122 in the substrate 100 are not etched, and the exposed surface area of ​​the first doped region 121 and the second doped region 122 is kept small, thereby specifically increasing the area of ​​the exposed doped polysilicon electrode layer 112. A first metal silicide layer 113 and a second metal silicide layer 123 of different thicknesses are formed through the exposed doped polysilicon electrode layer 112, the first doped region 121 and the second doped region 122. In this way, the contact resistance distribution is optimized. The thick first metal silicide layer 113 on the surface of the doped polysilicon electrode layer 112 can reduce the gate / contact hole resistance, optimize the gate conductivity, and thus improve the switching speed of the semiconductor structure; the thin second metal silicide layer 123 on the surface of the substrate 100 prevents excessive consumption of the substrate 100, avoids junction punch-through or increased leakage current, while still ensuring sufficient conductivity to ensure the off-state current IOFF.

[0096] Accordingly, according to some embodiments of the present disclosure, the embodiments of the present disclosure also provide a semiconductor structure on the other hand, which can be prepared by the semiconductor structure preparation method of any of the above embodiments, and has the same or corresponding technical features as the above embodiments, which will not be described in detail here.

[0097] refer to Figure 8 The semiconductor structure includes a substrate 100 having a first doping region 121 and a second doping region 122 therein.

[0098] The substrate 100 includes an array region 12 and a peripheral region 11 . The peripheral region 11 has a first doping region 121 and a second doping region 122 .

[0099] The semiconductor structure includes a gate dielectric layer 111 . The gate dielectric layer 111 is located on the surface of the substrate 100 . The gate dielectric layer 111 is located between the first doping region 121 and the second doping region 122 , with a small overlapping area or no overlapping area.

[0100] The semiconductor structure includes a doped polysilicon electrode layer 112 , which is located on the substrate 100 and on the surface of the gate dielectric layer 111 .

[0101] The semiconductor structure includes: a first sidewall 102, the first sidewall 102 is located on the substrate 100, and the first sidewall 102 is also located on the side of the doped polysilicon electrode layer 112 and a portion of the side of the first metal silicide layer 113; a second sidewall 103, the second sidewall 103 is located on the substrate 100, and the second sidewall 103 is located on the side of the first sidewall 102; a third sidewall 105, the third sidewall 105 is located on the substrate 100, and the third sidewall 105 is located on the side of the second sidewall 103.

[0102] The semiconductor structure includes a first metal silicide layer 113 , which is located on a surface of the doped polysilicon electrode layer 112 .

[0103] The semiconductor structure includes a second metal silicide layer 123 . The second metal silicide layer 123 is located in the first doping region 121 and the second doping region 122 . The thickness of the first metal silicide layer 113 is greater than that of the second metal silicide layer 123 .

[0104] Accordingly, according to some embodiments of the present disclosure, another aspect of the embodiments of the present disclosure further provides a storage structure, including the semiconductor structure provided by the above embodiments, and the technical features that are the same as or corresponding to the above embodiments will not be described in detail here.

[0105] The memory structure includes: the semiconductor structure provided in the above embodiment, wherein the semiconductor structure on the peripheral region in the above embodiment serves as a peripheral control circuit, and the semiconductor structure on the array region serves as a memory array.

[0106] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present disclosure, and that in actual applications, various changes in form and detail may be made thereto without departing from the spirit and scope of the present disclosure. Any person skilled in the art may make changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be subject to the scope defined in the claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: A substrate is provided, on which a doped polysilicon electrode layer is formed; a first sidewall is formed on the side of the doped polysilicon electrode layer; a second sidewall is formed on the surface of the substrate, the top surface of the doped polysilicon electrode layer, and the top and side surfaces of the first sidewall; and a protective sidewall is formed on the side of the second sidewall; Performing an ion implantation process on the substrate to form a first doping region and a second doping region, respectively, wherein the first doping region and the second doping region are respectively located on both sides of the doped polysilicon electrode layer; Patterning a portion of the height of the second sidewall spacer to expose a portion of the height of the sidewall spacer; Removing the protective sidewall spacer and the exposed portion of the first sidewall spacer, and exposing a portion of the side surface of the doped polysilicon electrode layer; A first metal silicide layer is formed in the doped polysilicon electrode layer, and a second metal silicide layer is formed in the first doping region and the second doping region. The thickness of the first metal silicide layer is greater than the thickness of the second metal silicide layer.

2. The method for preparing a semiconductor structure according to claim 1, wherein: A wet etching process is used to pattern a portion of the height of the second sidewall.

3. The method for preparing a semiconductor structure according to claim 2, wherein: The etching solution of the wet etching process includes diluted hydrofluoric acid or buffered oxide etching solution.

4. The method for preparing a semiconductor structure according to claim 1, wherein: A fluorine-based plasma etching process is used to pattern a portion of the height of the second sidewall spacer.

5. The method for preparing a semiconductor structure according to claim 2 or 4, characterized in that: The material of the first sidewall spacer is silicon nitride, and the material of the second sidewall spacer is silicon oxide; or the material of the first sidewall spacer is silicon carbide, and the material of the second sidewall spacer is silicon oxynitride.

6. The method for preparing a semiconductor structure according to claim 4, wherein: The proportion of oxygen in the etching gas of the second sidewall spacer at the height of the patterned portion is 5% to 20%.

7. The method for preparing a semiconductor structure according to claim 5, wherein: Before the second side wall at the height of the patterned part, it also includes: performing a plasma treatment or ion implantation process on the second side wall located on the surface of the substrate and the top surface of the doped polysilicon electrode layer away from the substrate, wherein, under the same etching process, the etching rate of the modified material of the second side wall is less than the etching rate of the unmodified material of the second side wall.

8. The method for preparing a semiconductor structure according to claim 7, wherein: The plasma of the plasma treatment includes N2 plasma, NH3 plasma or argon plasma; the ions of the ion implantation process include nitrogen, carbon or fluorine ions.

9. The method for preparing a semiconductor structure according to claim 1, wherein: The substrate includes an array region and a peripheral region, and the doped polysilicon electrode layer is located in the peripheral region; when forming the second sidewall, the second sidewall is formed on the array region; and a third sidewall is formed, the third sidewall is located on a side of the second sidewall, and when forming the third sidewall, the third sidewall is formed on the array region. After forming the third sidewall spacer, the method further includes forming a protection layer, wherein the protection layer is located in the array region.

10. A semiconductor structure prepared by the method for preparing a semiconductor structure according to any one of claims 1 to 9, characterized in that: include: a substrate, wherein the substrate has a first doping region and a second doping region; a doped polysilicon electrode layer, wherein the doped polysilicon electrode layer is located on the substrate; a first metal silicide layer, wherein the first metal silicide layer is located on a surface of the doped polysilicon electrode layer; a second metal silicide layer, wherein the second metal silicide layer is located in the first doping region and the second doping region, and the thickness of the first metal silicide layer is greater than the thickness of the second metal silicide layer; a first sidewall spacer, the first sidewall spacer being located on the substrate, and the first sidewall spacer being also located on a side surface of the doped polysilicon electrode layer and a portion of a side surface of the first metal silicide layer; a second sidewall, wherein the second sidewall is located on the substrate and is located on a side of the first sidewall; A third sidewall spacer is located on the substrate and on a side of the second sidewall spacer.

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