Semiconductor device

Abstract

There is provided a semiconductor device including: a lower interlayer insulating layer; an insulating pattern on the lower interlayer insulating layer and extending in a first horizontal direction; a plurality of semiconductor nanosheets stacked on an upper surface of the insulating pattern; a gate electrode extending in a second horizontal direction and surrounding the plurality of semiconductor nanosheets; a first source / drain region disposed on the insulating pattern at a first side of the gate electrode; a second source / drain region disposed on the insulating pattern at a second side of the gate electrode opposite the first side of the gate electrode; a lower source / drain contact penetrating the lower interlayer insulating layer and the insulating pattern, the lower source / drain contact being electrically connected to the second source / drain region; and a first insulating liner layer in contact with both sidewalls of the first portion of the lower source / drain contact.

Description

[0001] This application claims priority from Korean Patent Application No. 10-2024-0037549 filed on March 19, 2024, in the Korean Intellectual Property Office, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] The present disclosure relates to a semiconductor device, and more particularly, to a semiconductor device including an MBCFET™ (Multi-Bridge Channel Field Effect Transistor). Background Art

[0003] One scaling scheme for increasing the integration density of integrated circuit devices employs multi-gate transistors in which a fin-shaped or nanowire-shaped silicon body is formed on a substrate, and a gate is formed on a surface of the silicon body.

[0004] Because such multi-gate transistors use a three-dimensional channel, they can be easily scaled. Furthermore, their current control capability can be improved without increasing their gate length. Furthermore, multi-gate transistors can effectively suppress the short channel effect (SCE), in which the potential of the channel region is affected by the drain voltage. Summary of the Invention

[0005] The present disclosure describes a semiconductor device in which the reliability of the electrical connection between source / drain regions and lower source / drain contacts disposed in a backside region is improved.

[0006] According to some embodiments of the present disclosure, a semiconductor device is provided, comprising: a lower interlayer insulating layer; an insulating pattern disposed on an upper surface of the lower interlayer insulating layer; the insulating pattern extending in a first horizontal direction; a plurality of semiconductor nanosheets stacked on the upper surface of the insulating pattern, wherein each of the plurality of semiconductor nanosheets is spaced apart from each other in a vertical direction; a gate electrode extending on the insulating pattern in a second horizontal direction different from the first horizontal direction, the gate electrode surrounding the plurality of semiconductor nanosheets; a first source / drain region disposed on the insulating pattern at a first side of the gate electrode; and a second A source / drain region is arranged on the insulating pattern at the second side of the gate electrode opposite to the first side of the gate electrode in the first horizontal direction; a lower source / drain contact passes through the lower interlayer insulating layer and the insulating pattern in the vertical direction, the lower source / drain contact is electrically connected to the second source / drain region, the lower source / drain contact includes a first portion arranged below the second source / drain region and a second portion arranged below the first portion; and a first insulating liner layer is in contact with two side walls of the first portion of the lower source / drain contact in the first horizontal direction, the upper surface of the first insulating liner layer is in contact with the second source / drain region.

[0007] According to some embodiments of the present disclosure, a semiconductor device is provided, comprising: a lower interlayer insulating layer; an insulating pattern disposed on an upper surface of the lower interlayer insulating layer, the insulating pattern extending in a first horizontal direction; a field insulating layer disposed on an upper surface of the lower interlayer insulating layer, the field insulating layer covering a sidewall of the insulating pattern; a gate electrode on the insulating pattern and the field insulating layer, the gate electrode extending in a second horizontal direction different from the first horizontal direction; a first source / drain region disposed on the insulating pattern at a first side of the gate electrode; a second source / drain region disposed on the insulating pattern at a second side of the gate electrode opposite to the first side of the gate electrode in the first horizontal direction; a lower source / drain; and A contact member passes through the lower interlayer insulating layer and the insulating pattern in the vertical direction, and the lower source / drain contact member is electrically connected to the second source / drain region; a sacrificial pattern contacts the lower surface of the first source / drain region, and the sacrificial pattern includes silicon germanium; a first insulating liner layer contacts two side walls of the sacrificial pattern in the first horizontal direction, and the upper surface of the first insulating liner layer contacts the first source / drain region; and a second insulating liner layer contacts at least a portion of the two side walls of the lower source / drain contact member in the first horizontal direction, and the upper surface of the second insulating liner layer contacts the second source / drain region, and the vertical height of the upper surface of the second insulating liner layer is lower than the vertical height of the upper surface of the field insulating layer.

[0008] According to some embodiments of the present disclosure, a semiconductor device is provided, comprising: a lower interlayer insulating layer; an insulating pattern extending in a first horizontal direction on an upper surface of the lower interlayer insulating layer; a plurality of semiconductor nanosheets stacked on the upper surface of the insulating pattern, and each of the plurality of semiconductor nanosheets is spaced apart from each other in a vertical direction; a field insulating layer disposed on the upper surface of the lower interlayer insulating layer, the field insulating layer covering sidewalls of the insulating pattern; a gate electrode extending in a second horizontal direction different from the first horizontal direction on the insulating pattern, the gate electrode surrounding each of the plurality of semiconductor nanosheets; a first source / drain region disposed on the insulating pattern at a first side of the gate electrode, and a second source / drain region disposed on the insulating pattern at a second side of the gate electrode opposite to the first side of the gate electrode in the first horizontal direction; an upper interlayer insulating layer covering the first source / drain region and the second source / drain region on the field insulating layer; an upper source / drain contact penetrating the upper interlayer insulating layer in a vertical direction, the upper source / drain contact being electrically connected to the gate electrode. a first source / drain region; a lower source / drain contact passing through the lower interlayer insulating layer and the insulating pattern in a vertical direction, the lower source / drain contact being electrically connected to the second source / drain region, the lower source / drain contact comprising a first portion disposed below the second source / drain region and a second portion disposed below the first portion; a sacrificial pattern in contact with a lower surface of the first source / drain region, the sacrificial pattern comprising silicon germanium (SiGe); a first insulating liner in contact with two sidewalls of the sacrificial pattern in a first horizontal direction, the first insulating liner The upper surface of the pad layer contacts the first source / drain region, the vertical height of the lower surface of the first insulating pad layer is higher than the vertical height of the lower surface of the sacrificial pattern, and the second insulating pad layer contacts the two side walls of the first part of the lower source / drain contact in the first horizontal direction, the upper surface of the second insulating pad layer contacts the second source / drain region, the vertical height of the upper surface of the second insulating liner layer is lower than the vertical height of the upper surface of the field insulating layer, and the lower surface of the second insulating liner layer contacts the upper surface of the second part of the lower source / drain contact.

[0009] The objects and benefits of the embodiments of the present disclosure are not limited to the above-described embodiments. Other objects and advantages of the present disclosure that are not mentioned can be understood based on the following description and can be more clearly understood based on the description of the illustrative embodiments of the present disclosure. In addition, it will be readily understood that the objects and advantages of the present disclosure can be achieved using the devices shown in the claims and their combinations. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects and features of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the attached drawings.

[0011] Figure 1is a layout diagram illustrating a semiconductor device according to some embodiments of the present disclosure.

[0012] Figure 2 It is along Figure 1 Cross-sectional view taken along line AA'.

[0013] Figure 3 It is along Figure 1 Cross-sectional view taken along line BB'.

[0014] Figure 4 It is along Figure 1 Cross-sectional view taken along line C-C'.

[0015] Figure 5 、 Figure 6 、 Figure 7 、 Figure 8 、 Figure 9 、 Figure 10 、 Figure 11 、 Figure 12 、 Figure 13 、 Figure 14 、 Figure 15 、 Figure 16 、 Figure 17 、 Figure 18 、 Figure 19 、 Figure 20 、 Figure 21 、 Figure 22 、 Figure 23 、 Figure 24 、 Figure 25 、 Figure 26 、 Figure 27 、 Figure 28 、 Figure 29 、 Figure 30 、 Figure 31 、 Figure 32 、 Figure 33 、 Figure 34 、 Figure 35 、 Figure 36 and Figure 37 are diagrams illustrating intermediate structures corresponding to intermediate steps of a method for fabricating a semiconductor device according to some embodiments of the present disclosure.

[0016] Figure 38 and Figure 39 is a cross-sectional view illustrating a semiconductor device according to another embodiment of the present disclosure.

[0017] Figure 40 and Figure 41 is a cross-sectional view illustrating a semiconductor device according to another embodiment of the present disclosure.

[0018] Figure 42 and Figure 43 is a cross-sectional view illustrating a semiconductor device according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0019] The present disclosure will now be described more fully below with reference to the accompanying drawings in which various embodiments are shown. However, the present disclosure can be implemented in many different forms and should not be construed as limited to the example embodiments set forth herein. It should also be emphasized that the present disclosure provides details of optional examples, but this list of alternatives is not exhaustive. In addition, any consistency in details between the various examples should not be construed as requiring such details. Reference should be made to the language of the claims when determining the requirements of the present disclosure.

[0020] As used herein, the term "dummy" is used to refer to a component that has the same or similar structure and shape as an associated non-dummy component but does not perform the substantive function provided by the associated non-dummy component. In some cases, a "dummy" component can be electrically floating, or can be connected to various voltage sources but otherwise does not provide the same function of the non-dummy component it represents. For example, a dummy word line may not be connected to a memory cell, or may have a dummy memory cell connected thereto (wherein no data is read from the dummy memory cell). In some cases, a "dummy" element may also be a "sacrificial" element.

[0021] As used herein, the term "sacrificial" refers to a component that has the same or similar structure and shape as an associated non-sacrificial component, but may be formed of a different material and does not perform the substantial function provided by the associated non-sacrificial component. Additionally, some sacrificial components may be removed during manufacturing and replaced with non-sacrificial components, but in such cases, portions of the sacrificial components may remain in the finished product and still be referred to as sacrificial components.

[0022] Throughout this specification, when a component is described as "comprising" a particular element or group of elements, it should be understood that, unless the context indicates otherwise, the component is formed solely of the element or group of elements, or that the element or group of elements may be combined with additional elements to form the component. On the other hand, the term "consisting of" indicates that the component is formed solely of the listed element(s).

[0023] It will be understood that when an element is referred to as being “connected” or “coupled” to another element or being “on” another element, the element can be directly connected or coupled to or directly on the other element, or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, or as being “contacting” or “in contact with” another element (or any form of the word “contacting” is used), there are no intervening elements at the point of contact.

[0024] As used herein, components described as "electrically connected" are configured so that electrical signals can be transmitted from one component to another (although such electrical signals may be attenuated in strength as they are transmitted and may be selectively transmitted). Furthermore, components "directly electrically connected" form a common electrical node through electrical connection via one or more conductors (such as, for example, wires, pads, internal wires, through-vias, etc.). Thus, components directly electrically connected do not include components electrically connected through active elements (such as transistors or diodes).

[0025] As used herein, terms such as "same," "equal," "planar," "coplanar," "parallel," and "perpendicular" encompass identity or near identity, including variations that may occur due to conventional manufacturing processes. Unless the context or other statements indicate otherwise, the term "substantially" may be used herein to emphasize this meaning.

[0026] Ordinal numbers (such as "first," "second," "third," etc.) may simply be used as labels for specific elements, steps, etc. to distinguish them from one another. Terms not described with "first," "second," etc. in the specification may still be referred to as "first" or "second" in the claims. Furthermore, a term referenced with a specific ordinal number (e.g., "first") in a particular claim may be described elsewhere in the specification or in another claim with a different ordinal number (e.g., "second").

[0027] Hereinafter, in the drawings related to a semiconductor device according to some embodiments, a semiconductor device including a transistor MBCFET including a nanosheet is described. TM Examples of multi-bridge channel field-effect transistors are provided. However, the present disclosure is not limited thereto. In some embodiments, the semiconductor device may include a fin transistor (FinFET), a tunneling FET (field-effect transistor), or a three-dimensional (3D) transistor including a channel region having a fin-shaped pattern. Furthermore, the semiconductor device according to some embodiments may include a bipolar junction transistor or a lateral double-diffused MOS (metal oxide semiconductor) transistor (LDMOS). The semiconductor device may be a semiconductor chip in which an integrated circuit (such as a logic circuit formed by interconnecting the transistors described herein) is formed.

[0028] In the following, reference is made to Figures 1 to 4 Semiconductor devices according to some embodiments of the present disclosure are described.

[0029] Figure 1 is a layout diagram illustrating a semiconductor device according to some embodiments of the present disclosure. Figure 2 It is along Figure 1 Cross-sectional view taken along line AA'. Figure 3 It is along Figure 1Cross-sectional view taken along line BB'. Figure 4 It is along Figure 1 Cross-sectional view taken along line C-C'.

[0030] Reference Figures 1 to 4 The semiconductor device according to some embodiments of the present disclosure includes a lower interlayer insulating layer 100, an insulating pattern 101, a field insulating layer 105, a first plurality of nanosheets to a third plurality of nanosheets NW1, NW2, and NW3, a first gate electrode to a third gate electrode G1, G2, and G3, a first gate spacer to a third gate spacer 111, 112, and 113, a first gate insulating layer to a third gate insulating layer 121, 122, and 123, and a first capping pattern to a third capping pattern 131, 132, and 133. , a first source / drain region SD1 and a second source / drain region SD2, a first sacrificial pattern 141, a first insulating liner layer 151 and a second insulating liner layer 152, a first etch stop layer 160, a first upper interlayer insulating layer 170, a gate contact CB, an upper source / drain contact UCA, a lower source / drain contact BCA, an upper silicide layer USL, a lower silicide layer BSL, a second etch stop layer 180, a second upper interlayer insulating layer 190 and a first via V1 and a second via V2.

[0031] The lower interlayer insulating layer 100 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material. The low dielectric constant material may include, for example, fluorinated tetraethylorthosilicate (FTEOS), hydrogen silsesquioxane (HSQ), bisbenzocyclobutene (BCB), tetramethylorthosilicate (TMOS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS), trimethylsilylborate (TMSB), diacetoxydi-tert-butylsiloxane (DADBS), trimethylsilylphosphate (TMSP), polytetrafluoroethylene (PTFE), TOSZ (Tonen SilaZen), FSG (fluorinated silicate glass), nanofoam (such as polypropylene oxide or polyimide), CDO (carbon-doped silicon oxide), OSG (organosilicate glass), SiLK, amorphous fluorinated carbon, silica aerogel, silica xerogel, mesoporous silica, or a combination thereof. However, the present disclosure is not limited thereto.

[0032] Hereinafter, each of the first horizontal direction DR1 and the second horizontal direction DR2 may be defined as a direction parallel to the upper surface of the lower interlayer insulating layer 100. The second horizontal direction DR2 may be defined as a direction different from the first horizontal direction DR1. The vertical direction DR3 may be defined as a direction perpendicular to each of the first horizontal direction DR1 and the second horizontal direction DR2. That is, the vertical direction DR3 may be defined as a direction perpendicular to the upper surface of the lower interlayer insulating layer 100.

[0033] The insulating pattern 101 may extend in the first horizontal direction DR1 and may be disposed on the upper surface of the lower interlayer insulating layer 100. The insulating pattern 101 may protrude from the upper surface of the lower interlayer insulating layer 100 in the vertical direction DR3. The insulating pattern 101 may include an insulating material. For example, the insulating pattern 101 may include the same material as the lower interlayer insulating layer 100.

[0034] The field insulation layer 105 may be disposed on the upper surface of the lower interlayer insulation layer 100. The field insulation layer 105 may surround and / or cover the sidewalls of the insulation pattern 101. The upper surface of the insulation pattern 101 may protrude beyond the upper surface of the field insulation layer 105 in the vertical direction DR3. However, the present disclosure is not limited thereto. In some embodiments, the upper surface of the insulation pattern 101 may be coplanar with the upper surface of the field insulation layer 105. The field insulation layer 105 may include, for example, an oxide film, a nitride film, an oxynitride film, or a combination thereof.

[0035] A first plurality of nanosheets NW1 may be disposed on the insulating pattern 101. The first plurality of nanosheets NW1 may be disposed in a region where the insulating pattern 101 and the first gate electrode G1 intersect each other. A second plurality of nanosheets NW2 may be disposed on the insulating pattern 101. The second plurality of nanosheets NW2 may be disposed in a region where the insulating pattern 101 and the second gate electrode G2 intersect each other. The second plurality of nanosheets NW2 may be spaced apart from the first plurality of nanosheets NW1 in the first horizontal direction DR1. A third plurality of nanosheets NW3 may be disposed on the insulating pattern 101. The third plurality of nanosheets NW3 may be disposed in a region where the insulating pattern 101 and the third gate electrode G3 intersect each other. The third plurality of nanosheets NW3 may be spaced apart from the second plurality of nanosheets NW2 in the first horizontal direction DR1.

[0036] Each of the first to third pluralities of nanosheets NW1, NW2, and NW3 may include a plurality of stacked nanosheets, and individual nanosheets in each plurality of nanosheets are spaced apart from each other in the vertical direction DR3. Figure 2 and Figure 3In the figure, each of the first to third pluralities of nanosheets NW1, NW2, and NW3 is shown as comprising three nanosheets stacked and spaced apart in the vertical direction DR3. However, this is for ease of illustration, and the present disclosure is not limited thereto. In some embodiments, each of the first to third pluralities of nanosheets NW1, NW2, and NW3 may comprise four or more nanosheets stacked and spaced apart in the vertical direction DR3. Each nanosheet may be a two-dimensional nanostructure having a thickness ranging from 1 nm to 100 nm. Each nanosheet in the first to third pluralities of nanosheets NW1, NW2, and NW3 may be a semiconductor nanosheet. For example, each nanosheet in the first to third pluralities of nanosheets NW1, NW2, and NW3 may comprise silicon (Si). However, the present disclosure is not limited thereto. In some embodiments, each nanosheet in the first to third pluralities of nanosheets NW1, NW2, and NW3 may comprise silicon germanium (SiGe).

[0037] The first gate electrode G1 may extend in the second horizontal direction DR2 and be disposed on the insulating pattern 101 and the field insulating layer 105. The first gate electrode G1 may surround the first plurality of nanosheets NW1 (for example, each nanosheet in the first plurality of nanosheets NW1 may be surrounded by the first gate electrode, and the first gate electrode may extend in each space between adjacent nanosheets). The second gate electrode G2 may extend in the second horizontal direction DR2 and be disposed on the insulating pattern 101 and the field insulating layer 105. The second gate electrode G2 may surround the second plurality of nanosheets NW2. The second gate electrode G2 may be spaced apart from the first gate electrode G1 in the first horizontal direction DR1. The third gate electrode G3 may extend in the second horizontal direction DR2 and be disposed on the insulating pattern 101 and the field insulating layer 105. The third gate electrode G3 may surround the third plurality of nanosheets NW3. The third gate electrode G3 may be spaced apart from the second gate electrode G2 in the first horizontal direction DR1.

[0038] Each of the first to third gate electrodes G1, G2, and G3 may include, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TCN), or the like. At least one of (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and combinations thereof. Each of the first to third gate electrodes G1, G2, and G3 may include a conductive metal oxide, a conductive metal oxynitride, or the like, or may include an oxidation product of the above materials.

[0039] The first gate spacer 111 may be disposed on the upper surface of the uppermost nanosheet in the first plurality of nanosheets NW1 and the field insulating layer 105, and may extend along two opposing sidewalls of the first gate electrode G1 and in the second horizontal direction DR2. The second gate spacer 112 may be disposed on the upper surface of the uppermost nanosheet in the second plurality of nanosheets NW2 and the field insulating layer 105, and may extend along two opposing sidewalls of the second gate electrode G2 and in the second horizontal direction DR2. The third gate spacer 113 may be disposed on the upper surface of the uppermost nanosheet in the third plurality of nanosheets NW3 and the field insulating layer 105, and may extend along two opposing sidewalls of the third gate electrode G3 and in the second horizontal direction DR2.

[0040] Each of the first to third gate spacers 111, 112, and 113 may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon oxycarbonitride (SiOCN), silicon boronitride (SiBN), silicon oxyboronitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof. However, the present disclosure is not limited thereto.

[0041] The first source / drain region SD1 may be disposed between the first gate electrode G1 and the second gate electrode G2 and on the insulating pattern 101. The first source / drain region SD1 may contact sidewalls of the first plurality of nanosheets NW1 facing the first horizontal direction DR1 and sidewalls of the second plurality of nanosheets NW2 facing the first horizontal direction DR1. The second source / drain region SD2 may be disposed between the second gate electrode G2 and the third gate electrode G3 and on the insulating pattern 101. The second source / drain region SD2 may contact sidewalls of the second plurality of nanosheets NW2 facing the first horizontal direction DR1 and sidewalls of the third plurality of nanosheets NW3 facing the first horizontal direction DR1.

[0042] A lower surface of each of the first and second source / drain regions SD1 and SD2 may be positioned at a vertical height lower than a vertical height of an upper surface of the insulating pattern 101. A portion of a sidewall of each of the first and second source / drain regions SD1 and SD2 facing the first horizontal direction DR1 may contact the insulating pattern 101. A lower surface of each of the first and second source / drain regions SD1 and SD2 may be positioned at a vertical height lower than a vertical height of an upper surface of the field insulating layer 105. A portion of a sidewall of each of the first and second source / drain regions SD1 and SD2 facing the second horizontal direction DR2 may contact the field insulating layer 105. An upper surface of each of the first and second source / drain regions SD1 and SD2 may be positioned at a vertical height higher than a vertical height of an uppermost nanosheet of each of the first to third pluralities of nanosheets NW1, NW2, and NW3.

[0043] The first gate insulating layer 121 may be disposed between the first gate electrode G1 and the insulating pattern 101. The first gate insulating layer 121 may be disposed between the first gate electrode G1 and the field insulating layer 105. The first gate insulating layer 121 may be disposed between the first gate electrode G1 and the first gate spacer 111. The first gate insulating layer 121 may be disposed between the first gate electrode G1 and the first plurality of nanosheets NW1. The first gate insulating layer 121 may be disposed between the first gate electrode G1 and the first source / drain region SD1.

[0044] The second gate insulating layer 122 may be disposed between the second gate electrode G2 and the insulating pattern 101. The second gate insulating layer 122 may be disposed between the second gate electrode G2 and the field insulating layer 105. The second gate insulating layer 122 may be disposed between the second gate electrode G2 and the second gate spacer 112. The second gate insulating layer 122 may be disposed between the second gate electrode G2 and the second plurality of nanosheets NW2. The second gate insulating layer 122 may be disposed between the second gate electrode G2 and each of the first source / drain region SD1 and the second source / drain region SD2.

[0045] The third gate insulating layer 123 may be disposed between the third gate electrode G3 and the insulating pattern 101. The third gate insulating layer 123 may be disposed between the third gate electrode G3 and the field insulating layer 105. The third gate insulating layer 123 may be disposed between the third gate electrode G3 and the third gate spacer 113. The third gate insulating layer 123 may be disposed between the third gate electrode G3 and the third plurality of nanosheets NW3. The third gate insulating layer 123 may be disposed between the third gate electrode G3 and the second source / drain region SD2.

[0046] Each of the first to third gate insulating layers 121, 122, and 123 may contact the insulating pattern 101. Each of the first and second gate insulating layers 121, 122 may contact the first source / drain region SD1. Furthermore, each of the second and third gate insulating layers 122, 123 may contact the second source / drain region SD2. However, the present disclosure is not limited thereto. In some embodiments, an inner spacer may be disposed between each of the first and second gate insulating layers 121, 122 and the first source / drain region SD1. Furthermore, an inner spacer may be disposed between each of the second and third gate insulating layers 122, 123 and the second source / drain region SD2. The inner spacer may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon oxycarbonitride (SiOCN), silicon boronitride (SiBN), silicon oxyboronitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof. The present disclosure is not limited thereto.

[0047] Each of the first to third gate insulating layers 121, 122, and 123 may include at least one of silicon oxide, silicon oxynitride, silicon nitride, and a high dielectric constant material having a dielectric constant higher than that of silicon oxide. The high dielectric constant material may include, for example, at least one of hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0048] The semiconductor device according to some embodiments may include an NC (negative capacitance) FET using a negative capacitor. Each of the first to third gate insulating layers 121 , 122 , and 123 may include a ferroelectric material film having ferroelectric properties and a paraelectric material film having paraelectric properties.

[0049] A ferroelectric material film may have a negative capacitance, and a paraelectric material film may have a positive capacitance. For example, when two or more capacitors are connected in series and the capacitance of each capacitor has a positive value, the total capacitance is less than the capacitance of each individual capacitor. Conversely, when at least one of the capacitances of two or more capacitors connected in series has a negative value, the total capacitance may have a positive value and be greater than the absolute value of each individual capacitor.

[0050] When a ferroelectric material film having negative capacitance and a paraelectric material film having positive capacitance are connected in series, the total capacitance of the ferroelectric and paraelectric material films connected in series can be increased. This increase in total capacitance allows a transistor including the ferroelectric material film to have a subthreshold swing (SS) of less than 60 mV / decade at room temperature.

[0051] The ferroelectric material film may have ferroelectric properties. For example, the ferroelectric material film may include at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. In this regard, in one example, hafnium zirconium oxide may refer to a material obtained by doping hafnium oxide with zirconium (Zr). In another example, hafnium zirconium oxide may refer to a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0052] The ferroelectric material film may further include a dopant. For example, the dopant may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), zirconium (Zr), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). The type of dopant included in the ferroelectric material film may vary depending on the type of ferroelectric material included in the ferroelectric material film.

[0053] When the ferroelectric material film includes hafnium oxide, the dopant contained in the ferroelectric material film may include, for example, at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and yttrium (Y).

[0054] When the dopant is aluminum (Al), the ferroelectric material film may include 3 at % (atomic %) to 8 at % (atomic %) of aluminum. In this regard, the content of the dopant may be the content of aluminum based on the total of hafnium and aluminum.

[0055] When the dopant is silicon (Si), the ferroelectric material film may contain 2 to 10 at% silicon. When the dopant is yttrium (Y), the ferroelectric material film may contain 2 to 10 at% yttrium. When the dopant is gadolinium (Gd), the ferroelectric material film may contain 1 to 7 at% Gd. When the dopant is zirconium (Zr), the ferroelectric material film may contain 50 to 80 at% zirconium.

[0056] The paraelectric material film may have paraelectric properties. The paraelectric material film may include, for example, at least one of silicon oxide and a metal oxide having a high dielectric constant. The metal oxide contained in the paraelectric material film may include, for example, at least one of hafnium oxide, zirconium oxide, and aluminum oxide. However, the present disclosure is not limited thereto.

[0057] The ferroelectric material film and the paraelectric material film may include the same material. The ferroelectric material film may have ferroelectric properties, but the paraelectric material film may not have ferroelectric properties. For example, when each of the ferroelectric material film and the paraelectric material film includes hafnium oxide, the crystal structure of the hafnium oxide contained in the ferroelectric material film is different from the crystal structure of the hafnium oxide contained in the paraelectric material film.

[0058] The ferroelectric material film may have a thickness sized to exhibit ferroelectric properties. Although the thickness of the ferroelectric material film may be, for example, in the range of 0.5 nm to 10 nm, the present disclosure is not limited thereto. Because the critical thickness for exhibiting ferroelectric properties may vary based on the type of ferroelectric material, the thickness of the ferroelectric material film may vary depending on the type of ferroelectric material.

[0059] In one example, each of the first to third gate insulating layers 121, 122, and 123 may include one ferroelectric material film. In another example, each of the first to third gate insulating layers 121, 122, and 123 may include a plurality of ferroelectric material films spaced apart from each other. Each of the first to third gate insulating layers 121, 122, and 123 may have a stacked film structure in which a plurality of ferroelectric material films and a plurality of paraelectric material films are alternately stacked on top of each other.

[0060] A first etch stop layer 160 may be disposed on a sidewall of each of the first to third gate spacers 111, 112, and 113 that faces the first horizontal direction DR1. The first etch stop layer 160 may be disposed on an upper surface of each of the first and second source / drain regions SD1 and SD2. The first etch stop layer 160 may be disposed on a sidewall of each of the first and second source / drain regions SD1 and SD2 that faces the second horizontal direction DR2. The first etch stop layer 160 may be conformally formed. The first etch stop layer 160 may include at least one of aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, silicon oxide, silicon nitride, silicon oxynitride, and a low-k dielectric constant material.

[0061] The first covering pattern 131 may extend in the second horizontal direction DR2 and be disposed on each of the first gate spacer 111, the first gate insulating layer 121, and the first gate electrode G1. The second covering pattern 132 may extend in the second horizontal direction DR2 and be disposed on each of the second gate spacer 112, the second gate insulating layer 122, and the second gate electrode G2. The third covering pattern 133 may extend in the second horizontal direction DR2 and be disposed on each of the third gate spacer 113, the third gate insulating layer 123, and the third gate electrode G3. The lower surface of each of the first to third covering patterns 131, 132, and 133 may contact the first etch-stop layer 160. However, the present disclosure is not limited thereto. In some embodiments, the sidewalls of each of the first to third covering patterns 131, 132, and 133 may contact the first etch-stop layer 160. Each of the first to third capping patterns 131, 132, and 133 may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and combinations thereof. However, the present disclosure is not limited thereto.

[0062] A first upper interlayer insulating layer 170 may be disposed on the first etch stop layer 160. The first upper interlayer insulating layer 170 may be disposed on the sidewalls of each of the first to third capping patterns 131, 132, and 133. The first upper interlayer insulating layer 170 may cover the first source / drain region SD1 and the second source / drain region SD2 while being disposed on the field insulating layer 105. The upper surface of the first upper interlayer insulating layer 170 may be coplanar with the upper surface of each of the first to third capping patterns 131, 132, and 133. The first upper interlayer insulating layer 170 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material.

[0063] A first sacrificial pattern 141 may be disposed below the first source / drain region SD1. The upper surface of the first sacrificial pattern 141 may contact the lower surface of the first source / drain region SD1. Each of two opposing sidewalls of the first sacrificial pattern 141 in the first horizontal direction DR1 may contact the insulating pattern 101 and the lower interlayer insulating layer 100. The lower surface of the first sacrificial pattern 141 may contact the lower interlayer insulating layer 100. However, the present disclosure is not limited thereto. In some embodiments, the lower surface of the first sacrificial pattern 141 may contact the insulating pattern 101.

[0064] The upper surface of the first sacrificial pattern 141 may be positioned at a lower vertical height than the upper surface of the insulating pattern 101. Although not shown, the upper surface of the first sacrificial pattern 141 may be positioned at a lower vertical height than the upper surface of the field insulating layer 105. The width of the first sacrificial pattern 141 in the first horizontal direction DR1 may be smaller than the width of the first source / drain region SD1 in the first horizontal direction DR1. The first sacrificial pattern 141 may include silicon germanium (SiGe).

[0065] A lower source / drain contact BCA may be disposed below the second source / drain region SD2. The lower source / drain contact BCA may penetrate (or pass through) the lower interlayer insulating layer 100 and the insulating pattern 101 in the vertical direction DR3 to electrically connect to the second source / drain region SD2. The lower source / drain contact BCA may include a first portion BCA_1 and a second portion BCA_2 disposed below the first portion BCA_1.

[0066] The first portion BCA_1 of the lower source / drain contact BCA may overlap the insulating pattern 101 in the first horizontal direction DR1. The first portion BCA_1 of the lower source / drain contact BCA may be spaced apart from the insulating pattern 101 in the first horizontal direction DR1. The first portion BCA_1 of the lower source / drain contact BCA may overlap the field insulating layer 105 in the second horizontal direction DR2. The first portion BCA_1 of the lower source / drain contact BCA may be spaced apart from the field insulating layer 105 in the second horizontal direction DR2.

[0067] An upper surface of the second portion BCA_2 of the lower source / drain contact BCA may contact a lower surface of the first portion BCA_1 of the lower source / drain contact BCA. Each of two opposing sidewalls of the second portion BCA_2 of the lower source / drain contact BCA in the first horizontal direction DR1 may contact the lower interlayer insulating layer 100 and the insulating pattern 101. Each of two opposing sidewalls of the second portion BCA_2 of the lower source / drain contact BCA in the second horizontal direction DR2 may contact the lower interlayer insulating layer 100 and the field insulating layer 105.

[0068] The width of the second portion BCA_2 of the lower source / drain contact BCA in the first horizontal direction DR1 may be greater than the width of the first portion BCA_1 of the lower source / drain contact BCA in the first horizontal direction DR1. Furthermore, the width of the second portion BCA_2 of the lower source / drain contact BCA in the second horizontal direction DR2 may be greater than the width of the first portion BCA_1 of the lower source / drain contact BCA in the second horizontal direction DR2. At least a portion of the upper surface of the second portion BCA_2 of the lower source / drain contact BCA may be in contact with the insulating pattern 101. However, the present disclosure is not limited to this. The lower source / drain contact BCA may be formed as a single film. However, the present disclosure is not limited to this. In some embodiments, the lower source / drain contact BCA may be formed as a multilayer structure. The lower source / drain contact BCA may include a conductive material.

[0069] A lower silicide layer BSL may be disposed between the lower source / drain contact BCA and the second source / drain region SD2. The lower silicide layer BSL may be disposed along an interface between the lower source / drain contact BCA and the second source / drain region SD2. The lower silicide layer BSL may include, for example, a metal silicide material. The lower silicide layer BSL may overlap the insulating pattern 101 in the first horizontal direction DR1. Furthermore, the lower silicide layer BSL may overlap the field insulating layer 105 in the second horizontal direction DR2.

[0070] The first insulating liner layer 151 may be disposed below the first source / drain region SD1. The upper surface of the first insulating liner layer 151 may contact the lower surface of the first source / drain region SD1. The upper surface of the first insulating liner layer 151 may be coplanar with the upper surface of the first sacrificial pattern 141. Although not shown, the upper surface of the first insulating liner layer 151 may be positioned at a vertical height lower than the vertical height of the upper surface of the field insulating layer 105. For example, the lower surface of the first insulating liner layer 151 may be positioned at a vertical height higher than the vertical height of the lower surface of the first sacrificial pattern 141. The lower surface of the first insulating liner layer 151 may contact the insulating pattern 101. However, the present disclosure is not limited thereto. In some embodiments, the lower surface of the first insulating liner layer 151 may contact the lower interlayer insulating layer 100.

[0071] The first insulating liner layer 151 may surround a portion of the sidewalls of the first sacrificial pattern 141. For example, an inner sidewall of the first insulating liner layer 151 facing the first horizontal direction DR1 may contact the first sacrificial pattern 141. Although not shown, an inner sidewall of the first insulating liner layer 151 facing the second horizontal direction DR2 may contact the first sacrificial pattern 141. For example, an outer sidewall of the first insulating liner layer 151 facing the first horizontal direction DR1 may contact the insulating pattern 101. Although not shown, an outer sidewall of the first insulating liner layer 151 facing the second horizontal direction DR2 may contact the field insulating layer 105.

[0072] The slope of the outer sidewall of the first insulating liner layer 151 facing the first horizontal direction DR1 may be continuous with the slope of the sidewall of the first source / drain region SD1 facing the first horizontal direction DR1 (for example, the outer sidewall of the first insulating liner layer 151 facing the first horizontal direction DR1 may continuously contact the sidewall of the first source / drain region SD1 facing the first horizontal direction DR1, or the slope value of the outer sidewall of the first insulating liner layer 151 facing the first horizontal direction DR1 may be equal to the slope value of the sidewall of the first source / drain region SD1 facing the first horizontal direction DR1, or the outer sidewall of the first insulating liner layer 151 facing the first horizontal direction DR1 may have a profile complementary to the profile of the sidewall of the first source / drain region SD1 facing the first horizontal direction DR1, so that they are in contact or offset by a fixed distance). The first insulating liner layer 151 does not overlap with each of the first plurality of nanosheets NW1, the second plurality of nanosheets NW2, the first gate electrode G1, and the second gate electrode G2 in the vertical direction DR3.

[0073] A second insulating liner layer 152 may be disposed below the second source / drain region SD2. The upper surface of the second insulating liner layer 152 may contact the lower surface of the second source / drain region SD2. The upper surface of the second insulating liner layer 152 may be coplanar with the upper surface of the lower source / drain contact BCA. In other words, the upper surface of the second insulating liner layer 152 may be coplanar with the upper surface of the first portion BCA_1 of the lower source / drain contact BCA. The upper surface of the second insulating liner layer 152 may be positioned at a vertical height lower than the vertical height of the upper surface of the field insulating layer 105. The lower surface of the second insulating liner layer 152 may contact the upper surface of the second portion BCA_2 of the lower source / drain contact BCA. The upper surface of the second insulating liner layer 152 may not contact the lower silicide layer BSL. However, the present disclosure is not limited to this. In some embodiments, at least a portion of the upper surface of the second insulating liner layer 152 may contact the lower silicide layer BSL.

[0074] The second insulating liner layer 152 may surround the sidewalls of the first portion BCA_1 of the lower source / drain contact BCA. For example, the inner sidewall of the second insulating liner layer 152 facing the first horizontal direction DR1 may contact the first portion BCA_1 of the lower source / drain contact BCA. Furthermore, the inner sidewall of the second insulating liner layer 152 facing the second horizontal direction DR2 may contact the first portion BCA_1 of the lower source / drain contact BCA. For example, the outer sidewall of the second insulating liner layer 152 facing the first horizontal direction DR1 may contact the insulating pattern 101. The outer sidewall of the second insulating liner layer 152 in the second horizontal direction DR2 may contact the field insulating layer 105.

[0075] The slope of the outer sidewall of the second insulating liner layer 152 facing the first horizontal direction DR1 may be continuous with the slope of the sidewall of the second source / drain region SD2 facing the first horizontal direction DR1. The second insulating liner layer 152 does not overlap with each of the second and third nanosheets NW2, NW3, the second gate electrode G2, and the third gate electrode G3 in the vertical direction DR3.

[0076] The first insulating liner layer 151 and the second insulating liner layer 152 may include the same material. Each of the first insulating liner layer 151 and the second insulating liner layer 152 may include a material different from each of the insulating pattern 101 and the lower interlayer insulating layer 100. Each of the first insulating liner layer 151 and the second insulating liner layer 152 may include an insulating material having a low dielectric constant. For example, each of the first insulating liner layer 151 and the second insulating liner layer 152 may include silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), or silicon oxycarbonitride (SiOCN). However, the present disclosure is not limited thereto.

[0077] The upper source / drain contact UCA may be disposed between the first gate electrode G1 and the second gate electrode G2. The upper source / drain contact UCA may be disposed in the top of the first source / drain region SD1. The upper source / drain contact UCA may pass through the first upper interlayer insulating layer 170 and the first etch stop layer 160 in the vertical direction DR3 into the first source / drain region SD1. The upper source / drain contact UCA may be electrically connected to the first source / drain region SD1. Figure 2 , the upper source / drain contact UCA is shown as being formed as a single film. However, the present disclosure is not limited thereto. In some embodiments, the upper source / drain contact UCA may be formed as a multi-layer structure.

[0078] The upper surface of the upper source / drain contact UCA may be coplanar with the upper surface of the first upper interlayer insulating layer 170. However, the present disclosure is not limited thereto. In some embodiments, the upper surface of the upper source / drain contact UCA may be positioned at a vertical height higher than the vertical height of the upper surface of the first upper interlayer insulating layer 170. The upper source / drain contact UCA may include a conductive material.

[0079] The upper silicide layer USL may be disposed between the upper source / drain contact UCA and the first source / drain region SD1. The upper silicide layer USL may be disposed along an interface between the upper source / drain contact UCA and the first source / drain region SD1. The upper silicide layer USL may include a metal silicide material.

[0080] The gate contact CB may be disposed on top of the second gate electrode G2. The gate contact CB may penetrate the second capping pattern 132 in the vertical direction DR3 so as to be connected to the second gate electrode G2. Figure 3 In the figure, the gate contact CB is shown as being formed as a single film. However, the present disclosure is not limited thereto. In some embodiments, the gate contact CB may be formed as a multilayer structure. The upper surface of the gate contact CB may be coplanar with each of the upper surface of the upper source / drain contact UCA and the upper surface of the first upper interlayer insulating layer 170. However, the present disclosure is not limited thereto. The gate contact CB may include a conductive material.

[0081] The second etch stop layer 180 may be disposed on an upper surface of each of the upper source / drain contact UCA, the first to third capping patterns 131 , 132 , and 133 , and the first upper interlayer insulating layer 170 . Figures 2 to 4 , the second etch stop layer 180 is shown as being formed as a single film. However, the present disclosure is not limited thereto. In some embodiments, the second etch stop layer 180 may be formed as a multilayer structure. The second etch stop layer 180 may include at least one of aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material.

[0082] The second upper interlayer insulating layer 190 may be disposed on the second etch stop layer 180. The second upper interlayer insulating layer 190 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material.

[0083] The first via hole V1 may pass through the second upper interlayer insulating layer 190 and the second etch stop layer 180 in the vertical direction DR3 to be connected to the upper source / drain contact UCA. The second via hole V2 may penetrate the second upper interlayer insulating layer 190 and the second etch stop layer 180 in the vertical direction DR3 to be connected to the gate contact CB. Figure 2 and Figure 3In the embodiment, each of the first via hole V1 and the second via hole V2 is shown as being formed as a single film. However, the present disclosure is not limited thereto. In some embodiments, each of the first via hole V1 and the second via hole V2 may be formed as a multilayer structure. Each of the first via hole V1 and the second via hole V2 may include a conductive material.

[0084] In the following, reference is made to Figures 2 to 37 Methods for manufacturing semiconductor devices according to some embodiments of the present disclosure are described.

[0085] Figures 5 to 37 are diagrams of intermediate structures corresponding to intermediate steps of a method for fabricating a semiconductor device according to some embodiments of the present disclosure.

[0086] Reference Figure 5 and Figure 6 A substrate 10 may be provided. The substrate 10 may be a silicon substrate or a silicon-on-insulator (SOI). Alternatively, the substrate 10 may include silicon germanium, silicon germanium-on-insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. However, the present disclosure is not limited thereto.

[0087] Subsequently, a stacked structure 20 may be formed on the upper surface of the substrate 10. The stacked structure 20 may include a first semiconductor layer 21 and a second semiconductor layer 22, which are alternately stacked on top of each other and disposed on the upper surface of the substrate 10. For example, the first semiconductor layer 21 may be formed as the lowermost layer of the stacked structure 20, and the second semiconductor layer 22 may be formed as the uppermost layer of the stacked structure 20. However, the present disclosure is not limited thereto. In some embodiments, the first semiconductor layer 21 may be formed as the uppermost layer of the stacked structure 20. The first semiconductor layer 21 may include, for example, silicon germanium (SiGe). The second semiconductor layer 22 may include, for example, silicon (Si).

[0088] Subsequently, a portion of the stacked structure 20 may be etched. When etching the stacked structure 20, a portion of the substrate 10 may be etched. During this etching process, an active pattern 11 may be defined below the stacked structure 20 and on the upper surface of the substrate 10. The active pattern 11 may protrude from the upper surface of the substrate 10 in the vertical direction DR3. The active pattern 11 may extend in the first horizontal direction DR1.

[0089] Subsequently, a field insulation layer 105 may be formed on the upper surface of the substrate 10. The field insulation layer 105 may surround the sidewalls of the active pattern 11. The upper surface of the active pattern 11 may be positioned at a vertical height higher than the vertical height of the upper surface of the field insulation layer 105. Subsequently, a pad oxide layer 30 may be formed to cover the upper surface of the field insulation layer 105, the exposed sidewalls of each of the active patterns 11, and the sidewalls and upper surface of the stacked structure 20. The pad oxide layer 30 may be formed conformally. The pad oxide layer 30 may include, for example, silicon oxide (SiO2).

[0090] Reference Figure 7 and Figure 8 On the stacked structure 20 and the field insulating layer 105, first to third dummy gates DG1, DG2, and DG3 extending in the second horizontal direction DR2 and first to third dummy capping patterns DC1, DC2, and DC3 may be formed on the pad oxide layer 30. Specifically, the second dummy gate DG2 may be spaced apart from the first dummy gate DG1 in the first horizontal direction DR1. The third dummy gate DG3 may be spaced apart from the second dummy gate DG2 in the first horizontal direction DR1. The first dummy capping pattern DC1 may be disposed on the first dummy gate DG1. The second dummy capping pattern DC2 may be disposed on the second dummy gate DG2. The third dummy capping pattern DC3 may be disposed on the third dummy gate DG3. While forming the first to third dummy gates DG1, DG2, and DG3 and the first to third dummy cover patterns DC1, DC2, and DC3, the remaining portion of the pad oxide layer 30 except for the portion of the oxide layer 30 overlapping with each of the first to third dummy gates DG1, DG2, and DG3 in the vertical direction DR3 on the substrate 10 may be removed.

[0091] Next, a spacer material layer SM may be formed to cover the sidewalls of each of the first to third dummy gates DG1, DG2, and DG3, the sidewalls and upper surfaces of each of the first to third dummy capping patterns DC1, DC2, and DC3, the upper surface and exposed sidewalls of the stacked structure 20, and the upper surface of the field insulation layer 105. The spacer material layer SM may be formed conformally. The spacer material layer SM may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon oxycarbonitride (SiOCN), silicon boronitride (SiBN), silicon oxyboronitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof. However, the present disclosure is not limited thereto.

[0092] Reference Figure 9 and Figure 10, using the first to third dummy gates DG1, DG2, and DG3 and the first to third dummy cover patterns DC1, DC2, and DC3 as masks, the stacked structure can be etched ( Figure 7 20) to form a first source / drain trench ST1 and a second source / drain trench ST2. The first source / drain trench ST1 may be formed between the first dummy gate DG1 and the second dummy gate DG2. The second source / drain trench ST2 may be formed between the second dummy gate DG2 and the third dummy gate DG3. The lower surface of the second source / drain trench ST2 may be positioned at a vertical height lower than the vertical height of the upper surface of the field insulating layer 105. Although not shown, the bottom surface of the first source / drain trench ST1 may be positioned at a vertical height lower than the vertical height of the upper surface of the field insulating layer 105.

[0093] While forming the first source / drain trench ST1 and the second source / drain trench ST2, the spacer material layer ( Figure 7 The spacer material layer (SM) is formed on a portion of the upper surface of each of the first to third dummy cover patterns DC1, DC2, and DC3 and a portion of each of the first to third dummy cover patterns DC1, DC2, and DC3. Figure 7 Portions of the SM in FIG5 remaining on sidewalls of the first to third dummy capping patterns DC1, DC2, and DC3 and the first to third dummy gates DG1, DG2, and DG3 may be defined as first to third gate spacers 111, 112, and 113, respectively.

[0094] After forming the first source / drain trench ST1 and the second source / drain trench ST2, the second semiconductor layer ( Figure 7 A portion of the active pattern 11 remaining below the first dummy gate DG1 in 22 ) may be defined as a first plurality of nanosheets NW1 .

[0095] After forming the first source / drain trench ST1 and the second source / drain trench ST2, the second semiconductor layer ( Figure 7 The portion of the second semiconductor layer ( 22 ) remaining below the second dummy gate DG2 and on the active pattern 11 may be defined as a second plurality of nanosheets NW2 . After forming the first source / drain trench ST1 and the second source / drain trench ST2 , the second semiconductor layer ( Figure 7 The portion of 22 ) remaining under the third dummy gate DG3 and on the active pattern 11 may be defined as a third plurality of nanosheets NW3 .

[0096] Reference Figure 11 and Figure 12An insulating material layer 150 may be formed on the sidewalls and bottom surface of each of the first source / drain trench ST1 and the second source / drain trench ST2. For example, the insulating material layer 150 may be formed on the upper surface of the field insulating layer 105, the sidewalls of each of the first to third gate spacers 111, 112, and 113, and the upper surface of each of the first to third dummy capping patterns DC1, DC2, and DC3. For example, the insulating material layer 150 may be formed conformally. The insulating material layer 150 may include an insulating material having a low dielectric constant. For example, the insulating material layer 150 may include silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), or silicon oxycarbonitride (SiOCN). However, the present disclosure is not limited thereto.

[0097] Reference Figure 13 and Figure 14 , can be in the first source / drain trench and the second source / drain trench ( Figure 11 The third source / drain trench ST3 and the fourth source / drain trench ST4 are formed inside the first source / drain trench ( ST1 and ST2 ). For example, the first source / drain trench ( Figure 11 The insulating material layer 150 on the bottom surface of the substrate 10 (ST1 in the figure), the active pattern 11 and a portion of each of the substrate 10 are etched to form a third source / drain trench ST3 extending into the interior of the substrate 10. In addition, the second source / drain trench (ST1 in the figure) may be etched. Figure 11 and Figure 12 The insulating material layer 150 on the bottom surface of the substrate ST2 ), the active pattern 11 , and a portion of each of the substrate 10 are formed to form a fourth source / drain trench ST4 extending into the inner portion of the substrate 10 .

[0098] When forming the third source / drain trench ST3 and the fourth source / drain trench ST4, a portion of the insulating material layer 150 formed on the upper surface of the field insulating layer 105 and the upper surface of each of the first to third dummy capping patterns DC1, DC2, and DC3 may be etched. A portion of the insulating material layer 150 may remain on each of two opposing sidewalls of each of the third source / drain trench ST3 and the fourth source / drain trench ST4 in the first horizontal direction DR1. In addition, a portion of the insulating material layer 150 may remain on each of two opposing sidewalls of each of the third source / drain trench ST3 and the fourth source / drain trench ST4 in the second horizontal direction DR2.

[0099] Reference Figure 15 and Figure 16 , can be in the third source / drain trench ( Figure 13 A first sacrificial pattern 141 is formed inside the fourth source / drain trench ( Figure 13 and Figure 14 A second sacrificial pattern 142 is formed inside (ST4 in FIG). The upper surface of each of the first and second sacrificial patterns 141 and 142 may be positioned at a vertical height lower than the vertical height of the uppermost surface of the active pattern 11. The upper surface of each of the first and second sacrificial patterns 141 and 142 may be positioned at a vertical height lower than the vertical height of the upper surface of the field insulation layer 105. The lower surface of each of the first and second sacrificial patterns 141 and 142 may be positioned at a vertical height lower than the vertical height of the lower surface of the insulating material layer 150. At least a portion of each of two opposing sidewalls of each of the first and second sacrificial patterns 141 and 142 in the first horizontal direction DR1 may contact the insulating material layer 150. At least a portion of each of two opposing sidewalls of each of the first and second sacrificial patterns 141 and 142 in the second horizontal direction DR2 may contact the insulating material layer 150.

[0100] Reference Figure 17 and Figure 18 , can etch the insulating material layer ( Figure 15 and Figure 16 150) that is not covered by the upper surface of each of the first sacrificial pattern 141 and the second sacrificial pattern 142 (eg, the insulating material layer ( Figure 15 and Figure 16 The portion of the first sacrificial pattern 141 and the second sacrificial pattern 142 that does not overlap with each of the first and second sacrificial patterns 141 and 142 in the first and second horizontal directions DR1 and DR2 is formed to form each of the fifth source / drain trench ST5 and the sixth source / drain trench ST6. For example, the insulating material layer ( Figure 15 The portion of the first sacrificial pattern 141 not covered by the upper surface of the first sacrificial pattern 150 is etched to form a fifth source / drain trench ST5. Figure 15 and Figure 16 The portion of the insulating material layer 150 not covered by the upper surface of the second sacrificial pattern 142 is formed to form the sixth source / drain trench ST6. After forming the fifth source / drain trench ST5, the insulating material layer ( Figure 15 The remaining portion of the insulating material layer ( 150 ) is defined as a first insulating liner layer 151 . In addition, after forming the sixth source / drain trench ST6 , the insulating material layer ( Figure 15 and Figure 16 The remaining portion of 150 ) is defined as a second insulating liner layer 152 .

[0101] The upper surface of each of the first insulating liner layer 151 and the second insulating liner layer 152 may be positioned at a vertical height lower than the vertical height of the uppermost surface of the active pattern 11. The upper surface of the second insulating liner layer 152 may be positioned at a vertical height lower than the vertical height of the upper surface of the field insulating layer 105. Although not shown, the upper surface of the first insulating liner layer 151 may be positioned at a vertical height lower than the vertical height of the upper surface of the field insulating layer 105. The upper surface of the first insulating liner layer 151 may be coplanar with the upper surface of the first sacrificial pattern 141. In addition, the upper surface of the second insulating liner layer 152 may be coplanar with the upper surface of the second sacrificial pattern 142.

[0102] Reference Figure 19 and Figure 20 , can be inside the fifth source / drain trench ( Figure 17 ST5 in the figure) forms the first source / drain region SD1. In addition, the sixth source / drain trench ( Figure 17 A second source / drain region SD2 is formed inside (ST6 in step 1). A lower surface of the first source / drain region SD1 may contact each of the upper surfaces of the first sacrificial pattern 141 and the first insulating liner layer 151. Furthermore, a lower surface of the second source / drain region SD2 may contact each of the upper surfaces of the second sacrificial pattern 142 and the second insulating liner layer 152.

[0103] Subsequently, the exposed upper surface of the field insulating layer 105, the exposed sidewall of each of the first to third gate spacers 111, 112, and 113, the first to third dummy capping patterns ( Figure 17 A first etch stop layer 160 is formed on the exposed upper surface of each of the first source / drain region SD1 and the second source / drain region SD2, and on the exposed upper surface of each of the first source / drain region SD1 and the second source / drain region SD2. The first etch stop layer 160 may be formed conformally. Subsequently, a first upper interlayer insulating layer 170 may be formed on the first etch stop layer 160. Subsequently, a planarization process may be performed to expose the upper surface of each of the first to third dummy gates DG1, DG2, and DG3.

[0104] Reference Figure 21 and Figure 22 , the first dummy gate to the third dummy gate can be etched ( Figure 19 DG1, DG2 and DG3 in), pad oxide layer ( Figure 19 30) and the first semiconductor layer ( Figure 19 21). By etching the first dummy gate ( Figure 19 DG1 in), pad oxide layer ( Figure 19 30) and the first semiconductor layer ( Figure 19The space obtained by etching the second dummy gate ( Figure 19 DG2 in), pad oxide layer ( Figure 19 30) and the first semiconductor layer ( Figure 19 The space obtained by etching the third dummy gate ( Figure 19 DG3 in), pad oxide layer ( Figure 19 30) and the first semiconductor layer ( Figure 19 The space obtained by (a) in (21) can be defined as a third gate trench GT3.

[0105] Reference Figure 23 and Figure 24 , can be in the first gate trench ( Figure 21 A first gate insulating layer 121, a first gate electrode G1 and a first capping pattern 131 are sequentially provided inside the second gate trench (GT1). Figure 21 A second gate insulating layer 122, a second gate electrode G2 and a second covering pattern 132 are sequentially formed inside the third gate trench (GT2). Figure 21 A third gate insulating layer 123, a third gate electrode G3 and a third capping pattern 133 are sequentially formed inside the GT3 in FIG.

[0106] Reference Figures 25 to 27 An upper source / drain contact UCA may be formed on the first source / drain region SD1. The upper source / drain contact UCA may penetrate the first upper interlayer insulating layer 170 and the first etch stop layer 160 in the vertical direction DR3 and extend into the first source / drain region SD1. Furthermore, an upper silicide layer USL may be formed between the first source / drain region SD1 and the upper source / drain contact UCA. Furthermore, a gate contact CB connected to the second gate electrode G2 may penetrate the second capping pattern 132 in the vertical direction DR3.

[0107] Subsequently, a second etch-stop layer 180 and a second upper interlayer insulating layer 190 may be sequentially formed on the upper surface of each of the first upper interlayer insulating layer 170, the first to third capping patterns 131, 132, and 133, and the upper source / drain contact UCA. Subsequently, a first via hole V1 may be formed that penetrates the second etch-stop layer 180 and the second upper interlayer insulating layer 190 in the vertical direction DR3 so as to contact the upper source / drain contact UCA. Furthermore, a second via hole V2 may be formed that penetrates the second etch-stop layer 180 and the second upper interlayer insulating layer 190 in the vertical direction DR3 so as to contact the gate contact CB.

[0108] Reference Figures 28 to 30 , the etchable substrate ( Figures 25 to 27 10) and active pattern ( Figures 25 to 27 As a result, a portion of each of the first to third gate insulating layers 121, 122, and 123, a portion of each of the first and second source / drain regions SD1 and SD2, a portion of the field insulating layer 105, a portion of each of the first and second sacrificial patterns 141 and 142, and a portion of each of the first and second insulating liner layers 151 and 152 may be exposed.

[0109] Reference Figures 31 to 33 , can be achieved by etching the substrate ( Figures 25 to 27 10) and active pattern ( Figures 25 to 27 The lower interlayer insulating layer 100 and the insulating pattern 101 are respectively formed in the region obtained by etching the active pattern ( Figures 25 to 27 Insulation pattern 101 is formed in the region obtained by etching the substrate ( Figures 25 to 27 A lower interlayer insulating layer 100 is formed in the region obtained by step 10).

[0110] Reference Figure 34 and Figure 35 A first contact trench CT1 may be formed below the second source / drain region SD2. The first contact trench CT1 may penetrate a portion of the insulating pattern 101 and the lower interlayer insulating layer 100 in the vertical direction DR3 to expose the lower surface of the second insulating liner layer 152. When forming the first contact trench CT1, the second insulating liner layer 152 may be used as an etch stop layer. When forming the first contact trench CT1, a portion of the second sacrificial pattern 142 may be etched.

[0111] Reference Figure 36 and Figure 37 , can be etched through the first contact trench ( Figure 34 and Figure 35 The second sacrificial pattern exposed in CT1) Figure 34 and Figure 35 A portion of the lower surface of the second source / drain region SD2 between the second insulating liner layer 152 may be exposed through the second contact trench CT2.

[0112] Reference Figures 2 to 4 , can be in the second contact trench ( Figure 36 and Figure 37A lower source / drain contact BCA is formed inside the electrode CT2 in the lower insulating liner layer 152. A first portion BCA_1 of the lower source / drain contact BCA may be formed between the second insulating liner layer 152. Furthermore, a second portion BCA_2 of the lower source / drain contact BCA may be formed on each of a lower surface of the second insulating liner layer 152 and a lower surface of the first portion BCA_1 of the lower source / drain contact BCA.

[0113] The upper surface of the first portion BCA_1 of the lower source / drain contact BCA may be coplanar with the upper surface of the second insulating liner layer 152. However, the present disclosure is not limited thereto. The upper surface of the second portion BCA_2 of the lower source / drain contact BCA may contact the lower surface of the second insulating liner layer 152. Through this manufacturing process, a device such as Figures 2 to 4 The semiconductor device shown in .

[0114] In the method for manufacturing a semiconductor device according to some embodiments of the present disclosure, a second insulating liner layer 152 may be formed on the sidewalls of the second sacrificial pattern 142 instead of the lower source / drain contact BCA. After etching the substrate 10 and the active pattern 11, during the process of forming the lower interlayer insulating layer 100 and the insulating pattern 101, oxidation of the sidewalls of the second sacrificial pattern 142 in contact with the second insulating liner layer 152 can be prevented. Therefore, in the method for manufacturing a semiconductor device according to some embodiments of the present disclosure, after etching the second sacrificial pattern 142, the lower source / drain contact BCA can be stably formed.

[0115] Furthermore, in the method for manufacturing a semiconductor device according to some embodiments of the present disclosure, the second insulating liner layer 152 can function as an etch stop layer in the process of forming the second contact trench CT2 for forming the lower source / drain contact BCA. Therefore, the method for manufacturing a semiconductor device according to some embodiments of the present disclosure can ensure an improved process margin for forming the lower source / drain contact BCA.

[0116] The semiconductor device according to some embodiments of the present disclosure, as manufactured using the above-described manufacturing method, may include a second insulating liner layer 152 disposed on at least a portion of the sidewalls of the lower source / drain contact BCA. Furthermore, the first sacrificial pattern 141 and the first insulating liner layer 151 on the sidewalls of the first sacrificial pattern 141 may be disposed below the first source / drain region SD1 to which the upper source / drain contact UCA is connected. Therefore, the semiconductor device according to some embodiments of the present disclosure can improve the reliability of the electrical connection of the lower source / drain contact BCA.

[0117] In the following, reference is made to Figure 38 and Figure 39The following description focuses on the semiconductor device according to other embodiments of the present disclosure. Figures 1 to 4 The difference between the semiconductor devices shown in .

[0118] Figure 38 and Figure 39 is a cross-sectional view illustrating a semiconductor device according to another embodiment of the present disclosure.

[0119] Reference Figure 38 and Figure 39 In a semiconductor device according to a further embodiment of the present disclosure, the lower source / drain contact BCA2 does not contact the lower surface of the second insulating liner layer 152 .

[0120] The lower source / drain contact BCA2 may include a first portion BCA2_1 disposed between the second insulating liner layer 152 and a second portion BCA2_2 disposed below the first portion BCA2_1. An upper surface of the second portion BCA2_2 of the lower source / drain contact BCA2 may be spaced apart from an upper surface of the second insulating liner layer 152 in the vertical direction DR3. That is, the upper surface of the second portion BCA2_2 of the lower source / drain contact BCA2 does not contact the lower surface of the second insulating liner layer 152. For example, each of two opposing sidewalls of the first portion BCA2_1 of the lower source / drain contact BCA2 in the second horizontal direction DR2 may contact the insulating pattern 101.

[0121] In the following, reference is made to Figure 40 and Figure 41 , describes a semiconductor device according to yet other embodiments of the present disclosure. The following description focuses on its Figures 1 to 4 The difference between the semiconductor devices shown in .

[0122] Figure 40 and Figure 41 is a cross-sectional view illustrating a semiconductor device according to another embodiment of the present disclosure.

[0123] Reference Figure 40 and Figure 41 In the semiconductor device according to other embodiments of the present disclosure, the vertical height of the upper surface of the second insulating liner layer 352 may be lower than the vertical height of the upper surface of the lower source / drain contact BCA.

[0124] The upper surface of the first insulating liner layer 351 may be positioned at a vertical height lower than the vertical height of the upper surface of the first sacrificial pattern 141. Furthermore, the upper surface of the second insulating liner layer 352 may be positioned at a vertical height lower than the vertical height of the upper surface of the first portion BCA_1 of the lower source / drain contact BCA. The first source / drain region SD31 may contact a portion of the sidewall of the first sacrificial pattern 141 facing the first horizontal direction DR1. At least a portion of the second source / drain region SD32 may overlap with the first portion BCA_1 of the lower source / drain contact BCA in the first horizontal direction DR1. Furthermore, at least a portion of the second source / drain region SD32 may overlap with the first portion BCA_1 of the lower source / drain contact BCA in the second horizontal direction DR2. The lower silicide layer BSL3 may contact the upper surface of the second insulating liner layer 352.

[0125] In the following, reference is made to Figure 42 and Figure 43 , describes a semiconductor device according to still other embodiments of the present disclosure. The following description focuses on its Figures 1 to 4 The difference between the semiconductor devices shown in .

[0126] Figure 42 and Figure 43 is a cross-sectional view illustrating a semiconductor device according to another embodiment of the present disclosure.

[0127] Reference Figure 42 and Figure 43 In the semiconductor device according to other embodiments of the present disclosure, the vertical height of the upper surface of the second insulating liner layer 452 may be higher than the vertical height of the upper surface of the lower source / drain contact BCA.

[0128] The upper surface of the first insulating liner layer 451 may be positioned at a vertical height higher than the vertical height of the upper surface of the first sacrificial pattern 141. Furthermore, the upper surface of the second insulating liner layer 452 may be positioned at a vertical height higher than the vertical height of the upper surface of the first portion BCA_1 of the lower source / drain contact BCA. At least a portion of the first source / drain region SD41 may overlap the first insulating liner layer 451 in the first horizontal direction DR1. At least a portion of the first source / drain region SD41 may contact a portion of a sidewall of the first insulating liner layer 451 facing the first horizontal direction DR1.

[0129] At least a portion of the second source / drain region SD42 may overlap the second insulating liner layer 452 in the first horizontal direction DR1. Furthermore, at least a portion of the second source / drain region SD42 may overlap the second insulating liner layer 452 in the second horizontal direction DR2. At least a portion of the second source / drain region SD42 may contact a portion of an inner sidewall of the second insulating liner layer 452 in the first horizontal direction DR1. Furthermore, at least a portion of the second source / drain region SD42 may contact a portion of an inner sidewall of the second insulating liner layer 452 facing the second horizontal direction DR2.

[0130] The lower silicide layer BSL4 may contact an upper portion of the second insulating liner layer 452. For example, a sidewall of the lower silicide layer BSL4 facing the first horizontal direction DR1 may contact an inner sidewall of the second insulating liner layer 452. In addition, a sidewall of the lower silicide layer BSL4 facing the second horizontal direction DR2 may contact an inner sidewall of the second insulating liner layer 452.

[0131] Although the embodiments of the present disclosure have been described with reference to the accompanying drawings, the present disclosure is not limited to the above-described embodiments, but can be implemented in various forms. It will be understood by those skilled in the art that the present disclosure can be practiced in other specific forms without changing the technical spirit or basic characteristics of the present disclosure. Therefore, it should be understood that the embodiments described above are not restrictive in all aspects but illustrative.

Claims

1. A semiconductor device comprising: lower interlayer insulating layer; An insulating pattern is disposed on an upper surface of the lower interlayer insulating layer, the insulating pattern extending in a first horizontal direction; a plurality of semiconductor nanosheets stacked on an upper surface of the insulating pattern, wherein each semiconductor nanosheet of the plurality of semiconductor nanosheets is spaced apart from each other in a vertical direction; a gate electrode extending on the insulating pattern in a second horizontal direction different from the first horizontal direction, wherein in a vertical cross-sectional view, the gate electrode surrounds the plurality of semiconductor nanosheets; a first source / drain region disposed on the insulating pattern at a first side of the gate electrode; a second source / drain region disposed on the insulating pattern at a second side of the gate electrode opposite to the first side of the gate electrode in a first horizontal direction; a lower source / drain contact passing through the lower interlayer insulating layer and the insulating pattern in a vertical direction, the lower source / drain contact being electrically connected to the second source / drain region, the lower source / drain contact comprising a first portion disposed below the second source / drain region and a second portion disposed below the first portion; as well as The first insulating liner layer contacts a first sidewall in the first horizontal direction and a second sidewall opposite to the first sidewall of the first portion of the lower source / drain contact, and an upper surface of the first insulating liner layer contacts the second source / drain region.

2. The semiconductor device according to claim 1, wherein The first insulating liner layer contacts the third side wall of the first portion of the lower source / drain contact and the fourth side wall of the first portion of the lower source / drain contact, wherein the third side wall of the first portion of the lower source / drain contact is opposite to the fourth side wall of the first portion of the lower source / drain contact in a second horizontal direction.

3. The semiconductor device according to claim 1, wherein A portion of a sidewall of the second source / drain region in the first horizontal direction continuously contacts a portion of an outer sidewall of the first insulating liner layer in the first horizontal direction.

4. The semiconductor device according to claim 1, wherein The first insulating liner layer does not overlap the plurality of semiconductor nanosheets in a vertical direction, and does not overlap the gate electrode in a vertical direction.

5. The semiconductor device according to claim 1 , further comprising: an upper interlayer insulating layer covering the first source / drain region and the second source / drain region; as well as An upper source / drain contact passes through the upper interlayer insulating layer in a vertical direction, and the upper source / drain contact is electrically connected to the first source / drain region.

6. The semiconductor device according to claim 1, further comprising: a field insulating layer on an upper surface of the lower interlayer insulating layer, the field insulating layer surrounding a sidewall of the insulating pattern, The vertical height of the upper surface of the first insulating liner layer is lower than the vertical height of the upper surface of the field insulating layer.

7. The semiconductor device according to claim 1 , further comprising: The sacrificial pattern contacts the lower surface of the first source / drain region, and the sacrificial pattern comprises silicon germanium.

8. The semiconductor device according to claim 7, further comprising: The second insulating liner layer contacts two sidewalls of the sacrificial pattern in a first horizontal direction, and an upper surface of the second insulating liner layer contacts the first source / drain region.

9. The semiconductor device according to claim 1, wherein A lower surface of the first insulating liner layer contacts an upper surface of the second portion of the lower source / drain contact.

10. The semiconductor device according to claim 1, wherein A lower surface of the first insulating liner layer is vertically spaced apart from an upper surface of the second portion of the lower source / drain contact.

11. The semiconductor device according to any one of claims 1 to 10, further comprising: The lower silicide layer is disposed between the lower source / drain contact and the second source / drain region, and the lower silicide layer contacts the upper surface of the first insulating liner layer.

12. The semiconductor device according to claim 1, further comprising: The lower silicide layer is disposed between the lower source / drain contact and the second source / drain region, and the lower silicide layer contacts the inner sidewall of the first insulating liner layer in a first horizontal direction.

13. A semiconductor device comprising: lower interlayer insulating layer; An insulating pattern is disposed on an upper surface of the lower interlayer insulating layer, the insulating pattern extending in a first horizontal direction; a field insulating layer, disposed on an upper surface of the lower interlayer insulating layer, the field insulating layer covering a sidewall of the insulating pattern; a gate electrode on the insulating pattern and the field insulating layer, the gate electrode extending in a second horizontal direction different from the first horizontal direction; a first source / drain region disposed on the insulating pattern at a first side of the gate electrode; a second source / drain region disposed on the insulating pattern at a second side of the gate electrode opposite to the first side of the gate electrode in a first horizontal direction; a lower source / drain contact passing through the lower interlayer insulating layer and the insulating pattern in a vertical direction, the lower source / drain contact being electrically connected to the second source / drain region; a sacrificial pattern in contact with a lower surface of the first source / drain region; a first insulating liner layer in contact with the first sidewall and the second sidewall of the sacrificial pattern, wherein the second sidewall is opposite to the first sidewall in a first horizontal direction, and an upper surface of the first insulating liner layer is in contact with the first source / drain region; and A second insulating liner layer contacts the third side wall and at least a portion of the fourth side wall of the lower source / drain contact, wherein the fourth side wall is opposite to the third side wall in a first horizontal direction, an upper surface of the second insulating liner layer contacts the second source / drain region, and a vertical height of the upper surface of the second insulating liner layer is lower than a vertical height of the upper surface of the field insulating layer.

14. The semiconductor device according to claim 13, wherein An outer sidewall of the second insulating liner layer in the first horizontal direction contacts the insulating pattern, and an outer sidewall of the second insulating liner layer in the second horizontal direction contacts the field insulating layer.

15. The semiconductor device according to claim 13, wherein A vertical height of a lower surface of the first insulating liner layer is higher than a vertical height of a lower surface of the sacrificial pattern.

16. The semiconductor device according to claim 13, wherein Each of the first and second insulating liner layers includes a material different from that of each of the insulating patterns and the lower interlayer insulating layer.

17. The semiconductor device according to any one of claims 13 to 16, wherein An upper surface of the second insulating liner layer is coplanar with an upper surface of the lower source / drain contact.

18. The semiconductor device according to any one of claims 13 to 16, wherein A vertical height of an upper surface of the second insulating liner layer is lower than a vertical height of an upper surface of the lower source / drain contact.

19. The semiconductor device according to any one of claims 13 to 16, wherein A vertical height of an upper surface of the second insulating liner layer is higher than a vertical height of an upper surface of the lower source / drain contact.

20. A semiconductor device comprising: lower interlayer insulating layer; an insulating pattern extending in a first horizontal direction on an upper surface of the lower interlayer insulating layer; a plurality of semiconductor nanosheets stacked on an upper surface of the insulating pattern, wherein each semiconductor nanosheet of the plurality of semiconductor nanosheets is spaced apart from each other in a vertical direction; a field insulating layer, disposed on an upper surface of the lower interlayer insulating layer, the field insulating layer covering a sidewall of the insulating pattern; a gate electrode extending on the insulating pattern in a second horizontal direction different from the first horizontal direction, wherein in a vertical cross-sectional view, the gate electrode surrounds each semiconductor nanosheet of the plurality of semiconductor nanosheets; a first source / drain region disposed on the insulating pattern at a first side of the gate electrode; a second source / drain region disposed on the insulating pattern at a second side of the gate electrode opposite to the first side of the gate electrode in a first horizontal direction; an upper interlayer insulating layer covering the first source / drain region and the second source / drain region on the field insulating layer; an upper source / drain contact passing through the upper interlayer insulating layer in a vertical direction, the upper source / drain contact being electrically connected to the first source / drain region; a lower source / drain contact passing through the lower interlayer insulating layer and the insulating pattern in a vertical direction, the lower source / drain contact being electrically connected to the second source / drain region, the lower source / drain contact comprising a first portion disposed below the second source / drain region and a second portion disposed below the first portion; a sacrificial pattern in contact with a lower surface of the first source / drain region; a first insulating liner layer in contact with a first sidewall and a second sidewall of the sacrificial pattern, wherein the first sidewall of the sacrificial pattern is opposite to the second sidewall of the sacrificial pattern in a first horizontal direction, an upper surface of the first insulating liner layer is in contact with the first source / drain region, and a lower surface of the first insulating liner layer has a vertical height higher than a vertical height of a lower surface of the sacrificial pattern; and a second insulating liner layer in contact with the first side wall and the second side wall of the first portion of the lower source / drain contact, wherein the first side wall of the first portion of the lower source / drain contact is opposite to the second side wall of the first portion of the lower source / drain contact in a first horizontal direction, an upper surface of the second insulating liner layer in contact with the second source / drain region, a vertical height of the upper surface of the second insulating liner layer is lower than a vertical height of the upper surface of the field insulating layer, and a lower surface of the second insulating liner layer in contact with the upper surface of the second portion of the lower source / drain contact.

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