Packaging structure and preparation method thereof

Abstract

The embodiment of the invention discloses a packaging structure and a preparation method thereof. The packaging structure comprises a first transistor and a second transistor which are vertically stacked; the plastic package part wraps the first transistor and the second transistor to form a plastic package body; the front rewiring layer is arranged on the first surface of the plastic package body; the back rewiring layer is arranged on the second surface of the plastic package body; a plurality of plastic package via holes penetrating through the plastic package member, wherein the plastic package via holes are used for connecting the electrodes of the first transistor and the second transistor to the front surface rewiring layer or the back surface rewiring layer; and the interposer vertically penetrates through the plastic package part and is used for connecting the electrode connected with the back surface redistribution layer to the front surface redistribution layer. Through the mode, the V-MOS packaging integration level can be improved, the size of a packaging body is reduced, the conduction impedance, the parasitic inductance and the packaging cost are reduced, and the chip reliability is improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a packaging structure and a preparation method thereof. Background Art

[0002] As electronic products evolve toward miniaturization, high performance, and high integration, semiconductor packaging technology faces increasing challenges. In the power semiconductor field, product designs are gradually shifting from traditional integrated BCD (Bipolar-CMOS-DMOS) solutions to discrete V-MOS (Vertical Metal Oxide Semiconductor Field-Effect Transistor) integration. This shift places higher demands on packaging integration technology, including lower parasitic impedance, higher withstand voltage, improved heat dissipation, smaller package size, and lower cost.

[0003] Especially in high-performance application scenarios, when the device needs to achieve an impedance of 5 milliohms or below, the discrete V-MOS requires a thinner structural design and the package impedance needs to be smaller. The traditional wire bonding (WB) integration technology has become a bottleneck for performance improvement. Traditional V-MOS packaging methods have the following major problems: Currently, traditional vertical MOS is basically arranged in a flat manner and interconnected with the IC through bonding wires or clips, which significantly increases the package size and makes it difficult to meet miniaturization requirements. The interconnection path formed by traditional lead bonding is long and has high resistance, resulting in high overall device on-resistance, which is not conducive to reducing power consumption and improving efficiency. For some special MOS structures (such as common source configurations), only a few wafer foundries on the market implement them through wafer processing and are not open to the market, lacking a highly versatile packaging process solution. When it is necessary to integrate ultra-thin V-MOS with lower impedance (such as thickness under 100 microns), traditional die bonding processes are prone to reliability issues such as packaging material creep shorts and chip cracking. Traditional flat packaging methods have long heat dissipation paths and high thermal resistance, making it difficult to effectively dissipate heat in high-power applications, limiting device performance.

[0004] As the efficiency and power density requirements for power semiconductor devices in applications such as mobile devices, electric vehicles, and data centers continue to increase, there is an urgent need to develop new V-MOS packaging and integration technologies to achieve lower parasitic impedance, higher integration, and better heat dissipation performance while maintaining a reasonable cost level to meet the market's growing demand for high-performance power semiconductor devices. Summary of the Invention

[0005] The main technical problem solved by the embodiments of the present invention is to provide a packaging structure and a preparation method thereof, which can solve at least some of the defects of the existing V-groove MOS integration solution.

[0006] In the first aspect, an embodiment of the present invention provides a packaging structure, comprising: a first transistor and a second transistor arranged vertically stacked, wherein the opposite end faces of the first transistor and the second transistor are connected by chip bonding to form a common electrode; a plastic package, covering the first transistor and the second transistor to form a plastic package body; the plastic package body having a first surface and a second surface; a front redistribution layer, arranged on the first surface of the plastic package body; a back redistribution layer, arranged on the second surface of the plastic package body; a plurality of plastic package vias passing through the plastic package, wherein the plastic package vias are used to connect the electrodes of the first transistor and the electrodes of the second transistor to the front redistribution layer or the back redistribution layer; and an intermediate layer vertically passing through the plastic package, used to connect the electrodes connected to the back redistribution layer to the front redistribution layer.

[0007] Optionally, the packaging structure further includes: an integrated circuit chip, which is covered by the plastic package and arranged on a side of the intermediate layer away from the first transistor and the second transistor arranged vertically stacked, and the front side redistribution layer is connected to the input / output port of the integrated circuit chip.

[0008] Optionally, the packaging structure also includes: a first thin film layer arranged on an end face of the first transistor away from the second transistor; a plurality of first thin film vias penetrating the first thin film layer, the first thin film vias being used to connect the electrode of the first transistor to the front redistribution layer; a second thin film layer arranged on an end face of the integrated circuit chip close to the front redistribution layer; a plurality of second thin film vias penetrating the second thin film layer, the second thin film vias being used to connect the input / output port of the integrated circuit chip to the front redistribution layer.

[0009] Optionally, the source of the first transistor and the source of the second transistor are connected by chip bonding to form a source common electrode; the gate of the first transistor faces the back redistribution layer, and the gate of the second transistor faces the front redistribution layer; the drain of the first transistor is connected to the front redistribution layer.

[0010] Optionally, the plurality of plastic-encapsulated vias include a plurality of first plastic-encapsulated vias, a plurality of second plastic-encapsulated vias and a plurality of third plastic-encapsulated vias; the plurality of first plastic-encapsulated vias are used to connect the gate of the first transistor and the back redistribution layer; the first plastic-encapsulated vias are formed by secondary laser drilling and electroplating; the plurality of second plastic-encapsulated vias are used to connect the gate of the second transistor and the front redistribution layer; the second plastic-encapsulated vias are formed by secondary laser drilling and electroplating; the plurality of third plastic-encapsulated vias are used to connect the drain of the second transistor and the back redistribution layer; the third plastic-encapsulated vias are formed by one laser drilling and electroplating.

[0011] Optionally, a portion of the drain of the first transistor and the source of the second transistor are connected by chip bonding to form a drain-source common electrode; another portion of the drain of the first transistor faces the back redistribution layer, and the gate of the second transistor faces the front redistribution layer; the source and gate of the first transistor are connected to the front redistribution layer.

[0012] Optionally, the plurality of plastic-encapsulated vias include a plurality of first plastic-encapsulated vias, a plurality of second plastic-encapsulated vias and a plurality of third plastic-encapsulated vias; the plurality of first plastic-encapsulated vias are used to connect another part of the drain of the first transistor and the back redistribution layer; the first plastic-encapsulated vias are formed by secondary laser drilling and electroplating; the plurality of second plastic-encapsulated vias are used to connect the gate of the second transistor and the front redistribution layer; the second plastic-encapsulated vias are formed by secondary laser drilling and electroplating; the plurality of third plastic-encapsulated vias are used to connect the drain of the second transistor and the back redistribution layer; the third plastic-encapsulated vias are formed by one laser drilling and electroplating.

[0013] Optionally, the drain of the first transistor and the drain of the second transistor are connected by chip bonding to form a drain common electrode; the source and gate of the first transistor are connected to the front side redistribution layer.

[0014] Optionally, the plurality of plastic-encapsulated vias include a plurality of third plastic-encapsulated vias; the source and gate of the second transistor are connected to the back redistribution layer through the plurality of third plastic-encapsulated vias; and the third plastic-encapsulated vias are formed by one laser drilling and electroplating.

[0015] Optionally, both the first transistor and the second transistor are vertical power metal oxide semiconductor field effect transistors.

[0016] In a second aspect, an embodiment of the present invention provides a method for preparing a packaging structure, comprising: vertically stacking a first transistor and a second transistor, connecting them by chip bonding, so that the opposite end surfaces of the first transistor and the second transistor form a common electrode; arranging an interposer outside the vertically stacked first transistor and the second transistor; arranging an integrated circuit chip on a side of the interposer away from the vertically stacked first transistor and the second transistor; plastic-sealing the first transistor, the second transistor and the integrated circuit chip to form a plastic-sealed body, the plastic-sealed body having a first surface and a second surface; thinning the second surface of the plastic-sealed body so that the interposer is exposed to the second surface; forming a plurality of plastic-sealed vias on the plastic-sealed body, the plastic-sealed vias being used to connect the electrode of the first transistor and the electrode of the second transistor; forming a back-side redistribution layer on the second surface, the back-side redistribution layer being used to connect the electrode of the first transistor and / or the electrode of the second transistor to the interposer; forming a front-side redistribution layer on the first surface, the front-side redistribution layer being used to connect the electrode of the first transistor, the electrode of the second transistor to the input / output port of the integrated circuit chip.

[0017] Optionally, after connecting the first transistor and the second transistor by chip bonding so that the opposite end surfaces of the first transistor and the second transistor form a common electrode, the preparation method further includes: providing an adapter plate; the adapter plate has a first contact surface; setting the vertically stacked first transistor and the second transistor on the first contact surface, with the first transistor facing the first contact surface; setting the integrated circuit chip on the first contact surface; and removing the adapter plate after setting the plurality of pins.

[0018] Optionally, after forming the back side redistribution layer on the second surface, the preparation method further comprises: turning over the plastic package body on which the back side redistribution layer is formed, so that the back side redistribution layer faces the first contact surface.

[0019] Optionally, before vertically stacking the first transistor and the second transistor and connecting them via chip bonding to form a common electrode on the opposing end faces of the first and second transistors, the preparation method further includes: forming a first thin film layer on one end face of the first transistor and forming a plurality of first thin film vias in the first thin film layer; the first thin film layer facing the first contact surface; and forming a second thin film layer on one end face of the integrated circuit chip and forming a plurality of second thin film vias in the first thin film layer; the second thin film layer facing the first contact surface. Advantageous effects of embodiments of the present invention are: unlike prior art, embodiments of the present invention can increase the integration density of V-MOS packages, reduce package size, reduce on-resistance, parasitic inductance, and packaging costs, and improve chip reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] One or more embodiments are exemplarily illustrated by corresponding drawings, which do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0021] Figure 1 1 is a schematic structural diagram of a packaging structure provided by an embodiment of the present invention;

[0022] Figure 2 is a structural schematic diagram of another packaging structure provided by an embodiment of the present invention;

[0023] Figure 3 1 is a structural diagram of another packaging structure provided by an embodiment of the present invention;

[0024] Figure 4 yes Figure 2 A schematic diagram of a first structural embodiment of the packaging structure shown;

[0025] Figure 5 yes Figure 2 A second structural schematic diagram of the package structure shown;

[0026] Figure 6 yes Figure 2 A third structural schematic diagram of the package structure shown;

[0027] Figure 7 It is a schematic flow chart of a method for preparing a packaging structure provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0028] In order to facilitate the understanding of the present application, the present application is described in more detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that when an element is described as being "fixed to" another element, it can be directly on the other element, or there can be one or more centered elements therebetween. When an element is described as being "connected to" another element, it can be directly connected to the other element, or there can be one or more centered elements therebetween. The terms "upper", "lower", "inner", "outer", "bottom" and the like used in this specification indicate an orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third" and the like are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0029] Unless otherwise defined, all technical and scientific terms used in this specification have the same meanings as those commonly understood by those skilled in the art to which this application belongs. The terms used in this specification and in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" as used in this specification includes any and all combinations of one or more of the relevant listed items.

[0030] In addition, the technical features involved in different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0031] The technical solution in this application will be described below with reference to the accompanying drawings.

[0032] See Figure 1 An embodiment of the present invention provides a packaging structure, including a first transistor 110 and a second transistor 120 vertically stacked, a plastic package 140, a front redistribution layer 160, a back redistribution layer 170, a plurality of plastic package vias 141 and an intermediate layer 150.

[0033] In the embodiment of the present application, the first transistor 110 and the second transistor 120 are both vertical power metal-oxide semiconductor field-effect transistors (MOSFETs). The structure of a vertical power MOSFET allows current to flow perpendicular to the chip surface, resulting in lower on-resistance and higher current density than a planar MOS structure.

[0034] In some embodiments, the vertical power MOSFET may include a V-groove MOSFET, a vertical double-diffused MOSFET (VD-MOSFET), and a U-groove MOSFET.

[0035] The first transistor and the second transistor each have a first surface and a second surface opposite to each other, wherein the first surface is provided with a drain electrode, and the second surface is provided with a source electrode and a gate electrode.

[0036] In this package structure, the first transistor 110 and the second transistor 120 are arranged in a vertical stack, and the opposite end faces of the first transistor and the second transistor are connected by die bonding to form a common electrode. The common electrode can be a source common electrode, a drain common electrode, or a drain-source common electrode, depending on the specific implementation. The vertical stacking arrangement significantly reduces the footprint of the package and improves the integration level.

[0037] The plastic encapsulation member 140 encapsulates the first transistor 110 and the second transistor 120 to form a plastic encapsulation body. The entire plastic encapsulation body is in the shape of a rectangular parallelepiped and has a first surface and a second surface. The first surface is the upper surface of the plastic encapsulation body, and the second surface is the lower surface of the plastic encapsulation body. The plastic encapsulation member is typically made of epoxy resin or other insulating materials. It not only provides mechanical protection and electrical insulation, but also enhances the stability and reliability of the entire package structure and serves as a substrate for subsequent electrical interconnection. The plastic encapsulation process can be achieved through techniques such as molding or transfer molding to ensure that the plastic encapsulation material completely fills the gap between the transistor and the chip.

[0038] Front-side redistribution layer 160 is disposed on the first surface of the plastic package and is used to redistribute and connect the electrodes of first transistor 110 or second transistor 120. Made of a conductive material (such as copper), the front-side redistribution layer is formed into a specific conductive pattern through processes such as photolithography and electroplating, enabling complex electrical interconnections. Front-side redistribution layer 160 is connected to the input / output ports of integrated circuit chip 130, establishing an electrical connection between the integrated circuit chip and external circuits.

[0039] Backside redistribution layer 170 is disposed on the second surface of the plastic package. Similar in structure to frontside redistribution layer 160, but located on the opposite side of the plastic package, it is used to connect the electrodes of first transistor 110 or second transistor 120 and is connected to frontside redistribution layer 160 via interposer 150. The use of a backside redistribution layer expands wiring space and reduces line congestion.

[0040] Several plastic vias 141 extending through the plastic package connect the electrodes of the first transistor 110 and the second transistor 120 to the front-side redistribution layer 160 or the back-side redistribution layer 170. Plastic vias 141 are fabricated using a laser drilling and plating process and filled with conductive material to form vertical electrical pathways. Depending on the connection requirements, the plastic vias may require either a single laser drilling and plating process or a secondary laser drilling and plating process.

[0041] In an embodiment of the present application, an interposer 150 that vertically penetrates the plastic package is disposed on both sides of the first transistor 110 and the second transistor 120 that are vertically stacked, and is used to connect the electrodes connected to the back redistribution layer 170 to the front redistribution layer 160. The interposer 150 acts as a bridge for signal transmission, enabling the electrode signals on the back to be conducted to the front, thereby improving wiring flexibility. The interposer 140 may be composed of multiple layers of metal and insulating materials to form a three-dimensional interconnected structure, thereby realizing electrical interconnection between the front and back surfaces and providing a low-impedance channel for signal transmission. The design of the interposer may include multiple independent conductive paths to support the separate transmission of different signals or power supplies. In other embodiments, the interposer may be flexibly arranged according to actual application needs and design requirements, such as being arranged on all sides to form a surround structure; or being arranged on specific sides to form an asymmetric distribution.

[0042] The embodiment of the present application provides another packaging structure for the above packaging structure, and its structural diagram is as follows: Figure 2 As shown, based on the above packaging structure, the packaging structure provided in the embodiment of the present application further includes an integrated circuit chip 130 .

[0043] The integrated circuit chip 130 is also encapsulated by the plastic encapsulation member 140 and is disposed on a side of the interposer 150 away from the vertically stacked first and second transistors 110 and 120. The front-side redistribution layer 160 is connected to the input / output ports of the integrated circuit chip 130. The integrated circuit chip can be a control chip, a driver chip, or another functional chip, and is electrically connected to the transistors via the front-side redistribution layer 160.

[0044] An improved embodiment of the above-mentioned packaging structure further includes a first thin film layer 180 disposed on an end surface of the first transistor 110 away from the second transistor 120. The first thin film layer 180 is provided with a plurality of first thin film vias 181 penetrating the first thin film layer, for connecting the electrodes (such as the source, gate, or drain) of the first transistor 110 to the front-side redistribution layer 160. The first thin film layer 180 is made of an insulating material, such as polyimide or epoxy resin, to provide electrical isolation. The first thin film vias 181 are filled with a conductive material to form a vertical electrical path.

[0045] In another improved embodiment, the package structure further includes a second thin film layer 190 disposed on one end surface of the integrated circuit chip 130 near the front redistribution layer 160. Second thin film layer 190 is provided with a plurality of second thin film vias 191 extending through the second thin film layer for connecting the input / output ports of the integrated circuit chip 130 to the front redistribution layer 160. Second thin film layer 190 and first thin film layer 180 are made of the same insulating material, and second thin film vias 191 are filled with conductive material to achieve a reliable connection between the integrated circuit chip and the front redistribution layer 160.

[0046] By adopting a vertical stacking structure and utilizing chip bonding technology to form a common electrode, combined with plastic-encapsulated vias and a redistribution layer, this packaging structure achieves a highly integrated, small-sized, low-impedance semiconductor package. Compared to the traditional tiled layout, the vertical stacking layout can significantly reduce the occupied area and significantly increase the power density per unit area. The chip bonding connection avoids the long wire paths used in traditional wire bonding, reducing the conduction path length, thereby reducing the conduction impedance and parasitic inductance, and improving high-frequency performance. The introduction of the interposer simplifies the electrical interconnection between the front and back surfaces, supports more complex circuit topologies, and further optimizes circuit performance and heat dissipation characteristics.

[0047] Reference Figure 3 This embodiment provides another packaging structure. Figure 2 Based on the package structure shown, it further includes a first protection layer 210 , a second protection layer 220 and a plurality of pins 230 arranged on the front side redistribution layer 160 .

[0048] The first protective layer 210 completely covers the front-side redistribution layer 160 and is made of an insulating polymer material, typically polyimide or solvent-based photoresist. This protective layer, typically 10-50 microns thick, is formed into a uniform covering layer through lamination or spin coating. Photolithography then creates windows in specific areas to facilitate subsequent electrical connections. The first protective layer 210 not only provides mechanical protection against physical damage to the front-side redistribution layer but also acts as an electrical insulator, preventing short circuits and leakage.

[0049] The second protective layer 220 completely covers the backside redistribution layer 170. Its materials and fabrication process are similar to those of the first protective layer 210, but are typically optimized based on the backside environmental conditions and application requirements. The second protective layer 220 can be formed using a lamination process or a secondary plastic encapsulation process. Unlike the first protective layer 210, which requires a window for external connection, the second protective layer 220 primarily provides comprehensive protection for the backside redistribution layer, preventing corrosion and mechanical wear caused by the external environment.

[0050] Several pins 230, located on the front-side redistribution layer 160, extend through the first protective layer 210, providing a connection interface between the package structure and external circuitry. Pins 230 can be implemented as copper pillars, solder balls, or other conductive structures, and can be arranged in a matrix or perimeter pattern depending on the specific application. Pins 230 are securely connected to the pads on the front-side redistribution layer 160 through a reflow soldering process, forming a low-impedance electrical path. The size and spacing of pins 230 conform to industry standards, facilitating automated assembly in system-level applications.

[0051] Reference Figure 4 This embodiment demonstrates a packaging structure implementation for a source common electrode configuration. In this structure, the first transistor 110 and the second transistor 120 are vertically stacked with their sources directly connected via die bonding technology to form a source common electrode, suitable for high-efficiency synchronous rectification and half-bridge circuits.

[0052] In terms of electrode layout, the gate of the first transistor 110 faces the backside redistribution layer 170, while the gate of the second transistor 120 faces the frontside redistribution layer 160. The drain of the first transistor 110 is connected to the frontside redistribution layer 160 via a via in the first thin film layer 180, forming a complete electrical path. This three-dimensional electrode arrangement fully utilizes space resources, making the package structure more compact and efficient.

[0053] In this embodiment, the connection between the drain of the first transistor and the front-side redistribution layer can also be achieved using other connection methods, such as: forming a conductive layer on the side of the transistor to connect to the front-side redistribution layer through sidewall metallization technology; using metal bond wire technology to connect the drain and the redistribution layer through a short distance of metal wire; or using materials such as conductive adhesive to form a flexible connection. It is even possible to reserve a special metal extension structure during the transistor manufacturing process to directly contact the redistribution layer.

[0054] Different distribution strategies are used for the vias connecting the electrodes to optimize the electrical performance. Figure 4 As can be seen, the first plastic-encapsulated vias 1411 connecting the gate of the first transistor 110 are arranged in a single row with equal spacing, ensuring uniform transmission of the gate signal. This single-row arrangement can be expanded to a double-row layout, allowing for flexible adjustment based on actual driving requirements. Similarly, the second plastic-encapsulated vias 1412 connecting the gate of the second transistor 120 are also arranged with regular equal spacing, ensuring timing consistency of the switching signals.

[0055] The third plastic via 1413 connecting to the drain of the second transistor 120 utilizes a dot-matrix distribution, evenly spaced across the drain region. This dot-matrix distribution is particularly well-suited for high-current applications, effectively dispersing current density and reducing the risk of local hotspots. Similarly, the first thin-film via 181 connecting to the drain of the first transistor 110 also utilizes a dot-matrix distribution, further optimizing the high-current transmission path.

[0056] The connection between the integrated circuit chip 130 and the front-side redistribution layer 160 utilizes a hybrid distribution strategy. Some second-film vias 191 are arranged in a row along the edge of the chip's input / output ports, primarily for transmitting control signals. Other second-film vias 191 are arranged in a dot matrix, primarily for power and ground connections, meeting the transmission requirements of different signal types.

[0057] By way of example and not limitation, both first and second plastic-encapsulated vias 1411 and 1412 are fabricated using a secondary laser drilling and electroplating process. This process first forms a first truncated cone-shaped hole on the surface of the plastic package, followed by a second, precision-drilled hole at its base, resulting in a composite hole structure with precisely controlled depth and diameter. After drilling, the holes are cleaned to remove residue, a metal seed layer is deposited, and finally, a conductive material is electroplated to form a high-quality electrical path.

[0058] In contrast, the third plastic-encapsulated via 1413 uses a simpler one-time laser drilling and electroplating process, which is suitable for application scenarios with a shallow depth but requiring large current to pass through.

[0059] Through electrode configuration and via distribution strategies, this embodiment achieves a highly integrated, low-impedance, and thermally-efficient package structure suitable for the demanding requirements of modern high-frequency, high-power density applications. The source common electrode design significantly shortens the current loop path, reduces parasitic inductance, and improves overall circuit performance and reliability.

[0060] Reference Figure 5 This embodiment presents a package structure with a drain-source common electrode configuration. In this structure, a portion of the drain of the first transistor 110 and the source of the second transistor 120 are connected via die bonding to form a drain-source common electrode. This structure is suitable for applications where the drain and source need to form a specific circuit topology, such as a cascade circuit or a specific drive circuit.

[0061] In this structure, the drain of first transistor 110 is positioned toward back-side redistribution layer 170, preserving its ability to connect to the back-side circuitry. The gate of second transistor 120 faces front-side redistribution layer 160, facilitating the reception of upper-layer control signals. The source and gate of first transistor 110 are connected to front-side redistribution layer 160 via first thin-film vias 181, forming a complete control loop.

[0062] The electrodes are connected using a variety of via structures, whose distribution is carefully designed to optimize electrical performance. Figure 5 In the example, first plastic vias 1411 connecting to the other drain portion of first transistor 110 are arranged at equal intervals, forming a regular single-row structure. This evenly spaced arrangement ensures uniform current distribution and reduces the risk of local hot spots. In practical applications, depending on current density requirements, a dual-row configuration can be implemented to further improve current-carrying capacity.

[0063] Second plastic-encapsulated vias 1412, connecting to the gate of the second transistor 120, are also arranged with equal spacing and located in the gate region of the second transistor 120. This regular arrangement ensures uniform transmission of gate drive signals, improving switching performance and consistency. Given the high timing requirements of gate signals, a uniform distribution of vias helps minimize drive delay variations and enhance overall system response.

[0064] The third plastic via 1413 connecting to the drain of the second transistor 120 is arranged in a dot matrix, evenly covering the drain area. This dot matrix is ​​suitable for high-current applications, effectively dispersing current density and improving heat distribution. Depending on power requirements, the dot matrix can be designed in 3×3, 4×4, or even larger sizes to meet the needs of applications with different current levels.

[0065] The first thin film via 181 adopts a mixed distribution strategy. The part of the via connected to the source of the first transistor 110 is arranged in a row to facilitate efficient transmission of the source current; while the part connected to the gate adopts a dot matrix distribution to ensure that the control signal can evenly cover the entire gate area.

[0066] The second thin film vias 191 also adopt a mixed distribution, with one part arranged in a regular row along the edge of the input / output port of the integrated circuit chip 130 for transmitting control and low current signals; the other part adopts a dot matrix distribution, mainly used for power and ground connections to meet high current requirements.

[0067] The package structure with a drain-source common electrode configuration offers unique circuit topology advantages, making it particularly suitable for power management applications that require a specific current path. Through carefully designed electrode configuration and via distribution, efficient and compact power device packaging is achieved, meeting the stringent requirements of modern electronic devices for miniaturization, high efficiency, and high reliability.

[0068] Reference Figure 6 This embodiment demonstrates a package structure with a drain common electrode configuration. In this design, the drain of the first transistor 10 and the drain of the second transistor 120 are directly connected via die bonding to form a drain common electrode. This structure is suitable for applications that require a shared drain current path, such as synchronous buck converters or push-pull output stages in power amplifiers.

[0069] The drain-common electrode structure optimizes the power transmission path between the two transistors, significantly reducing drain connection resistance and effectively improving power conversion efficiency. Compared to the traditional parallel arrangement structure, the vertically stacked drain-common design significantly reduces the package area and improves thermal management performance.

[0070] In this structure, the source and gate of first transistor 110 connect to front-side redistribution layer 160 through first thin-film vias 181, forming a control and power input path. The source and gate of second transistor 120 connect to back-side redistribution layer 170 through third plastic vias 1413, providing back-side control and power connections. This double-sided connection design fully utilizes the three-dimensional space of the package, achieving an optimal electrical path layout.

[0071] The third plastic-encapsulated via 1413 utilizes a flexible hybrid distribution strategy. The vias connecting to the gate of the second transistor 120 are arranged in a row with equal spacing along the gate edge, ensuring even distribution of the gate control signal. The vias connecting to the source are arranged in a dotted pattern, covering the source area and effectively distributing high current density. This differentiated distribution fully considers the electrical characteristics of different electrodes, prioritizing signal integrity in the gate area and current carrying capacity in the source area.

[0072] The first thin-film vias 181 also adopt a mixed distribution. The vias connecting to the gate of the first transistor 110 are arranged in a regular row to optimize the transmission path of the gate drive signal, while the vias connecting to the source adopt a dot matrix distribution to ensure uniform flow of high current and reduce hot spot effects.

[0073] A similar hybrid distribution strategy is employed for the second thin-film vias 191 connecting the integrated circuit chip 130 to the front-side redistribution layer 160. Vias are arranged in a row along the chip's I / O port edges, primarily for transmitting control and low-current signals. Vias in the power and ground connection areas are arranged in a dotted pattern to accommodate high-current transmission requirements.

[0074] The drain common electrode structure achieves efficient and compact power device packaging through vertical stacking and die bonding technology. The optimized via distribution strategy ensures efficient electrical signal transmission and uniform heat distribution, meeting the stringent power density and reliability requirements of modern electronic devices. Compared to traditional packaging solutions, this not only reduces on-resistance and parasitic inductance, but also shrinks package size, improving overall system performance.

[0075] Reference Figure 7 This embodiment describes in detail a method for preparing a packaging structure, which specifically includes the following steps:

[0076] Step S110: vertically stacking the first transistor and the second transistor, and connecting them by chip bonding, so that opposite end surfaces of the first transistor and the second transistor form a common electrode.

[0077] Specifically, the chip bonding process uses a precision temperature and pressure control system, usually carried out in the temperature range of 200-300°C, and applies appropriate pressure to form a metal atomic-level bond between the two transistor electrodes. Depending on the application requirements, different stacking methods can be selected: when the source of the first transistor faces the second transistor and the source of the second transistor faces the first transistor, a source common electrode structure is formed; when the drains of the two transistors are opposite, a drain common electrode structure is formed; when the drain of the first transistor is opposite to the source of the second transistor, a drain-source common electrode structure is formed. Direct bonding technology avoids the parasitic inductance and resistance of traditional lead connections and significantly improves electrical performance. In actual operation, the surface of the transistor needs to undergo special cleaning treatment to remove oxides and impurities to ensure that the electrical and mechanical properties of the bonding interface are optimal.

[0078] Step S120 : disposing an interposer outside the vertically stacked first transistor and the second transistor.

[0079] It should be noted that the "external" here refers to the interposer being placed outside the transistor stack, but this does not limit the specific configuration and can be flexibly arranged according to actual application needs and design requirements. The interposer can be placed in a variety of ways: it can be placed on only two sides, forming two vertical conductive channels; it can be placed on all four sides, forming a wraparound structure; or it can be placed on specific sides, creating an asymmetrical distribution.

[0080] In the embodiment of the present application, the main function of the interposer is to provide a vertical conductive channel to connect the back redistribution layer to the front redistribution layer. The arrangement on both sides can not only realize the electrical interconnection of the front and back surfaces, but also reserve sufficient space for the transistor, which is convenient for plastic packaging material filling and thermal management.

[0081] Specifically, the interposer is usually composed of a multi-layer structure, including alternating metal conductive layers and dielectric insulating layers. The interposer is made using high-precision assembly technology, and can use highly conductive metals such as copper and aluminum to form vertically penetrating conductive channels. The positioning of the interposer requires precise alignment to ensure that it maintains an appropriate distance from the transistor to avoid electrical interference while ensuring the reliability of subsequent interconnections. The interposer not only provides electrical connection functions, but also plays a mechanical support role to a certain extent, enhancing the stability of the overall packaging structure. The material selection and design of the interposer also take into account the matching of thermal expansion coefficients to reduce reliability issues caused by thermal stress.

[0082] Step S130 : placing an integrated circuit chip on a side of the interposer away from the vertically stacked first transistor and the second transistor.

[0083] Specifically, with the interposer as the reference point, the integrated circuit chip is placed on the outside of the interposer, that is, the interposer is located between the transistor stack and the integrated circuit chip, forming a sequential arrangement of transistor stack → interposer → integrated circuit chip. During the setup process, the position of the interposer relative to the transistor stack is first determined, with one side of the interposer facing the transistor stack (near end) and the other side facing away from the transistor stack (far end). The integrated circuit chip is placed on the far side of the interposer.

[0084] High-precision placement equipment is used to place integrated circuit chips, with positioning accuracy typically controlled within ±25 microns to ensure precise alignment of their input / output ports with the subsequently formed redistribution layer. Depending on their functional requirements, integrated circuit chips can be control chips, driver chips, or other functional chips. Their surfaces are typically pre-prepared with thin film layers and vias to facilitate subsequent electrical connections to the redistribution layer. Appropriate pressure must be maintained during chip placement to avoid mechanical damage. In some applications, thermally conductive material may be added between the integrated circuit chip and the substrate to improve thermal management.

[0085] Step S140: plastic-encapsulating the first transistor, the second transistor, and the integrated circuit chip to form a plastic-encapsulated body having a first surface and a second surface.

[0086] By way of example and not limitation, the encapsulation process utilizes transfer molding technology, wherein an epoxy resin-based encapsulation compound is heated to a fluid state and then injected into the mold cavity under pressure to completely cover the first transistor, the second transistor, and the integrated circuit chip. The encapsulation material typically utilizes an epoxy resin composite containing silica filler, with the filler content controlled to balance fluidity and thermal expansion coefficient. The molding process must be performed in a vacuum environment to avoid bubble formation, and the curing time of the encapsulation compound is controlled. A post-curing heat treatment is then performed to ensure complete cross-linking of the resin and improve mechanical strength and thermal stability.

[0087] After forming, the plastic encapsulation body presents two primary surfaces: the first surface (top) and the second surface (bottom). Plastic encapsulation design focuses on the following aspects: First, the thermal expansion coefficient of the encapsulation material must match that of the transistor and IC chip materials to reduce thermal stress; second, the thickness of the encapsulation body must be evenly distributed to avoid warping; and third, the encapsulation material must completely fill the gaps between components to prevent voids and delamination. For ultra-thin transistor structures, a special low-stress encapsulation process is used to reduce mechanical stress during the encapsulation process, preventing chip cracking and adhesive creepage shorts.

[0088] Step S150: thinning the second surface of the plastic package body so that the interposer is exposed on the second surface.

[0089] Specifically, a thinning process is performed on the second surface of the plastic package body in order to expose the intermediary layer to the second surface. As an example and not a limitation, the thinning process can adopt precision back grinding technology, first using a coarse grinding wheel for rapid material removal to control the removal rate; then switching to a fine grinding wheel for fine grinding to reduce the removal rate and ensure surface flatness. Finally, chemical mechanical polishing (CMP) is performed using an alkaline polishing solution to reduce the surface roughness. A precision thickness control system is used during the thinning process to monitor the remaining thickness in real time to ensure that the intermediary layer is just exposed without being damaged.

[0090] The key to thinning technology lies in precisely controlling the uniformity of material removal and endpoint detection, typically achieved through real-time monitoring using laser or capacitive thickness measurement systems. To prevent wafer warping and damage during the thinning process, a temporary adhesive is often used to secure the plastic package to the supporting substrate and then release it after thinning is complete. This process step not only exposes the conductive pathways of the interposer to the backside but also significantly reduces the package thickness, improving heat dissipation and reducing thermal resistance.

[0091] Step S160: forming a plurality of plastic-encapsulated vias on the plastic-encapsulated body, wherein the plastic-encapsulated vias are used to connect the electrode of the first transistor and the electrode of the second transistor.

[0092] Specifically, vias are formed using precision laser drilling technology, typically using a 355nm UV laser with controlled pulse width to achieve high-precision micro-hole processing. The drilling process employs a multi-pulse, layer-by-layer ablation method to minimize heat-affected zones and ensure smooth hole walls.

[0093] For vias connecting deep electrodes, a two-stage laser drilling process is used: a larger diameter first truncated cone-shaped hole is first formed on the surface; a second laser drilling operation is then performed at the bottom of the first hole, forming a smaller diameter second truncated cone-shaped hole that penetrates to the target electrode. In contrast, for vias with higher current capacity requirements but shallower depths, a single laser drilling process is used to simplify the process.

[0094] After drilling, plasma or chemical cleaning is performed to remove molten debris and carbides generated during drilling. A titanium / copper seed layer is then deposited on the inner wall of the hole, providing a conductive foundation for subsequent electroplating. Finally, copper is filled in through electroplating to form a complete conductive path. Pulse reverse plating technology is used to ensure uniform filling of deep holes and avoid void formation.

[0095] Step S170: forming a backside redistribution layer on the second surface, wherein the backside redistribution layer is used to connect the electrode of the first transistor and / or the electrode of the second transistor to the interposer.

[0096] Specifically, the preparation of the back redistribution layer adopts semiconductor-grade precision processing technology. First, a metal seed layer is deposited on the entire second surface through physical vapor deposition (PVD) technology. It is usually a titanium / copper double-layer structure, with the titanium layer as an adhesion layer and the copper layer as a conductive base. Subsequently, a photolithography process is carried out to apply photoresist, which is exposed and developed through a mask to form a negative image of the redistribution pattern. Then an electroplating process is carried out to deposit a copper layer in the exposed area. The copper electroplating solution usually uses a copper sulfate system to control the current density and ensure uniform deposition. After the electroplating is completed, the photoresist is removed, and then the excess seed layer is removed by wet etching. Finally, a passivation treatment is performed to prevent copper oxidation.

[0097] The design of the backside redistribution layer adheres to strict electrical regulations, controlling the width of power lines to carry high currents and signal lines to optimize signal transmission. The circuit layout considers current distribution uniformity and heat dissipation requirements to avoid hotspot formation. The redistribution layer forms precise alignment connections with the exposed interposer and plastic vias, establishing a complete electrical network and providing a path for signal transmission between the front and back surfaces. The entire manufacturing process is carried out in a dust-free environment to ensure the integrity and reliability of the micron-level structure.

[0098] Step S180: forming a front-side redistribution layer on the first surface, wherein the front-side redistribution layer is used to connect the electrodes of the first transistor, the electrodes of the second transistor, and the input / output ports of the integrated circuit chip.

[0099] The fabrication process for the front-side redistribution layer (RDL) is similar to that for the back-side, but the more complex interconnections required require higher precision. The front-side RDL typically employs a multilayer design, consisting of a primary conductive layer and possible additional layers. The primary conductive layer is copper; for high-frequency applications, it is sometimes plated with gold to reduce surface oxidation and improve solderability.

[0100] The design of the front-side rewiring pattern must balance multiple requirements: separating power and signal lines to minimize interference; using differential pairs for critical signal lines to improve interference immunity; and increasing heat-dissipating copper areas in heat-sensitive areas to optimize thermal management. The photolithography process utilizes high-resolution masks and advanced exposure equipment to control alignment accuracy and ensure precise formation of the complex pattern. This step is crucial in establishing the interconnect network between the first and second transistors and the integrated circuit die to achieve complete circuit functionality.

[0101] After the first transistor and the second transistor are connected via chip bonding in step S110, this embodiment further includes providing an adapter plate. The adapter plate has a first contact surface for temporarily supporting and securing the package assembly. The adapter plate is typically made of ceramic, polymer composite materials, or metal substrates with good high-temperature stability and high flatness. A special release agent is applied to the surface to facilitate subsequent separation. The adapter plate is slightly larger than the final package size, and the thickness is controlled to provide sufficient mechanical strength to support subsequent processing operations.

[0102] The vertically stacked first and second transistors are positioned on the first contact surface of the adapter plate, with the first transistor facing the first contact surface. Positioning of the first transistor is accomplished using high-precision placement equipment. A temporary adhesive, typically a thermoplastic or thermosetting adhesive, can be applied between the first transistor and the adapter plate. This adhesive cures at a specific temperature to form a reliable connection while ensuring that it can be completely removed later.

[0103] The integrated circuit chip is also placed on the first contact surface of the adapter board, using the same bonding method as the first transistor. An appropriate distance is maintained between the integrated circuit chip and the first transistor to reserve space for the interposer. Using the adapter board as a temporary substrate ensures that the components maintain accurate relative positioning in three-dimensional space, laying the foundation for subsequent processing.

[0104] After forming the back side redistribution layer in step S170, this embodiment further includes the step of flipping the plastic package body forming the back side redistribution layer so that the back side redistribution layer faces the first contact surface of the adapter board. The flipping operation uses a dedicated flipping device to fix the package body by vacuum adsorption or mechanical clamping, and then rotate it 180 degrees. The flipping process must be precisely controlled to avoid mechanical damage and positional displacement. After flipping, the first surface of the package body faces upward, which facilitates the subsequent front side redistribution layer manufacturing process.

[0105] After the fabrication method completes the steps of setting several pins, the interposer plate needs to be removed. This removal process typically uses a thermal release technique, heating the entire structure to the softening temperature of the adhesive. The interposer plate is then separated by shear force or vacuum suction. After removal, the package structure is completely free of its temporary support, forming a self-contained package that is easily accessible for subsequent testing and application.

[0106] Before vertically stacking the first transistor and the second transistor, this embodiment also includes forming a first thin film layer on one end face of the first transistor and forming a plurality of first thin film conduction holes in the first thin film layer. The first thin film layer is formed by a spin coating process using materials such as polyimide or benzocyclobutene (BCB). The thin film conduction holes are formed by photolithography and dry etching processes and are precisely aligned with the electrodes of the first transistor. The holes are filled with conductive material by physical vapor deposition and electroplating processes to form a vertical conduction path. The first thin film layer is arranged toward the first contact surface of the adapter plate to provide an interface for the connection between the transistor and the front redistribution layer.

[0107] Similarly, a second thin film layer is formed on one end surface of the integrated circuit chip, and a plurality of second thin film vias are formed in the second thin film layer. The materials and preparation process of the second thin film layer are similar to those of the first thin film layer, but the layout of the vias is customized based on the input / output port distribution of the integrated circuit chip. The second thin film layer is also positioned toward the first contact surface of the adapter board, ensuring a reliable connection between the integrated circuit chip and the front-side redistribution layer.

[0108] After forming the backside redistribution layer in step S170 , this embodiment further includes performing a second plastic encapsulation or lamination on the backside redistribution layer to form a second protection layer.

[0109] Specifically, the second protective layer can be formed using two process methods: for applications requiring high mechanical strength, a second plastic encapsulation process is used, using liquid epoxy molding compound for injection molding; if there are strict requirements on the thickness of the second protective layer, a lamination process is used, using polyimide (PI) or polybenzoxazole (PBO) film, applying pressure and hot pressing at a specific temperature to form a protective layer of uniform thickness.

[0110] The following factors should be considered when selecting the protective layer material: a dielectric strength of at least 1kV / mil to ensure electrical insulation; a thermal expansion coefficient that matches the substrate material to reduce thermal stress; good moisture resistance to prevent reliability issues caused by moisture absorption; and excellent adhesion and chemical resistance. The lamination process utilizes a precisely controlled heat press, with a heating and cooling rate of 3-5°C / minute to avoid material stress caused by thermal shock. For applications requiring heat dissipation from the backside, windows are sometimes opened in specific areas of the protective layer to expose the metal heat dissipation area for improved heat dissipation efficiency.

[0111] After forming the front redistribution layer in step S180, this embodiment further includes laminating the front redistribution layer to form a first protective layer, and arranging a plurality of pins on the front redistribution layer so that the plurality of pins pass through the first protective layer.

[0112] Specifically, the first protective layer is made of solvent-based photoresist or dry film. The lamination process uses a vacuum laminator, applying uniform pressure at a specific temperature to ensure the absence of bubbles and wrinkles. After lamination, a photolithography process is performed to create windows where pins are required, exposing the pads of the underlying redistribution layer.

[0113] Pin production utilizes two primary processes: For ball grid array (BGA) packages, solder balls are applied to the pads via screen printing or dispensing, typically using a tin-lead alloy or lead-free solder. For column grid array (PGA) packages, copper pillars are formed on the pads via electroplating, topped with a tin layer to enhance solderability. The pin layout is designed based on product specifications and can be a full array, perimeter array, or a hybrid layout, with spacing meeting PCB assembly requirements. Once the pins are formed, the entire package is manufactured and, after electrical testing and reliability verification, is ready for system-level integration.

[0114] These additional process steps further enhance the packaging fabrication method. By incorporating an interposer as a temporary support substrate, precise fabrication of complex three-dimensional structures is achieved. The flipping process allows for precision machining of both the front and back surfaces, while preformed film layers and vias provide the foundation for electrical interconnection. This complete manufacturing process ensures the high integration density, low impedance, and high reliability of the final packaged product, meeting the stringent requirements of modern electronic devices.

[0115] based on Figure 4 The packaging structure shown in FIG. 1 is a block diagram of a package structure. This embodiment provides a preparation method, focusing on describing a specific implementation scheme of the source common electrode configuration.

[0116] In this embodiment, the source of the first transistor is arranged toward the second transistor, while the source of the second transistor is arranged toward the first transistor. The sources of the two transistors face each other directly, making it easy to connect them together through a chip bonding process to form a source common electrode. The source common electrode structure has significant advantages in synchronous rectification circuits and power half-bridge circuits, minimizing loop area, reducing source loop inductance, and improving switching performance.

[0117] The die bonding process utilizes precisely controlled temperature and pressure parameters to promote interdiffusion of metal atoms between the two source surfaces, forming a strong metal bonding interface. The metallurgical structure of the bonding interface exhibits typical transition region characteristics, ensuring a low-impedance electrical connection and high mechanical strength.

[0118] For the formation of connection paths, this embodiment adopts three different plastic package via structures, which are used to connect different electrodes respectively:

[0119] The first plastic via, formed using a secondary laser drilling and electroplating process, connects the gate of the first transistor to the backside redistribution layer. This secondary laser drilling process first forms a larger-diameter first truncated cone-shaped hole on the surface of the plastic package. A second precision laser drilling process then forms a smaller-diameter second truncated cone-shaped hole at the bottom of the first hole, ensuring that the top diameter of the second truncated cone is smaller than the bottom diameter of the first. This stepped structure significantly improves metal filling uniformity within the deep hole, enhancing electrical connection reliability.

[0120] After the vias are formed, plasma cleaning is performed to remove debris generated by laser drilling. A titanium / copper seed layer is then deposited on the inner walls of the vias, providing a conductive foundation for subsequent electroplating. The electroplating process utilizes pulsed reverse current technology to control the deposition rate uniformity and ensure complete filling of deep vias without voids or cracks.

[0121] The second plastic via, also using a secondary laser drilling and electroplating process, connects the gate of the second transistor to the front-side redistribution layer, following a similar process flow as the first plastic via. High-quality gate signal transmission is crucial to transistor switching performance, so the via design emphasizes minimizing parasitic inductance and resistance to ensure a fast and clean gate drive signal.

[0122] The third plastic-encapsulated via uses a single laser drilling and electroplating process to connect the drain of the second transistor to the backside redistribution layer. Compared to the secondary drilling process, the single drilling process is more streamlined and suitable for applications with moderate depth but high current flow. As the main current channel, the drain typically requires multiple parallel vias to form a low-impedance path. The vias are distributed in a uniform lattice arrangement to optimize current distribution and thermal management.

[0123] The drain of the first transistor is connected to the front-side redistribution layer through a first thin-film via pre-formed on the transistor. This first thin-film via passes through the first thin-film layer and directly connects to the drain metal layer, eliminating the need for a long conductive path through the entire plastic package and significantly reducing connection impedance.

[0124] The entire structure forms a complete three-dimensional interconnect network, connecting the electrodes of the two vertically stacked transistors to different levels of redistribution layers. The common source structure simplifies the source connection path, while the gate and drain are connected to the redistribution layers through specially designed vias, achieving an optimal electrical interconnect layout.

[0125] based on Figure 5 The package structure shown in FIG. 1 is a block diagram of a package structure shown in FIG. 1 , and this embodiment provides another preparation method, focusing on describing a specific implementation scheme of the drain-source common electrode configuration.

[0126] In this embodiment, the drain of the first transistor is arranged toward the second transistor, while the source of the second transistor is arranged toward the first transistor. With this layout, a portion of the drain of the first transistor is directly connected to the source of the second transistor through the chip bonding process, forming a unique drain-source common electrode structure. The hybrid common electrode configuration is particularly suitable for certain specific circuit topologies, such as common-source common-drain amplifiers, bootstrap circuits, or certain types of power conversion circuits, and can form internal feedback paths or specific bias networks.

[0127] The die bonding process utilizes a precise temperature gradient control system, gradually decreasing the temperature from the center outward to ensure uniform bonding at the interface without thermal stress. A special metal filler material is used at the bonding interface to enhance conductivity, while a stress relief structure is designed around the bonding area to prevent interface reliability issues caused by thermal expansion coefficient mismatch.

[0128] It's worth noting that the drain of the first transistor isn't entirely connected to the source of the second transistor. Instead, a portion of the drain is left facing the backside redistribution layer, allowing for independent connections to external circuits. This partial connection increases the flexibility of the circuit topology and enables the implementation of more complex circuit functions.

[0129] For the formation of electrode connection paths, this embodiment also adopts three different plastic package via hole structures:

[0130] The first plastic-encapsulated via, formed using a secondary laser drilling and electroplating process, connects the remaining drain electrode of the first transistor to the backside redistribution layer. Precisely controlled drilling parameters ensure precise contact with the target electrode without damaging surrounding structures. The via's interior undergoes a special treatment, first with plasma activation, then using electroless chemical deposition to form the initial conductive layer. Finally, pulse electroplating is used to fill the via with copper, ensuring a fill uniformity exceeding 95% within the deep hole.

[0131] The second plastic-encapsulated via, also using a secondary laser drilling and electroplating process, connects the gate of the second transistor to the front-side redistribution layer. The reliability of the gate connection is crucial to the stable operation of the transistor. Therefore, during the via production process, special attention is paid to controlling the hole wall quality. A special multi-pulse cleaning laser technology is used to remove drilling debris, ensuring smooth hole walls and improving the quality of subsequent metal deposition.

[0132] The third plastic via, using a single laser-drilled electroplating process, connects the drain of the second transistor to the backside redistribution layer. As the primary current path, the third plastic via is typically larger in diameter than other vias and utilizes a higher copper fill ratio to ensure low impedance for high currents. The vias are distributed in an optimized lattice pattern, optimized through electromagnetic field simulation to minimize current concentration and self-induction effects.

[0133] The gate and source of the first transistor are connected to the front-side redistribution layer through a first thin-film via pre-formed on the transistor. The first thin-film vias utilize a hybrid distribution strategy, with the vias connecting the gate arranged linearly and evenly spaced to ensure uniform gate drive signal transmission. The vias connecting the source utilize a lattice layout to optimize high-current transmission paths. The conductive material filling the thin-film vias is a copper-tungsten alloy, which increases the hardness and stability of the filler material and reduces the risk of stress cracking under thermal cycling conditions.

[0134] based on Figure 6 The package structure shown in FIG. 1 is a block diagram of a package structure shown in FIG. 1 , and this embodiment provides another preparation method, focusing on describing a specific implementation scheme of the drain common electrode configuration.

[0135] In this embodiment, the drain of the first transistor is positioned toward the second transistor, while the drain of the second transistor is positioned toward the first transistor. Through a precise die bonding process, the drains of the two transistors are directly connected to form a common drain electrode. This common drain electrode structure is suitable for circuit applications that require sharing the same drain potential, such as push-pull output stages, synchronous buck converters, or certain types of power amplifiers, providing an ideal solution for optimizing current paths.

[0136] During chip bonding, the drain metal surfaces of two transistors come into direct contact at a specific temperature, where uniform pressure forms a diffusion layer between metal atoms, establishing a strong electrical and mechanical connection. To enhance the stability of the bonding interface, a special transition metal layer can be pre-deposited on the drain surface to promote metallurgical bonding and improve long-term reliability.

[0137] In the drain common electrode structure, the gate and source of the first transistor are connected to the front-side redistribution layer through the first thin-film via, while the gate and source of the second transistor are connected to the back-side redistribution layer through the third plastic package via. This double-sided connection design fully utilizes the wiring resources on both the front and back surfaces of the package, achieving optimized signal and power distribution.

[0138] The third plastic-encapsulated vias are formed using a single laser drilling and electroplating process, employing a hybrid layout strategy. The vias connecting to the gate of the second transistor are arranged in a row with equal spacing along the gate edge, forming a regular linear distribution. This arrangement ensures uniform distribution of gate control signals, minimizing switching delay variations caused by gate drive imbalance. Meanwhile, the vias connecting to the source are arranged in a dotted pattern, covering the majority of the source area, ensuring uniform transmission of high current.

[0139] Dot-matrix vias typically utilize a 5×5 or larger matrix, with the aperture diameter adjusted based on current density requirements. The minimum spacing between vias is maintained at least 1.5 times the aperture diameter to ensure mechanical strength and plating process reliability. This dot-matrix layout not only optimizes current flow but also improves thermal distribution, reducing the formation of localized hot spots.

[0140] The first thin-film vias also employ a hybrid distribution strategy. The vias connecting to the gate of the first transistor are arranged in a regular row, ensuring accurate transmission of control signals. The vias connecting to the source utilize an optimized lattice distribution, with a density proportional to the expected current load, providing a low-impedance current loop. The design of the thin-film vias fully considers signal integrity and current-carrying capacity, optimizing the connection between the front-side redistribution layer and the first transistor electrode.

[0141] The drain common electrode structure provides several significant advantages: first, the shared drain eliminates additional connection paths and reduces power loss; second, the vertical stacking design minimizes the package area and improves power density; third, the symmetrical via distribution improves thermal management performance, allowing heat to be more evenly distributed outside the package; finally, the double-sided connection design increases wiring flexibility and simplifies system-level integration.

[0142] Different from the existing technology, the packaging structure and preparation method provided by the present invention achieve a highly integrated packaging layout through an innovative vertical stacking transistor structure combined with chip bonding technology, which greatly reduces the package area occupied compared to the traditional flat tiling method and greatly improves the power density per unit area; and the chip bonding method is used to form a common electrode, eliminating the long wire path of traditional wire bonding, significantly reducing the on-resistance and parasitic inductance, and directly improving the circuit efficiency and switching performance; in addition, the innovative plastic-encapsulated via design and redistribution layer structure optimize the electrical connection path, reduce signal transmission delay and power loss, and improve the current distribution uniformity and thermal management efficiency; finally, a variety of common electrode configuration schemes (source common, drain common, drain-source common) meet the needs of different circuit topologies and adapt to various application scenarios.

[0143] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Based on the idea of ​​the present application, the technical features in the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations in different aspects of the present application as above, which are not provided in detail for the sake of simplicity. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A packaging structure, characterized in that: include: A first transistor and a second transistor are vertically stacked, wherein opposite end surfaces of the first transistor and the second transistor are connected by chip bonding to form a common electrode; A plastic package covering the first transistor and the second transistor to form a plastic package body; the plastic package body has a first surface and a second surface; A front redistribution layer is provided on the first surface of the plastic package body; A back redistribution layer is provided on the second surface of the plastic package body; a plurality of plastic-encapsulated vias penetrating the plastic-encapsulated component, wherein the plastic-encapsulated vias are used to connect the electrode of the first transistor and the electrode of the second transistor to the front-side redistribution layer or the back-side redistribution layer; as well as The intermediate layer vertically penetrates the plastic package and is used to connect the electrodes connected to the back redistribution layer to the front redistribution layer.

2. The packaging structure according to claim 1, wherein: Also includes: An integrated circuit chip is wrapped by the plastic package and is arranged on a side of the interposer away from the first transistor and the second transistor vertically stacked. The front side redistribution layer is connected to the input / output port of the integrated circuit chip.

3. The packaging structure according to claim 2, wherein: Also includes: A first thin film layer provided on an end surface of the first transistor away from the second transistor; a plurality of first thin film vias penetrating the first thin film layer, wherein the first thin film vias are used to connect the electrodes of the first transistor to the front side redistribution layer; A second thin film layer is provided on one end surface of the integrated circuit chip close to the front redistribution layer; A plurality of second thin film vias penetrate the second thin film layer, wherein the second thin film vias are used to connect the input / output port of the integrated circuit chip to the front side redistribution layer.

4. The packaging structure according to claim 1, wherein: The source electrode of the first transistor and the source electrode of the second transistor are connected by chip bonding to form a source common electrode; The gate of the first transistor faces the back redistribution layer, and the gate of the second transistor faces the front redistribution layer; A drain of the first transistor is connected to the front side redistribution layer.

5. The packaging structure according to claim 4, wherein: The plurality of plastic-sealed via holes include a plurality of first plastic-sealed via holes, a plurality of second plastic-sealed via holes and a plurality of third plastic-sealed via holes; The plurality of first plastic-encapsulated vias are used to connect the gate of the first transistor and the backside redistribution layer; The first plastic-encapsulated via hole is formed by secondary laser drilling and electroplating; The plurality of second plastic-encapsulated vias are used to connect the gate of the second transistor and the front-side redistribution layer; The second plastic-encapsulated via hole is formed by secondary laser drilling and electroplating; The plurality of third plastic-encapsulated vias are used to connect the drain of the second transistor and the backside redistribution layer; the third plastic-encapsulated vias are formed by one laser drilling and electroplating process.

6. The packaging structure according to claim 1, wherein: A portion of the drain of the first transistor and the source of the second transistor are connected by chip bonding to form a drain-source common electrode; Another portion of the drain of the first transistor faces the back redistribution layer, and the gate of the second transistor faces the front redistribution layer; A source and a gate of the first transistor are connected to the front side redistribution layer.

7. The packaging structure according to claim 6, wherein: The plurality of plastic-sealed via holes include a plurality of first plastic-sealed via holes, a plurality of second plastic-sealed via holes and a plurality of third plastic-sealed via holes; The plurality of first plastic-encapsulated vias are used to connect another portion of the drain of the first transistor and the backside redistribution layer; The first plastic-encapsulated via hole is formed by secondary laser drilling and electroplating; The plurality of second plastic-encapsulated vias are used to connect the gate of the second transistor and the front-side redistribution layer; The second plastic-encapsulated via hole is formed by secondary laser drilling and electroplating; The plurality of third plastic-encapsulated vias are used to connect the drain of the second transistor and the backside redistribution layer; the third plastic-encapsulated vias are formed by one laser drilling and electroplating process.

8. The packaging structure according to claim 1, wherein: The drain of the first transistor and the drain of the second transistor are connected by chip bonding to form a drain common electrode; A source and a gate of the first transistor are connected to the front side redistribution layer.

9. The packaging structure according to claim 8, wherein: The plurality of plastic-sealed vias include a plurality of third plastic-sealed vias; The source and gate of the second transistor are connected to the backside redistribution layer through the plurality of third plastic-encapsulated vias; the third plastic-encapsulated vias are formed by one laser drilling and electroplating process.

10. The packaging structure according to any one of claims 1 to 9, characterized in that: The first transistor and the second transistor are both vertical power metal oxide semiconductor field effect transistors.

11. A method for preparing a packaging structure, characterized in that: include: vertically stacking a first transistor and a second transistor, and connecting them by chip bonding so that opposite end surfaces of the first transistor and the second transistor form a common electrode; Disposing an interposer outside the vertically stacked first and second transistors; Disposing an integrated circuit chip on a side of the interposer away from the vertically stacked first and second transistors; Performing plastic packaging on the first transistor, the second transistor, and the integrated circuit chip to form a plastic packaging body, wherein the plastic packaging body has a first surface and a second surface; Thinning the second surface of the plastic package body so that the intermediate layer is exposed on the second surface; forming a plurality of plastic-encapsulated vias on the plastic-encapsulated body, wherein the plastic-encapsulated vias are used to connect the electrode of the first transistor and the electrode of the second transistor; forming a backside redistribution layer on the second surface, wherein the backside redistribution layer is used to connect the electrode of the first transistor and / or the electrode of the second transistor to the interposer; A front side redistribution layer is formed on the first surface, and the front side redistribution layer is used to connect the electrodes of the first transistor, the electrodes of the second transistor and the input / output ports of the integrated circuit chip.

12. The preparation method according to claim 11, characterized in that After connecting the first transistor and the second transistor by chip bonding so that the opposite end surfaces of the first transistor and the second transistor form a common electrode, the method further includes: Providing an adapter plate; the adapter plate has a first contact surface; Disposing a vertically stacked first transistor and a second transistor on the first contact surface, with the first transistor facing the first contact surface; placing the integrated circuit chip on the first contact surface; and After the plurality of pins are set, the adapter board is removed.

13. The preparation method according to claim 12, characterized in that After forming a backside redistribution layer on the second surface, the method further includes: The plastic package body on which the back side redistribution layer is formed is turned over so that the back side redistribution layer faces the first contact surface.

14. The preparation method according to claim 11, characterized in that Before vertically stacking the first transistor and the second transistor and connecting them by chip bonding so that the opposite end surfaces of the first transistor and the second transistor form a common electrode, the method further includes: forming a first thin film layer on one end surface of the first transistor, and forming a plurality of first thin film conductive holes in the first thin film layer; the first thin film layer faces the first contact surface; A second film layer is formed on one end surface of the integrated circuit chip, and a plurality of second film conducting holes are formed in the first film layer; the second film layer faces the first contact surface.

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